@W: MT530 :"e:\libero_11p7_updates\downloaded\dspan_gl2_df\igloo2\extended_adder\extended_adder_2_input\hdl\dotp_multadd_dotp_multadd_0_hard_mult_addsub.vhd":113:4:113:5|Found inferred clock Extended_adder_2_input|clk which controls 52 sequential elements including U0.dotp_multadd_0.U0. This clock has no specified timing constraint which may adversely impact design performance. 
