#Build: Synplify Pro J-2015.03M-SP1-2, Build 266R, Dec 14 2015 #install: D:\11.7 Installation\Synplify #OS: Windows 7 6.1 #Hostname: W764-EDARAP1 #Implementation: synthesis Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Synopsys Verilog Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. @I::"D:\11.7 Installation\Synplify\lib\generic\smartfusion2.v" @I::"D:\11.7 Installation\Synplify\lib\vlog\hypermods.v" @I::"D:\11.7 Installation\Synplify\lib\vlog\umr_capim.v" @I::"D:\11.7 Installation\Synplify\lib\vlog\scemi_objects.v" @I::"D:\11.7 Installation\Synplify\lib\vlog\scemi_pipes.svh" @I::"D:\DG0669\SF2_CodeShadowing_LPDDR_DF\Libero\HWBootEngine_method\CodeShadowing_Fabric\component\work\CodeShadowing_Fabric\CCC_0\CodeShadowing_Fabric_CCC_0_FCCC.v" @I::"D:\DG0669\SF2_CodeShadowing_LPDDR_DF\Libero\HWBootEngine_method\CodeShadowing_Fabric\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" @I::"D:\DG0669\SF2_CodeShadowing_LPDDR_DF\Libero\HWBootEngine_method\CodeShadowing_Fabric\component\work\CodeShadowing_Fabric\FABOSC_0\CodeShadowing_Fabric_FABOSC_0_OSC.v" @I::"D:\DG0669\SF2_CodeShadowing_LPDDR_DF\Libero\HWBootEngine_method\CodeShadowing_Fabric\component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v" @I::"D:\DG0669\SF2_CodeShadowing_LPDDR_DF\Libero\HWBootEngine_method\CodeShadowing_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v" @I::"D:\DG0669\SF2_CodeShadowing_LPDDR_DF\Libero\HWBootEngine_method\CodeShadowing_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v" @I::"D:\DG0669\SF2_CodeShadowing_LPDDR_DF\Libero\HWBootEngine_method\CodeShadowing_Fabric\hdl\AHB_IF.v" @I::"D:\DG0669\SF2_CodeShadowing_LPDDR_DF\Libero\HWBootEngine_method\CodeShadowing_Fabric\hdl\AXI_IF.v" @I::"D:\DG0669\SF2_CodeShadowing_LPDDR_DF\Libero\HWBootEngine_method\CodeShadowing_Fabric\hdl\MDDR_Config.v" @I::"D:\DG0669\SF2_CodeShadowing_LPDDR_DF\Libero\HWBootEngine_method\CodeShadowing_Fabric\hdl\SPI_to_MDDR.v" @I::"D:\DG0669\SF2_CodeShadowing_LPDDR_DF\Libero\HWBootEngine_method\CodeShadowing_Fabric\component\work\HW_Boot_Engine\HW_Boot_Engine.v" @I::"D:\DG0669\SF2_CodeShadowing_LPDDR_DF\Libero\HWBootEngine_method\CodeShadowing_Fabric\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v" @I::"D:\DG0669\SF2_CodeShadowing_LPDDR_DF\Libero\HWBootEngine_method\CodeShadowing_Fabric\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v" @I::"D:\DG0669\SF2_CodeShadowing_LPDDR_DF\Libero\HWBootEngine_method\CodeShadowing_Fabric\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v" @I::"D:\DG0669\SF2_CodeShadowing_LPDDR_DF\Libero\HWBootEngine_method\CodeShadowing_Fabric\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v" @I::"D:\DG0669\SF2_CodeShadowing_LPDDR_DF\Libero\HWBootEngine_method\CodeShadowing_Fabric\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v" @I::"D:\DG0669\SF2_CodeShadowing_LPDDR_DF\Libero\HWBootEngine_method\CodeShadowing_Fabric\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v" @I::"D:\DG0669\SF2_CodeShadowing_LPDDR_DF\Libero\HWBootEngine_method\CodeShadowing_Fabric\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v" @I::"D:\DG0669\SF2_CodeShadowing_LPDDR_DF\Libero\HWBootEngine_method\CodeShadowing_Fabric\component\work\CodeShadowing_Fabric_MSS\CodeShadowing_Fabric_MSS_syn.v" @I::"D:\DG0669\SF2_CodeShadowing_LPDDR_DF\Libero\HWBootEngine_method\CodeShadowing_Fabric\component\work\CodeShadowing_Fabric_MSS\CodeShadowing_Fabric_MSS.v" @I::"D:\DG0669\SF2_CodeShadowing_LPDDR_DF\Libero\HWBootEngine_method\CodeShadowing_Fabric\component\work\CodeShadowing_Fabric\CodeShadowing_Fabric.v" Verilog syntax check successful! Options changed - recompiling Selecting top level module CodeShadowing_Fabric @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC @N:CG364 : smartfusion2.v(372) | Synthesizing module GND @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT @N:CG364 : smartfusion2.v(727) | Synthesizing module CCC @N:CG364 : CodeShadowing_Fabric_CCC_0_FCCC.v(5) | Synthesizing module CodeShadowing_Fabric_CCC_0_FCCC @N:CG364 : smartfusion2.v(274) | Synthesizing module OUTBUF @N:CG364 : smartfusion2.v(326) | Synthesizing module OUTBUF_DIFF @N:CG364 : smartfusion2.v(286) | Synthesizing module BIBUF @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF @N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF @N:CG364 : CodeShadowing_Fabric_MSS_syn.v(5) | Synthesizing module MSS_075 @N:CG364 : CodeShadowing_Fabric_MSS.v(9) | Synthesizing module CodeShadowing_Fabric_MSS @W:CG775 : coreahblite.v(23) | Found Component CoreAHBLite in library COREAHBLITE_LIB @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000010000 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z1 @N:CG364 : coreahblite_defaultslavesm.v(20) | Synthesizing module COREAHBLITE_DEFAULTSLAVESM SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 HRESPEXTEND=1'b1 Generated name = COREAHBLITE_DEFAULTSLAVESM_0s_0_1 @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000010000 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_0_16_0s_0_1_0 @N:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000000 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z2 @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_0_0_0s_0_1_0 @N:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. @N:CG364 : coreahblite_slavearbiter.v(20) | Synthesizing module COREAHBLITE_SLAVEARBITER SYNC_RESET=32'b00000000000000000000000000000000 M0EXTEND=4'b0000 M0DONE=4'b0001 M0LOCK=4'b0010 M0LOCKEXTEND=4'b0011 M1EXTEND=4'b0100 M1DONE=4'b0101 M1LOCK=4'b0110 M1LOCKEXTEND=4'b0111 M2EXTEND=4'b1000 M2DONE=4'b1001 M2LOCK=4'b1010 M2LOCKEXTEND=4'b1011 M3EXTEND=4'b1100 M3DONE=4'b1101 M3LOCK=4'b1110 M3LOCKEXTEND=4'b1111 MASTER_0=4'b0001 MASTER_1=4'b0010 MASTER_2=4'b0100 MASTER_3=4'b1000 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVEARBITER_Z3 @N:CG364 : coreahblite_slavestage.v(22) | Synthesizing module COREAHBLITE_SLAVESTAGE SYNC_RESET=32'b00000000000000000000000000000000 TRN_IDLE=1'b0 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVESTAGE_0s_0_0 @N:CG364 : coreahblite_matrix4x16.v(23) | Synthesizing module COREAHBLITE_MATRIX4X16 MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M0_AHBSLOTENABLE=17'b00000000000010000 M1_AHBSLOTENABLE=17'b00000000000000000 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = COREAHBLITE_MATRIX4X16_1_1_0_16_0_0_0_0s @N:CG364 : coreahblite.v(23) | Synthesizing module CoreAHBLite FAMILY=6'b010011 MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 M0_AHBSLOT0ENABLE=1'b0 M0_AHBSLOT1ENABLE=1'b0 M0_AHBSLOT2ENABLE=1'b0 M0_AHBSLOT3ENABLE=1'b0 M0_AHBSLOT4ENABLE=1'b1 M0_AHBSLOT5ENABLE=1'b0 M0_AHBSLOT6ENABLE=1'b0 M0_AHBSLOT7ENABLE=1'b0 M0_AHBSLOT8ENABLE=1'b0 M0_AHBSLOT9ENABLE=1'b0 M0_AHBSLOT10ENABLE=1'b0 M0_AHBSLOT11ENABLE=1'b0 M0_AHBSLOT12ENABLE=1'b0 M0_AHBSLOT13ENABLE=1'b0 M0_AHBSLOT14ENABLE=1'b0 M0_AHBSLOT15ENABLE=1'b0 M0_AHBSLOT16ENABLE=1'b0 M1_AHBSLOT0ENABLE=1'b0 M1_AHBSLOT1ENABLE=1'b0 M1_AHBSLOT2ENABLE=1'b0 M1_AHBSLOT3ENABLE=1'b0 M1_AHBSLOT4ENABLE=1'b0 M1_AHBSLOT5ENABLE=1'b0 M1_AHBSLOT6ENABLE=1'b0 M1_AHBSLOT7ENABLE=1'b0 M1_AHBSLOT8ENABLE=1'b0 M1_AHBSLOT9ENABLE=1'b0 M1_AHBSLOT10ENABLE=1'b0 M1_AHBSLOT11ENABLE=1'b0 M1_AHBSLOT12ENABLE=1'b0 M1_AHBSLOT13ENABLE=1'b0 M1_AHBSLOT14ENABLE=1'b0 M1_AHBSLOT15ENABLE=1'b0 M1_AHBSLOT16ENABLE=1'b0 M2_AHBSLOT0ENABLE=1'b0 M2_AHBSLOT1ENABLE=1'b0 M2_AHBSLOT2ENABLE=1'b0 M2_AHBSLOT3ENABLE=1'b0 M2_AHBSLOT4ENABLE=1'b0 M2_AHBSLOT5ENABLE=1'b0 M2_AHBSLOT6ENABLE=1'b0 M2_AHBSLOT7ENABLE=1'b0 M2_AHBSLOT8ENABLE=1'b0 M2_AHBSLOT9ENABLE=1'b0 M2_AHBSLOT10ENABLE=1'b0 M2_AHBSLOT11ENABLE=1'b0 M2_AHBSLOT12ENABLE=1'b0 M2_AHBSLOT13ENABLE=1'b0 M2_AHBSLOT14ENABLE=1'b0 M2_AHBSLOT15ENABLE=1'b0 M2_AHBSLOT16ENABLE=1'b0 M3_AHBSLOT0ENABLE=1'b0 M3_AHBSLOT1ENABLE=1'b0 M3_AHBSLOT2ENABLE=1'b0 M3_AHBSLOT3ENABLE=1'b0 M3_AHBSLOT4ENABLE=1'b0 M3_AHBSLOT5ENABLE=1'b0 M3_AHBSLOT6ENABLE=1'b0 M3_AHBSLOT7ENABLE=1'b0 M3_AHBSLOT8ENABLE=1'b0 M3_AHBSLOT9ENABLE=1'b0 M3_AHBSLOT10ENABLE=1'b0 M3_AHBSLOT11ENABLE=1'b0 M3_AHBSLOT12ENABLE=1'b0 M3_AHBSLOT13ENABLE=1'b0 M3_AHBSLOT14ENABLE=1'b0 M3_AHBSLOT15ENABLE=1'b0 M3_AHBSLOT16ENABLE=1'b0 SYNC_RESET=32'b00000000000000000000000000000000 M0_AHBSLOTENABLE=17'b00000000000010000 M1_AHBSLOTENABLE=17'b00000000000000000 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SC=16'b0000000000000000 Generated name = CoreAHBLite_Z4 @N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP FAMILY=32'b00000000000000000000000000010011 MDDR_IN_USE=32'b00000000000000000000000000000001 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000 DEVICE_090=32'b00000000000000000000000000000000 VERSION_MAJOR=32'b00000000000000000000000000000111 VERSION_MINOR=32'b00000000000000000000000000000000 VERSION_MAJOR_VECTOR=16'b0000000000000111 VERSION_MINOR_VECTOR=16'b0000000000000000 S0=2'b00 S1=2'b01 S2=2'b10 Generated name = CoreConfigP_Z5 @W:CL113 : coreconfigp.v(626) | Feedback mux created for signal soft_reset_reg[16:0]. @W:CL250 : coreconfigp.v(626) | All reachable assignments to soft_reset_reg[16:0] assign 0, register removed by optimization @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000 DEVICE_090=32'b00000000000000000000000000000000 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z6 @W:CL169 : coreresetp.v(1613) | Pruning register count_ddr[13:0] @W:CL169 : coreresetp.v(1581) | Pruning register count_sdif3[12:0] @W:CL169 : coreresetp.v(1549) | Pruning register count_sdif2[12:0] @W:CL169 : coreresetp.v(1517) | Pruning register count_sdif1[12:0] @W:CL169 : coreresetp.v(1485) | Pruning register count_sdif0[12:0] @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif0_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif0_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_rcosc @W:CL169 : coreresetp.v(1365) | Pruning register count_sdif3_enable @W:CL169 : coreresetp.v(1300) | Pruning register count_sdif2_enable @W:CL169 : coreresetp.v(1235) | Pruning register count_sdif1_enable @W:CL169 : coreresetp.v(1170) | Pruning register count_sdif0_enable @W:CL169 : coreresetp.v(1089) | Pruning register count_ddr_enable @N:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0 @W:CL169 : coreresetp.v(1089) | Pruning register release_ext_reset @W:CL169 : coreresetp.v(1433) | Pruning register EXT_RESET_OUT_int @W:CL169 : coreresetp.v(1433) | Pruning register sm2_state[2:0] @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_q1 @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_clk_base @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ @N:CG364 : CodeShadowing_Fabric_FABOSC_0_OSC.v(5) | Synthesizing module CodeShadowing_Fabric_FABOSC_0_OSC @N:CG364 : AHB_IF.v(21) | Synthesizing module AHB_IF Idle_1=3'b000 Write_FIC_0=3'b001 Write_FIC_1=3'b010 Write_FIC_2=3'b011 Read_FIC_0=3'b100 Read_FIC_1=3'b101 Read_FIC_2=3'b110 Data_size=5'b00000 Generated name = AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7 @W:CL190 : AHB_IF.v(80) | Optimizing register bit HTRANS[0] to a constant 0 @W:CL260 : AHB_IF.v(80) | Pruning register bit 0 of HTRANS[1:0] @N:CG364 : AXI_IF.v(21) | Synthesizing module AXI_IF Idle_0=3'b000 Idle_1=3'b001 Write_0=3'b010 Write_1=3'b011 Bresp_0=3'b100 Generated name = AXI_IF_0s_1s_2s_3s_4294967292s @W:CG360 : AXI_IF.v(52) | No assignment to wire ARID @W:CG360 : AXI_IF.v(53) | No assignment to wire ARADDR @W:CG360 : AXI_IF.v(54) | No assignment to wire ARLEN @W:CG360 : AXI_IF.v(55) | No assignment to wire ARSIZE @W:CG360 : AXI_IF.v(56) | No assignment to wire ARLOCK @W:CG360 : AXI_IF.v(57) | No assignment to wire ARBURST @W:CG360 : AXI_IF.v(58) | No assignment to wire ARVALID @W:CG133 : AXI_IF.v(66) | No assignment to RREADY @W:CL190 : AXI_IF.v(81) | Optimizing register bit AWBURST[1] to a constant 0 @W:CL190 : AXI_IF.v(81) | Optimizing register bit AWSIZE[2] to a constant 0 @W:CL260 : AXI_IF.v(81) | Pruning register bit 1 of AWBURST[1:0] @W:CL260 : AXI_IF.v(81) | Pruning register bit 2 of AWSIZE[2:0] @N:CG364 : MDDR_Config.v(22) | Synthesizing module MDDR_Config Idle=3'b000 Write_0=3'b001 Write_1=3'b010 Write_2=3'b011 Read_0=3'b100 Read_1=3'b101 Write_3=3'b110 Generated name = MDDR_Config_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_Z8 @N:CG364 : SPI_to_MDDR.v(24) | Synthesizing module SPI_to_MDDR Idle=4'b0000 Reg_init=4'b0001 Write_cmd=4'b0010 Read_statusTx=4'b0011 Read_statusTx2=4'b0100 Read_status=4'b0101 Read_status2=4'b0110 Read=4'b0111 Read2=4'b1000 Read3=4'b1001 write_ddr=4'b1010 next_block=4'b1011 stop_st=4'b1100 SPI_disable=4'b1101 final_st=4'b1111 block_length=12'b010000000100 File_size=12'b000010000000 Generated name = SPI_to_MDDR_Z9 @N:CL134 : SPI_to_MDDR.v(77) | Found RAM read_byte, depth=1028, width=8 @N:CL134 : SPI_to_MDDR.v(77) | Found RAM read_byte, depth=1028, width=8 @N:CL134 : SPI_to_MDDR.v(77) | Found RAM read_byte, depth=1028, width=8 @N:CL134 : SPI_to_MDDR.v(77) | Found RAM read_byte, depth=1028, width=8 @N:CL134 : SPI_to_MDDR.v(77) | Found RAM read_byte, depth=1028, width=8 @N:CL134 : SPI_to_MDDR.v(77) | Found RAM read_byte, depth=1028, width=8 @N:CL134 : SPI_to_MDDR.v(77) | Found RAM read_byte, depth=1028, width=8 @N:CL134 : SPI_to_MDDR.v(77) | Found RAM read_byte, depth=1028, width=8 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit ADDR[0] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit ADDR[1] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit ADDR[5] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit ADDR[6] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit ADDR[7] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit ADDR[8] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit ADDR[9] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit ADDR[10] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit ADDR[11] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit ADDR[13] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit ADDR[14] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit ADDR[18] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit ADDR[19] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit ADDR[20] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit ADDR[21] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit ADDR[22] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit ADDR[23] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit ADDR[24] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit ADDR[25] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit ADDR[26] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit ADDR[27] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit ADDR[28] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit ADDR[29] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit ADDR[31] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit DATAOUT[8] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit DATAOUT[9] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit DATAOUT[11] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit DATAOUT[12] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit DATAOUT[13] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit DATAOUT[14] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit DATAOUT[15] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit DATAOUT[16] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit DATAOUT[17] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit DATAOUT[19] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit DATAOUT[20] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit DATAOUT[21] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit DATAOUT[22] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit DATAOUT[23] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit DATAOUT[26] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit DATAOUT[27] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit DATAOUT[28] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit DATAOUT[30] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit DATAOUT[31] to a constant 0 @W:CL260 : SPI_to_MDDR.v(77) | Pruning register bit 31 of ADDR[31:0] @W:CL279 : SPI_to_MDDR.v(77) | Pruning register bits 29 to 18 of ADDR[31:0] @W:CL279 : SPI_to_MDDR.v(77) | Pruning register bits 14 to 13 of ADDR[31:0] @W:CL279 : SPI_to_MDDR.v(77) | Pruning register bits 11 to 5 of ADDR[31:0] @W:CL279 : SPI_to_MDDR.v(77) | Pruning register bits 1 to 0 of ADDR[31:0] @W:CL279 : SPI_to_MDDR.v(77) | Pruning register bits 31 to 30 of DATAOUT[31:0] @W:CL279 : SPI_to_MDDR.v(77) | Pruning register bits 28 to 26 of DATAOUT[31:0] @W:CL279 : SPI_to_MDDR.v(77) | Pruning register bits 23 to 19 of DATAOUT[31:0] @W:CL279 : SPI_to_MDDR.v(77) | Pruning register bits 17 to 11 of DATAOUT[31:0] @W:CL279 : SPI_to_MDDR.v(77) | Pruning register bits 9 to 8 of DATAOUT[31:0] @N:CG364 : HW_Boot_Engine.v(9) | Synthesizing module HW_Boot_Engine @N:CG364 : smartfusion2.v(718) | Synthesizing module SYSRESET @N:CG364 : CodeShadowing_Fabric.v(9) | Synthesizing module CodeShadowing_Fabric @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit nblocks[8] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit nblocks[9] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit nblocks[10] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit nblocks[11] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit block_address[0] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit block_address[1] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit block_address[2] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit block_address[3] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit block_address[4] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit block_address[5] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit block_address[6] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit block_address[7] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit block_address[8] to a constant 0 @W:CL190 : SPI_to_MDDR.v(77) | Optimizing register bit block_address[9] to a constant 0 @W:CL279 : SPI_to_MDDR.v(77) | Pruning register bits 9 to 0 of block_address[23:0] @W:CL279 : SPI_to_MDDR.v(77) | Pruning register bits 11 to 8 of nblocks[11:0] @N:CL201 : SPI_to_MDDR.v(77) | Trying to extract state machine for register SPI_current_state Extracted state machine for register SPI_current_state State machine has 15 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1111 @W:CL279 : SPI_to_MDDR.v(77) | Pruning register bits 17 to 16 of ADDR[17:15] @W:CL260 : SPI_to_MDDR.v(77) | Pruning register bit 25 of DATAOUT[25:24] @W:CL246 : SPI_to_MDDR.v(30) | Input port bits 31 to 9 of DATAIN[31:0] are unused @N:CL201 : MDDR_Config.v(174) | Trying to extract state machine for register apb_fsm_current_state Extracted state machine for register apb_fsm_current_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @W:CL156 : MDDR_Config.v(47) | *Input DDRC_Reg[120][15:0] to expression [pmux] has undriven bits that are tied to 0 -- simulation mismatch possible. @W:CL156 : MDDR_Config.v(47) | *Input DDRC_Reg[121][15:0] to expression [pmux] has undriven bits that are tied to 0 -- simulation mismatch possible. @W:CL156 : MDDR_Config.v(47) | *Input DDRC_Reg[122][15:0] to expression [pmux] has undriven bits that are tied to 0 -- simulation mismatch possible. @W:CL156 : MDDR_Config.v(47) | *Input DDRC_Reg[123][15:0] to expression [pmux] has undriven bits that are tied to 0 -- simulation mismatch possible. @W:CL156 : MDDR_Config.v(47) | *Input DDRC_Reg[124][15:0] to expression [pmux] has undriven bits that are tied to 0 -- simulation mismatch possible. @W:CL156 : MDDR_Config.v(47) | *Input DDRC_Reg[125][15:0] to expression [pmux] has undriven bits that are tied to 0 -- simulation mismatch possible. @W:CL156 : MDDR_Config.v(47) | *Input DDRC_Reg[126][15:0] to expression [pmux] has undriven bits that are tied to 0 -- simulation mismatch possible. @W:CL156 : MDDR_Config.v(47) | *Input DDRC_Reg[127][15:0] to expression [pmux] has undriven bits that are tied to 0 -- simulation mismatch possible. @W:CL159 : MDDR_Config.v(27) | Input PSLVERR is unused @W:CL159 : MDDR_Config.v(28) | Input PRDATA is unused @N:CL201 : AXI_IF.v(81) | Trying to extract state machine for register axi_fsm_current_state Extracted state machine for register axi_fsm_current_state State machine has 5 reachable states with original encodings of: 000 001 010 011 100 @W:CL260 : AXI_IF.v(81) | Pruning register bit 1 of AWSIZE[1:0] @A:CL153 : AXI_IF.v(66) | *Unassigned bits of RREADY are referenced and tied to 0 -- simulation mismatch possible. @W:CL157 : AXI_IF.v(52) | *Output ARID has undriven bits -- simulation mismatch possible. @W:CL157 : AXI_IF.v(53) | *Output ARADDR has undriven bits -- simulation mismatch possible. @W:CL157 : AXI_IF.v(54) | *Output ARLEN has undriven bits -- simulation mismatch possible. @W:CL157 : AXI_IF.v(55) | *Output ARSIZE has undriven bits -- simulation mismatch possible. @W:CL157 : AXI_IF.v(56) | *Output ARLOCK has undriven bits -- simulation mismatch possible. @W:CL157 : AXI_IF.v(57) | *Output ARBURST has undriven bits -- simulation mismatch possible. @W:CL157 : AXI_IF.v(58) | *Output ARVALID has undriven bits -- simulation mismatch possible. @W:CL159 : AXI_IF.v(47) | Input BID is unused @W:CL159 : AXI_IF.v(48) | Input BRESP is unused @W:CL159 : AXI_IF.v(59) | Input ARREADY is unused @W:CL159 : AXI_IF.v(61) | Input RID is unused @W:CL159 : AXI_IF.v(62) | Input RDATA is unused @W:CL159 : AXI_IF.v(63) | Input RRESP is unused @W:CL159 : AXI_IF.v(64) | Input RLAST is unused @W:CL159 : AXI_IF.v(65) | Input RVALID is unused @N:CL201 : AHB_IF.v(80) | Trying to extract state machine for register ahb_fsm_current_state Extracted state machine for register ahb_fsm_current_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @W:CL157 : CodeShadowing_Fabric_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : CodeShadowing_Fabric_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible. @W:CL157 : CodeShadowing_Fabric_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : CodeShadowing_Fabric_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits -- simulation mismatch possible. @W:CL159 : CodeShadowing_Fabric_FABOSC_0_OSC.v(14) | Input XTL is unused @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @W:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused @W:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused @W:CL159 : coreresetp.v(59) | Input SDIF0_SPLL_LOCK is unused @W:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused @W:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused @W:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused @W:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused @W:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused @W:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused @W:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused @W:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused @W:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused @W:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused @W:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused @W:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused @W:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused @W:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused @W:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused @W:CL159 : coreresetp.v(107) | Input SOFT_EXT_RESET_OUT is unused @W:CL159 : coreresetp.v(108) | Input SOFT_RESET_F2M is unused @W:CL159 : coreresetp.v(109) | Input SOFT_M3_RESET is unused @W:CL159 : coreresetp.v(110) | Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused @W:CL159 : coreresetp.v(111) | Input SOFT_FDDR_CORE_RESET is unused @W:CL159 : coreresetp.v(112) | Input SOFT_SDIF0_PHY_RESET is unused @W:CL159 : coreresetp.v(113) | Input SOFT_SDIF0_CORE_RESET is unused @W:CL159 : coreresetp.v(114) | Input SOFT_SDIF1_PHY_RESET is unused @W:CL159 : coreresetp.v(115) | Input SOFT_SDIF1_CORE_RESET is unused @W:CL159 : coreresetp.v(116) | Input SOFT_SDIF2_PHY_RESET is unused @W:CL159 : coreresetp.v(117) | Input SOFT_SDIF2_CORE_RESET is unused @W:CL159 : coreresetp.v(118) | Input SOFT_SDIF3_PHY_RESET is unused @W:CL159 : coreresetp.v(119) | Input SOFT_SDIF3_CORE_RESET is unused @W:CL159 : coreresetp.v(123) | Input SOFT_SDIF0_0_CORE_RESET is unused @W:CL159 : coreresetp.v(124) | Input SOFT_SDIF0_1_CORE_RESET is unused @N:CL201 : coreconfigp.v(447) | Trying to extract state machine for register state Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL247 : coreahblite.v(120) | Input port bit 0 of HTRANS_M0[1:0] is unused @W:CL247 : coreahblite.v(131) | Input port bit 0 of HTRANS_M1[1:0] is unused @W:CL247 : coreahblite.v(142) | Input port bit 0 of HTRANS_M2[1:0] is unused @W:CL247 : coreahblite.v(153) | Input port bit 0 of HTRANS_M3[1:0] is unused @W:CL247 : coreahblite.v(163) | Input port bit 1 of HRESP_S0[1:0] is unused @W:CL247 : coreahblite.v(176) | Input port bit 1 of HRESP_S1[1:0] is unused @W:CL247 : coreahblite.v(189) | Input port bit 1 of HRESP_S2[1:0] is unused @W:CL247 : coreahblite.v(202) | Input port bit 1 of HRESP_S3[1:0] is unused @W:CL247 : coreahblite.v(215) | Input port bit 1 of HRESP_S4[1:0] is unused @W:CL247 : coreahblite.v(228) | Input port bit 1 of HRESP_S5[1:0] is unused @W:CL247 : coreahblite.v(241) | Input port bit 1 of HRESP_S6[1:0] is unused @W:CL247 : coreahblite.v(254) | Input port bit 1 of HRESP_S7[1:0] is unused @W:CL247 : coreahblite.v(267) | Input port bit 1 of HRESP_S8[1:0] is unused @W:CL247 : coreahblite.v(280) | Input port bit 1 of HRESP_S9[1:0] is unused @W:CL247 : coreahblite.v(293) | Input port bit 1 of HRESP_S10[1:0] is unused @W:CL247 : coreahblite.v(306) | Input port bit 1 of HRESP_S11[1:0] is unused @W:CL247 : coreahblite.v(319) | Input port bit 1 of HRESP_S12[1:0] is unused @W:CL247 : coreahblite.v(332) | Input port bit 1 of HRESP_S13[1:0] is unused @W:CL247 : coreahblite.v(345) | Input port bit 1 of HRESP_S14[1:0] is unused @W:CL247 : coreahblite.v(358) | Input port bit 1 of HRESP_S15[1:0] is unused @W:CL247 : coreahblite.v(371) | Input port bit 1 of HRESP_S16[1:0] is unused @W:CL159 : coreahblite.v(123) | Input HBURST_M0 is unused @W:CL159 : coreahblite.v(124) | Input HPROT_M0 is unused @W:CL159 : coreahblite.v(134) | Input HBURST_M1 is unused @W:CL159 : coreahblite.v(135) | Input HPROT_M1 is unused @W:CL159 : coreahblite.v(145) | Input HBURST_M2 is unused @W:CL159 : coreahblite.v(146) | Input HPROT_M2 is unused @W:CL159 : coreahblite.v(156) | Input HBURST_M3 is unused @W:CL159 : coreahblite.v(157) | Input HPROT_M3 is unused @W:CL159 : coreahblite_matrix4x16.v(51) | Input HWDATA_M1 is unused @W:CL159 : coreahblite_matrix4x16.v(60) | Input HWDATA_M2 is unused @W:CL159 : coreahblite_matrix4x16.v(69) | Input HWDATA_M3 is unused @W:CL159 : coreahblite_matrix4x16.v(73) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_matrix4x16.v(74) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_matrix4x16.v(75) | Input HRESP_S0 is unused @W:CL159 : coreahblite_matrix4x16.v(84) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_matrix4x16.v(85) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_matrix4x16.v(86) | Input HRESP_S1 is unused @W:CL159 : coreahblite_matrix4x16.v(95) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_matrix4x16.v(96) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_matrix4x16.v(97) | Input HRESP_S2 is unused @W:CL159 : coreahblite_matrix4x16.v(106) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_matrix4x16.v(107) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_matrix4x16.v(108) | Input HRESP_S3 is unused @W:CL159 : coreahblite_matrix4x16.v(128) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(129) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(130) | Input HRESP_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(139) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(140) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(141) | Input HRESP_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(150) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(151) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(152) | Input HRESP_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(161) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(162) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(163) | Input HRESP_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(172) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(173) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(174) | Input HRESP_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(183) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(184) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(185) | Input HRESP_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(194) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(195) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(196) | Input HRESP_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(205) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(206) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(207) | Input HRESP_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(216) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(217) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(218) | Input HRESP_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(227) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(228) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(229) | Input HRESP_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(238) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_matrix4x16.v(239) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_matrix4x16.v(240) | Input HRESP_S15 is unused @W:CL159 : coreahblite_matrix4x16.v(249) | Input HRDATA_S16 is unused @W:CL159 : coreahblite_matrix4x16.v(250) | Input HREADYOUT_S16 is unused @W:CL159 : coreahblite_matrix4x16.v(251) | Input HRESP_S16 is unused @N:CL201 : coreahblite_slavearbiter.v(449) | Trying to extract state machine for register arbRegSMCurrentState Extracted state machine for register arbRegSMCurrentState State machine has 16 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 @W:CL159 : coreahblite_masterstage.v(42) | Input SDATAREADY is unused @W:CL159 : coreahblite_masterstage.v(43) | Input SHRESP is unused @W:CL159 : coreahblite_masterstage.v(52) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_masterstage.v(53) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S16 is unused @W:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S16 is unused @W:CL246 : coreahblite_masterstage.v(42) | Input port bits 16 to 5 of SDATAREADY[16:0] are unused @W:CL246 : coreahblite_masterstage.v(42) | Input port bits 3 to 0 of SDATAREADY[16:0] are unused @W:CL246 : coreahblite_masterstage.v(43) | Input port bits 16 to 5 of SHRESP[16:0] are unused @W:CL246 : coreahblite_masterstage.v(43) | Input port bits 3 to 0 of SHRESP[16:0] are unused @W:CL159 : coreahblite_masterstage.v(52) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_masterstage.v(53) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S16 is unused @W:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S16 is unused @W:CL247 : CodeShadowing_Fabric_MSS.v(124) | Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 87MB peak: 93MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Mar 23 11:55:14 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode @N:NF107 : CodeShadowing_Fabric.v(9) | Selected library: work cell: CodeShadowing_Fabric view verilog as top level @N:NF107 : CodeShadowing_Fabric.v(9) | Selected library: work cell: CodeShadowing_Fabric view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 78MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Mar 23 11:55:15 2016 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Mar 23 11:55:15 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Options changed - recompiling @N:NF107 : CodeShadowing_Fabric.v(9) | Selected library: work cell: CodeShadowing_Fabric view verilog as top level @N:NF107 : CodeShadowing_Fabric.v(9) | Selected library: work cell: CodeShadowing_Fabric view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 84MB peak: 85MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Mar 23 11:55:16 2016 ###########################################################] Pre-mapping Report Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Linked File: CodeShadowing_Fabric_scck.rpt Printing clock summary report in "D:\DG0669\SF2_CodeShadowing_LPDDR_DF\Libero\HWBootEngine_method\CodeShadowing_Fabric\synthesis\CodeShadowing_Fabric_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 121MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 121MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 121MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 122MB) @W:BN132 : coreahblite_matrix4x16.v(3626) | Removing user instance CoreAHBLite_0.matrix4x16.slavestage_16, because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_15 @W:BN132 : coreahblite_matrix4x16.v(3580) | Removing user instance CoreAHBLite_0.matrix4x16.slavestage_15, because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_14 @W:BN132 : coreahblite_matrix4x16.v(3534) | Removing user instance CoreAHBLite_0.matrix4x16.slavestage_14, because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_13 @W:BN132 : coreahblite_matrix4x16.v(3488) | Removing user instance CoreAHBLite_0.matrix4x16.slavestage_13, because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_12 @W:BN132 : coreahblite_matrix4x16.v(3442) | Removing user instance CoreAHBLite_0.matrix4x16.slavestage_12, because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_11 @W:BN132 : coreahblite_matrix4x16.v(3396) | Removing user instance CoreAHBLite_0.matrix4x16.slavestage_11, because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3304) | Removing user instance CoreAHBLite_0.matrix4x16.slavestage_9, because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3258) | Removing user instance CoreAHBLite_0.matrix4x16.slavestage_8, because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3212) | Removing user instance CoreAHBLite_0.matrix4x16.slavestage_7, because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3166) | Removing user instance CoreAHBLite_0.matrix4x16.slavestage_6, because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10 @N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF0_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF1_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF3_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1388) | Removing sequential instance RESET_N_F2M_int of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_RELEASED_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance INIT_DONE_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0s_0_1_0_2(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0s_0_1_0_2(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0s_0_1_0_2(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0s_0_1_0_1(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0s_0_1_0_1(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0s_0_1_0_1(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0s_0_1_0_0(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0s_0_1_0_0(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0s_0_1_0_0(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2703) | Removing instance masterstage_1 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0s_0_1_0_2(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2767) | Removing instance masterstage_2 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0s_0_1_0_1(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2831) | Removing instance masterstage_3 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0s_0_1_0_0(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2890) | Removing instance slavestage_0 of view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance sm0_state[6:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(546) | Removing sequential instance FIC_2_APB_M_PRDATA[31:0] of view:PrimLib.dffre(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(546) | Removing sequential instance FIC_2_APB_M_PSLVERR of view:PrimLib.dffre(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(769) | Removing sequential instance sm1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(946) | Removing sequential instance CONFIG2_DONE_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1170) | Removing sequential instance sdif0_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(769) | Removing sequential instance sm1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(946) | Removing sequential instance CONFIG2_DONE_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(583) | Removing sequential instance SDIF_RELEASED_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(566) | Removing sequential instance INIT_DONE_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(603) | Removing sequential instance control_reg_1[1:0] of view:PrimLib.dffre(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif0_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif1_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif2_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif3_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1646) | Removing sequential instance ddr_settled_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(963) | Removing sequential instance sdif3_spll_lock_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(929) | Removing sequential instance CONFIG1_DONE_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(583) | Removing sequential instance SDIF_RELEASED_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(566) | Removing sequential instance INIT_DONE_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[3:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif0_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif1_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif2_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif3_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1646) | Removing sequential instance ddr_settled_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(963) | Removing sequential instance sdif3_spll_lock_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(929) | Removing sequential instance CONFIG1_DONE_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1485) | Removing sequential instance release_sdif0_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1517) | Removing sequential instance release_sdif1_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1549) | Removing sequential instance release_sdif2_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1581) | Removing sequential instance release_sdif3_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1613) | Removing sequential instance ddr_settled of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN115 : coreahblite_slavestage.v(87) | Removing instance slave_arbiter of view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_0(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(755) | Removing sequential instance sm0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(870) | Removing sequential instance sdif0_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(884) | Removing sequential instance sdif1_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(898) | Removing sequential instance sdif2_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(912) | Removing sequential instance sdif3_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(856) | Removing sequential instance sm0_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(755) | Removing sequential instance sm0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(870) | Removing sequential instance sdif0_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(884) | Removing sequential instance sdif1_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(898) | Removing sequential instance sdif2_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(912) | Removing sequential instance sdif3_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(856) | Removing sequential instance sm0_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance arbRegSMCurrentState[15:0] of view:PrimLib.statemachine(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_0(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(676) | Removing sequential instance SDIF0_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(695) | Removing sequential instance SDIF1_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(714) | Removing sequential instance SDIF2_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(733) | Removing sequential instance SDIF3_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(676) | Removing sequential instance SDIF0_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(695) | Removing sequential instance SDIF1_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(714) | Removing sequential instance SDIF2_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(733) | Removing sequential instance SDIF3_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(676) | Removing sequential instance SDIF0_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(695) | Removing sequential instance SDIF1_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(714) | Removing sequential instance SDIF2_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(733) | Removing sequential instance SDIF3_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(676) | Removing sequential instance SDIF0_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(695) | Removing sequential instance SDIF1_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(714) | Removing sequential instance SDIF2_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(733) | Removing sequential instance SDIF3_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs syn_allowed_resources : blockrams=109 set on top level netlist CodeShadowing_Fabric Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 150MB) @S |Clock Summary ***************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ------------------------------------------------------------------------------------------------------------------------- CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_1 System 100.0 MHz 10.000 system system_clkgroup ========================================================================================================================= @W:MT530 : codeshadowing_fabric_mss.v(1352) | Found inferred clock CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock which controls 669 sequential elements including CodeShadowing_Fabric_MSS_0.MSS_ADLIB_INST. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : codeshadowing_fabric_mss.v(1352) | Found inferred clock CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock which controls 114 sequential elements including CodeShadowing_Fabric_MSS_0.MSS_ADLIB_INST. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[0] on net HW_Boot_Engine_0_AXI_IF_ARADDR[0] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[1] on net HW_Boot_Engine_0_AXI_IF_ARADDR[1] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[2] on net HW_Boot_Engine_0_AXI_IF_ARADDR[2] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[3] on net HW_Boot_Engine_0_AXI_IF_ARADDR[3] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[4] on net HW_Boot_Engine_0_AXI_IF_ARADDR[4] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[5] on net HW_Boot_Engine_0_AXI_IF_ARADDR[5] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[6] on net HW_Boot_Engine_0_AXI_IF_ARADDR[6] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[7] on net HW_Boot_Engine_0_AXI_IF_ARADDR[7] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[8] on net HW_Boot_Engine_0_AXI_IF_ARADDR[8] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[9] on net HW_Boot_Engine_0_AXI_IF_ARADDR[9] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[10] on net HW_Boot_Engine_0_AXI_IF_ARADDR[10] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[11] on net HW_Boot_Engine_0_AXI_IF_ARADDR[11] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[12] on net HW_Boot_Engine_0_AXI_IF_ARADDR[12] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[13] on net HW_Boot_Engine_0_AXI_IF_ARADDR[13] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[14] on net HW_Boot_Engine_0_AXI_IF_ARADDR[14] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[15] on net HW_Boot_Engine_0_AXI_IF_ARADDR[15] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[16] on net HW_Boot_Engine_0_AXI_IF_ARADDR[16] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[17] on net HW_Boot_Engine_0_AXI_IF_ARADDR[17] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[18] on net HW_Boot_Engine_0_AXI_IF_ARADDR[18] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[19] on net HW_Boot_Engine_0_AXI_IF_ARADDR[19] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[20] on net HW_Boot_Engine_0_AXI_IF_ARADDR[20] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[21] on net HW_Boot_Engine_0_AXI_IF_ARADDR[21] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[22] on net HW_Boot_Engine_0_AXI_IF_ARADDR[22] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[23] on net HW_Boot_Engine_0_AXI_IF_ARADDR[23] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[24] on net HW_Boot_Engine_0_AXI_IF_ARADDR[24] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[25] on net HW_Boot_Engine_0_AXI_IF_ARADDR[25] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[26] on net HW_Boot_Engine_0_AXI_IF_ARADDR[26] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[27] on net HW_Boot_Engine_0_AXI_IF_ARADDR[27] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[28] on net HW_Boot_Engine_0_AXI_IF_ARADDR[28] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[29] on net HW_Boot_Engine_0_AXI_IF_ARADDR[29] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[30] on net HW_Boot_Engine_0_AXI_IF_ARADDR[30] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[31] on net HW_Boot_Engine_0_AXI_IF_ARADDR[31] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARBURST_t[0] on net HW_Boot_Engine_0_AXI_IF_ARBURST[0] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARBURST_t[1] on net HW_Boot_Engine_0_AXI_IF_ARBURST[1] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARID_t[0] on net HW_Boot_Engine_0_AXI_IF_ARID[0] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARID_t[1] on net HW_Boot_Engine_0_AXI_IF_ARID[1] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARID_t[2] on net HW_Boot_Engine_0_AXI_IF_ARID[2] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARID_t[3] on net HW_Boot_Engine_0_AXI_IF_ARID[3] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARLEN_t[0] on net HW_Boot_Engine_0_AXI_IF_ARLEN[0] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARLEN_t[1] on net HW_Boot_Engine_0_AXI_IF_ARLEN[1] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARLEN_t[2] on net HW_Boot_Engine_0_AXI_IF_ARLEN[2] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARLEN_t[3] on net HW_Boot_Engine_0_AXI_IF_ARLEN[3] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARLOCK_t[0] on net HW_Boot_Engine_0_AXI_IF_ARLOCK[0] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARLOCK_t[1] on net HW_Boot_Engine_0_AXI_IF_ARLOCK[1] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARSIZE_t[0] on net HW_Boot_Engine_0_AXI_IF_ARSIZE[0] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARSIZE_t[1] on net HW_Boot_Engine_0_AXI_IF_ARSIZE[1] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARVALID_t on net HW_Boot_Engine_0_AXI_IF_ARVALID has its enable tied to GND (module CodeShadowing_Fabric) @N:BN225 : | Writing default property annotation file D:\DG0669\SF2_CodeShadowing_LPDDR_DF\Libero\HWBootEngine_method\CodeShadowing_Fabric\synthesis\CodeShadowing_Fabric.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 80MB peak: 150MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Mar 23 11:55:17 2016 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB) @W:MO111 : codeshadowing_fabric_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module CodeShadowing_Fabric_FABOSC_0_OSC) @W:MO111 : codeshadowing_fabric_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module CodeShadowing_Fabric_FABOSC_0_OSC) @W:MO111 : codeshadowing_fabric_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module CodeShadowing_Fabric_FABOSC_0_OSC) @W:MO111 : codeshadowing_fabric_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module CodeShadowing_Fabric_FABOSC_0_OSC) @W:MO111 : axi_if.v(58) | Tristate driver ARVALID on net ARVALID has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(57) | Tristate driver ARBURST_1 on net ARBURST_1 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(57) | Tristate driver ARBURST_2 on net ARBURST_2 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(56) | Tristate driver ARLOCK_1 on net ARLOCK_1 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(56) | Tristate driver ARLOCK_2 on net ARLOCK_2 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(55) | Tristate driver ARSIZE_1 on net ARSIZE_1 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(55) | Tristate driver ARSIZE_2 on net ARSIZE_2 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(54) | Tristate driver ARLEN_1 on net ARLEN_1 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(54) | Tristate driver ARLEN_2 on net ARLEN_2 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(54) | Tristate driver ARLEN_3 on net ARLEN_3 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(54) | Tristate driver ARLEN_4 on net ARLEN_4 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_1 on net ARADDR_1 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_2 on net ARADDR_2 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_3 on net ARADDR_3 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_4 on net ARADDR_4 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_5 on net ARADDR_5 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_6 on net ARADDR_6 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_7 on net ARADDR_7 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_8 on net ARADDR_8 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_9 on net ARADDR_9 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_10 on net ARADDR_10 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_11 on net ARADDR_11 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_12 on net ARADDR_12 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_13 on net ARADDR_13 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_14 on net ARADDR_14 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_15 on net ARADDR_15 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_16 on net ARADDR_16 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_17 on net ARADDR_17 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_18 on net ARADDR_18 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_19 on net ARADDR_19 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_20 on net ARADDR_20 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_21 on net ARADDR_21 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_22 on net ARADDR_22 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_23 on net ARADDR_23 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_24 on net ARADDR_24 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_25 on net ARADDR_25 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_26 on net ARADDR_26 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_27 on net ARADDR_27 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_28 on net ARADDR_28 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_29 on net ARADDR_29 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_30 on net ARADDR_30 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_31 on net ARADDR_31 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(53) | Tristate driver ARADDR_32 on net ARADDR_32 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(52) | Tristate driver ARID_1 on net ARID_1 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(52) | Tristate driver ARID_2 on net ARID_2 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(52) | Tristate driver ARID_3 on net ARID_3 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : axi_if.v(52) | Tristate driver ARID_4 on net ARID_4 has its enable tied to GND (module AXI_IF_0s_1s_2s_3s_4294967292s) @W:MO111 : | Tristate driver ARID_t[0] on net ARID[0] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARID_t[1] on net ARID[1] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARID_t[2] on net ARID[2] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARID_t[3] on net ARID[3] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[0] on net ARADDR[0] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[1] on net ARADDR[1] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[2] on net ARADDR[2] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[3] on net ARADDR[3] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[4] on net ARADDR[4] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[5] on net ARADDR[5] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[6] on net ARADDR[6] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[7] on net ARADDR[7] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[8] on net ARADDR[8] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[9] on net ARADDR[9] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[10] on net ARADDR[10] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[11] on net ARADDR[11] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[12] on net ARADDR[12] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[13] on net ARADDR[13] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[14] on net ARADDR[14] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[15] on net ARADDR[15] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[16] on net ARADDR[16] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[17] on net ARADDR[17] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[18] on net ARADDR[18] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[19] on net ARADDR[19] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[20] on net ARADDR[20] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[21] on net ARADDR[21] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[22] on net ARADDR[22] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[23] on net ARADDR[23] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[24] on net ARADDR[24] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[25] on net ARADDR[25] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[26] on net ARADDR[26] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[27] on net ARADDR[27] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[28] on net ARADDR[28] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[29] on net ARADDR[29] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[30] on net ARADDR[30] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARADDR_t[31] on net ARADDR[31] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARLEN_t[0] on net ARLEN[0] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARLEN_t[1] on net ARLEN[1] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARLEN_t[2] on net ARLEN[2] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARLEN_t[3] on net ARLEN[3] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARSIZE_t[0] on net ARSIZE[0] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARSIZE_t[1] on net ARSIZE[1] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARLOCK_t[0] on net ARLOCK[0] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARLOCK_t[1] on net ARLOCK[1] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARBURST_t[0] on net ARBURST[0] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARBURST_t[1] on net ARBURST[1] has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver ARVALID_t on net ARVALID has its enable tied to GND (module HW_Boot_Engine) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[0] on net HW_Boot_Engine_0_AXI_IF_ARADDR[0] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[1] on net HW_Boot_Engine_0_AXI_IF_ARADDR[1] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[2] on net HW_Boot_Engine_0_AXI_IF_ARADDR[2] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[3] on net HW_Boot_Engine_0_AXI_IF_ARADDR[3] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[4] on net HW_Boot_Engine_0_AXI_IF_ARADDR[4] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[5] on net HW_Boot_Engine_0_AXI_IF_ARADDR[5] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[6] on net HW_Boot_Engine_0_AXI_IF_ARADDR[6] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[7] on net HW_Boot_Engine_0_AXI_IF_ARADDR[7] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[8] on net HW_Boot_Engine_0_AXI_IF_ARADDR[8] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[9] on net HW_Boot_Engine_0_AXI_IF_ARADDR[9] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[10] on net HW_Boot_Engine_0_AXI_IF_ARADDR[10] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[11] on net HW_Boot_Engine_0_AXI_IF_ARADDR[11] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[12] on net HW_Boot_Engine_0_AXI_IF_ARADDR[12] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[13] on net HW_Boot_Engine_0_AXI_IF_ARADDR[13] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[14] on net HW_Boot_Engine_0_AXI_IF_ARADDR[14] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[15] on net HW_Boot_Engine_0_AXI_IF_ARADDR[15] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[16] on net HW_Boot_Engine_0_AXI_IF_ARADDR[16] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[17] on net HW_Boot_Engine_0_AXI_IF_ARADDR[17] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[18] on net HW_Boot_Engine_0_AXI_IF_ARADDR[18] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[19] on net HW_Boot_Engine_0_AXI_IF_ARADDR[19] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[20] on net HW_Boot_Engine_0_AXI_IF_ARADDR[20] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[21] on net HW_Boot_Engine_0_AXI_IF_ARADDR[21] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[22] on net HW_Boot_Engine_0_AXI_IF_ARADDR[22] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[23] on net HW_Boot_Engine_0_AXI_IF_ARADDR[23] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[24] on net HW_Boot_Engine_0_AXI_IF_ARADDR[24] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[25] on net HW_Boot_Engine_0_AXI_IF_ARADDR[25] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[26] on net HW_Boot_Engine_0_AXI_IF_ARADDR[26] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[27] on net HW_Boot_Engine_0_AXI_IF_ARADDR[27] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[28] on net HW_Boot_Engine_0_AXI_IF_ARADDR[28] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[29] on net HW_Boot_Engine_0_AXI_IF_ARADDR[29] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[30] on net HW_Boot_Engine_0_AXI_IF_ARADDR[30] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARADDR_t[31] on net HW_Boot_Engine_0_AXI_IF_ARADDR[31] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARBURST_t[0] on net HW_Boot_Engine_0_AXI_IF_ARBURST[0] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARBURST_t[1] on net HW_Boot_Engine_0_AXI_IF_ARBURST[1] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARID_t[0] on net HW_Boot_Engine_0_AXI_IF_ARID[0] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARID_t[1] on net HW_Boot_Engine_0_AXI_IF_ARID[1] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARID_t[2] on net HW_Boot_Engine_0_AXI_IF_ARID[2] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARID_t[3] on net HW_Boot_Engine_0_AXI_IF_ARID[3] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARLEN_t[0] on net HW_Boot_Engine_0_AXI_IF_ARLEN[0] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARLEN_t[1] on net HW_Boot_Engine_0_AXI_IF_ARLEN[1] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARLEN_t[2] on net HW_Boot_Engine_0_AXI_IF_ARLEN[2] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARLEN_t[3] on net HW_Boot_Engine_0_AXI_IF_ARLEN[3] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARLOCK_t[0] on net HW_Boot_Engine_0_AXI_IF_ARLOCK[0] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARLOCK_t[1] on net HW_Boot_Engine_0_AXI_IF_ARLOCK[1] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARSIZE_t[0] on net HW_Boot_Engine_0_AXI_IF_ARSIZE[0] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARSIZE_t[1] on net HW_Boot_Engine_0_AXI_IF_ARSIZE[1] has its enable tied to GND (module CodeShadowing_Fabric) @W:MO111 : | Tristate driver HW_Boot_Engine_0_AXI_IF_ARVALID_t on net HW_Boot_Engine_0_AXI_IF_ARVALID has its enable tied to GND (module CodeShadowing_Fabric) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB) Encoding state machine CORECONFIGP_0.state[2:0] (view:work.CodeShadowing_Fabric(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[16] of view:PrimLib.dffr(prim) in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[17] of view:PrimLib.dffr(prim) in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[18] of view:PrimLib.dffr(prim) in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[19] of view:PrimLib.dffr(prim) in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[20] of view:PrimLib.dffr(prim) in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[21] of view:PrimLib.dffr(prim) in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[22] of view:PrimLib.dffr(prim) in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[23] of view:PrimLib.dffr(prim) in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[24] of view:PrimLib.dffr(prim) in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[25] of view:PrimLib.dffr(prim) in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[26] of view:PrimLib.dffr(prim) in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[27] of view:PrimLib.dffr(prim) in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[28] of view:PrimLib.dffr(prim) in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[29] of view:PrimLib.dffr(prim) in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[30] of view:PrimLib.dffr(prim) in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[31] of view:PrimLib.dffr(prim) in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.paddr[11] of view:PrimLib.dffr(prim) in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] of view:PrimLib.dffr(prim) in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[16] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[0] is always 0, optimizing ... @W:MO160 : coreconfigp.v(255) | Register bit CORECONFIGP_0.paddr[16] is always 0, optimizing ... @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.paddr[14] of view:PrimLib.dffr(prim) in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_4.masterDataInProg[3] of view:PrimLib.dffr(prim) in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_4.masterDataInProg[2] of view:PrimLib.dffr(prim) in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_4.masterDataInProg[1] of view:PrimLib.dffr(prim) in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @W:BN132 : coreahblite_masterstage.v(163) | Removing instance CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[1], because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_0.regHTRANS @W:BN132 : coreahblite_masterstage.v(163) | Removing instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[31], because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28] @W:BN132 : coreahblite_masterstage.v(163) | Removing instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[29], because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28] Encoding state machine arbRegSMCurrentState[15:0] (view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_1(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[12] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[8] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[4] is always 0, optimizing ... Encoding state machine ahb_fsm_current_state[6:0] (view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 @N:BN362 : ahb_if.v(80) | Removing sequential instance DATAOUT[9] of view:PrimLib.dffr(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7(verilog) because there are no references to its outputs @N:BN362 : ahb_if.v(80) | Removing sequential instance DATAOUT[10] of view:PrimLib.dffr(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7(verilog) because there are no references to its outputs @N:BN362 : ahb_if.v(80) | Removing sequential instance DATAOUT[11] of view:PrimLib.dffr(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7(verilog) because there are no references to its outputs @N:BN362 : ahb_if.v(80) | Removing sequential instance DATAOUT[12] of view:PrimLib.dffr(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7(verilog) because there are no references to its outputs @N:BN362 : ahb_if.v(80) | Removing sequential instance DATAOUT[13] of view:PrimLib.dffr(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7(verilog) because there are no references to its outputs @N:BN362 : ahb_if.v(80) | Removing sequential instance DATAOUT[14] of view:PrimLib.dffr(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7(verilog) because there are no references to its outputs @N:BN362 : ahb_if.v(80) | Removing sequential instance DATAOUT[15] of view:PrimLib.dffr(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7(verilog) because there are no references to its outputs @N:BN362 : ahb_if.v(80) | Removing sequential instance DATAOUT[16] of view:PrimLib.dffr(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7(verilog) because there are no references to its outputs @N:BN362 : ahb_if.v(80) | Removing sequential instance DATAOUT[17] of view:PrimLib.dffr(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7(verilog) because there are no references to its outputs @N:BN362 : ahb_if.v(80) | Removing sequential instance DATAOUT[18] of view:PrimLib.dffr(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7(verilog) because there are no references to its outputs @N:BN362 : ahb_if.v(80) | Removing sequential instance DATAOUT[19] of view:PrimLib.dffr(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7(verilog) because there are no references to its outputs @N:BN362 : ahb_if.v(80) | Removing sequential instance DATAOUT[20] of view:PrimLib.dffr(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7(verilog) because there are no references to its outputs @N:BN362 : ahb_if.v(80) | Removing sequential instance DATAOUT[21] of view:PrimLib.dffr(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7(verilog) because there are no references to its outputs @N:BN362 : ahb_if.v(80) | Removing sequential instance DATAOUT[22] of view:PrimLib.dffr(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7(verilog) because there are no references to its outputs @N:BN362 : ahb_if.v(80) | Removing sequential instance DATAOUT[23] of view:PrimLib.dffr(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7(verilog) because there are no references to its outputs @N:BN362 : ahb_if.v(80) | Removing sequential instance DATAOUT[24] of view:PrimLib.dffr(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7(verilog) because there are no references to its outputs @N:BN362 : ahb_if.v(80) | Removing sequential instance DATAOUT[25] of view:PrimLib.dffr(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7(verilog) because there are no references to its outputs @N:BN362 : ahb_if.v(80) | Removing sequential instance DATAOUT[26] of view:PrimLib.dffr(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7(verilog) because there are no references to its outputs @N:BN362 : ahb_if.v(80) | Removing sequential instance DATAOUT[27] of view:PrimLib.dffr(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7(verilog) because there are no references to its outputs @N:BN362 : ahb_if.v(80) | Removing sequential instance DATAOUT[28] of view:PrimLib.dffr(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7(verilog) because there are no references to its outputs @N:BN362 : ahb_if.v(80) | Removing sequential instance DATAOUT[29] of view:PrimLib.dffr(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7(verilog) because there are no references to its outputs @N:BN362 : ahb_if.v(80) | Removing sequential instance DATAOUT[30] of view:PrimLib.dffr(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7(verilog) because there are no references to its outputs @N:BN362 : ahb_if.v(80) | Removing sequential instance DATAOUT[31] of view:PrimLib.dffr(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7(verilog) because there are no references to its outputs @W:MO160 : ahb_if.v(80) | Register bit HWDATA_int[31] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA_int[30] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA_int[28] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA_int[27] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA_int[26] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA_int[23] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA_int[22] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA_int[21] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA_int[20] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA_int[19] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA_int[17] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA_int[16] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA_int[15] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA_int[14] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA_int[13] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA_int[12] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA_int[11] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA_int[9] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA_int[8] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR_int[31] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR_int[29] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR_int[28] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR_int[27] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR_int[26] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR_int[25] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR_int[24] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR_int[23] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR_int[22] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR_int[21] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR_int[20] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR_int[19] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR_int[18] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR_int[14] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR_int[13] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR_int[11] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR_int[10] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR_int[9] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR_int[8] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR_int[7] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR_int[6] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR_int[5] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR_int[1] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR_int[0] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA[31] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA[30] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA[28] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA[27] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA[26] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA[23] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA[22] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA[21] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA[20] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA[19] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA[17] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA[16] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA[15] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA[14] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA[13] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA[12] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA[11] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA[9] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HWDATA[8] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR[31] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR[29] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR[28] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR[27] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR[26] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR[25] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR[24] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR[23] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR[22] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR[21] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR[20] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR[19] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR[18] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR[14] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR[13] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR[11] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR[10] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR[9] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR[8] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR[7] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR[6] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR[5] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR[1] is always 0, optimizing ... @W:MO160 : ahb_if.v(80) | Register bit HADDR[0] is always 0, optimizing ... Encoding state machine axi_fsm_current_state[4:0] (view:work.AXI_IF_0s_1s_2s_3s_4294967292s(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 Encoding state machine apb_fsm_current_state[6:0] (view:work.MDDR_Config_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_Z8(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 @N: : mddr_config.v(174) | Found counter in view:work.MDDR_Config_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_Z8(verilog) inst PADDR_int[15:2] @N: : mddr_config.v(174) | Found counter in view:work.MDDR_Config_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_Z8(verilog) inst count_delay[11:0] @N: : mddr_config.v(174) | Found counter in view:work.MDDR_Config_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_Z8(verilog) inst i[6:0] Encoding state machine SPI_current_state[14:0] (view:work.SPI_to_MDDR_Z9(verilog)) original code -> new code 0000 -> 000000000000001 0001 -> 000000000000010 0010 -> 000000000000100 0011 -> 000000000001000 0100 -> 000000000010000 0101 -> 000000000100000 0110 -> 000000001000000 0111 -> 000000010000000 1000 -> 000000100000000 1001 -> 000001000000000 1010 -> 000010000000000 1011 -> 000100000000000 1100 -> 001000000000000 1101 -> 010000000000000 1111 -> 100000000000000 @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[31:24] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[15:8] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[39:32] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[47:40] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[55:48] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[63:56] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[31:24] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[23:16] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[39:32] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[47:40] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[55:48] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[63:56] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[39:32] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[31:24] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[47:40] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[55:48] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[63:56] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[23:16] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[31:24] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[39:32] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[47:40] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[55:48] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[63:56] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[23:16] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[31:24] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[47:40] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[39:32] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[55:48] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[63:56] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[23:16] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[31:24] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[55:48] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[39:32] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[47:40] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[63:56] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[23:16] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[31:24] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[63:56] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[39:32] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[47:40] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[55:48] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[23:16] with specified coding style. Inferring block RAM. @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[63:56] with specified coding style. Inferring block RAM. @W:FX107 : spi_to_mddr.v(77) | No read/write conflict check. Possible simulation mismatch! @N:MF707 : spi_to_mddr.v(77) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for read_byte[63:56] (view:work.SPI_to_MDDR_Z9(verilog)). @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[55:48] with specified coding style. Inferring block RAM. @W:FX107 : spi_to_mddr.v(77) | No read/write conflict check. Possible simulation mismatch! @N:MF707 : spi_to_mddr.v(77) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for read_byte[55:48] (view:work.SPI_to_MDDR_Z9(verilog)). @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[47:40] with specified coding style. Inferring block RAM. @W:FX107 : spi_to_mddr.v(77) | No read/write conflict check. Possible simulation mismatch! @N:MF707 : spi_to_mddr.v(77) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for read_byte[47:40] (view:work.SPI_to_MDDR_Z9(verilog)). @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[39:32] with specified coding style. Inferring block RAM. @W:FX107 : spi_to_mddr.v(77) | No read/write conflict check. Possible simulation mismatch! @N:MF707 : spi_to_mddr.v(77) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for read_byte[39:32] (view:work.SPI_to_MDDR_Z9(verilog)). @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[31:24] with specified coding style. Inferring block RAM. @W:FX107 : spi_to_mddr.v(77) | No read/write conflict check. Possible simulation mismatch! @N:MF707 : spi_to_mddr.v(77) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for read_byte[31:24] (view:work.SPI_to_MDDR_Z9(verilog)). @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[23:16] with specified coding style. Inferring block RAM. @W:FX107 : spi_to_mddr.v(77) | No read/write conflict check. Possible simulation mismatch! @N:MF707 : spi_to_mddr.v(77) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for read_byte[23:16] (view:work.SPI_to_MDDR_Z9(verilog)). @N:FX403 : spi_to_mddr.v(77) | Property "block_ram" or "no_rw_check" found for RAM read_byte[15:8] with specified coding style. Inferring block RAM. @W:FX107 : spi_to_mddr.v(77) | No read/write conflict check. Possible simulation mismatch! @N:MF707 : spi_to_mddr.v(77) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for read_byte[15:8] (view:work.SPI_to_MDDR_Z9(verilog)). @W:BN132 : spi_to_mddr.v(77) | Removing sequential instance HW_Boot_Engine_0.SPI_to_MDDR_0.AXI_DATA_rst_6, because it is equivalent to instance HW_Boot_Engine_0.SPI_to_MDDR_0.AXI_DATA_rst_5 @W:BN132 : spi_to_mddr.v(77) | Removing sequential instance HW_Boot_Engine_0.SPI_to_MDDR_0.AXI_DATA_rst_5, because it is equivalent to instance HW_Boot_Engine_0.SPI_to_MDDR_0.AXI_DATA_rst_4 @W:BN132 : spi_to_mddr.v(77) | Removing sequential instance HW_Boot_Engine_0.SPI_to_MDDR_0.AXI_DATA_rst_4, because it is equivalent to instance HW_Boot_Engine_0.SPI_to_MDDR_0.AXI_DATA_rst_3 @W:BN132 : spi_to_mddr.v(77) | Removing sequential instance HW_Boot_Engine_0.SPI_to_MDDR_0.AXI_DATA_rst_3, because it is equivalent to instance HW_Boot_Engine_0.SPI_to_MDDR_0.AXI_DATA_rst_2 @W:BN132 : spi_to_mddr.v(77) | Removing sequential instance HW_Boot_Engine_0.SPI_to_MDDR_0.AXI_DATA_rst_2, because it is equivalent to instance HW_Boot_Engine_0.SPI_to_MDDR_0.AXI_DATA_rst_1 @W:BN132 : spi_to_mddr.v(77) | Removing sequential instance HW_Boot_Engine_0.SPI_to_MDDR_0.AXI_DATA_rst_1, because it is equivalent to instance HW_Boot_Engine_0.SPI_to_MDDR_0.AXI_DATA_rst_0 @W:BN132 : spi_to_mddr.v(77) | Removing sequential instance HW_Boot_Engine_0.SPI_to_MDDR_0.AXI_DATA_rst_0, because it is equivalent to instance HW_Boot_Engine_0.SPI_to_MDDR_0.AXI_DATA_rst @N: : spi_to_mddr.v(77) | Found counter in view:work.SPI_to_MDDR_Z9(verilog) inst nblocks[7:0] @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[0] in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_4.slave_arbiter.arbRegSMCurrentState[14] in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_4.slave_arbiter.arbRegSMCurrentState[15] in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_4.slave_arbiter.arbRegSMCurrentState[2] in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_4.slave_arbiter.arbRegSMCurrentState[3] in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_4.slave_arbiter.arbRegSMCurrentState[6] in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_4.slave_arbiter.arbRegSMCurrentState[7] in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_4.slave_arbiter.arbRegSMCurrentState[10] in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_4.slave_arbiter.arbRegSMCurrentState[11] in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(229) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[10] in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB) @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_4.slave_arbiter.arbRegSMCurrentState[5] in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 145MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 145MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB) Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 145MB) Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 164MB peak: 166MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:01s 1.72ns 649 / 516 @N:BN362 : | Removing sequential instance HW_Boot_Engine_0.SPI_to_MDDR_0.read_byte_4_read_byte_0_0_en in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance HW_Boot_Engine_0.SPI_to_MDDR_0.read_byte_3_read_byte_0_0_en in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance HW_Boot_Engine_0.SPI_to_MDDR_0.read_byte_2_read_byte_0_0_en in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance HW_Boot_Engine_0.SPI_to_MDDR_0.read_byte_1_read_byte_0_0_en in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance HW_Boot_Engine_0.SPI_to_MDDR_0.read_byte_0_read_byte_0_0_en in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance HW_Boot_Engine_0.SPI_to_MDDR_0.read_byte_read_byte_0_0_en in hierarchy view:work.CodeShadowing_Fabric(verilog) because there are no references to its outputs @N:FP130 : | Promoting Net MSS_HPMS_READY on CLKINT I_313 @N:FP130 : | Promoting Net HW_Boot_Engine_0.MDDR_Config_0_DRAM_Ready on CLKINT I_314 @N:FP130 : | Promoting Net CORECONFIGP_0_APB_S_PCLK on CLKINT I_315 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 164MB peak: 166MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 164MB peak: 166MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 1 non-gated/non-generated clock tree(s) driving 438 clock pin(s) of sequential element(s) 1 gated/generated clock tree(s) driving 94 clock pin(s) of sequential element(s) 0 instances converted, 94 sequential instances remain driven by gated/generated clocks =================================== Non-Gated/Non-Generated Clocks ==================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ------------------------------------------------------------------------------------------------------- ClockId0002 CCC_0.GL0_INST CLKINT 438 CORERESETP_0.MSS_HPMS_READY_int ======================================================================================================= ========================================================================================= Gated/Generated Clocks ========================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 CodeShadowing_Fabric_MSS_0.MSS_ADLIB_INST MSS_075 94 CodeShadowing_Fabric_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_075 =========================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 133MB peak: 166MB) Writing Analyst data base D:\DG0669\SF2_CodeShadowing_LPDDR_DF\Libero\HWBootEngine_method\CodeShadowing_Fabric\synthesis\synwork\CodeShadowing_Fabric_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 162MB peak: 166MB) Writing EDIF Netlist and constraint files @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF J-2015.03M-SP1-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 163MB peak: 166MB) Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 162MB peak: 166MB) @W:MT246 : codeshadowing_fabric_ccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:CodeShadowing_Fabric_MSS_0.FIC_2_APB_M_PCLK" @W:MT420 : | Found inferred clock CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:CCC_0.GL0_net" @S |##### START OF TIMING REPORT #####[ # Timing Report written on Wed Mar 23 11:55:21 2016 # Top view: CodeShadowing_Fabric Requested Frequency: 100.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 2.545 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------------------------------------------------------- CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 134.5 MHz 10.000 7.437 2.563 inferred Inferred_clkgroup_0 CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 165.1 MHz 10.000 6.055 2.545 inferred Inferred_clkgroup_1 System 100.0 MHz 1029.4 MHz 10.000 0.971 9.029 system system_clkgroup ================================================================================================================================================================ Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 10.000 9.029 | No paths - | No paths - | No paths - CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock | 10.000 2.563 | No paths - | No paths - | No paths - CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock | 10.000 3.945 | No paths - | 5.000 3.662 | 5.000 2.545 ========================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CodeShadowing_Fabric_MSS_0.MSS_ADLIB_INST CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_FM0_READYOUT CoreAHBLite_0_AHBmslave4_HREADY 3.469 2.563 CodeShadowing_Fabric_MSS_0.MSS_ADLIB_INST CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_AWREADY_HREADYOUT0 HW_Boot_Engine_0_AXI_IF_AWREADY 3.980 3.299 CodeShadowing_Fabric_MSS_0.MSS_ADLIB_INST CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_BVALID HW_Boot_Engine_0_AXI_IF_BVALID 3.457 3.764 HW_Boot_Engine_0.AHB_IF_0.AHB_BUSY CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock SLE Q AHB_IF_0_AHB_BUSY 0.076 4.060 HW_Boot_Engine_0.SPI_to_MDDR_0.SPI_current_state[11] CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SPI_current_state[11] 0.094 4.168 HW_Boot_Engine_0.SPI_to_MDDR_0.SPI_current_state[10] CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SPI_current_state[10] 0.094 4.178 HW_Boot_Engine_0.SPI_to_MDDR_0.SPI_current_state[9] CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SPI_current_state[9] 0.076 4.266 HW_Boot_Engine_0.SPI_to_MDDR_0.SPI_current_state[7] CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SPI_current_state[7] 0.076 4.479 CoreAHBLite_0.matrix4x16.masterstage_0.masterRegAddrSel CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock SLE Q masterRegAddrSel 0.094 4.500 CoreAHBLite_0.matrix4x16.masterstage_0.regHTRANS CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock SLE Q regHTRANS 0.094 4.550 ================================================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ CoreAHBLite_0.matrix4x16.masterstage_0.masterRegAddrSel CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock SLE D d_masterRegAddrSel 9.778 2.563 CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[2] CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock SLE EN masterAddrClockEnable 9.707 2.849 CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[3] CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock SLE EN masterAddrClockEnable 9.707 2.849 CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[4] CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock SLE EN masterAddrClockEnable 9.707 2.849 CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[12] CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock SLE EN masterAddrClockEnable 9.707 2.849 CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[15] CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock SLE EN masterAddrClockEnable 9.707 2.849 CoreAHBLite_0.matrix4x16.masterstage_0.regHTRANS CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock SLE EN masterAddrClockEnable 9.707 2.849 CoreAHBLite_0.matrix4x16.masterstage_0.regHWRITE CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock SLE EN masterAddrClockEnable 9.707 2.849 HW_Boot_Engine_0.AHB_IF_0.HADDR[12] CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock SLE D HADDR_9[12] 9.778 3.033 HW_Boot_Engine_0.AXI_IF_0.axi_fsm_current_state[3] CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock SLE D axi_fsm_current_state_ns[3] 9.778 3.299 ========================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 7.215 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 2.563 Number of logic level(s): 4 Starting point: CodeShadowing_Fabric_MSS_0.MSS_ADLIB_INST / F_FM0_READYOUT Ending point: CoreAHBLite_0.matrix4x16.masterstage_0.masterRegAddrSel / D The start point is clocked by CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE The end point is clocked by CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------- CodeShadowing_Fabric_MSS_0.MSS_ADLIB_INST MSS_075 F_FM0_READYOUT Out 3.469 3.469 - CoreAHBLite_0_AHBmslave4_HREADY Net - - 0.989 - 11 CoreAHBLite_0.matrix4x16.masterstage_0.masterAddrClockEnable_0_a2_2 CFG4 C In - 4.458 - CoreAHBLite_0.matrix4x16.masterstage_0.masterAddrClockEnable_0_a2_2 CFG4 Y Out 0.194 4.652 - N_142 Net - - 0.483 - 1 CoreAHBLite_0.matrix4x16.masterstage_0.masterAddrClockEnable_0_a2 CFG4 B In - 5.135 - CoreAHBLite_0.matrix4x16.masterstage_0.masterAddrClockEnable_0_a2 CFG4 Y Out 0.143 5.278 - N_138 Net - - 0.483 - 1 CoreAHBLite_0.matrix4x16.masterstage_0.masterAddrClockEnable_0 CFG4 D In - 5.761 - CoreAHBLite_0.matrix4x16.masterstage_0.masterAddrClockEnable_0 CFG4 Y Out 0.236 5.997 - masterAddrClockEnable Net - - 0.843 - 8 CoreAHBLite_0.matrix4x16.masterstage_0.d_masterRegAddrSel_0 CFG4 D In - 6.841 - CoreAHBLite_0.matrix4x16.masterstage_0.d_masterRegAddrSel_0 CFG4 Y Out 0.236 7.077 - d_masterRegAddrSel Net - - 0.138 - 1 CoreAHBLite_0.matrix4x16.masterstage_0.masterRegAddrSel SLE D In - 7.215 - =============================================================================================================================================== Total path delay (propagation time + setup) of 7.437 is 4.500(60.5%) logic and 2.937(39.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORECONFIGP_0.psel CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q psel 0.094 2.545 CORECONFIGP_0.state[1] CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q state[1] 0.076 3.662 CORECONFIGP_0.paddr[13] CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q paddr[13] 0.094 3.684 CORECONFIGP_0.state[0] CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q state[0] 0.076 3.745 CORECONFIGP_0.paddr[15] CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q paddr[15] 0.094 3.765 CORECONFIGP_0.paddr[12] CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q paddr[12] 0.094 3.873 CORECONFIGP_0.MDDR_PENABLE CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q CORECONFIGP_0_MDDR_APBmslave_PENABLE 0.094 3.906 CodeShadowing_Fabric_MSS_0.MSS_ADLIB_INST CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_075 MDDR_FABRIC_PREADY CORECONFIGP_0_MDDR_APBmslave_PREADY 4.525 3.945 HW_Boot_Engine_0.MDDR_Config_0.i[1] CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q i[1] 0.076 4.908 HW_Boot_Engine_0.MDDR_Config_0.i[2] CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q i[2] 0.076 4.932 ======================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CodeShadowing_Fabric_MSS_0.MSS_ADLIB_INST CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_075 MDDR_FABRIC_PSEL N_4 4.270 2.545 CORECONFIGP_0.FIC_2_APB_M_PREADY CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN N_771_i_0 4.707 2.665 CORECONFIGP_0.state[1] CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D state_ns[1] 4.778 2.697 CORECONFIGP_0.MDDR_PENABLE CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D N_769_i_0 4.778 3.662 CORECONFIGP_0.psel CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D state_187_d_i_0 4.778 3.738 CodeShadowing_Fabric_MSS_0.MSS_ADLIB_INST CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_075 MDDR_FABRIC_PENABLE CORECONFIGP_0_MDDR_APBmslave_PENABLE 4.972 3.906 HW_Boot_Engine_0.MDDR_Config_0.PWDATA[0] CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN N_463_i_0 9.707 4.908 HW_Boot_Engine_0.MDDR_Config_0.PWDATA[1] CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN N_463_i_0 9.707 4.908 HW_Boot_Engine_0.MDDR_Config_0.PWDATA[2] CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN N_463_i_0 9.707 4.908 HW_Boot_Engine_0.MDDR_Config_0.PWDATA[3] CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN N_463_i_0 9.707 4.908 ========================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.000 - Setup time: 0.730 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.270 - Propagation time: 1.725 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 2.545 Number of logic level(s): 1 Starting point: CORECONFIGP_0.psel / Q Ending point: CodeShadowing_Fabric_MSS_0.MSS_ADLIB_INST / MDDR_FABRIC_PSEL The start point is clocked by CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock [falling] on pin CLK The end point is clocked by CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock [rising] on pin CLK_MDDR_APB Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------- CORECONFIGP_0.psel SLE Q Out 0.094 0.094 - psel Net - - 0.509 - 1 CORECONFIGP_0.MDDR_PSEL_i CFG4 B In - 0.603 - CORECONFIGP_0.MDDR_PSEL_i CFG4 Y Out 0.143 0.746 - N_4 Net - - 0.980 - 3 CodeShadowing_Fabric_MSS_0.MSS_ADLIB_INST MSS_075 MDDR_FABRIC_PSEL In - 1.725 - ======================================================================================================================= Total path delay (propagation time + setup) of 2.455 is 0.967(39.4%) logic and 1.488(60.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------- FABOSC_0.I_RCOSC_25_50MHZ System RCOSC_25_50MHZ CLKOUT FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC 0.000 9.029 ================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------- CCC_0.CCC_INST System CCC RCOSC_25_50MHZ FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC 10.000 9.029 ====================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 10.000 - Propagation time: 0.971 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 9.029 Number of logic level(s): 0 Starting point: FABOSC_0.I_RCOSC_25_50MHZ / CLKOUT Ending point: CCC_0.CCC_INST / RCOSC_25_50MHZ The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------- FABOSC_0.I_RCOSC_25_50MHZ RCOSC_25_50MHZ CLKOUT Out 0.000 0.000 - FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC Net - - 0.971 - 1 CCC_0.CCC_INST CCC RCOSC_25_50MHZ In - 0.971 - ===================================================================================================================================== Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 162MB peak: 166MB) Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 162MB peak: 166MB) --------------------------------------- Resource Usage Report for CodeShadowing_Fabric Mapping to part: m2s090tsfbga484-1 Cell usage: CCC 1 use CLKINT 4 uses MSS_075 1 use RCOSC_25_50MHZ 1 use SYSRESET 1 use CFG1 7 uses CFG2 82 uses CFG3 121 uses CFG4 235 uses Carry primitives used for arithmetic functions: ARI1 170 uses Sequential Cells: SLE 516 uses DSP Blocks: 0 I/O ports: 68 I/O primitives: 66 BIBUF 22 uses INBUF 6 uses OUTBUF 35 uses OUTBUF_DIFF 1 use TRIBUFF 2 uses Global Clock Buffers: 4 RAM/ROM usage summary Block Rams (RAM1K18) : 7 Total LUTs: 615 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 252; LUTs = 252; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 516 + 0 + 252 + 0 = 768; Total number of LUTs after P&R: 615 + 0 + 252 + 0 = 867; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 52MB peak: 166MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime # Wed Mar 23 11:55:21 2016 ###########################################################]