`timescale 1 ns/100 ps
// Version: v11.4 11.4.0.112


module MSS_120(
       CAN_RXBUS_MGPIO3A_H2F_A,
       CAN_RXBUS_MGPIO3A_H2F_B,
       CAN_TX_EBL_MGPIO4A_H2F_A,
       CAN_TX_EBL_MGPIO4A_H2F_B,
       CAN_TXBUS_MGPIO2A_H2F_A,
       CAN_TXBUS_MGPIO2A_H2F_B,
       CLK_CONFIG_APB,
       COMMS_INT,
       CONFIG_PRESET_N,
       EDAC_ERROR,
       F_FM0_RDATA,
       F_FM0_READYOUT,
       F_FM0_RESP,
       F_FM1_RDATA,
       F_FM1_READYOUT,
       F_FM1_RESP,
       F_HM0_ADDR,
       F_HM0_ENABLE,
       F_HM0_SEL,
       F_HM0_SIZE,
       F_HM0_TRANS1,
       F_HM0_WDATA,
       F_HM0_WRITE,
       F_HM1_ADDR,
       F_HM1_ENABLE,
       F_HM1_SEL,
       F_HM1_SIZE,
       F_HM1_TRANS1,
       F_HM1_WDATA,
       F_HM1_WRITE,
       FAB_CHRGVBUS,
       FAB_DISCHRGVBUS,
       FAB_DMPULLDOWN,
       FAB_DPPULLDOWN,
       FAB_DRVVBUS,
       FAB_IDPULLUP,
       FAB_OPMODE,
       FAB_SUSPENDM,
       FAB_TERMSEL,
       FAB_TXVALID,
       FAB_VCONTROL,
       FAB_VCONTROLLOADM,
       FAB_XCVRSEL,
       FAB_XDATAOUT,
       FACC_GLMUX_SEL,
       FIC32_0_MASTER,
       FIC32_1_MASTER,
       FPGA_RESET_N,
       GTX_CLK,
       H2F_INTERRUPT,
       H2F_NMI,
       H2FCALIB,
       I2C0_SCL_MGPIO31B_H2F_A,
       I2C0_SCL_MGPIO31B_H2F_B,
       I2C0_SDA_MGPIO30B_H2F_A,
       I2C0_SDA_MGPIO30B_H2F_B,
       I2C1_SCL_MGPIO1A_H2F_A,
       I2C1_SCL_MGPIO1A_H2F_B,
       I2C1_SDA_MGPIO0A_H2F_A,
       I2C1_SDA_MGPIO0A_H2F_B,
       MDCF,
       MDOENF,
       MDOF,
       MMUART0_CTS_MGPIO19B_H2F_A,
       MMUART0_CTS_MGPIO19B_H2F_B,
       MMUART0_DCD_MGPIO22B_H2F_A,
       MMUART0_DCD_MGPIO22B_H2F_B,
       MMUART0_DSR_MGPIO20B_H2F_A,
       MMUART0_DSR_MGPIO20B_H2F_B,
       MMUART0_DTR_MGPIO18B_H2F_A,
       MMUART0_DTR_MGPIO18B_H2F_B,
       MMUART0_RI_MGPIO21B_H2F_A,
       MMUART0_RI_MGPIO21B_H2F_B,
       MMUART0_RTS_MGPIO17B_H2F_A,
       MMUART0_RTS_MGPIO17B_H2F_B,
       MMUART0_RXD_MGPIO28B_H2F_A,
       MMUART0_RXD_MGPIO28B_H2F_B,
       MMUART0_SCK_MGPIO29B_H2F_A,
       MMUART0_SCK_MGPIO29B_H2F_B,
       MMUART0_TXD_MGPIO27B_H2F_A,
       MMUART0_TXD_MGPIO27B_H2F_B,
       MMUART1_DTR_MGPIO12B_H2F_A,
       MMUART1_RTS_MGPIO11B_H2F_A,
       MMUART1_RTS_MGPIO11B_H2F_B,
       MMUART1_RXD_MGPIO26B_H2F_A,
       MMUART1_RXD_MGPIO26B_H2F_B,
       MMUART1_SCK_MGPIO25B_H2F_A,
       MMUART1_SCK_MGPIO25B_H2F_B,
       MMUART1_TXD_MGPIO24B_H2F_A,
       MMUART1_TXD_MGPIO24B_H2F_B,
       MPLL_LOCK,
       PER2_FABRIC_PADDR,
       PER2_FABRIC_PENABLE,
       PER2_FABRIC_PSEL,
       PER2_FABRIC_PWDATA,
       PER2_FABRIC_PWRITE,
       RTC_MATCH,
       SLEEPDEEP,
       SLEEPHOLDACK,
       SLEEPING,
       SMBALERT_NO0,
       SMBALERT_NO1,
       SMBSUS_NO0,
       SMBSUS_NO1,
       SPI0_CLK_OUT,
       SPI0_SDI_MGPIO5A_H2F_A,
       SPI0_SDI_MGPIO5A_H2F_B,
       SPI0_SDO_MGPIO6A_H2F_A,
       SPI0_SDO_MGPIO6A_H2F_B,
       SPI0_SS0_MGPIO7A_H2F_A,
       SPI0_SS0_MGPIO7A_H2F_B,
       SPI0_SS1_MGPIO8A_H2F_A,
       SPI0_SS1_MGPIO8A_H2F_B,
       SPI0_SS2_MGPIO9A_H2F_A,
       SPI0_SS2_MGPIO9A_H2F_B,
       SPI0_SS3_MGPIO10A_H2F_A,
       SPI0_SS3_MGPIO10A_H2F_B,
       SPI0_SS4_MGPIO19A_H2F_A,
       SPI0_SS5_MGPIO20A_H2F_A,
       SPI0_SS6_MGPIO21A_H2F_A,
       SPI0_SS7_MGPIO22A_H2F_A,
       SPI1_CLK_OUT,
       SPI1_SDI_MGPIO11A_H2F_A,
       SPI1_SDI_MGPIO11A_H2F_B,
       SPI1_SDO_MGPIO12A_H2F_A,
       SPI1_SDO_MGPIO12A_H2F_B,
       SPI1_SS0_MGPIO13A_H2F_A,
       SPI1_SS0_MGPIO13A_H2F_B,
       SPI1_SS1_MGPIO14A_H2F_A,
       SPI1_SS1_MGPIO14A_H2F_B,
       SPI1_SS2_MGPIO15A_H2F_A,
       SPI1_SS2_MGPIO15A_H2F_B,
       SPI1_SS3_MGPIO16A_H2F_A,
       SPI1_SS3_MGPIO16A_H2F_B,
       SPI1_SS4_MGPIO17A_H2F_A,
       SPI1_SS5_MGPIO18A_H2F_A,
       SPI1_SS6_MGPIO23A_H2F_A,
       SPI1_SS7_MGPIO24A_H2F_A,
       TCGF,
       TRACECLK,
       TRACEDATA,
       TX_CLK,
       TX_ENF,
       TX_ERRF,
       TXCTL_EN_RIF,
       TXD_RIF,
       TXDF,
       TXEV,
       WDOGTIMEOUT,
       F_ARREADY_HREADYOUT1,
       F_AWREADY_HREADYOUT0,
       F_BID,
       F_BRESP_HRESP0,
       F_BVALID,
       F_RDATA_HRDATA01,
       F_RID,
       F_RLAST,
       F_RRESP_HRESP1,
       F_RVALID,
       F_WREADY,
       MDDR_FABRIC_PRDATA,
       MDDR_FABRIC_PREADY,
       MDDR_FABRIC_PSLVERR,
       REV_ARADDR,
       REV_ARBURST,
       REV_ARID,
       REV_ARLEN,
       REV_ARLOCK,
       REV_ARSIZE,
       REV_AWADDR,
       REV_AWLOCK,
       REV_AWSIZE,
       REV_RREADY,
       REV_WID,
       REV_WSTRB,
       CAN_RXBUS_F2H_SCP,
       CAN_TX_EBL_F2H_SCP,
       CAN_TXBUS_F2H_SCP,
       CLK_BASE,
       COLF,
       CRSF,
       F2_DMAREADY,
       F2H_INTERRUPT,
       F2HCALIB,
       F_DMAREADY,
       F_FM0_ADDR,
       F_FM0_ENABLE,
       F_FM0_MASTLOCK,
       F_FM0_READY,
       F_FM0_SEL,
       F_FM0_SIZE,
       F_FM0_TRANS1,
       F_FM0_WDATA,
       F_FM0_WRITE,
       F_FM1_ADDR,
       F_FM1_ENABLE,
       F_FM1_MASTLOCK,
       F_FM1_READY,
       F_FM1_SEL,
       F_FM1_SIZE,
       F_FM1_TRANS1,
       F_FM1_WDATA,
       F_FM1_WRITE,
       F_HM0_RDATA,
       F_HM0_READY,
       F_HM0_RESP,
       F_HM1_RDATA,
       F_HM1_READY,
       F_HM1_RESP,
       FAB_AVALID,
       FAB_HOSTDISCON,
       FAB_IDDIG,
       FAB_LINESTATE,
       FAB_M3_RESET_N,
       FAB_PLL_LOCK,
       FAB_RXACTIVE,
       FAB_RXERROR,
       FAB_RXVALID,
       FAB_RXVALIDH,
       FAB_SESSEND,
       FAB_TXREADY,
       FAB_VBUSVALID,
       FAB_VSTATUS,
       FAB_XDATAIN,
       GTX_CLKPF,
       I2C0_BCLK,
       I2C0_SCL_F2H_SCP,
       I2C0_SDA_F2H_SCP,
       I2C1_BCLK,
       I2C1_SCL_F2H_SCP,
       I2C1_SDA_F2H_SCP,
       MDIF,
       MGPIO0A_F2H_GPIN,
       MGPIO10A_F2H_GPIN,
       MGPIO11A_F2H_GPIN,
       MGPIO11B_F2H_GPIN,
       MGPIO12A_F2H_GPIN,
       MGPIO13A_F2H_GPIN,
       MGPIO14A_F2H_GPIN,
       MGPIO15A_F2H_GPIN,
       MGPIO16A_F2H_GPIN,
       MGPIO17B_F2H_GPIN,
       MGPIO18B_F2H_GPIN,
       MGPIO19B_F2H_GPIN,
       MGPIO1A_F2H_GPIN,
       MGPIO20B_F2H_GPIN,
       MGPIO21B_F2H_GPIN,
       MGPIO22B_F2H_GPIN,
       MGPIO24B_F2H_GPIN,
       MGPIO25B_F2H_GPIN,
       MGPIO26B_F2H_GPIN,
       MGPIO27B_F2H_GPIN,
       MGPIO28B_F2H_GPIN,
       MGPIO29B_F2H_GPIN,
       MGPIO2A_F2H_GPIN,
       MGPIO30B_F2H_GPIN,
       MGPIO31B_F2H_GPIN,
       MGPIO3A_F2H_GPIN,
       MGPIO4A_F2H_GPIN,
       MGPIO5A_F2H_GPIN,
       MGPIO6A_F2H_GPIN,
       MGPIO7A_F2H_GPIN,
       MGPIO8A_F2H_GPIN,
       MGPIO9A_F2H_GPIN,
       MMUART0_CTS_F2H_SCP,
       MMUART0_DCD_F2H_SCP,
       MMUART0_DSR_F2H_SCP,
       MMUART0_DTR_F2H_SCP,
       MMUART0_RI_F2H_SCP,
       MMUART0_RTS_F2H_SCP,
       MMUART0_RXD_F2H_SCP,
       MMUART0_SCK_F2H_SCP,
       MMUART0_TXD_F2H_SCP,
       MMUART1_CTS_F2H_SCP,
       MMUART1_DCD_F2H_SCP,
       MMUART1_DSR_F2H_SCP,
       MMUART1_RI_F2H_SCP,
       MMUART1_RTS_F2H_SCP,
       MMUART1_RXD_F2H_SCP,
       MMUART1_SCK_F2H_SCP,
       MMUART1_TXD_F2H_SCP,
       PER2_FABRIC_PRDATA,
       PER2_FABRIC_PREADY,
       PER2_FABRIC_PSLVERR,
       RCGF,
       RX_CLKPF,
       RX_DVF,
       RX_ERRF,
       RX_EV,
       RXDF,
       SLEEPHOLDREQ,
       SMBALERT_NI0,
       SMBALERT_NI1,
       SMBSUS_NI0,
       SMBSUS_NI1,
       SPI0_CLK_IN,
       SPI0_SDI_F2H_SCP,
       SPI0_SDO_F2H_SCP,
       SPI0_SS0_F2H_SCP,
       SPI0_SS1_F2H_SCP,
       SPI0_SS2_F2H_SCP,
       SPI0_SS3_F2H_SCP,
       SPI1_CLK_IN,
       SPI1_SDI_F2H_SCP,
       SPI1_SDO_F2H_SCP,
       SPI1_SS0_F2H_SCP,
       SPI1_SS1_F2H_SCP,
       SPI1_SS2_F2H_SCP,
       SPI1_SS3_F2H_SCP,
       TX_CLKPF,
       USER_MSS_GPIO_RESET_N,
       USER_MSS_RESET_N,
       XCLK_FAB,
       CLK_MDDR_APB,
       F_ARADDR_HADDR1,
       F_ARBURST_HTRANS1,
       F_ARID_HSEL1,
       F_ARLEN_HBURST1,
       F_ARLOCK_HMASTLOCK1,
       F_ARSIZE_HSIZE1,
       F_ARVALID_HWRITE1,
       F_AWADDR_HADDR0,
       F_AWBURST_HTRANS0,
       F_AWID_HSEL0,
       F_AWLEN_HBURST0,
       F_AWLOCK_HMASTLOCK0,
       F_AWSIZE_HSIZE0,
       F_AWVALID_HWRITE0,
       F_BREADY,
       F_RMW_AXI,
       F_RREADY,
       F_WDATA_HWDATA01,
       F_WID_HREADY01,
       F_WLAST,
       F_WSTRB,
       F_WVALID,
       FPGA_MDDR_ARESET_N,
       MDDR_FABRIC_PADDR,
       MDDR_FABRIC_PENABLE,
       MDDR_FABRIC_PSEL,
       MDDR_FABRIC_PWDATA,
       MDDR_FABRIC_PWRITE,
       PRESET_N,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_IN,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_IN,
       DM_IN,
       DRAM_DQ_IN,
       DRAM_DQS_IN,
       DRAM_FIFO_WE_IN,
       I2C0_SCL_USBC_DATA1_MGPIO31B_IN,
       I2C0_SDA_USBC_DATA0_MGPIO30B_IN,
       I2C1_SCL_USBA_DATA4_MGPIO1A_IN,
       I2C1_SDA_USBA_DATA3_MGPIO0A_IN,
       MGPIO0B_IN,
       MGPIO10B_IN,
       MGPIO1B_IN,
       MGPIO25A_IN,
       MGPIO26A_IN,
       MGPIO27A_IN,
       MGPIO28A_IN,
       MGPIO29A_IN,
       MGPIO2B_IN,
       MGPIO30A_IN,
       MGPIO31A_IN,
       MGPIO3B_IN,
       MGPIO4B_IN,
       MGPIO5B_IN,
       MGPIO6B_IN,
       MGPIO7B_IN,
       MGPIO8B_IN,
       MGPIO9B_IN,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_IN,
       MMUART0_DCD_MGPIO22B_IN,
       MMUART0_DSR_MGPIO20B_IN,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_IN,
       MMUART0_RI_MGPIO21B_IN,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_IN,
       MMUART0_RXD_USBC_STP_MGPIO28B_IN,
       MMUART0_SCK_USBC_NXT_MGPIO29B_IN,
       MMUART0_TXD_USBC_DIR_MGPIO27B_IN,
       MMUART1_CTS_MGPIO13B_IN,
       MMUART1_DCD_MGPIO16B_IN,
       MMUART1_DSR_MGPIO14B_IN,
       MMUART1_DTR_MGPIO12B_IN,
       MMUART1_RI_MGPIO15B_IN,
       MMUART1_RTS_MGPIO11B_IN,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_IN,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_IN,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_IN,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN,
       RGMII_MDC_RMII_MDC_IN,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN,
       RGMII_RX_CLK_IN,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN,
       RGMII_RXD3_USBB_DATA4_IN,
       RGMII_TX_CLK_IN,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_IN,
       RGMII_TXD1_RMII_TXD1_USBB_STP_IN,
       RGMII_TXD2_USBB_DATA5_IN,
       RGMII_TXD3_USBB_DATA6_IN,
       SPI0_SCK_USBA_XCLK_IN,
       SPI0_SDI_USBA_DIR_MGPIO5A_IN,
       SPI0_SDO_USBA_STP_MGPIO6A_IN,
       SPI0_SS0_USBA_NXT_MGPIO7A_IN,
       SPI0_SS1_USBA_DATA5_MGPIO8A_IN,
       SPI0_SS2_USBA_DATA6_MGPIO9A_IN,
       SPI0_SS3_USBA_DATA7_MGPIO10A_IN,
       SPI0_SS4_MGPIO19A_IN,
       SPI0_SS5_MGPIO20A_IN,
       SPI0_SS6_MGPIO21A_IN,
       SPI0_SS7_MGPIO22A_IN,
       SPI1_SCK_IN,
       SPI1_SDI_MGPIO11A_IN,
       SPI1_SDO_MGPIO12A_IN,
       SPI1_SS0_MGPIO13A_IN,
       SPI1_SS1_MGPIO14A_IN,
       SPI1_SS2_MGPIO15A_IN,
       SPI1_SS3_MGPIO16A_IN,
       SPI1_SS4_MGPIO17A_IN,
       SPI1_SS5_MGPIO18A_IN,
       SPI1_SS6_MGPIO23A_IN,
       SPI1_SS7_MGPIO24A_IN,
       USBC_XCLK_IN,
       USBD_DATA0_IN,
       USBD_DATA1_IN,
       USBD_DATA2_IN,
       USBD_DATA3_IN,
       USBD_DATA4_IN,
       USBD_DATA5_IN,
       USBD_DATA6_IN,
       USBD_DATA7_MGPIO23B_IN,
       USBD_DIR_IN,
       USBD_NXT_IN,
       USBD_STP_IN,
       USBD_XCLK_IN,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT,
       DRAM_ADDR,
       DRAM_BA,
       DRAM_CASN,
       DRAM_CKE,
       DRAM_CLK,
       DRAM_CSN,
       DRAM_DM_RDQS_OUT,
       DRAM_DQ_OUT,
       DRAM_DQS_OUT,
       DRAM_FIFO_WE_OUT,
       DRAM_ODT,
       DRAM_RASN,
       DRAM_RSTN,
       DRAM_WEN,
       I2C0_SCL_USBC_DATA1_MGPIO31B_OUT,
       I2C0_SDA_USBC_DATA0_MGPIO30B_OUT,
       I2C1_SCL_USBA_DATA4_MGPIO1A_OUT,
       I2C1_SDA_USBA_DATA3_MGPIO0A_OUT,
       MGPIO0B_OUT,
       MGPIO10B_OUT,
       MGPIO1B_OUT,
       MGPIO25A_OUT,
       MGPIO26A_OUT,
       MGPIO27A_OUT,
       MGPIO28A_OUT,
       MGPIO29A_OUT,
       MGPIO2B_OUT,
       MGPIO30A_OUT,
       MGPIO31A_OUT,
       MGPIO3B_OUT,
       MGPIO4B_OUT,
       MGPIO5B_OUT,
       MGPIO6B_OUT,
       MGPIO7B_OUT,
       MGPIO8B_OUT,
       MGPIO9B_OUT,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT,
       MMUART0_DCD_MGPIO22B_OUT,
       MMUART0_DSR_MGPIO20B_OUT,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT,
       MMUART0_RI_MGPIO21B_OUT,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT,
       MMUART0_RXD_USBC_STP_MGPIO28B_OUT,
       MMUART0_SCK_USBC_NXT_MGPIO29B_OUT,
       MMUART0_TXD_USBC_DIR_MGPIO27B_OUT,
       MMUART1_CTS_MGPIO13B_OUT,
       MMUART1_DCD_MGPIO16B_OUT,
       MMUART1_DSR_MGPIO14B_OUT,
       MMUART1_DTR_MGPIO12B_OUT,
       MMUART1_RI_MGPIO15B_OUT,
       MMUART1_RTS_MGPIO11B_OUT,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT,
       RGMII_MDC_RMII_MDC_OUT,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT,
       RGMII_RX_CLK_OUT,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT,
       RGMII_RXD3_USBB_DATA4_OUT,
       RGMII_TX_CLK_OUT,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT,
       RGMII_TXD1_RMII_TXD1_USBB_STP_OUT,
       RGMII_TXD2_USBB_DATA5_OUT,
       RGMII_TXD3_USBB_DATA6_OUT,
       SPI0_SCK_USBA_XCLK_OUT,
       SPI0_SDI_USBA_DIR_MGPIO5A_OUT,
       SPI0_SDO_USBA_STP_MGPIO6A_OUT,
       SPI0_SS0_USBA_NXT_MGPIO7A_OUT,
       SPI0_SS1_USBA_DATA5_MGPIO8A_OUT,
       SPI0_SS2_USBA_DATA6_MGPIO9A_OUT,
       SPI0_SS3_USBA_DATA7_MGPIO10A_OUT,
       SPI0_SS4_MGPIO19A_OUT,
       SPI0_SS5_MGPIO20A_OUT,
       SPI0_SS6_MGPIO21A_OUT,
       SPI0_SS7_MGPIO22A_OUT,
       SPI1_SCK_OUT,
       SPI1_SDI_MGPIO11A_OUT,
       SPI1_SDO_MGPIO12A_OUT,
       SPI1_SS0_MGPIO13A_OUT,
       SPI1_SS1_MGPIO14A_OUT,
       SPI1_SS2_MGPIO15A_OUT,
       SPI1_SS3_MGPIO16A_OUT,
       SPI1_SS4_MGPIO17A_OUT,
       SPI1_SS5_MGPIO18A_OUT,
       SPI1_SS6_MGPIO23A_OUT,
       SPI1_SS7_MGPIO24A_OUT,
       USBC_XCLK_OUT,
       USBD_DATA0_OUT,
       USBD_DATA1_OUT,
       USBD_DATA2_OUT,
       USBD_DATA3_OUT,
       USBD_DATA4_OUT,
       USBD_DATA5_OUT,
       USBD_DATA6_OUT,
       USBD_DATA7_MGPIO23B_OUT,
       USBD_DIR_OUT,
       USBD_NXT_OUT,
       USBD_STP_OUT,
       USBD_XCLK_OUT,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_OE,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_OE,
       DM_OE,
       DRAM_DQ_OE,
       DRAM_DQS_OE,
       I2C0_SCL_USBC_DATA1_MGPIO31B_OE,
       I2C0_SDA_USBC_DATA0_MGPIO30B_OE,
       I2C1_SCL_USBA_DATA4_MGPIO1A_OE,
       I2C1_SDA_USBA_DATA3_MGPIO0A_OE,
       MGPIO0B_OE,
       MGPIO10B_OE,
       MGPIO1B_OE,
       MGPIO25A_OE,
       MGPIO26A_OE,
       MGPIO27A_OE,
       MGPIO28A_OE,
       MGPIO29A_OE,
       MGPIO2B_OE,
       MGPIO30A_OE,
       MGPIO31A_OE,
       MGPIO3B_OE,
       MGPIO4B_OE,
       MGPIO5B_OE,
       MGPIO6B_OE,
       MGPIO7B_OE,
       MGPIO8B_OE,
       MGPIO9B_OE,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_OE,
       MMUART0_DCD_MGPIO22B_OE,
       MMUART0_DSR_MGPIO20B_OE,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_OE,
       MMUART0_RI_MGPIO21B_OE,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_OE,
       MMUART0_RXD_USBC_STP_MGPIO28B_OE,
       MMUART0_SCK_USBC_NXT_MGPIO29B_OE,
       MMUART0_TXD_USBC_DIR_MGPIO27B_OE,
       MMUART1_CTS_MGPIO13B_OE,
       MMUART1_DCD_MGPIO16B_OE,
       MMUART1_DSR_MGPIO14B_OE,
       MMUART1_DTR_MGPIO12B_OE,
       MMUART1_RI_MGPIO15B_OE,
       MMUART1_RTS_MGPIO11B_OE,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_OE,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_OE,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_OE,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE,
       RGMII_MDC_RMII_MDC_OE,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE,
       RGMII_RX_CLK_OE,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE,
       RGMII_RXD3_USBB_DATA4_OE,
       RGMII_TX_CLK_OE,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_OE,
       RGMII_TXD1_RMII_TXD1_USBB_STP_OE,
       RGMII_TXD2_USBB_DATA5_OE,
       RGMII_TXD3_USBB_DATA6_OE,
       SPI0_SCK_USBA_XCLK_OE,
       SPI0_SDI_USBA_DIR_MGPIO5A_OE,
       SPI0_SDO_USBA_STP_MGPIO6A_OE,
       SPI0_SS0_USBA_NXT_MGPIO7A_OE,
       SPI0_SS1_USBA_DATA5_MGPIO8A_OE,
       SPI0_SS2_USBA_DATA6_MGPIO9A_OE,
       SPI0_SS3_USBA_DATA7_MGPIO10A_OE,
       SPI0_SS4_MGPIO19A_OE,
       SPI0_SS5_MGPIO20A_OE,
       SPI0_SS6_MGPIO21A_OE,
       SPI0_SS7_MGPIO22A_OE,
       SPI1_SCK_OE,
       SPI1_SDI_MGPIO11A_OE,
       SPI1_SDO_MGPIO12A_OE,
       SPI1_SS0_MGPIO13A_OE,
       SPI1_SS1_MGPIO14A_OE,
       SPI1_SS2_MGPIO15A_OE,
       SPI1_SS3_MGPIO16A_OE,
       SPI1_SS4_MGPIO17A_OE,
       SPI1_SS5_MGPIO18A_OE,
       SPI1_SS6_MGPIO23A_OE,
       SPI1_SS7_MGPIO24A_OE,
       USBC_XCLK_OE,
       USBD_DATA0_OE,
       USBD_DATA1_OE,
       USBD_DATA2_OE,
       USBD_DATA3_OE,
       USBD_DATA4_OE,
       USBD_DATA5_OE,
       USBD_DATA6_OE,
       USBD_DATA7_MGPIO23B_OE,
       USBD_DIR_OE,
       USBD_NXT_OE,
       USBD_STP_OE,
       USBD_XCLK_OE
    );
output CAN_RXBUS_MGPIO3A_H2F_A;
output CAN_RXBUS_MGPIO3A_H2F_B;
output CAN_TX_EBL_MGPIO4A_H2F_A;
output CAN_TX_EBL_MGPIO4A_H2F_B;
output CAN_TXBUS_MGPIO2A_H2F_A;
output CAN_TXBUS_MGPIO2A_H2F_B;
output CLK_CONFIG_APB;
output COMMS_INT;
output CONFIG_PRESET_N;
output [7:0] EDAC_ERROR;
output [31:0] F_FM0_RDATA;
output F_FM0_READYOUT;
output F_FM0_RESP;
output [31:0] F_FM1_RDATA;
output F_FM1_READYOUT;
output F_FM1_RESP;
output [31:0] F_HM0_ADDR;
output F_HM0_ENABLE;
output F_HM0_SEL;
output [1:0] F_HM0_SIZE;
output F_HM0_TRANS1;
output [31:0] F_HM0_WDATA;
output F_HM0_WRITE;
output [31:0] F_HM1_ADDR;
output F_HM1_ENABLE;
output F_HM1_SEL;
output [1:0] F_HM1_SIZE;
output F_HM1_TRANS1;
output [31:0] F_HM1_WDATA;
output F_HM1_WRITE;
output FAB_CHRGVBUS;
output FAB_DISCHRGVBUS;
output FAB_DMPULLDOWN;
output FAB_DPPULLDOWN;
output FAB_DRVVBUS;
output FAB_IDPULLUP;
output [1:0] FAB_OPMODE;
output FAB_SUSPENDM;
output FAB_TERMSEL;
output FAB_TXVALID;
output [3:0] FAB_VCONTROL;
output FAB_VCONTROLLOADM;
output [1:0] FAB_XCVRSEL;
output [7:0] FAB_XDATAOUT;
output FACC_GLMUX_SEL;
output [1:0] FIC32_0_MASTER;
output [1:0] FIC32_1_MASTER;
output FPGA_RESET_N;
output GTX_CLK;
output [15:0] H2F_INTERRUPT;
output H2F_NMI;
output H2FCALIB;
output I2C0_SCL_MGPIO31B_H2F_A;
output I2C0_SCL_MGPIO31B_H2F_B;
output I2C0_SDA_MGPIO30B_H2F_A;
output I2C0_SDA_MGPIO30B_H2F_B;
output I2C1_SCL_MGPIO1A_H2F_A;
output I2C1_SCL_MGPIO1A_H2F_B;
output I2C1_SDA_MGPIO0A_H2F_A;
output I2C1_SDA_MGPIO0A_H2F_B;
output MDCF;
output MDOENF;
output MDOF;
output MMUART0_CTS_MGPIO19B_H2F_A;
output MMUART0_CTS_MGPIO19B_H2F_B;
output MMUART0_DCD_MGPIO22B_H2F_A;
output MMUART0_DCD_MGPIO22B_H2F_B;
output MMUART0_DSR_MGPIO20B_H2F_A;
output MMUART0_DSR_MGPIO20B_H2F_B;
output MMUART0_DTR_MGPIO18B_H2F_A;
output MMUART0_DTR_MGPIO18B_H2F_B;
output MMUART0_RI_MGPIO21B_H2F_A;
output MMUART0_RI_MGPIO21B_H2F_B;
output MMUART0_RTS_MGPIO17B_H2F_A;
output MMUART0_RTS_MGPIO17B_H2F_B;
output MMUART0_RXD_MGPIO28B_H2F_A;
output MMUART0_RXD_MGPIO28B_H2F_B;
output MMUART0_SCK_MGPIO29B_H2F_A;
output MMUART0_SCK_MGPIO29B_H2F_B;
output MMUART0_TXD_MGPIO27B_H2F_A;
output MMUART0_TXD_MGPIO27B_H2F_B;
output MMUART1_DTR_MGPIO12B_H2F_A;
output MMUART1_RTS_MGPIO11B_H2F_A;
output MMUART1_RTS_MGPIO11B_H2F_B;
output MMUART1_RXD_MGPIO26B_H2F_A;
output MMUART1_RXD_MGPIO26B_H2F_B;
output MMUART1_SCK_MGPIO25B_H2F_A;
output MMUART1_SCK_MGPIO25B_H2F_B;
output MMUART1_TXD_MGPIO24B_H2F_A;
output MMUART1_TXD_MGPIO24B_H2F_B;
output MPLL_LOCK;
output [16:2] PER2_FABRIC_PADDR;
output PER2_FABRIC_PENABLE;
output PER2_FABRIC_PSEL;
output [31:0] PER2_FABRIC_PWDATA;
output PER2_FABRIC_PWRITE;
output RTC_MATCH;
output SLEEPDEEP;
output SLEEPHOLDACK;
output SLEEPING;
output SMBALERT_NO0;
output SMBALERT_NO1;
output SMBSUS_NO0;
output SMBSUS_NO1;
output SPI0_CLK_OUT;
output SPI0_SDI_MGPIO5A_H2F_A;
output SPI0_SDI_MGPIO5A_H2F_B;
output SPI0_SDO_MGPIO6A_H2F_A;
output SPI0_SDO_MGPIO6A_H2F_B;
output SPI0_SS0_MGPIO7A_H2F_A;
output SPI0_SS0_MGPIO7A_H2F_B;
output SPI0_SS1_MGPIO8A_H2F_A;
output SPI0_SS1_MGPIO8A_H2F_B;
output SPI0_SS2_MGPIO9A_H2F_A;
output SPI0_SS2_MGPIO9A_H2F_B;
output SPI0_SS3_MGPIO10A_H2F_A;
output SPI0_SS3_MGPIO10A_H2F_B;
output SPI0_SS4_MGPIO19A_H2F_A;
output SPI0_SS5_MGPIO20A_H2F_A;
output SPI0_SS6_MGPIO21A_H2F_A;
output SPI0_SS7_MGPIO22A_H2F_A;
output SPI1_CLK_OUT;
output SPI1_SDI_MGPIO11A_H2F_A;
output SPI1_SDI_MGPIO11A_H2F_B;
output SPI1_SDO_MGPIO12A_H2F_A;
output SPI1_SDO_MGPIO12A_H2F_B;
output SPI1_SS0_MGPIO13A_H2F_A;
output SPI1_SS0_MGPIO13A_H2F_B;
output SPI1_SS1_MGPIO14A_H2F_A;
output SPI1_SS1_MGPIO14A_H2F_B;
output SPI1_SS2_MGPIO15A_H2F_A;
output SPI1_SS2_MGPIO15A_H2F_B;
output SPI1_SS3_MGPIO16A_H2F_A;
output SPI1_SS3_MGPIO16A_H2F_B;
output SPI1_SS4_MGPIO17A_H2F_A;
output SPI1_SS5_MGPIO18A_H2F_A;
output SPI1_SS6_MGPIO23A_H2F_A;
output SPI1_SS7_MGPIO24A_H2F_A;
output [9:0] TCGF;
output TRACECLK;
output [3:0] TRACEDATA;
output TX_CLK;
output TX_ENF;
output TX_ERRF;
output TXCTL_EN_RIF;
output [3:0] TXD_RIF;
output [7:0] TXDF;
output TXEV;
output WDOGTIMEOUT;
output F_ARREADY_HREADYOUT1;
output F_AWREADY_HREADYOUT0;
output [3:0] F_BID;
output [1:0] F_BRESP_HRESP0;
output F_BVALID;
output [63:0] F_RDATA_HRDATA01;
output [3:0] F_RID;
output F_RLAST;
output [1:0] F_RRESP_HRESP1;
output F_RVALID;
output F_WREADY;
output [15:0] MDDR_FABRIC_PRDATA;
output MDDR_FABRIC_PREADY;
output MDDR_FABRIC_PSLVERR;
output [31:0] REV_ARADDR;
output [1:0] REV_ARBURST;
output [3:0] REV_ARID;
output [3:0] REV_ARLEN;
output [1:0] REV_ARLOCK;
output [1:0] REV_ARSIZE;
output [31:0] REV_AWADDR;
output [1:0] REV_AWLOCK;
output [1:0] REV_AWSIZE;
output REV_RREADY;
output [3:0] REV_WID;
output [7:0] REV_WSTRB;
input  CAN_RXBUS_F2H_SCP;
input  CAN_TX_EBL_F2H_SCP;
input  CAN_TXBUS_F2H_SCP;
input  CLK_BASE;
input  COLF;
input  CRSF;
input  [1:0] F2_DMAREADY;
input  [15:0] F2H_INTERRUPT;
input  F2HCALIB;
input  [1:0] F_DMAREADY;
input  [31:0] F_FM0_ADDR;
input  F_FM0_ENABLE;
input  F_FM0_MASTLOCK;
input  F_FM0_READY;
input  F_FM0_SEL;
input  [1:0] F_FM0_SIZE;
input  F_FM0_TRANS1;
input  [31:0] F_FM0_WDATA;
input  F_FM0_WRITE;
input  [31:0] F_FM1_ADDR;
input  F_FM1_ENABLE;
input  F_FM1_MASTLOCK;
input  F_FM1_READY;
input  F_FM1_SEL;
input  [1:0] F_FM1_SIZE;
input  F_FM1_TRANS1;
input  [31:0] F_FM1_WDATA;
input  F_FM1_WRITE;
input  [31:0] F_HM0_RDATA;
input  F_HM0_READY;
input  F_HM0_RESP;
input  [31:0] F_HM1_RDATA;
input  F_HM1_READY;
input  F_HM1_RESP;
input  FAB_AVALID;
input  FAB_HOSTDISCON;
input  FAB_IDDIG;
input  [1:0] FAB_LINESTATE;
input  FAB_M3_RESET_N;
input  FAB_PLL_LOCK;
input  FAB_RXACTIVE;
input  FAB_RXERROR;
input  FAB_RXVALID;
input  FAB_RXVALIDH;
input  FAB_SESSEND;
input  FAB_TXREADY;
input  FAB_VBUSVALID;
input  [7:0] FAB_VSTATUS;
input  [7:0] FAB_XDATAIN;
input  GTX_CLKPF;
input  I2C0_BCLK;
input  I2C0_SCL_F2H_SCP;
input  I2C0_SDA_F2H_SCP;
input  I2C1_BCLK;
input  I2C1_SCL_F2H_SCP;
input  I2C1_SDA_F2H_SCP;
input  MDIF;
input  MGPIO0A_F2H_GPIN;
input  MGPIO10A_F2H_GPIN;
input  MGPIO11A_F2H_GPIN;
input  MGPIO11B_F2H_GPIN;
input  MGPIO12A_F2H_GPIN;
input  MGPIO13A_F2H_GPIN;
input  MGPIO14A_F2H_GPIN;
input  MGPIO15A_F2H_GPIN;
input  MGPIO16A_F2H_GPIN;
input  MGPIO17B_F2H_GPIN;
input  MGPIO18B_F2H_GPIN;
input  MGPIO19B_F2H_GPIN;
input  MGPIO1A_F2H_GPIN;
input  MGPIO20B_F2H_GPIN;
input  MGPIO21B_F2H_GPIN;
input  MGPIO22B_F2H_GPIN;
input  MGPIO24B_F2H_GPIN;
input  MGPIO25B_F2H_GPIN;
input  MGPIO26B_F2H_GPIN;
input  MGPIO27B_F2H_GPIN;
input  MGPIO28B_F2H_GPIN;
input  MGPIO29B_F2H_GPIN;
input  MGPIO2A_F2H_GPIN;
input  MGPIO30B_F2H_GPIN;
input  MGPIO31B_F2H_GPIN;
input  MGPIO3A_F2H_GPIN;
input  MGPIO4A_F2H_GPIN;
input  MGPIO5A_F2H_GPIN;
input  MGPIO6A_F2H_GPIN;
input  MGPIO7A_F2H_GPIN;
input  MGPIO8A_F2H_GPIN;
input  MGPIO9A_F2H_GPIN;
input  MMUART0_CTS_F2H_SCP;
input  MMUART0_DCD_F2H_SCP;
input  MMUART0_DSR_F2H_SCP;
input  MMUART0_DTR_F2H_SCP;
input  MMUART0_RI_F2H_SCP;
input  MMUART0_RTS_F2H_SCP;
input  MMUART0_RXD_F2H_SCP;
input  MMUART0_SCK_F2H_SCP;
input  MMUART0_TXD_F2H_SCP;
input  MMUART1_CTS_F2H_SCP;
input  MMUART1_DCD_F2H_SCP;
input  MMUART1_DSR_F2H_SCP;
input  MMUART1_RI_F2H_SCP;
input  MMUART1_RTS_F2H_SCP;
input  MMUART1_RXD_F2H_SCP;
input  MMUART1_SCK_F2H_SCP;
input  MMUART1_TXD_F2H_SCP;
input  [31:0] PER2_FABRIC_PRDATA;
input  PER2_FABRIC_PREADY;
input  PER2_FABRIC_PSLVERR;
input  [9:0] RCGF;
input  RX_CLKPF;
input  RX_DVF;
input  RX_ERRF;
input  RX_EV;
input  [7:0] RXDF;
input  SLEEPHOLDREQ;
input  SMBALERT_NI0;
input  SMBALERT_NI1;
input  SMBSUS_NI0;
input  SMBSUS_NI1;
input  SPI0_CLK_IN;
input  SPI0_SDI_F2H_SCP;
input  SPI0_SDO_F2H_SCP;
input  SPI0_SS0_F2H_SCP;
input  SPI0_SS1_F2H_SCP;
input  SPI0_SS2_F2H_SCP;
input  SPI0_SS3_F2H_SCP;
input  SPI1_CLK_IN;
input  SPI1_SDI_F2H_SCP;
input  SPI1_SDO_F2H_SCP;
input  SPI1_SS0_F2H_SCP;
input  SPI1_SS1_F2H_SCP;
input  SPI1_SS2_F2H_SCP;
input  SPI1_SS3_F2H_SCP;
input  TX_CLKPF;
input  USER_MSS_GPIO_RESET_N;
input  USER_MSS_RESET_N;
input  XCLK_FAB;
input  CLK_MDDR_APB;
input  [31:0] F_ARADDR_HADDR1;
input  [1:0] F_ARBURST_HTRANS1;
input  [3:0] F_ARID_HSEL1;
input  [3:0] F_ARLEN_HBURST1;
input  [1:0] F_ARLOCK_HMASTLOCK1;
input  [1:0] F_ARSIZE_HSIZE1;
input  F_ARVALID_HWRITE1;
input  [31:0] F_AWADDR_HADDR0;
input  [1:0] F_AWBURST_HTRANS0;
input  [3:0] F_AWID_HSEL0;
input  [3:0] F_AWLEN_HBURST0;
input  [1:0] F_AWLOCK_HMASTLOCK0;
input  [1:0] F_AWSIZE_HSIZE0;
input  F_AWVALID_HWRITE0;
input  F_BREADY;
input  F_RMW_AXI;
input  F_RREADY;
input  [63:0] F_WDATA_HWDATA01;
input  [3:0] F_WID_HREADY01;
input  F_WLAST;
input  [7:0] F_WSTRB;
input  F_WVALID;
input  FPGA_MDDR_ARESET_N;
input  [10:2] MDDR_FABRIC_PADDR;
input  MDDR_FABRIC_PENABLE;
input  MDDR_FABRIC_PSEL;
input  [15:0] MDDR_FABRIC_PWDATA;
input  MDDR_FABRIC_PWRITE;
input  PRESET_N;
input  CAN_RXBUS_USBA_DATA1_MGPIO3A_IN;
input  CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN;
input  CAN_TXBUS_USBA_DATA0_MGPIO2A_IN;
input  [4:0] DM_IN;
input  [35:0] DRAM_DQ_IN;
input  [4:0] DRAM_DQS_IN;
input  [2:0] DRAM_FIFO_WE_IN;
input  I2C0_SCL_USBC_DATA1_MGPIO31B_IN;
input  I2C0_SDA_USBC_DATA0_MGPIO30B_IN;
input  I2C1_SCL_USBA_DATA4_MGPIO1A_IN;
input  I2C1_SDA_USBA_DATA3_MGPIO0A_IN;
input  MGPIO0B_IN;
input  MGPIO10B_IN;
input  MGPIO1B_IN;
input  MGPIO25A_IN;
input  MGPIO26A_IN;
input  MGPIO27A_IN;
input  MGPIO28A_IN;
input  MGPIO29A_IN;
input  MGPIO2B_IN;
input  MGPIO30A_IN;
input  MGPIO31A_IN;
input  MGPIO3B_IN;
input  MGPIO4B_IN;
input  MGPIO5B_IN;
input  MGPIO6B_IN;
input  MGPIO7B_IN;
input  MGPIO8B_IN;
input  MGPIO9B_IN;
input  MMUART0_CTS_USBC_DATA7_MGPIO19B_IN;
input  MMUART0_DCD_MGPIO22B_IN;
input  MMUART0_DSR_MGPIO20B_IN;
input  MMUART0_DTR_USBC_DATA6_MGPIO18B_IN;
input  MMUART0_RI_MGPIO21B_IN;
input  MMUART0_RTS_USBC_DATA5_MGPIO17B_IN;
input  MMUART0_RXD_USBC_STP_MGPIO28B_IN;
input  MMUART0_SCK_USBC_NXT_MGPIO29B_IN;
input  MMUART0_TXD_USBC_DIR_MGPIO27B_IN;
input  MMUART1_CTS_MGPIO13B_IN;
input  MMUART1_DCD_MGPIO16B_IN;
input  MMUART1_DSR_MGPIO14B_IN;
input  MMUART1_DTR_MGPIO12B_IN;
input  MMUART1_RI_MGPIO15B_IN;
input  MMUART1_RTS_MGPIO11B_IN;
input  MMUART1_RXD_USBC_DATA3_MGPIO26B_IN;
input  MMUART1_SCK_USBC_DATA4_MGPIO25B_IN;
input  MMUART1_TXD_USBC_DATA2_MGPIO24B_IN;
input  RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN;
input  RGMII_MDC_RMII_MDC_IN;
input  RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN;
input  RGMII_RX_CLK_IN;
input  RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN;
input  RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN;
input  RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN;
input  RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN;
input  RGMII_RXD3_USBB_DATA4_IN;
input  RGMII_TX_CLK_IN;
input  RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN;
input  RGMII_TXD0_RMII_TXD0_USBB_DIR_IN;
input  RGMII_TXD1_RMII_TXD1_USBB_STP_IN;
input  RGMII_TXD2_USBB_DATA5_IN;
input  RGMII_TXD3_USBB_DATA6_IN;
input  SPI0_SCK_USBA_XCLK_IN;
input  SPI0_SDI_USBA_DIR_MGPIO5A_IN;
input  SPI0_SDO_USBA_STP_MGPIO6A_IN;
input  SPI0_SS0_USBA_NXT_MGPIO7A_IN;
input  SPI0_SS1_USBA_DATA5_MGPIO8A_IN;
input  SPI0_SS2_USBA_DATA6_MGPIO9A_IN;
input  SPI0_SS3_USBA_DATA7_MGPIO10A_IN;
input  SPI0_SS4_MGPIO19A_IN;
input  SPI0_SS5_MGPIO20A_IN;
input  SPI0_SS6_MGPIO21A_IN;
input  SPI0_SS7_MGPIO22A_IN;
input  SPI1_SCK_IN;
input  SPI1_SDI_MGPIO11A_IN;
input  SPI1_SDO_MGPIO12A_IN;
input  SPI1_SS0_MGPIO13A_IN;
input  SPI1_SS1_MGPIO14A_IN;
input  SPI1_SS2_MGPIO15A_IN;
input  SPI1_SS3_MGPIO16A_IN;
input  SPI1_SS4_MGPIO17A_IN;
input  SPI1_SS5_MGPIO18A_IN;
input  SPI1_SS6_MGPIO23A_IN;
input  SPI1_SS7_MGPIO24A_IN;
input  USBC_XCLK_IN;
input  USBD_DATA0_IN;
input  USBD_DATA1_IN;
input  USBD_DATA2_IN;
input  USBD_DATA3_IN;
input  USBD_DATA4_IN;
input  USBD_DATA5_IN;
input  USBD_DATA6_IN;
input  USBD_DATA7_MGPIO23B_IN;
input  USBD_DIR_IN;
input  USBD_NXT_IN;
input  USBD_STP_IN;
input  USBD_XCLK_IN;
output CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT;
output CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT;
output CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT;
output [15:0] DRAM_ADDR;
output [2:0] DRAM_BA;
output DRAM_CASN;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CSN;
output [4:0] DRAM_DM_RDQS_OUT;
output [35:0] DRAM_DQ_OUT;
output [4:0] DRAM_DQS_OUT;
output [2:0] DRAM_FIFO_WE_OUT;
output DRAM_ODT;
output DRAM_RASN;
output DRAM_RSTN;
output DRAM_WEN;
output I2C0_SCL_USBC_DATA1_MGPIO31B_OUT;
output I2C0_SDA_USBC_DATA0_MGPIO30B_OUT;
output I2C1_SCL_USBA_DATA4_MGPIO1A_OUT;
output I2C1_SDA_USBA_DATA3_MGPIO0A_OUT;
output MGPIO0B_OUT;
output MGPIO10B_OUT;
output MGPIO1B_OUT;
output MGPIO25A_OUT;
output MGPIO26A_OUT;
output MGPIO27A_OUT;
output MGPIO28A_OUT;
output MGPIO29A_OUT;
output MGPIO2B_OUT;
output MGPIO30A_OUT;
output MGPIO31A_OUT;
output MGPIO3B_OUT;
output MGPIO4B_OUT;
output MGPIO5B_OUT;
output MGPIO6B_OUT;
output MGPIO7B_OUT;
output MGPIO8B_OUT;
output MGPIO9B_OUT;
output MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT;
output MMUART0_DCD_MGPIO22B_OUT;
output MMUART0_DSR_MGPIO20B_OUT;
output MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT;
output MMUART0_RI_MGPIO21B_OUT;
output MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT;
output MMUART0_RXD_USBC_STP_MGPIO28B_OUT;
output MMUART0_SCK_USBC_NXT_MGPIO29B_OUT;
output MMUART0_TXD_USBC_DIR_MGPIO27B_OUT;
output MMUART1_CTS_MGPIO13B_OUT;
output MMUART1_DCD_MGPIO16B_OUT;
output MMUART1_DSR_MGPIO14B_OUT;
output MMUART1_DTR_MGPIO12B_OUT;
output MMUART1_RI_MGPIO15B_OUT;
output MMUART1_RTS_MGPIO11B_OUT;
output MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT;
output MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT;
output MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT;
output RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT;
output RGMII_MDC_RMII_MDC_OUT;
output RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT;
output RGMII_RX_CLK_OUT;
output RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT;
output RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT;
output RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT;
output RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT;
output RGMII_RXD3_USBB_DATA4_OUT;
output RGMII_TX_CLK_OUT;
output RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT;
output RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT;
output RGMII_TXD1_RMII_TXD1_USBB_STP_OUT;
output RGMII_TXD2_USBB_DATA5_OUT;
output RGMII_TXD3_USBB_DATA6_OUT;
output SPI0_SCK_USBA_XCLK_OUT;
output SPI0_SDI_USBA_DIR_MGPIO5A_OUT;
output SPI0_SDO_USBA_STP_MGPIO6A_OUT;
output SPI0_SS0_USBA_NXT_MGPIO7A_OUT;
output SPI0_SS1_USBA_DATA5_MGPIO8A_OUT;
output SPI0_SS2_USBA_DATA6_MGPIO9A_OUT;
output SPI0_SS3_USBA_DATA7_MGPIO10A_OUT;
output SPI0_SS4_MGPIO19A_OUT;
output SPI0_SS5_MGPIO20A_OUT;
output SPI0_SS6_MGPIO21A_OUT;
output SPI0_SS7_MGPIO22A_OUT;
output SPI1_SCK_OUT;
output SPI1_SDI_MGPIO11A_OUT;
output SPI1_SDO_MGPIO12A_OUT;
output SPI1_SS0_MGPIO13A_OUT;
output SPI1_SS1_MGPIO14A_OUT;
output SPI1_SS2_MGPIO15A_OUT;
output SPI1_SS3_MGPIO16A_OUT;
output SPI1_SS4_MGPIO17A_OUT;
output SPI1_SS5_MGPIO18A_OUT;
output SPI1_SS6_MGPIO23A_OUT;
output SPI1_SS7_MGPIO24A_OUT;
output USBC_XCLK_OUT;
output USBD_DATA0_OUT;
output USBD_DATA1_OUT;
output USBD_DATA2_OUT;
output USBD_DATA3_OUT;
output USBD_DATA4_OUT;
output USBD_DATA5_OUT;
output USBD_DATA6_OUT;
output USBD_DATA7_MGPIO23B_OUT;
output USBD_DIR_OUT;
output USBD_NXT_OUT;
output USBD_STP_OUT;
output USBD_XCLK_OUT;
output CAN_RXBUS_USBA_DATA1_MGPIO3A_OE;
output CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE;
output CAN_TXBUS_USBA_DATA0_MGPIO2A_OE;
output [4:0] DM_OE;
output [35:0] DRAM_DQ_OE;
output [4:0] DRAM_DQS_OE;
output I2C0_SCL_USBC_DATA1_MGPIO31B_OE;
output I2C0_SDA_USBC_DATA0_MGPIO30B_OE;
output I2C1_SCL_USBA_DATA4_MGPIO1A_OE;
output I2C1_SDA_USBA_DATA3_MGPIO0A_OE;
output MGPIO0B_OE;
output MGPIO10B_OE;
output MGPIO1B_OE;
output MGPIO25A_OE;
output MGPIO26A_OE;
output MGPIO27A_OE;
output MGPIO28A_OE;
output MGPIO29A_OE;
output MGPIO2B_OE;
output MGPIO30A_OE;
output MGPIO31A_OE;
output MGPIO3B_OE;
output MGPIO4B_OE;
output MGPIO5B_OE;
output MGPIO6B_OE;
output MGPIO7B_OE;
output MGPIO8B_OE;
output MGPIO9B_OE;
output MMUART0_CTS_USBC_DATA7_MGPIO19B_OE;
output MMUART0_DCD_MGPIO22B_OE;
output MMUART0_DSR_MGPIO20B_OE;
output MMUART0_DTR_USBC_DATA6_MGPIO18B_OE;
output MMUART0_RI_MGPIO21B_OE;
output MMUART0_RTS_USBC_DATA5_MGPIO17B_OE;
output MMUART0_RXD_USBC_STP_MGPIO28B_OE;
output MMUART0_SCK_USBC_NXT_MGPIO29B_OE;
output MMUART0_TXD_USBC_DIR_MGPIO27B_OE;
output MMUART1_CTS_MGPIO13B_OE;
output MMUART1_DCD_MGPIO16B_OE;
output MMUART1_DSR_MGPIO14B_OE;
output MMUART1_DTR_MGPIO12B_OE;
output MMUART1_RI_MGPIO15B_OE;
output MMUART1_RTS_MGPIO11B_OE;
output MMUART1_RXD_USBC_DATA3_MGPIO26B_OE;
output MMUART1_SCK_USBC_DATA4_MGPIO25B_OE;
output MMUART1_TXD_USBC_DATA2_MGPIO24B_OE;
output RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE;
output RGMII_MDC_RMII_MDC_OE;
output RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE;
output RGMII_RX_CLK_OE;
output RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE;
output RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE;
output RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE;
output RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE;
output RGMII_RXD3_USBB_DATA4_OE;
output RGMII_TX_CLK_OE;
output RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE;
output RGMII_TXD0_RMII_TXD0_USBB_DIR_OE;
output RGMII_TXD1_RMII_TXD1_USBB_STP_OE;
output RGMII_TXD2_USBB_DATA5_OE;
output RGMII_TXD3_USBB_DATA6_OE;
output SPI0_SCK_USBA_XCLK_OE;
output SPI0_SDI_USBA_DIR_MGPIO5A_OE;
output SPI0_SDO_USBA_STP_MGPIO6A_OE;
output SPI0_SS0_USBA_NXT_MGPIO7A_OE;
output SPI0_SS1_USBA_DATA5_MGPIO8A_OE;
output SPI0_SS2_USBA_DATA6_MGPIO9A_OE;
output SPI0_SS3_USBA_DATA7_MGPIO10A_OE;
output SPI0_SS4_MGPIO19A_OE;
output SPI0_SS5_MGPIO20A_OE;
output SPI0_SS6_MGPIO21A_OE;
output SPI0_SS7_MGPIO22A_OE;
output SPI1_SCK_OE;
output SPI1_SDI_MGPIO11A_OE;
output SPI1_SDO_MGPIO12A_OE;
output SPI1_SS0_MGPIO13A_OE;
output SPI1_SS1_MGPIO14A_OE;
output SPI1_SS2_MGPIO15A_OE;
output SPI1_SS3_MGPIO16A_OE;
output SPI1_SS4_MGPIO17A_OE;
output SPI1_SS5_MGPIO18A_OE;
output SPI1_SS6_MGPIO23A_OE;
output SPI1_SS7_MGPIO24A_OE;
output USBC_XCLK_OE;
output USBD_DATA0_OE;
output USBD_DATA1_OE;
output USBD_DATA2_OE;
output USBD_DATA3_OE;
output USBD_DATA4_OE;
output USBD_DATA5_OE;
output USBD_DATA6_OE;
output USBD_DATA7_MGPIO23B_OE;
output USBD_DIR_OE;
output USBD_NXT_OE;
output USBD_STP_OE;
output USBD_XCLK_OE;

    parameter INIT = 'h0 ;
    parameter ACT_UBITS = 'hFFFFFFFFFFFFFF ;
    parameter MEMORYFILE = "" ;
    
endmodule


module CodeShadowing_Fabric_MSS(
       FIC_0_AHB_S_HADDR,
       FIC_0_AHB_S_HSIZE,
       FIC_0_AHB_S_HTRANS,
       FIC_0_AHB_S_HWDATA,
       FIC_2_APB_M_PRDATA,
       MDDR_APB_S_PADDR,
       MDDR_APB_S_PWDATA,
       MDDR_DDR_AXI_S_ARADDR,
       MDDR_DDR_AXI_S_ARBURST,
       MDDR_DDR_AXI_S_ARID,
       MDDR_DDR_AXI_S_ARLEN,
       MDDR_DDR_AXI_S_ARLOCK,
       MDDR_DDR_AXI_S_ARSIZE,
       MDDR_DDR_AXI_S_AWADDR,
       MDDR_DDR_AXI_S_AWBURST,
       MDDR_DDR_AXI_S_AWID,
       MDDR_DDR_AXI_S_AWLEN,
       MDDR_DDR_AXI_S_AWLOCK,
       MDDR_DDR_AXI_S_AWSIZE,
       MDDR_DDR_AXI_S_WDATA,
       MDDR_DDR_AXI_S_WID,
       MDDR_DDR_AXI_S_WSTRB,
       FIC_0_AHB_S_HRDATA,
       FIC_2_APB_M_PADDR,
       FIC_2_APB_M_PWDATA,
       MDDR_ADDR,
       MDDR_APB_S_PRDATA,
       MDDR_BA,
       MDDR_DDR_AXI_S_BID,
       MDDR_DDR_AXI_S_BRESP,
       MDDR_DDR_AXI_S_RDATA,
       MDDR_DDR_AXI_S_RID,
       MDDR_DDR_AXI_S_RRESP,
       MDDR_DM_RDQS,
       MDDR_DQ,
       MDDR_DQS,
       MDDR_DQS_N,
       FIC_0_AHB_S_HMASTLOCK,
       FIC_0_AHB_S_HREADY,
       FIC_0_AHB_S_HSEL,
       FIC_0_AHB_S_HWRITE,
       FIC_2_APB_M_PREADY,
       FIC_2_APB_M_PSLVERR,
       GPIO_11_F2M,
       GPIO_12_F2M,
       M3_RESET_N,
       MCCC_CLK_BASE,
       MCCC_CLK_BASE_PLL_LOCK,
       MDDR_APB_S_PCLK,
       MDDR_APB_S_PENABLE,
       MDDR_APB_S_PRESET_N,
       MDDR_APB_S_PSEL,
       MDDR_APB_S_PWRITE,
       MDDR_DDR_AXI_S_ARVALID,
       MDDR_DDR_AXI_S_AWVALID,
       MDDR_DDR_AXI_S_BREADY,
       MDDR_DDR_AXI_S_RMW,
       MDDR_DDR_AXI_S_RREADY,
       MDDR_DDR_AXI_S_WLAST,
       MDDR_DDR_AXI_S_WVALID,
       MDDR_DDR_CORE_RESET_N,
       MDDR_DQS_TMATCH_0_IN,
       MMUART_0_RXD,
       SPI_0_DI,
       FIC_0_AHB_S_HREADYOUT,
       FIC_0_AHB_S_HRESP,
       FIC_2_APB_M_PCLK,
       FIC_2_APB_M_PENABLE,
       FIC_2_APB_M_PRESET_N,
       FIC_2_APB_M_PSEL,
       FIC_2_APB_M_PWRITE,
       GPIO_0_M2F,
       GPIO_10_M2F,
       GPIO_1_M2F,
       GPIO_2_M2F,
       GPIO_3_M2F,
       GPIO_4_M2F,
       GPIO_8_M2F,
       GPIO_9_M2F,
       MDDR_APB_S_PREADY,
       MDDR_APB_S_PSLVERR,
       MDDR_CAS_N,
       MDDR_CKE,
       MDDR_CLK,
       MDDR_CLK_N,
       MDDR_CS_N,
       MDDR_DDR_AXI_S_ARREADY,
       MDDR_DDR_AXI_S_AWREADY,
       MDDR_DDR_AXI_S_BVALID,
       MDDR_DDR_AXI_S_RLAST,
       MDDR_DDR_AXI_S_RVALID,
       MDDR_DDR_AXI_S_WREADY,
       MDDR_DQS_TMATCH_0_OUT,
       MDDR_ODT,
       MDDR_RAS_N,
       MDDR_RESET_N,
       MDDR_WE_N,
       MMUART_0_TXD,
       MSS_RESET_N_M2F,
       SPI_0_DO,
       SPI_0_CLK,
       SPI_0_SS0
    );
input  [31:0] FIC_0_AHB_S_HADDR;
input  [1:0] FIC_0_AHB_S_HSIZE;
input  [1:0] FIC_0_AHB_S_HTRANS;
input  [31:0] FIC_0_AHB_S_HWDATA;
input  [31:0] FIC_2_APB_M_PRDATA;
input  [10:2] MDDR_APB_S_PADDR;
input  [15:0] MDDR_APB_S_PWDATA;
input  [31:0] MDDR_DDR_AXI_S_ARADDR;
input  [1:0] MDDR_DDR_AXI_S_ARBURST;
input  [3:0] MDDR_DDR_AXI_S_ARID;
input  [3:0] MDDR_DDR_AXI_S_ARLEN;
input  [1:0] MDDR_DDR_AXI_S_ARLOCK;
input  [1:0] MDDR_DDR_AXI_S_ARSIZE;
input  [31:0] MDDR_DDR_AXI_S_AWADDR;
input  [1:0] MDDR_DDR_AXI_S_AWBURST;
input  [3:0] MDDR_DDR_AXI_S_AWID;
input  [3:0] MDDR_DDR_AXI_S_AWLEN;
input  [1:0] MDDR_DDR_AXI_S_AWLOCK;
input  [1:0] MDDR_DDR_AXI_S_AWSIZE;
input  [63:0] MDDR_DDR_AXI_S_WDATA;
input  [3:0] MDDR_DDR_AXI_S_WID;
input  [7:0] MDDR_DDR_AXI_S_WSTRB;
output [31:0] FIC_0_AHB_S_HRDATA;
output [16:2] FIC_2_APB_M_PADDR;
output [31:0] FIC_2_APB_M_PWDATA;
output [15:0] MDDR_ADDR;
output [15:0] MDDR_APB_S_PRDATA;
output [2:0] MDDR_BA;
output [3:0] MDDR_DDR_AXI_S_BID;
output [1:0] MDDR_DDR_AXI_S_BRESP;
output [63:0] MDDR_DDR_AXI_S_RDATA;
output [3:0] MDDR_DDR_AXI_S_RID;
output [1:0] MDDR_DDR_AXI_S_RRESP;
inout  [1:0] MDDR_DM_RDQS;
inout  [15:0] MDDR_DQ;
inout  [1:0] MDDR_DQS;
inout  [1:0] MDDR_DQS_N;
input  FIC_0_AHB_S_HMASTLOCK;
input  FIC_0_AHB_S_HREADY;
input  FIC_0_AHB_S_HSEL;
input  FIC_0_AHB_S_HWRITE;
input  FIC_2_APB_M_PREADY;
input  FIC_2_APB_M_PSLVERR;
input  GPIO_11_F2M;
input  GPIO_12_F2M;
input  M3_RESET_N;
input  MCCC_CLK_BASE;
input  MCCC_CLK_BASE_PLL_LOCK;
input  MDDR_APB_S_PCLK;
input  MDDR_APB_S_PENABLE;
input  MDDR_APB_S_PRESET_N;
input  MDDR_APB_S_PSEL;
input  MDDR_APB_S_PWRITE;
input  MDDR_DDR_AXI_S_ARVALID;
input  MDDR_DDR_AXI_S_AWVALID;
input  MDDR_DDR_AXI_S_BREADY;
input  MDDR_DDR_AXI_S_RMW;
input  MDDR_DDR_AXI_S_RREADY;
input  MDDR_DDR_AXI_S_WLAST;
input  MDDR_DDR_AXI_S_WVALID;
input  MDDR_DDR_CORE_RESET_N;
input  MDDR_DQS_TMATCH_0_IN;
input  MMUART_0_RXD;
input  SPI_0_DI;
output FIC_0_AHB_S_HREADYOUT;
output FIC_0_AHB_S_HRESP;
output FIC_2_APB_M_PCLK;
output FIC_2_APB_M_PENABLE;
output FIC_2_APB_M_PRESET_N;
output FIC_2_APB_M_PSEL;
output FIC_2_APB_M_PWRITE;
output GPIO_0_M2F;
output GPIO_10_M2F;
output GPIO_1_M2F;
output GPIO_2_M2F;
output GPIO_3_M2F;
output GPIO_4_M2F;
output GPIO_8_M2F;
output GPIO_9_M2F;
output MDDR_APB_S_PREADY;
output MDDR_APB_S_PSLVERR;
output MDDR_CAS_N;
output MDDR_CKE;
output MDDR_CLK;
output MDDR_CLK_N;
output MDDR_CS_N;
output MDDR_DDR_AXI_S_ARREADY;
output MDDR_DDR_AXI_S_AWREADY;
output MDDR_DDR_AXI_S_BVALID;
output MDDR_DDR_AXI_S_RLAST;
output MDDR_DDR_AXI_S_RVALID;
output MDDR_DDR_AXI_S_WREADY;
output MDDR_DQS_TMATCH_0_OUT;
output MDDR_ODT;
output MDDR_RAS_N;
output MDDR_RESET_N;
output MDDR_WE_N;
output MMUART_0_TXD;
output MSS_RESET_N_M2F;
output SPI_0_DO;
inout  SPI_0_CLK;
inout  SPI_0_SS0;

    wire \DRAM_ADDR_net_0[0] , \DRAM_ADDR_net_0[1] , 
        \DRAM_ADDR_net_0[2] , \DRAM_ADDR_net_0[3] , 
        \DRAM_ADDR_net_0[4] , \DRAM_ADDR_net_0[5] , 
        \DRAM_ADDR_net_0[6] , \DRAM_ADDR_net_0[7] , 
        \DRAM_ADDR_net_0[8] , \DRAM_ADDR_net_0[9] , 
        \DRAM_ADDR_net_0[10] , \DRAM_ADDR_net_0[11] , 
        \DRAM_ADDR_net_0[12] , \DRAM_ADDR_net_0[13] , 
        \DRAM_ADDR_net_0[14] , \DRAM_ADDR_net_0[15] , 
        \DRAM_BA_net_0[0] , \DRAM_BA_net_0[1] , \DRAM_BA_net_0[2] , 
        MSS_ADLIB_INST_DRAM_CASN, MSS_ADLIB_INST_DRAM_CKE, 
        MSS_ADLIB_INST_DRAM_CLK, MSS_ADLIB_INST_DRAM_CSN, 
        MDDR_DM_RDQS_0_PAD_Y, MDDR_DM_RDQS_1_PAD_Y, MDDR_DQ_0_PAD_Y, 
        MDDR_DQ_1_PAD_Y, MDDR_DQ_2_PAD_Y, MDDR_DQ_3_PAD_Y, 
        MDDR_DQ_4_PAD_Y, MDDR_DQ_5_PAD_Y, MDDR_DQ_6_PAD_Y, 
        MDDR_DQ_7_PAD_Y, MDDR_DQ_8_PAD_Y, MDDR_DQ_9_PAD_Y, 
        MDDR_DQ_10_PAD_Y, MDDR_DQ_11_PAD_Y, MDDR_DQ_12_PAD_Y, 
        MDDR_DQ_13_PAD_Y, MDDR_DQ_14_PAD_Y, MDDR_DQ_15_PAD_Y, 
        MDDR_DQS_0_PAD_Y, MDDR_DQS_1_PAD_Y, MDDR_DQS_TMATCH_0_IN_PAD_Y, 
        MSS_ADLIB_INST_DRAM_ODT, MSS_ADLIB_INST_DRAM_RASN, 
        MSS_ADLIB_INST_DRAM_RSTN, MSS_ADLIB_INST_DRAM_WEN, 
        MMUART_0_RXD_PAD_Y, 
        MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OUT, VCC_net_1, 
        GND_net_1, SPI_0_CLK_PAD_Y, SPI_0_DI_PAD_Y, SPI_0_SS0_PAD_Y, 
        \DRAM_DM_RDQS_OUT_net_0[0] , \DRAM_DM_RDQS_OUT_net_0[1] , 
        \DRAM_DQ_OUT_net_0[0] , \DRAM_DQ_OUT_net_0[1] , 
        \DRAM_DQ_OUT_net_0[2] , \DRAM_DQ_OUT_net_0[3] , 
        \DRAM_DQ_OUT_net_0[4] , \DRAM_DQ_OUT_net_0[5] , 
        \DRAM_DQ_OUT_net_0[6] , \DRAM_DQ_OUT_net_0[7] , 
        \DRAM_DQ_OUT_net_0[8] , \DRAM_DQ_OUT_net_0[9] , 
        \DRAM_DQ_OUT_net_0[10] , \DRAM_DQ_OUT_net_0[11] , 
        \DRAM_DQ_OUT_net_0[12] , \DRAM_DQ_OUT_net_0[13] , 
        \DRAM_DQ_OUT_net_0[14] , \DRAM_DQ_OUT_net_0[15] , 
        \DRAM_DQS_OUT_net_0[0] , \DRAM_DQS_OUT_net_0[1] , 
        \DRAM_FIFO_WE_OUT_net_0[0] , 
        MSS_ADLIB_INST_SPI0_SCK_USBA_XCLK_OUT, 
        MSS_ADLIB_INST_SPI0_SDO_USBA_STP_MGPIO6A_OUT, 
        MSS_ADLIB_INST_SPI0_SS0_USBA_NXT_MGPIO7A_OUT, 
        \DRAM_DQS_OE_net_0[0] , \DRAM_DQS_OE_net_0[1] , 
        \FIC_0_AHB_S_HADDR_c[0] , \FIC_0_AHB_S_HADDR_c[1] , 
        \FIC_0_AHB_S_HADDR_c[2] , \FIC_0_AHB_S_HADDR_c[3] , 
        \FIC_0_AHB_S_HADDR_c[4] , \FIC_0_AHB_S_HADDR_c[5] , 
        \FIC_0_AHB_S_HADDR_c[6] , \FIC_0_AHB_S_HADDR_c[7] , 
        \FIC_0_AHB_S_HADDR_c[8] , \FIC_0_AHB_S_HADDR_c[9] , 
        \FIC_0_AHB_S_HADDR_c[10] , \FIC_0_AHB_S_HADDR_c[11] , 
        \FIC_0_AHB_S_HADDR_c[12] , \FIC_0_AHB_S_HADDR_c[13] , 
        \FIC_0_AHB_S_HADDR_c[14] , \FIC_0_AHB_S_HADDR_c[15] , 
        \FIC_0_AHB_S_HADDR_c[16] , \FIC_0_AHB_S_HADDR_c[17] , 
        \FIC_0_AHB_S_HADDR_c[18] , \FIC_0_AHB_S_HADDR_c[19] , 
        \FIC_0_AHB_S_HADDR_c[20] , \FIC_0_AHB_S_HADDR_c[21] , 
        \FIC_0_AHB_S_HADDR_c[22] , \FIC_0_AHB_S_HADDR_c[23] , 
        \FIC_0_AHB_S_HADDR_c[24] , \FIC_0_AHB_S_HADDR_c[25] , 
        \FIC_0_AHB_S_HADDR_c[26] , \FIC_0_AHB_S_HADDR_c[27] , 
        \FIC_0_AHB_S_HADDR_c[28] , \FIC_0_AHB_S_HADDR_c[29] , 
        \FIC_0_AHB_S_HADDR_c[30] , \FIC_0_AHB_S_HADDR_c[31] , 
        FIC_0_AHB_S_HMASTLOCK_c, FIC_0_AHB_S_HREADY_c, 
        FIC_0_AHB_S_HSEL_c, \FIC_0_AHB_S_HSIZE_c[0] , 
        \FIC_0_AHB_S_HSIZE_c[1] , \FIC_0_AHB_S_HTRANS_c[1] , 
        \FIC_0_AHB_S_HWDATA_c[0] , \FIC_0_AHB_S_HWDATA_c[1] , 
        \FIC_0_AHB_S_HWDATA_c[2] , \FIC_0_AHB_S_HWDATA_c[3] , 
        \FIC_0_AHB_S_HWDATA_c[4] , \FIC_0_AHB_S_HWDATA_c[5] , 
        \FIC_0_AHB_S_HWDATA_c[6] , \FIC_0_AHB_S_HWDATA_c[7] , 
        \FIC_0_AHB_S_HWDATA_c[8] , \FIC_0_AHB_S_HWDATA_c[9] , 
        \FIC_0_AHB_S_HWDATA_c[10] , \FIC_0_AHB_S_HWDATA_c[11] , 
        \FIC_0_AHB_S_HWDATA_c[12] , \FIC_0_AHB_S_HWDATA_c[13] , 
        \FIC_0_AHB_S_HWDATA_c[14] , \FIC_0_AHB_S_HWDATA_c[15] , 
        \FIC_0_AHB_S_HWDATA_c[16] , \FIC_0_AHB_S_HWDATA_c[17] , 
        \FIC_0_AHB_S_HWDATA_c[18] , \FIC_0_AHB_S_HWDATA_c[19] , 
        \FIC_0_AHB_S_HWDATA_c[20] , \FIC_0_AHB_S_HWDATA_c[21] , 
        \FIC_0_AHB_S_HWDATA_c[22] , \FIC_0_AHB_S_HWDATA_c[23] , 
        \FIC_0_AHB_S_HWDATA_c[24] , \FIC_0_AHB_S_HWDATA_c[25] , 
        \FIC_0_AHB_S_HWDATA_c[26] , \FIC_0_AHB_S_HWDATA_c[27] , 
        \FIC_0_AHB_S_HWDATA_c[28] , \FIC_0_AHB_S_HWDATA_c[29] , 
        \FIC_0_AHB_S_HWDATA_c[30] , \FIC_0_AHB_S_HWDATA_c[31] , 
        FIC_0_AHB_S_HWRITE_c, \FIC_2_APB_M_PRDATA_c[0] , 
        \FIC_2_APB_M_PRDATA_c[1] , \FIC_2_APB_M_PRDATA_c[2] , 
        \FIC_2_APB_M_PRDATA_c[3] , \FIC_2_APB_M_PRDATA_c[4] , 
        \FIC_2_APB_M_PRDATA_c[5] , \FIC_2_APB_M_PRDATA_c[6] , 
        \FIC_2_APB_M_PRDATA_c[7] , \FIC_2_APB_M_PRDATA_c[8] , 
        \FIC_2_APB_M_PRDATA_c[9] , \FIC_2_APB_M_PRDATA_c[10] , 
        \FIC_2_APB_M_PRDATA_c[11] , \FIC_2_APB_M_PRDATA_c[12] , 
        \FIC_2_APB_M_PRDATA_c[13] , \FIC_2_APB_M_PRDATA_c[14] , 
        \FIC_2_APB_M_PRDATA_c[15] , \FIC_2_APB_M_PRDATA_c[16] , 
        \FIC_2_APB_M_PRDATA_c[17] , \FIC_2_APB_M_PRDATA_c[18] , 
        \FIC_2_APB_M_PRDATA_c[19] , \FIC_2_APB_M_PRDATA_c[20] , 
        \FIC_2_APB_M_PRDATA_c[21] , \FIC_2_APB_M_PRDATA_c[22] , 
        \FIC_2_APB_M_PRDATA_c[23] , \FIC_2_APB_M_PRDATA_c[24] , 
        \FIC_2_APB_M_PRDATA_c[25] , \FIC_2_APB_M_PRDATA_c[26] , 
        \FIC_2_APB_M_PRDATA_c[27] , \FIC_2_APB_M_PRDATA_c[28] , 
        \FIC_2_APB_M_PRDATA_c[29] , \FIC_2_APB_M_PRDATA_c[30] , 
        \FIC_2_APB_M_PRDATA_c[31] , FIC_2_APB_M_PREADY_c, 
        FIC_2_APB_M_PSLVERR_c, GPIO_11_F2M_c, GPIO_12_F2M_c, 
        M3_RESET_N_c, MCCC_CLK_BASE_c, MCCC_CLK_BASE_PLL_LOCK_c, 
        \MDDR_APB_S_PADDR_c[2] , \MDDR_APB_S_PADDR_c[3] , 
        \MDDR_APB_S_PADDR_c[4] , \MDDR_APB_S_PADDR_c[5] , 
        \MDDR_APB_S_PADDR_c[6] , \MDDR_APB_S_PADDR_c[7] , 
        \MDDR_APB_S_PADDR_c[8] , \MDDR_APB_S_PADDR_c[9] , 
        \MDDR_APB_S_PADDR_c[10] , MDDR_APB_S_PCLK_c, 
        MDDR_APB_S_PENABLE_c, MDDR_APB_S_PRESET_N_c, MDDR_APB_S_PSEL_c, 
        \MDDR_APB_S_PWDATA_c[0] , \MDDR_APB_S_PWDATA_c[1] , 
        \MDDR_APB_S_PWDATA_c[2] , \MDDR_APB_S_PWDATA_c[3] , 
        \MDDR_APB_S_PWDATA_c[4] , \MDDR_APB_S_PWDATA_c[5] , 
        \MDDR_APB_S_PWDATA_c[6] , \MDDR_APB_S_PWDATA_c[7] , 
        \MDDR_APB_S_PWDATA_c[8] , \MDDR_APB_S_PWDATA_c[9] , 
        \MDDR_APB_S_PWDATA_c[10] , \MDDR_APB_S_PWDATA_c[11] , 
        \MDDR_APB_S_PWDATA_c[12] , \MDDR_APB_S_PWDATA_c[13] , 
        \MDDR_APB_S_PWDATA_c[14] , \MDDR_APB_S_PWDATA_c[15] , 
        MDDR_APB_S_PWRITE_c, \MDDR_DDR_AXI_S_ARADDR_c[0] , 
        \MDDR_DDR_AXI_S_ARADDR_c[1] , \MDDR_DDR_AXI_S_ARADDR_c[2] , 
        \MDDR_DDR_AXI_S_ARADDR_c[3] , \MDDR_DDR_AXI_S_ARADDR_c[4] , 
        \MDDR_DDR_AXI_S_ARADDR_c[5] , \MDDR_DDR_AXI_S_ARADDR_c[6] , 
        \MDDR_DDR_AXI_S_ARADDR_c[7] , \MDDR_DDR_AXI_S_ARADDR_c[8] , 
        \MDDR_DDR_AXI_S_ARADDR_c[9] , \MDDR_DDR_AXI_S_ARADDR_c[10] , 
        \MDDR_DDR_AXI_S_ARADDR_c[11] , \MDDR_DDR_AXI_S_ARADDR_c[12] , 
        \MDDR_DDR_AXI_S_ARADDR_c[13] , \MDDR_DDR_AXI_S_ARADDR_c[14] , 
        \MDDR_DDR_AXI_S_ARADDR_c[15] , \MDDR_DDR_AXI_S_ARADDR_c[16] , 
        \MDDR_DDR_AXI_S_ARADDR_c[17] , \MDDR_DDR_AXI_S_ARADDR_c[18] , 
        \MDDR_DDR_AXI_S_ARADDR_c[19] , \MDDR_DDR_AXI_S_ARADDR_c[20] , 
        \MDDR_DDR_AXI_S_ARADDR_c[21] , \MDDR_DDR_AXI_S_ARADDR_c[22] , 
        \MDDR_DDR_AXI_S_ARADDR_c[23] , \MDDR_DDR_AXI_S_ARADDR_c[24] , 
        \MDDR_DDR_AXI_S_ARADDR_c[25] , \MDDR_DDR_AXI_S_ARADDR_c[26] , 
        \MDDR_DDR_AXI_S_ARADDR_c[27] , \MDDR_DDR_AXI_S_ARADDR_c[28] , 
        \MDDR_DDR_AXI_S_ARADDR_c[29] , \MDDR_DDR_AXI_S_ARADDR_c[30] , 
        \MDDR_DDR_AXI_S_ARADDR_c[31] , \MDDR_DDR_AXI_S_ARBURST_c[0] , 
        \MDDR_DDR_AXI_S_ARBURST_c[1] , \MDDR_DDR_AXI_S_ARID_c[0] , 
        \MDDR_DDR_AXI_S_ARID_c[1] , \MDDR_DDR_AXI_S_ARID_c[2] , 
        \MDDR_DDR_AXI_S_ARID_c[3] , \MDDR_DDR_AXI_S_ARLEN_c[0] , 
        \MDDR_DDR_AXI_S_ARLEN_c[1] , \MDDR_DDR_AXI_S_ARLEN_c[2] , 
        \MDDR_DDR_AXI_S_ARLEN_c[3] , \MDDR_DDR_AXI_S_ARLOCK_c[0] , 
        \MDDR_DDR_AXI_S_ARLOCK_c[1] , \MDDR_DDR_AXI_S_ARSIZE_c[0] , 
        \MDDR_DDR_AXI_S_ARSIZE_c[1] , MDDR_DDR_AXI_S_ARVALID_c, 
        \MDDR_DDR_AXI_S_AWADDR_c[0] , \MDDR_DDR_AXI_S_AWADDR_c[1] , 
        \MDDR_DDR_AXI_S_AWADDR_c[2] , \MDDR_DDR_AXI_S_AWADDR_c[3] , 
        \MDDR_DDR_AXI_S_AWADDR_c[4] , \MDDR_DDR_AXI_S_AWADDR_c[5] , 
        \MDDR_DDR_AXI_S_AWADDR_c[6] , \MDDR_DDR_AXI_S_AWADDR_c[7] , 
        \MDDR_DDR_AXI_S_AWADDR_c[8] , \MDDR_DDR_AXI_S_AWADDR_c[9] , 
        \MDDR_DDR_AXI_S_AWADDR_c[10] , \MDDR_DDR_AXI_S_AWADDR_c[11] , 
        \MDDR_DDR_AXI_S_AWADDR_c[12] , \MDDR_DDR_AXI_S_AWADDR_c[13] , 
        \MDDR_DDR_AXI_S_AWADDR_c[14] , \MDDR_DDR_AXI_S_AWADDR_c[15] , 
        \MDDR_DDR_AXI_S_AWADDR_c[16] , \MDDR_DDR_AXI_S_AWADDR_c[17] , 
        \MDDR_DDR_AXI_S_AWADDR_c[18] , \MDDR_DDR_AXI_S_AWADDR_c[19] , 
        \MDDR_DDR_AXI_S_AWADDR_c[20] , \MDDR_DDR_AXI_S_AWADDR_c[21] , 
        \MDDR_DDR_AXI_S_AWADDR_c[22] , \MDDR_DDR_AXI_S_AWADDR_c[23] , 
        \MDDR_DDR_AXI_S_AWADDR_c[24] , \MDDR_DDR_AXI_S_AWADDR_c[25] , 
        \MDDR_DDR_AXI_S_AWADDR_c[26] , \MDDR_DDR_AXI_S_AWADDR_c[27] , 
        \MDDR_DDR_AXI_S_AWADDR_c[28] , \MDDR_DDR_AXI_S_AWADDR_c[29] , 
        \MDDR_DDR_AXI_S_AWADDR_c[30] , \MDDR_DDR_AXI_S_AWADDR_c[31] , 
        \MDDR_DDR_AXI_S_AWBURST_c[0] , \MDDR_DDR_AXI_S_AWBURST_c[1] , 
        \MDDR_DDR_AXI_S_AWID_c[0] , \MDDR_DDR_AXI_S_AWID_c[1] , 
        \MDDR_DDR_AXI_S_AWID_c[2] , \MDDR_DDR_AXI_S_AWID_c[3] , 
        \MDDR_DDR_AXI_S_AWLEN_c[0] , \MDDR_DDR_AXI_S_AWLEN_c[1] , 
        \MDDR_DDR_AXI_S_AWLEN_c[2] , \MDDR_DDR_AXI_S_AWLEN_c[3] , 
        \MDDR_DDR_AXI_S_AWLOCK_c[0] , \MDDR_DDR_AXI_S_AWLOCK_c[1] , 
        \MDDR_DDR_AXI_S_AWSIZE_c[0] , \MDDR_DDR_AXI_S_AWSIZE_c[1] , 
        MDDR_DDR_AXI_S_AWVALID_c, MDDR_DDR_AXI_S_BREADY_c, 
        MDDR_DDR_AXI_S_RMW_c, MDDR_DDR_AXI_S_RREADY_c, 
        \MDDR_DDR_AXI_S_WDATA_c[0] , \MDDR_DDR_AXI_S_WDATA_c[1] , 
        \MDDR_DDR_AXI_S_WDATA_c[2] , \MDDR_DDR_AXI_S_WDATA_c[3] , 
        \MDDR_DDR_AXI_S_WDATA_c[4] , \MDDR_DDR_AXI_S_WDATA_c[5] , 
        \MDDR_DDR_AXI_S_WDATA_c[6] , \MDDR_DDR_AXI_S_WDATA_c[7] , 
        \MDDR_DDR_AXI_S_WDATA_c[8] , \MDDR_DDR_AXI_S_WDATA_c[9] , 
        \MDDR_DDR_AXI_S_WDATA_c[10] , \MDDR_DDR_AXI_S_WDATA_c[11] , 
        \MDDR_DDR_AXI_S_WDATA_c[12] , \MDDR_DDR_AXI_S_WDATA_c[13] , 
        \MDDR_DDR_AXI_S_WDATA_c[14] , \MDDR_DDR_AXI_S_WDATA_c[15] , 
        \MDDR_DDR_AXI_S_WDATA_c[16] , \MDDR_DDR_AXI_S_WDATA_c[17] , 
        \MDDR_DDR_AXI_S_WDATA_c[18] , \MDDR_DDR_AXI_S_WDATA_c[19] , 
        \MDDR_DDR_AXI_S_WDATA_c[20] , \MDDR_DDR_AXI_S_WDATA_c[21] , 
        \MDDR_DDR_AXI_S_WDATA_c[22] , \MDDR_DDR_AXI_S_WDATA_c[23] , 
        \MDDR_DDR_AXI_S_WDATA_c[24] , \MDDR_DDR_AXI_S_WDATA_c[25] , 
        \MDDR_DDR_AXI_S_WDATA_c[26] , \MDDR_DDR_AXI_S_WDATA_c[27] , 
        \MDDR_DDR_AXI_S_WDATA_c[28] , \MDDR_DDR_AXI_S_WDATA_c[29] , 
        \MDDR_DDR_AXI_S_WDATA_c[30] , \MDDR_DDR_AXI_S_WDATA_c[31] , 
        \MDDR_DDR_AXI_S_WDATA_c[32] , \MDDR_DDR_AXI_S_WDATA_c[33] , 
        \MDDR_DDR_AXI_S_WDATA_c[34] , \MDDR_DDR_AXI_S_WDATA_c[35] , 
        \MDDR_DDR_AXI_S_WDATA_c[36] , \MDDR_DDR_AXI_S_WDATA_c[37] , 
        \MDDR_DDR_AXI_S_WDATA_c[38] , \MDDR_DDR_AXI_S_WDATA_c[39] , 
        \MDDR_DDR_AXI_S_WDATA_c[40] , \MDDR_DDR_AXI_S_WDATA_c[41] , 
        \MDDR_DDR_AXI_S_WDATA_c[42] , \MDDR_DDR_AXI_S_WDATA_c[43] , 
        \MDDR_DDR_AXI_S_WDATA_c[44] , \MDDR_DDR_AXI_S_WDATA_c[45] , 
        \MDDR_DDR_AXI_S_WDATA_c[46] , \MDDR_DDR_AXI_S_WDATA_c[47] , 
        \MDDR_DDR_AXI_S_WDATA_c[48] , \MDDR_DDR_AXI_S_WDATA_c[49] , 
        \MDDR_DDR_AXI_S_WDATA_c[50] , \MDDR_DDR_AXI_S_WDATA_c[51] , 
        \MDDR_DDR_AXI_S_WDATA_c[52] , \MDDR_DDR_AXI_S_WDATA_c[53] , 
        \MDDR_DDR_AXI_S_WDATA_c[54] , \MDDR_DDR_AXI_S_WDATA_c[55] , 
        \MDDR_DDR_AXI_S_WDATA_c[56] , \MDDR_DDR_AXI_S_WDATA_c[57] , 
        \MDDR_DDR_AXI_S_WDATA_c[58] , \MDDR_DDR_AXI_S_WDATA_c[59] , 
        \MDDR_DDR_AXI_S_WDATA_c[60] , \MDDR_DDR_AXI_S_WDATA_c[61] , 
        \MDDR_DDR_AXI_S_WDATA_c[62] , \MDDR_DDR_AXI_S_WDATA_c[63] , 
        \MDDR_DDR_AXI_S_WID_c[0] , \MDDR_DDR_AXI_S_WID_c[1] , 
        \MDDR_DDR_AXI_S_WID_c[2] , \MDDR_DDR_AXI_S_WID_c[3] , 
        MDDR_DDR_AXI_S_WLAST_c, \MDDR_DDR_AXI_S_WSTRB_c[0] , 
        \MDDR_DDR_AXI_S_WSTRB_c[1] , \MDDR_DDR_AXI_S_WSTRB_c[2] , 
        \MDDR_DDR_AXI_S_WSTRB_c[3] , \MDDR_DDR_AXI_S_WSTRB_c[4] , 
        \MDDR_DDR_AXI_S_WSTRB_c[5] , \MDDR_DDR_AXI_S_WSTRB_c[6] , 
        \MDDR_DDR_AXI_S_WSTRB_c[7] , MDDR_DDR_AXI_S_WVALID_c, 
        MDDR_DDR_CORE_RESET_N_c, \FIC_0_AHB_S_HRDATA_c[0] , 
        \FIC_0_AHB_S_HRDATA_c[1] , \FIC_0_AHB_S_HRDATA_c[2] , 
        \FIC_0_AHB_S_HRDATA_c[3] , \FIC_0_AHB_S_HRDATA_c[4] , 
        \FIC_0_AHB_S_HRDATA_c[5] , \FIC_0_AHB_S_HRDATA_c[6] , 
        \FIC_0_AHB_S_HRDATA_c[7] , \FIC_0_AHB_S_HRDATA_c[8] , 
        \FIC_0_AHB_S_HRDATA_c[9] , \FIC_0_AHB_S_HRDATA_c[10] , 
        \FIC_0_AHB_S_HRDATA_c[11] , \FIC_0_AHB_S_HRDATA_c[12] , 
        \FIC_0_AHB_S_HRDATA_c[13] , \FIC_0_AHB_S_HRDATA_c[14] , 
        \FIC_0_AHB_S_HRDATA_c[15] , \FIC_0_AHB_S_HRDATA_c[16] , 
        \FIC_0_AHB_S_HRDATA_c[17] , \FIC_0_AHB_S_HRDATA_c[18] , 
        \FIC_0_AHB_S_HRDATA_c[19] , \FIC_0_AHB_S_HRDATA_c[20] , 
        \FIC_0_AHB_S_HRDATA_c[21] , \FIC_0_AHB_S_HRDATA_c[22] , 
        \FIC_0_AHB_S_HRDATA_c[23] , \FIC_0_AHB_S_HRDATA_c[24] , 
        \FIC_0_AHB_S_HRDATA_c[25] , \FIC_0_AHB_S_HRDATA_c[26] , 
        \FIC_0_AHB_S_HRDATA_c[27] , \FIC_0_AHB_S_HRDATA_c[28] , 
        \FIC_0_AHB_S_HRDATA_c[29] , \FIC_0_AHB_S_HRDATA_c[30] , 
        \FIC_0_AHB_S_HRDATA_c[31] , FIC_0_AHB_S_HREADYOUT_c, 
        FIC_0_AHB_S_HRESP_c, \FIC_2_APB_M_PADDR_c[2] , 
        \FIC_2_APB_M_PADDR_c[3] , \FIC_2_APB_M_PADDR_c[4] , 
        \FIC_2_APB_M_PADDR_c[5] , \FIC_2_APB_M_PADDR_c[6] , 
        \FIC_2_APB_M_PADDR_c[7] , \FIC_2_APB_M_PADDR_c[8] , 
        \FIC_2_APB_M_PADDR_c[9] , \FIC_2_APB_M_PADDR_c[10] , 
        \FIC_2_APB_M_PADDR_c[11] , \FIC_2_APB_M_PADDR_c[12] , 
        \FIC_2_APB_M_PADDR_c[13] , \FIC_2_APB_M_PADDR_c[14] , 
        \FIC_2_APB_M_PADDR_c[15] , \FIC_2_APB_M_PADDR_c[16] , 
        FIC_2_APB_M_PCLK_c, FIC_2_APB_M_PENABLE_c, 
        FIC_2_APB_M_PRESET_N_c, FIC_2_APB_M_PSEL_c, 
        \FIC_2_APB_M_PWDATA_c[0] , \FIC_2_APB_M_PWDATA_c[1] , 
        \FIC_2_APB_M_PWDATA_c[2] , \FIC_2_APB_M_PWDATA_c[3] , 
        \FIC_2_APB_M_PWDATA_c[4] , \FIC_2_APB_M_PWDATA_c[5] , 
        \FIC_2_APB_M_PWDATA_c[6] , \FIC_2_APB_M_PWDATA_c[7] , 
        \FIC_2_APB_M_PWDATA_c[8] , \FIC_2_APB_M_PWDATA_c[9] , 
        \FIC_2_APB_M_PWDATA_c[10] , \FIC_2_APB_M_PWDATA_c[11] , 
        \FIC_2_APB_M_PWDATA_c[12] , \FIC_2_APB_M_PWDATA_c[13] , 
        \FIC_2_APB_M_PWDATA_c[14] , \FIC_2_APB_M_PWDATA_c[15] , 
        \FIC_2_APB_M_PWDATA_c[16] , \FIC_2_APB_M_PWDATA_c[17] , 
        \FIC_2_APB_M_PWDATA_c[18] , \FIC_2_APB_M_PWDATA_c[19] , 
        \FIC_2_APB_M_PWDATA_c[20] , \FIC_2_APB_M_PWDATA_c[21] , 
        \FIC_2_APB_M_PWDATA_c[22] , \FIC_2_APB_M_PWDATA_c[23] , 
        \FIC_2_APB_M_PWDATA_c[24] , \FIC_2_APB_M_PWDATA_c[25] , 
        \FIC_2_APB_M_PWDATA_c[26] , \FIC_2_APB_M_PWDATA_c[27] , 
        \FIC_2_APB_M_PWDATA_c[28] , \FIC_2_APB_M_PWDATA_c[29] , 
        \FIC_2_APB_M_PWDATA_c[30] , \FIC_2_APB_M_PWDATA_c[31] , 
        FIC_2_APB_M_PWRITE_c, GPIO_0_M2F_c, GPIO_10_M2F_c, 
        GPIO_1_M2F_c, GPIO_2_M2F_c, GPIO_3_M2F_c, GPIO_4_M2F_c, 
        GPIO_8_M2F_c, GPIO_9_M2F_c, \MDDR_APB_S_PRDATA_c[0] , 
        \MDDR_APB_S_PRDATA_c[1] , \MDDR_APB_S_PRDATA_c[2] , 
        \MDDR_APB_S_PRDATA_c[3] , \MDDR_APB_S_PRDATA_c[4] , 
        \MDDR_APB_S_PRDATA_c[5] , \MDDR_APB_S_PRDATA_c[6] , 
        \MDDR_APB_S_PRDATA_c[7] , \MDDR_APB_S_PRDATA_c[8] , 
        \MDDR_APB_S_PRDATA_c[9] , \MDDR_APB_S_PRDATA_c[10] , 
        \MDDR_APB_S_PRDATA_c[11] , \MDDR_APB_S_PRDATA_c[12] , 
        \MDDR_APB_S_PRDATA_c[13] , \MDDR_APB_S_PRDATA_c[14] , 
        \MDDR_APB_S_PRDATA_c[15] , MDDR_APB_S_PREADY_c, 
        MDDR_APB_S_PSLVERR_c, MDDR_DDR_AXI_S_ARREADY_c, 
        MDDR_DDR_AXI_S_AWREADY_c, \MDDR_DDR_AXI_S_BID_c[0] , 
        \MDDR_DDR_AXI_S_BID_c[1] , \MDDR_DDR_AXI_S_BID_c[2] , 
        \MDDR_DDR_AXI_S_BID_c[3] , \MDDR_DDR_AXI_S_BRESP_c[0] , 
        \MDDR_DDR_AXI_S_BRESP_c[1] , MDDR_DDR_AXI_S_BVALID_c, 
        \MDDR_DDR_AXI_S_RDATA_c[0] , \MDDR_DDR_AXI_S_RDATA_c[1] , 
        \MDDR_DDR_AXI_S_RDATA_c[2] , \MDDR_DDR_AXI_S_RDATA_c[3] , 
        \MDDR_DDR_AXI_S_RDATA_c[4] , \MDDR_DDR_AXI_S_RDATA_c[5] , 
        \MDDR_DDR_AXI_S_RDATA_c[6] , \MDDR_DDR_AXI_S_RDATA_c[7] , 
        \MDDR_DDR_AXI_S_RDATA_c[8] , \MDDR_DDR_AXI_S_RDATA_c[9] , 
        \MDDR_DDR_AXI_S_RDATA_c[10] , \MDDR_DDR_AXI_S_RDATA_c[11] , 
        \MDDR_DDR_AXI_S_RDATA_c[12] , \MDDR_DDR_AXI_S_RDATA_c[13] , 
        \MDDR_DDR_AXI_S_RDATA_c[14] , \MDDR_DDR_AXI_S_RDATA_c[15] , 
        \MDDR_DDR_AXI_S_RDATA_c[16] , \MDDR_DDR_AXI_S_RDATA_c[17] , 
        \MDDR_DDR_AXI_S_RDATA_c[18] , \MDDR_DDR_AXI_S_RDATA_c[19] , 
        \MDDR_DDR_AXI_S_RDATA_c[20] , \MDDR_DDR_AXI_S_RDATA_c[21] , 
        \MDDR_DDR_AXI_S_RDATA_c[22] , \MDDR_DDR_AXI_S_RDATA_c[23] , 
        \MDDR_DDR_AXI_S_RDATA_c[24] , \MDDR_DDR_AXI_S_RDATA_c[25] , 
        \MDDR_DDR_AXI_S_RDATA_c[26] , \MDDR_DDR_AXI_S_RDATA_c[27] , 
        \MDDR_DDR_AXI_S_RDATA_c[28] , \MDDR_DDR_AXI_S_RDATA_c[29] , 
        \MDDR_DDR_AXI_S_RDATA_c[30] , \MDDR_DDR_AXI_S_RDATA_c[31] , 
        \MDDR_DDR_AXI_S_RDATA_c[32] , \MDDR_DDR_AXI_S_RDATA_c[33] , 
        \MDDR_DDR_AXI_S_RDATA_c[34] , \MDDR_DDR_AXI_S_RDATA_c[35] , 
        \MDDR_DDR_AXI_S_RDATA_c[36] , \MDDR_DDR_AXI_S_RDATA_c[37] , 
        \MDDR_DDR_AXI_S_RDATA_c[38] , \MDDR_DDR_AXI_S_RDATA_c[39] , 
        \MDDR_DDR_AXI_S_RDATA_c[40] , \MDDR_DDR_AXI_S_RDATA_c[41] , 
        \MDDR_DDR_AXI_S_RDATA_c[42] , \MDDR_DDR_AXI_S_RDATA_c[43] , 
        \MDDR_DDR_AXI_S_RDATA_c[44] , \MDDR_DDR_AXI_S_RDATA_c[45] , 
        \MDDR_DDR_AXI_S_RDATA_c[46] , \MDDR_DDR_AXI_S_RDATA_c[47] , 
        \MDDR_DDR_AXI_S_RDATA_c[48] , \MDDR_DDR_AXI_S_RDATA_c[49] , 
        \MDDR_DDR_AXI_S_RDATA_c[50] , \MDDR_DDR_AXI_S_RDATA_c[51] , 
        \MDDR_DDR_AXI_S_RDATA_c[52] , \MDDR_DDR_AXI_S_RDATA_c[53] , 
        \MDDR_DDR_AXI_S_RDATA_c[54] , \MDDR_DDR_AXI_S_RDATA_c[55] , 
        \MDDR_DDR_AXI_S_RDATA_c[56] , \MDDR_DDR_AXI_S_RDATA_c[57] , 
        \MDDR_DDR_AXI_S_RDATA_c[58] , \MDDR_DDR_AXI_S_RDATA_c[59] , 
        \MDDR_DDR_AXI_S_RDATA_c[60] , \MDDR_DDR_AXI_S_RDATA_c[61] , 
        \MDDR_DDR_AXI_S_RDATA_c[62] , \MDDR_DDR_AXI_S_RDATA_c[63] , 
        \MDDR_DDR_AXI_S_RID_c[0] , \MDDR_DDR_AXI_S_RID_c[1] , 
        \MDDR_DDR_AXI_S_RID_c[2] , \MDDR_DDR_AXI_S_RID_c[3] , 
        MDDR_DDR_AXI_S_RLAST_c, \MDDR_DDR_AXI_S_RRESP_c[0] , 
        \MDDR_DDR_AXI_S_RRESP_c[1] , MDDR_DDR_AXI_S_RVALID_c, 
        MDDR_DDR_AXI_S_WREADY_c, MSS_RESET_N_M2F_c, \DM_OE_net_0[0] , 
        \DM_OE_net_0[1] , \DRAM_DQ_OE_net_0[0] , \DRAM_DQ_OE_net_0[1] , 
        \DRAM_DQ_OE_net_0[2] , \DRAM_DQ_OE_net_0[3] , 
        \DRAM_DQ_OE_net_0[4] , \DRAM_DQ_OE_net_0[5] , 
        \DRAM_DQ_OE_net_0[6] , \DRAM_DQ_OE_net_0[7] , 
        \DRAM_DQ_OE_net_0[8] , \DRAM_DQ_OE_net_0[9] , 
        \DRAM_DQ_OE_net_0[10] , \DRAM_DQ_OE_net_0[11] , 
        \DRAM_DQ_OE_net_0[12] , \DRAM_DQ_OE_net_0[13] , 
        \DRAM_DQ_OE_net_0[14] , \DRAM_DQ_OE_net_0[15] , 
        MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OE, 
        MSS_ADLIB_INST_SPI0_SCK_USBA_XCLK_OE, 
        MSS_ADLIB_INST_SPI0_SDO_USBA_STP_MGPIO6A_OE, 
        MSS_ADLIB_INST_SPI0_SS0_USBA_NXT_MGPIO7A_OE;
    
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[3]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[3]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[3] ));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[18]  (.PAD(FIC_2_APB_M_PRDATA[18]), 
        .Y(\FIC_2_APB_M_PRDATA_c[18] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[52]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[52] ), .PAD(MDDR_DDR_AXI_S_RDATA[52]));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_11_PAD (.D(
        \DRAM_ADDR_net_0[11] ), .PAD(MDDR_ADDR[11]));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[5]  (.D(\FIC_0_AHB_S_HRDATA_c[5] ), 
        .PAD(FIC_0_AHB_S_HRDATA[5]));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[6]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[6]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[6] ));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[25]  (.D(
        \FIC_0_AHB_S_HRDATA_c[25] ), .PAD(FIC_0_AHB_S_HRDATA[25]));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[30]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[30]), .Y(\MDDR_DDR_AXI_S_WDATA_c[30] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[7]  (.PAD(MDDR_DDR_AXI_S_WDATA[7])
        , .Y(\MDDR_DDR_AXI_S_WDATA_c[7] ));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[11]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[11]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[11] ));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[7]  (.PAD(FIC_0_AHB_S_HADDR[7]), .Y(
        \FIC_0_AHB_S_HADDR_c[7] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[59]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[59]), .Y(\MDDR_DDR_AXI_S_WDATA_c[59] ));
    OUTBUF \MDDR_APB_S_PRDATA_obuf[1]  (.D(\MDDR_APB_S_PRDATA_c[1] ), 
        .PAD(MDDR_APB_S_PRDATA[1]));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[13]  (.D(
        \FIC_0_AHB_S_HRDATA_c[13] ), .PAD(FIC_0_AHB_S_HRDATA[13]));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[61]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[61]), .Y(\MDDR_DDR_AXI_S_WDATA_c[61] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[26]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[26]), .Y(\MDDR_DDR_AXI_S_WDATA_c[26] ));
    INBUF MCCC_CLK_BASE_PLL_LOCK_ibuf (.PAD(MCCC_CLK_BASE_PLL_LOCK), 
        .Y(MCCC_CLK_BASE_PLL_LOCK_c));
    INBUF MDDR_DDR_AXI_S_RMW_ibuf (.PAD(MDDR_DDR_AXI_S_RMW), .Y(
        MDDR_DDR_AXI_S_RMW_c));
    INBUF \MDDR_APB_S_PWDATA_ibuf[9]  (.PAD(MDDR_APB_S_PWDATA[9]), .Y(
        \MDDR_APB_S_PWDATA_c[9] ));
    OUTBUF GPIO_8_M2F_obuf (.D(GPIO_8_M2F_c), .PAD(GPIO_8_M2F));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[21]  (.PAD(FIC_0_AHB_S_HWDATA[21]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[21] ));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[24]  (.D(
        \FIC_0_AHB_S_HRDATA_c[24] ), .PAD(FIC_0_AHB_S_HRDATA[24]));
    INBUF MCCC_CLK_BASE_ibuf (.PAD(MCCC_CLK_BASE), .Y(MCCC_CLK_BASE_c));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[30]  (.PAD(FIC_2_APB_M_PRDATA[30]), 
        .Y(\FIC_2_APB_M_PRDATA_c[30] ));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[7]  (.D(\FIC_0_AHB_S_HRDATA_c[7] ), 
        .PAD(FIC_0_AHB_S_HRDATA[7]));
    OUTBUF \MDDR_APB_S_PRDATA_obuf[5]  (.D(\MDDR_APB_S_PRDATA_c[5] ), 
        .PAD(MDDR_APB_S_PRDATA[5]));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_10_PAD (.PAD(MDDR_DQ[10]), 
        .D(\DRAM_DQ_OUT_net_0[10] ), .E(\DRAM_DQ_OE_net_0[10] ), .Y(
        MDDR_DQ_10_PAD_Y));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[29]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[29]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[29] ));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[20]  (.D(
        \FIC_2_APB_M_PWDATA_c[20] ), .PAD(FIC_2_APB_M_PWDATA[20]));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[2]  (.PAD(MDDR_DDR_AXI_S_WDATA[2])
        , .Y(\MDDR_DDR_AXI_S_WDATA_c[2] ));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[10]  (.PAD(FIC_0_AHB_S_HADDR[10]), 
        .Y(\FIC_0_AHB_S_HADDR_c[10] ));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[1]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[1]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[1] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[0]  (.PAD(MDDR_DDR_AXI_S_WDATA[0])
        , .Y(\MDDR_DDR_AXI_S_WDATA_c[0] ));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[24]  (.PAD(FIC_2_APB_M_PRDATA[24]), 
        .Y(\FIC_2_APB_M_PRDATA_c[24] ));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_BA_0_PAD (.D(
        \DRAM_BA_net_0[0] ), .PAD(MDDR_BA[0]));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[24]  (.D(
        \FIC_2_APB_M_PWDATA_c[24] ), .PAD(FIC_2_APB_M_PWDATA[24]));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[10]  (.D(
        \FIC_2_APB_M_PWDATA_c[10] ), .PAD(FIC_2_APB_M_PWDATA[10]));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[29]  (.PAD(FIC_0_AHB_S_HWDATA[29]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[29] ));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[15]  (.PAD(FIC_0_AHB_S_HWDATA[15]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[15] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[34]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[34] ), .PAD(MDDR_DDR_AXI_S_RDATA[34]));
    OUTBUF \MDDR_APB_S_PRDATA_obuf[9]  (.D(\MDDR_APB_S_PRDATA_c[9] ), 
        .PAD(MDDR_APB_S_PRDATA[9]));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[18]  (.PAD(FIC_0_AHB_S_HADDR[18]), 
        .Y(\FIC_0_AHB_S_HADDR_c[18] ));
    INBUF #( .IOSTD("") )  MMUART_0_RXD_PAD (.PAD(MMUART_0_RXD), .Y(
        MMUART_0_RXD_PAD_Y));
    INBUF \MDDR_APB_S_PWDATA_ibuf[6]  (.PAD(MDDR_APB_S_PWDATA[6]), .Y(
        \MDDR_APB_S_PWDATA_c[6] ));
    INBUF MDDR_APB_S_PSEL_ibuf (.PAD(MDDR_APB_S_PSEL), .Y(
        MDDR_APB_S_PSEL_c));
    INBUF \FIC_0_AHB_S_HSIZE_ibuf[1]  (.PAD(FIC_0_AHB_S_HSIZE[1]), .Y(
        \FIC_0_AHB_S_HSIZE_c[1] ));
    INBUF \MDDR_DDR_AXI_S_ARLEN_ibuf[2]  (.PAD(MDDR_DDR_AXI_S_ARLEN[2])
        , .Y(\MDDR_DDR_AXI_S_ARLEN_c[2] ));
    OUTBUF FIC_0_AHB_S_HRESP_obuf (.D(FIC_0_AHB_S_HRESP_c), .PAD(
        FIC_0_AHB_S_HRESP));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_14_PAD (.PAD(MDDR_DQ[14]), 
        .D(\DRAM_DQ_OUT_net_0[14] ), .E(\DRAM_DQ_OE_net_0[14] ), .Y(
        MDDR_DQ_14_PAD_Y));
    INBUF \MDDR_DDR_AXI_S_ARLEN_ibuf[1]  (.PAD(MDDR_DDR_AXI_S_ARLEN[1])
        , .Y(\MDDR_DDR_AXI_S_ARLEN_c[1] ));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[14]  (.PAD(FIC_2_APB_M_PRDATA[14]), 
        .Y(\FIC_2_APB_M_PRDATA_c[14] ));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[6]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[6]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[6] ));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[31]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[31]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[31] ));
    INBUF \MDDR_APB_S_PWDATA_ibuf[0]  (.PAD(MDDR_APB_S_PWDATA[0]), .Y(
        \MDDR_APB_S_PWDATA_c[0] ));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[14]  (.D(
        \FIC_2_APB_M_PWDATA_c[14] ), .PAD(FIC_2_APB_M_PWDATA[14]));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_15_PAD (.PAD(MDDR_DQ[15]), 
        .D(\DRAM_DQ_OUT_net_0[15] ), .E(\DRAM_DQ_OE_net_0[15] ), .Y(
        MDDR_DQ_15_PAD_Y));
    INBUF \MDDR_DDR_AXI_S_WSTRB_ibuf[4]  (.PAD(MDDR_DDR_AXI_S_WSTRB[4])
        , .Y(\MDDR_DDR_AXI_S_WSTRB_c[4] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[32]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[32] ), .PAD(MDDR_DDR_AXI_S_RDATA[32]));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[25]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[25]), .Y(\MDDR_DDR_AXI_S_WDATA_c[25] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[8]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[8] ), .PAD(MDDR_DDR_AXI_S_RDATA[8]));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[18]  (.PAD(FIC_0_AHB_S_HWDATA[18]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[18] ));
    INBUF FIC_2_APB_M_PSLVERR_ibuf (.PAD(FIC_2_APB_M_PSLVERR), .Y(
        FIC_2_APB_M_PSLVERR_c));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[39]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[39]), .Y(\MDDR_DDR_AXI_S_WDATA_c[39] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[13]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[13] ), .PAD(MDDR_DDR_AXI_S_RDATA[13]));
    OUTBUF \MDDR_APB_S_PRDATA_obuf[6]  (.D(\MDDR_APB_S_PRDATA_c[6] ), 
        .PAD(MDDR_APB_S_PRDATA[6]));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[28]  (.D(
        \FIC_2_APB_M_PWDATA_c[28] ), .PAD(FIC_2_APB_M_PWDATA[28]));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[29]  (.PAD(FIC_0_AHB_S_HADDR[29]), 
        .Y(\FIC_0_AHB_S_HADDR_c[29] ));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[26]  (.D(
        \FIC_0_AHB_S_HRDATA_c[26] ), .PAD(FIC_0_AHB_S_HRDATA[26]));
    OUTBUF \MDDR_APB_S_PRDATA_obuf[15]  (.D(\MDDR_APB_S_PRDATA_c[15] ), 
        .PAD(MDDR_APB_S_PRDATA[15]));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[1]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[1]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[1] ));
    OUTBUF \MDDR_APB_S_PRDATA_obuf[0]  (.D(\MDDR_APB_S_PRDATA_c[0] ), 
        .PAD(MDDR_APB_S_PRDATA[0]));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_12_PAD (.PAD(MDDR_DQ[12]), 
        .D(\DRAM_DQ_OUT_net_0[12] ), .E(\DRAM_DQ_OE_net_0[12] ), .Y(
        MDDR_DQ_12_PAD_Y));
    INBUF M3_RESET_N_ibuf (.PAD(M3_RESET_N), .Y(M3_RESET_N_c));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[30]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[30]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[30] ));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[26]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[26]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[26] ));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[18]  (.D(
        \FIC_2_APB_M_PWDATA_c[18] ), .PAD(FIC_2_APB_M_PWDATA[18]));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[20]  (.PAD(FIC_0_AHB_S_HWDATA[20]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[20] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[28]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[28]), .Y(\MDDR_DDR_AXI_S_WDATA_c[28] ));
    OUTBUF \FIC_2_APB_M_PADDR_obuf[7]  (.D(\FIC_2_APB_M_PADDR_c[7] ), 
        .PAD(FIC_2_APB_M_PADDR[7]));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[16]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[16]), .Y(\MDDR_DDR_AXI_S_WDATA_c[16] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[23]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[23]), .Y(\MDDR_DDR_AXI_S_WDATA_c[23] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[1]  (.PAD(MDDR_DDR_AXI_S_WDATA[1])
        , .Y(\MDDR_DDR_AXI_S_WDATA_c[1] ));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[31]  (.D(
        \FIC_0_AHB_S_HRDATA_c[31] ), .PAD(FIC_0_AHB_S_HRDATA[31]));
    OUTBUF \FIC_2_APB_M_PADDR_obuf[4]  (.D(\FIC_2_APB_M_PADDR_c[4] ), 
        .PAD(FIC_2_APB_M_PADDR[4]));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[15]  (.PAD(FIC_0_AHB_S_HADDR[15]), 
        .Y(\FIC_0_AHB_S_HADDR_c[15] ));
    OUTBUF \MDDR_DDR_AXI_S_BID_obuf[3]  (.D(\MDDR_DDR_AXI_S_BID_c[3] ), 
        .PAD(MDDR_DDR_AXI_S_BID[3]));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[31]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[31]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[31] ));
    INBUF MDDR_APB_S_PRESET_N_ibuf (.PAD(MDDR_APB_S_PRESET_N), .Y(
        MDDR_APB_S_PRESET_N_c));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[13]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[13]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[13] ));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_RESET_N_PAD (.D(
        MSS_ADLIB_INST_DRAM_RSTN), .PAD(MDDR_RESET_N));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_1_PAD (.D(
        \DRAM_ADDR_net_0[1] ), .PAD(MDDR_ADDR[1]));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[24]  (.PAD(FIC_0_AHB_S_HADDR[24]), 
        .Y(\FIC_0_AHB_S_HADDR_c[24] ));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[26]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[26]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[26] ));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[26]  (.PAD(FIC_0_AHB_S_HWDATA[26]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[26] ));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[21]  (.PAD(FIC_0_AHB_S_HADDR[21]), 
        .Y(\FIC_0_AHB_S_HADDR_c[21] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[20]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[20] ), .PAD(MDDR_DDR_AXI_S_RDATA[20]));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[53]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[53] ), .PAD(MDDR_DDR_AXI_S_RDATA[53]));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[20]  (.D(
        \FIC_0_AHB_S_HRDATA_c[20] ), .PAD(FIC_0_AHB_S_HRDATA[20]));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[47]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[47] ), .PAD(MDDR_DDR_AXI_S_RDATA[47]));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[29]  (.D(
        \FIC_2_APB_M_PWDATA_c[29] ), .PAD(FIC_2_APB_M_PWDATA[29]));
    INBUF FIC_0_AHB_S_HMASTLOCK_ibuf (.PAD(FIC_0_AHB_S_HMASTLOCK), .Y(
        FIC_0_AHB_S_HMASTLOCK_c));
    INBUF \MDDR_APB_S_PWDATA_ibuf[12]  (.PAD(MDDR_APB_S_PWDATA[12]), 
        .Y(\MDDR_APB_S_PWDATA_c[12] ));
    BIBUF #( .IOSTD("") )  SPI_0_CLK_PAD (.PAD(SPI_0_CLK), .D(
        MSS_ADLIB_INST_SPI0_SCK_USBA_XCLK_OUT), .E(
        MSS_ADLIB_INST_SPI0_SCK_USBA_XCLK_OE), .Y(SPI_0_CLK_PAD_Y));
    INBUF MDDR_DDR_AXI_S_AWVALID_ibuf (.PAD(MDDR_DDR_AXI_S_AWVALID), 
        .Y(MDDR_DDR_AXI_S_AWVALID_c));
    INBUF \MDDR_DDR_AXI_S_AWLOCK_ibuf[0]  (.PAD(
        MDDR_DDR_AXI_S_AWLOCK[0]), .Y(\MDDR_DDR_AXI_S_AWLOCK_c[0] ));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[5]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[5]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[5] ));
    GND GND (.Y(GND_net_1));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[56]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[56]), .Y(\MDDR_DDR_AXI_S_WDATA_c[56] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[21]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[21] ), .PAD(MDDR_DDR_AXI_S_RDATA[21]));
    INBUF \MDDR_DDR_AXI_S_WID_ibuf[3]  (.PAD(MDDR_DDR_AXI_S_WID[3]), 
        .Y(\MDDR_DDR_AXI_S_WID_c[3] ));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_0_PAD (.PAD(MDDR_DQ[0]), .D(
        \DRAM_DQ_OUT_net_0[0] ), .E(\DRAM_DQ_OE_net_0[0] ), .Y(
        MDDR_DQ_0_PAD_Y));
    INBUF \MDDR_DDR_AXI_S_ARID_ibuf[0]  (.PAD(MDDR_DDR_AXI_S_ARID[0]), 
        .Y(\MDDR_DDR_AXI_S_ARID_c[0] ));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[19]  (.D(
        \FIC_2_APB_M_PWDATA_c[19] ), .PAD(FIC_2_APB_M_PWDATA[19]));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[4]  (.PAD(FIC_0_AHB_S_HADDR[4]), .Y(
        \FIC_0_AHB_S_HADDR_c[4] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[15]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[15]), .Y(\MDDR_DDR_AXI_S_WDATA_c[15] ));
    OUTBUF \FIC_2_APB_M_PADDR_obuf[13]  (.D(\FIC_2_APB_M_PADDR_c[13] ), 
        .PAD(FIC_2_APB_M_PADDR[13]));
    INBUF GPIO_12_F2M_ibuf (.PAD(GPIO_12_F2M), .Y(GPIO_12_F2M_c));
    INBUF MDDR_DDR_AXI_S_WLAST_ibuf (.PAD(MDDR_DDR_AXI_S_WLAST), .Y(
        MDDR_DDR_AXI_S_WLAST_c));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[40]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[40]), .Y(\MDDR_DDR_AXI_S_WDATA_c[40] ));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[22]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[22]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[22] ));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[0]  (.PAD(FIC_0_AHB_S_HWDATA[0]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[0] ));
    OUTBUF \MDDR_DDR_AXI_S_RID_obuf[1]  (.D(\MDDR_DDR_AXI_S_RID_c[1] ), 
        .PAD(MDDR_DDR_AXI_S_RID[1]));
    INBUF \MDDR_APB_S_PADDR_ibuf[9]  (.PAD(MDDR_APB_S_PADDR[9]), .Y(
        \MDDR_APB_S_PADDR_c[9] ));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[18]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[18]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[18] ));
    INBUF \MDDR_APB_S_PWDATA_ibuf[2]  (.PAD(MDDR_APB_S_PWDATA[2]), .Y(
        \MDDR_APB_S_PWDATA_c[2] ));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[23]  (.PAD(FIC_2_APB_M_PRDATA[23]), 
        .Y(\FIC_2_APB_M_PRDATA_c[23] ));
    INBUF \MDDR_DDR_AXI_S_ARLEN_ibuf[3]  (.PAD(MDDR_DDR_AXI_S_ARLEN[3])
        , .Y(\MDDR_DDR_AXI_S_ARLEN_c[3] ));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[4]  (.PAD(FIC_2_APB_M_PRDATA[4]), 
        .Y(\FIC_2_APB_M_PRDATA_c[4] ));
    INBUF \MDDR_DDR_AXI_S_ARLOCK_ibuf[0]  (.PAD(
        MDDR_DDR_AXI_S_ARLOCK[0]), .Y(\MDDR_DDR_AXI_S_ARLOCK_c[0] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[18]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[18]), .Y(\MDDR_DDR_AXI_S_WDATA_c[18] ));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_11_PAD (.PAD(MDDR_DQ[11]), 
        .D(\DRAM_DQ_OUT_net_0[11] ), .E(\DRAM_DQ_OE_net_0[11] ), .Y(
        MDDR_DQ_11_PAD_Y));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[9]  (.PAD(MDDR_DDR_AXI_S_WDATA[9])
        , .Y(\MDDR_DDR_AXI_S_WDATA_c[9] ));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[21]  (.PAD(FIC_2_APB_M_PRDATA[21]), 
        .Y(\FIC_2_APB_M_PRDATA_c[21] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[13]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[13]), .Y(\MDDR_DDR_AXI_S_WDATA_c[13] ));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[13]  (.PAD(FIC_2_APB_M_PRDATA[13]), 
        .Y(\FIC_2_APB_M_PRDATA_c[13] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[33]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[33] ), .PAD(MDDR_DDR_AXI_S_RDATA[33]));
    OUTBUF \FIC_2_APB_M_PADDR_obuf[14]  (.D(\FIC_2_APB_M_PADDR_c[14] ), 
        .PAD(FIC_2_APB_M_PADDR[14]));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[12]  (.D(
        \FIC_0_AHB_S_HRDATA_c[12] ), .PAD(FIC_0_AHB_S_HRDATA[12]));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[24]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[24]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[24] ));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_4_PAD (.D(
        \DRAM_ADDR_net_0[4] ), .PAD(MDDR_ADDR[4]));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[4]  (.D(\FIC_2_APB_M_PWDATA_c[4] ), 
        .PAD(FIC_2_APB_M_PWDATA[4]));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[27]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[27]), .Y(\MDDR_DDR_AXI_S_WDATA_c[27] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[22]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[22]), .Y(\MDDR_DDR_AXI_S_WDATA_c[22] ));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[27]  (.PAD(FIC_0_AHB_S_HADDR[27]), 
        .Y(\FIC_0_AHB_S_HADDR_c[27] ));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[5]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[5]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[5] ));
    OUTBUF \MDDR_APB_S_PRDATA_obuf[2]  (.D(\MDDR_APB_S_PRDATA_c[2] ), 
        .PAD(MDDR_APB_S_PRDATA[2]));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[6]  (.PAD(MDDR_DDR_AXI_S_WDATA[6])
        , .Y(\MDDR_DDR_AXI_S_WDATA_c[6] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[55]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[55]), .Y(\MDDR_DDR_AXI_S_WDATA_c[55] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[44]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[44] ), .PAD(MDDR_DDR_AXI_S_RDATA[44]));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_5_PAD (.D(
        \DRAM_ADDR_net_0[5] ), .PAD(MDDR_ADDR[5]));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[11]  (.PAD(FIC_2_APB_M_PRDATA[11]), 
        .Y(\FIC_2_APB_M_PRDATA_c[11] ));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[18]  (.D(
        \FIC_0_AHB_S_HRDATA_c[18] ), .PAD(FIC_0_AHB_S_HRDATA[18]));
    BIBUF #( .IOSTD("") )  SPI_0_SS0_PAD (.PAD(SPI_0_SS0), .D(
        MSS_ADLIB_INST_SPI0_SS0_USBA_NXT_MGPIO7A_OUT), .E(
        MSS_ADLIB_INST_SPI0_SS0_USBA_NXT_MGPIO7A_OE), .Y(
        SPI_0_SS0_PAD_Y));
    OUTBUF \FIC_2_APB_M_PADDR_obuf[5]  (.D(\FIC_2_APB_M_PADDR_c[5] ), 
        .PAD(FIC_2_APB_M_PADDR[5]));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[23]  (.PAD(FIC_0_AHB_S_HADDR[23]), 
        .Y(\FIC_0_AHB_S_HADDR_c[23] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[10]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[10] ), .PAD(MDDR_DDR_AXI_S_RDATA[10]));
    INBUF \MDDR_DDR_AXI_S_AWLOCK_ibuf[1]  (.PAD(
        MDDR_DDR_AXI_S_AWLOCK[1]), .Y(\MDDR_DDR_AXI_S_AWLOCK_c[1] ));
    INBUF \MDDR_DDR_AXI_S_WSTRB_ibuf[5]  (.PAD(MDDR_DDR_AXI_S_WSTRB[5])
        , .Y(\MDDR_DDR_AXI_S_WSTRB_c[5] ));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_CKE_PAD (.D(
        MSS_ADLIB_INST_DRAM_CKE), .PAD(MDDR_CKE));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[36]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[36]), .Y(\MDDR_DDR_AXI_S_WDATA_c[36] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[26]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[26] ), .PAD(MDDR_DDR_AXI_S_RDATA[26]));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[27]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[27]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[27] ));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_8_PAD (.PAD(MDDR_DQ[8]), .D(
        \DRAM_DQ_OUT_net_0[8] ), .E(\DRAM_DQ_OE_net_0[8] ), .Y(
        MDDR_DQ_8_PAD_Y));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[15]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[15]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[15] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[5]  (.PAD(MDDR_DDR_AXI_S_WDATA[5])
        , .Y(\MDDR_DDR_AXI_S_WDATA_c[5] ));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[3]  (.D(\FIC_0_AHB_S_HRDATA_c[3] ), 
        .PAD(FIC_0_AHB_S_HRDATA[3]));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[42]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[42] ), .PAD(MDDR_DDR_AXI_S_RDATA[42]));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[8]  (.D(\FIC_0_AHB_S_HRDATA_c[8] ), 
        .PAD(FIC_0_AHB_S_HRDATA[8]));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[23]  (.D(
        \FIC_0_AHB_S_HRDATA_c[23] ), .PAD(FIC_0_AHB_S_HRDATA[23]));
    OUTBUF MDDR_DDR_AXI_S_WREADY_obuf (.D(MDDR_DDR_AXI_S_WREADY_c), 
        .PAD(MDDR_DDR_AXI_S_WREADY));
    OUTBUF \MDDR_DDR_AXI_S_BID_obuf[2]  (.D(\MDDR_DDR_AXI_S_BID_c[2] ), 
        .PAD(MDDR_DDR_AXI_S_BID[2]));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[17]  (.PAD(FIC_0_AHB_S_HWDATA[17]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[17] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[58]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[58]), .Y(\MDDR_DDR_AXI_S_WDATA_c[58] ));
    INBUF \MDDR_DDR_AXI_S_AWID_ibuf[3]  (.PAD(MDDR_DDR_AXI_S_AWID[3]), 
        .Y(\MDDR_DDR_AXI_S_AWID_c[3] ));
    OUTBUF \FIC_2_APB_M_PADDR_obuf[8]  (.D(\FIC_2_APB_M_PADDR_c[8] ), 
        .PAD(FIC_2_APB_M_PADDR[8]));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[49]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[49]), .Y(\MDDR_DDR_AXI_S_WDATA_c[49] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[25]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[25] ), .PAD(MDDR_DDR_AXI_S_RDATA[25]));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[11]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[11] ), .PAD(MDDR_DDR_AXI_S_RDATA[11]));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[13]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[13]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[13] ));
    OUTBUF GPIO_4_M2F_obuf (.D(GPIO_4_M2F_c), .PAD(GPIO_4_M2F));
    INBUF #( .IOSTD("") )  SPI_0_DI_PAD (.PAD(SPI_0_DI), .Y(
        SPI_0_DI_PAD_Y));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[53]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[53]), .Y(\MDDR_DDR_AXI_S_WDATA_c[53] ));
    INBUF \MDDR_APB_S_PWDATA_ibuf[11]  (.PAD(MDDR_APB_S_PWDATA[11]), 
        .Y(\MDDR_APB_S_PWDATA_c[11] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[28]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[28] ), .PAD(MDDR_DDR_AXI_S_RDATA[28]));
    INBUF \MDDR_DDR_AXI_S_AWSIZE_ibuf[1]  (.PAD(
        MDDR_DDR_AXI_S_AWSIZE[1]), .Y(\MDDR_DDR_AXI_S_AWSIZE_c[1] ));
    INBUF \MDDR_DDR_AXI_S_ARSIZE_ibuf[0]  (.PAD(
        MDDR_DDR_AXI_S_ARSIZE[0]), .Y(\MDDR_DDR_AXI_S_ARSIZE_c[0] ));
    INBUF \MDDR_DDR_AXI_S_ARLOCK_ibuf[1]  (.PAD(
        MDDR_DDR_AXI_S_ARLOCK[1]), .Y(\MDDR_DDR_AXI_S_ARLOCK_c[1] ));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_2_PAD (.D(
        \DRAM_ADDR_net_0[2] ), .PAD(MDDR_ADDR[2]));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_13_PAD (.PAD(MDDR_DQ[13]), 
        .D(\DRAM_DQ_OUT_net_0[13] ), .E(\DRAM_DQ_OE_net_0[13] ), .Y(
        MDDR_DQ_13_PAD_Y));
    OUTBUF MSS_RESET_N_M2F_obuf (.D(MSS_RESET_N_M2F_c), .PAD(
        MSS_RESET_N_M2F));
    OUTBUF \FIC_2_APB_M_PADDR_obuf[2]  (.D(\FIC_2_APB_M_PADDR_c[2] ), 
        .PAD(FIC_2_APB_M_PADDR[2]));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[0]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[0]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[0] ));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[11]  (.D(
        \FIC_0_AHB_S_HRDATA_c[11] ), .PAD(FIC_0_AHB_S_HRDATA[11]));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[26]  (.PAD(FIC_0_AHB_S_HADDR[26]), 
        .Y(\FIC_0_AHB_S_HADDR_c[26] ));
    INBUF \MDDR_DDR_AXI_S_ARID_ibuf[1]  (.PAD(MDDR_DDR_AXI_S_ARID[1]), 
        .Y(\MDDR_DDR_AXI_S_ARID_c[1] ));
    TRIBUFF MMUART_0_TXD_PAD (.D(
        MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OUT), .E(
        MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OE), .PAD(
        MMUART_0_TXD));
    INBUF MDDR_DDR_CORE_RESET_N_ibuf (.PAD(MDDR_DDR_CORE_RESET_N), .Y(
        MDDR_DDR_CORE_RESET_N_c));
    BIBUF_DIFF #( .IOSTD("SSTL15I") )  MDDR_DQS_1_PAD (.D(
        \DRAM_DQS_OUT_net_0[1] ), .E(\DRAM_DQS_OE_net_0[1] ), .PADP(
        MDDR_DQS[1]), .PADN(MDDR_DQS_N[1]), .Y(MDDR_DQS_1_PAD_Y));
    OUTBUF MDDR_DDR_AXI_S_RVALID_obuf (.D(MDDR_DDR_AXI_S_RVALID_c), 
        .PAD(MDDR_DDR_AXI_S_RVALID));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[2]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[2]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[2] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[50]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[50] ), .PAD(MDDR_DDR_AXI_S_RDATA[50]));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_13_PAD (.D(
        \DRAM_ADDR_net_0[13] ), .PAD(MDDR_ADDR[13]));
    INBUF FIC_0_AHB_S_HWRITE_ibuf (.PAD(FIC_0_AHB_S_HWRITE), .Y(
        FIC_0_AHB_S_HWRITE_c));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[25]  (.PAD(FIC_0_AHB_S_HWDATA[25]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[25] ));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[4]  (.D(\FIC_0_AHB_S_HRDATA_c[4] ), 
        .PAD(FIC_0_AHB_S_HRDATA[4]));
    VCC VCC (.Y(VCC_net_1));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[21]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[21]), .Y(\MDDR_DDR_AXI_S_WDATA_c[21] ));
    OUTBUF FIC_2_APB_M_PSEL_obuf (.D(FIC_2_APB_M_PSEL_c), .PAD(
        FIC_2_APB_M_PSEL));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[19]  (.D(
        \FIC_0_AHB_S_HRDATA_c[19] ), .PAD(FIC_0_AHB_S_HRDATA[19]));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[1]  (.PAD(FIC_0_AHB_S_HADDR[1]), .Y(
        \FIC_0_AHB_S_HADDR_c[1] ));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[1]  (.D(\FIC_0_AHB_S_HRDATA_c[1] ), 
        .PAD(FIC_0_AHB_S_HRDATA[1]));
    INBUF \MDDR_DDR_AXI_S_WID_ibuf[2]  (.PAD(MDDR_DDR_AXI_S_WID[2]), 
        .Y(\MDDR_DDR_AXI_S_WID_c[2] ));
    OUTBUF MDDR_APB_S_PSLVERR_obuf (.D(MDDR_APB_S_PSLVERR_c), .PAD(
        MDDR_APB_S_PSLVERR));
    INBUF \MDDR_DDR_AXI_S_WSTRB_ibuf[2]  (.PAD(MDDR_DDR_AXI_S_WSTRB[2])
        , .Y(\MDDR_DDR_AXI_S_WSTRB_c[2] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[35]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[35]), .Y(\MDDR_DDR_AXI_S_WDATA_c[35] ));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_BA_1_PAD (.D(
        \DRAM_BA_net_0[1] ), .PAD(MDDR_BA[1]));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ODT_PAD (.D(
        MSS_ADLIB_INST_DRAM_ODT), .PAD(MDDR_ODT));
    INBUF GPIO_11_F2M_ibuf (.PAD(GPIO_11_F2M), .Y(GPIO_11_F2M_c));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[5]  (.PAD(FIC_0_AHB_S_HWDATA[5]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[5] ));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[2]  (.D(\FIC_0_AHB_S_HRDATA_c[2] ), 
        .PAD(FIC_0_AHB_S_HRDATA[2]));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[30]  (.PAD(FIC_0_AHB_S_HADDR[30]), 
        .Y(\FIC_0_AHB_S_HADDR_c[30] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[51]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[51] ), .PAD(MDDR_DDR_AXI_S_RDATA[51]));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[17]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[17]), .Y(\MDDR_DDR_AXI_S_WDATA_c[17] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[12]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[12]), .Y(\MDDR_DDR_AXI_S_WDATA_c[12] ));
    OUTBUF \MDDR_APB_S_PRDATA_obuf[12]  (.D(\MDDR_APB_S_PRDATA_c[12] ), 
        .PAD(MDDR_APB_S_PRDATA[12]));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[28]  (.PAD(FIC_0_AHB_S_HWDATA[28]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[28] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[4]  (.PAD(MDDR_DDR_AXI_S_WDATA[4])
        , .Y(\MDDR_DDR_AXI_S_WDATA_c[4] ));
    INBUF \MDDR_APB_S_PADDR_ibuf[6]  (.PAD(MDDR_APB_S_PADDR[6]), .Y(
        \MDDR_APB_S_PADDR_c[6] ));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_7_PAD (.D(
        \DRAM_ADDR_net_0[7] ), .PAD(MDDR_ADDR[7]));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[22]  (.PAD(FIC_0_AHB_S_HADDR[22]), 
        .Y(\FIC_0_AHB_S_HADDR_c[22] ));
    INBUF \MDDR_APB_S_PADDR_ibuf[10]  (.PAD(MDDR_APB_S_PADDR[10]), .Y(
        \MDDR_APB_S_PADDR_c[10] ));
    INBUF \MDDR_DDR_AXI_S_WSTRB_ibuf[6]  (.PAD(MDDR_DDR_AXI_S_WSTRB[6])
        , .Y(\MDDR_DDR_AXI_S_WSTRB_c[6] ));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[7]  (.PAD(FIC_0_AHB_S_HWDATA[7]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[7] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[38]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[38]), .Y(\MDDR_DDR_AXI_S_WDATA_c[38] ));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[17]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[17]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[17] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[60]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[60]), .Y(\MDDR_DDR_AXI_S_WDATA_c[60] ));
    INBUF \MDDR_APB_S_PADDR_ibuf[2]  (.PAD(MDDR_APB_S_PADDR[2]), .Y(
        \MDDR_APB_S_PADDR_c[2] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[16]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[16] ), .PAD(MDDR_DDR_AXI_S_RDATA[16]));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[0]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[0]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[0] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[33]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[33]), .Y(\MDDR_DDR_AXI_S_WDATA_c[33] ));
    INBUF \MDDR_DDR_AXI_S_ARBURST_ibuf[1]  (.PAD(
        MDDR_DDR_AXI_S_ARBURST[1]), .Y(\MDDR_DDR_AXI_S_ARBURST_c[1] ));
    INBUF MDDR_APB_S_PCLK_ibuf (.PAD(MDDR_APB_S_PCLK), .Y(
        MDDR_APB_S_PCLK_c));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[23]  (.D(
        \FIC_2_APB_M_PWDATA_c[23] ), .PAD(FIC_2_APB_M_PWDATA[23]));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[6]  (.D(\FIC_0_AHB_S_HRDATA_c[6] ), 
        .PAD(FIC_0_AHB_S_HRDATA[6]));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[2]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[2]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[2] ));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[21]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[21]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[21] ));
    INBUF \MDDR_DDR_AXI_S_AWID_ibuf[2]  (.PAD(MDDR_DDR_AXI_S_AWID[2]), 
        .Y(\MDDR_DDR_AXI_S_AWID_c[2] ));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[31]  (.D(
        \FIC_2_APB_M_PWDATA_c[31] ), .PAD(FIC_2_APB_M_PWDATA[31]));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DM_RDQS_1_PAD (.PAD(
        MDDR_DM_RDQS[1]), .D(\DRAM_DM_RDQS_OUT_net_0[1] ), .E(
        \DM_OE_net_0[1] ), .Y(MDDR_DM_RDQS_1_PAD_Y));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[3]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[3] ), .PAD(MDDR_DDR_AXI_S_RDATA[3]));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[24]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[24]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[24] ));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[15]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[15]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[15] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[15]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[15] ), .PAD(MDDR_DDR_AXI_S_RDATA[15]));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[28]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[28]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[28] ));
    OUTBUF FIC_0_AHB_S_HREADYOUT_obuf (.D(FIC_0_AHB_S_HREADYOUT_c), 
        .PAD(FIC_0_AHB_S_HREADYOUT));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[30]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[30] ), .PAD(MDDR_DDR_AXI_S_RDATA[30]));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[13]  (.D(
        \FIC_2_APB_M_PWDATA_c[13] ), .PAD(FIC_2_APB_M_PWDATA[13]));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[29]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[29] ), .PAD(MDDR_DDR_AXI_S_RDATA[29]));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[18]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[18] ), .PAD(MDDR_DDR_AXI_S_RDATA[18]));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_RAS_N_PAD (.D(
        MSS_ADLIB_INST_DRAM_RASN), .PAD(MDDR_RAS_N));
    INBUF \MDDR_DDR_AXI_S_AWLEN_ibuf[0]  (.PAD(MDDR_DDR_AXI_S_AWLEN[0])
        , .Y(\MDDR_DDR_AXI_S_AWLEN_c[0] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[57]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[57]), .Y(\MDDR_DDR_AXI_S_WDATA_c[57] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[52]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[52]), .Y(\MDDR_DDR_AXI_S_WDATA_c[52] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[24]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[24]), .Y(\MDDR_DDR_AXI_S_WDATA_c[24] ));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_9_PAD (.PAD(MDDR_DQ[9]), .D(
        \DRAM_DQ_OUT_net_0[9] ), .E(\DRAM_DQ_OE_net_0[9] ), .Y(
        MDDR_DQ_9_PAD_Y));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[20]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[20]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[20] ));
    INBUF \MDDR_APB_S_PADDR_ibuf[8]  (.PAD(MDDR_APB_S_PADDR[8]), .Y(
        \MDDR_APB_S_PADDR_c[8] ));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[20]  (.PAD(FIC_2_APB_M_PRDATA[20]), 
        .Y(\FIC_2_APB_M_PRDATA_c[20] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[56]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[56] ), .PAD(MDDR_DDR_AXI_S_RDATA[56]));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[43]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[43] ), .PAD(MDDR_DDR_AXI_S_RDATA[43]));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[31]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[31] ), .PAD(MDDR_DDR_AXI_S_RDATA[31]));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[11]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[11]), .Y(\MDDR_DDR_AXI_S_WDATA_c[11] ));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[8]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[8]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[8] ));
    MSS_120 #( .INIT(1438'h00000000003612000000000000000000000000000000000000000000000000000000000000000000000000000000000001203610000000000000000000000000000000000000000F00000000F000000000000000000000000000000007FFFFFFFB000001007C31C90464A00609040104003FFFFE4000000100000400000000F0F11C00000000DF5C010842108421000001FE34001FF8000000400000000000671007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
        , .ACT_UBITS(56'hFFFFFFFFFFFFFF), .MEMORYFILE("ENVM_init.mem")
         )  MSS_ADLIB_INST (.CAN_RXBUS_MGPIO3A_H2F_A(), 
        .CAN_RXBUS_MGPIO3A_H2F_B(GPIO_3_M2F_c), 
        .CAN_TX_EBL_MGPIO4A_H2F_A(), .CAN_TX_EBL_MGPIO4A_H2F_B(
        GPIO_4_M2F_c), .CAN_TXBUS_MGPIO2A_H2F_A(), 
        .CAN_TXBUS_MGPIO2A_H2F_B(GPIO_2_M2F_c), .CLK_CONFIG_APB(
        FIC_2_APB_M_PCLK_c), .COMMS_INT(), .CONFIG_PRESET_N(
        FIC_2_APB_M_PRESET_N_c), .EDAC_ERROR({nc0, nc1, nc2, nc3, nc4, 
        nc5, nc6, nc7}), .F_FM0_RDATA({\FIC_0_AHB_S_HRDATA_c[31] , 
        \FIC_0_AHB_S_HRDATA_c[30] , \FIC_0_AHB_S_HRDATA_c[29] , 
        \FIC_0_AHB_S_HRDATA_c[28] , \FIC_0_AHB_S_HRDATA_c[27] , 
        \FIC_0_AHB_S_HRDATA_c[26] , \FIC_0_AHB_S_HRDATA_c[25] , 
        \FIC_0_AHB_S_HRDATA_c[24] , \FIC_0_AHB_S_HRDATA_c[23] , 
        \FIC_0_AHB_S_HRDATA_c[22] , \FIC_0_AHB_S_HRDATA_c[21] , 
        \FIC_0_AHB_S_HRDATA_c[20] , \FIC_0_AHB_S_HRDATA_c[19] , 
        \FIC_0_AHB_S_HRDATA_c[18] , \FIC_0_AHB_S_HRDATA_c[17] , 
        \FIC_0_AHB_S_HRDATA_c[16] , \FIC_0_AHB_S_HRDATA_c[15] , 
        \FIC_0_AHB_S_HRDATA_c[14] , \FIC_0_AHB_S_HRDATA_c[13] , 
        \FIC_0_AHB_S_HRDATA_c[12] , \FIC_0_AHB_S_HRDATA_c[11] , 
        \FIC_0_AHB_S_HRDATA_c[10] , \FIC_0_AHB_S_HRDATA_c[9] , 
        \FIC_0_AHB_S_HRDATA_c[8] , \FIC_0_AHB_S_HRDATA_c[7] , 
        \FIC_0_AHB_S_HRDATA_c[6] , \FIC_0_AHB_S_HRDATA_c[5] , 
        \FIC_0_AHB_S_HRDATA_c[4] , \FIC_0_AHB_S_HRDATA_c[3] , 
        \FIC_0_AHB_S_HRDATA_c[2] , \FIC_0_AHB_S_HRDATA_c[1] , 
        \FIC_0_AHB_S_HRDATA_c[0] }), .F_FM0_READYOUT(
        FIC_0_AHB_S_HREADYOUT_c), .F_FM0_RESP(FIC_0_AHB_S_HRESP_c), 
        .F_FM1_RDATA({nc8, nc9, nc10, nc11, nc12, nc13, nc14, nc15, 
        nc16, nc17, nc18, nc19, nc20, nc21, nc22, nc23, nc24, nc25, 
        nc26, nc27, nc28, nc29, nc30, nc31, nc32, nc33, nc34, nc35, 
        nc36, nc37, nc38, nc39}), .F_FM1_READYOUT(), .F_FM1_RESP(), 
        .F_HM0_ADDR({nc40, nc41, nc42, nc43, nc44, nc45, nc46, nc47, 
        nc48, nc49, nc50, nc51, nc52, nc53, nc54, nc55, nc56, nc57, 
        nc58, nc59, nc60, nc61, nc62, nc63, nc64, nc65, nc66, nc67, 
        nc68, nc69, nc70, nc71}), .F_HM0_ENABLE(), .F_HM0_SEL(), 
        .F_HM0_SIZE({nc72, nc73}), .F_HM0_TRANS1(), .F_HM0_WDATA({nc74, 
        nc75, nc76, nc77, nc78, nc79, nc80, nc81, nc82, nc83, nc84, 
        nc85, nc86, nc87, nc88, nc89, nc90, nc91, nc92, nc93, nc94, 
        nc95, nc96, nc97, nc98, nc99, nc100, nc101, nc102, nc103, 
        nc104, nc105}), .F_HM0_WRITE(), .F_HM1_ADDR({nc106, nc107, 
        nc108, nc109, nc110, nc111, nc112, nc113, nc114, nc115, nc116, 
        nc117, nc118, nc119, nc120, nc121, nc122, nc123, nc124, nc125, 
        nc126, nc127, nc128, nc129, nc130, nc131, nc132, nc133, nc134, 
        nc135, nc136, nc137}), .F_HM1_ENABLE(), .F_HM1_SEL(), 
        .F_HM1_SIZE({nc138, nc139}), .F_HM1_TRANS1(), .F_HM1_WDATA({
        nc140, nc141, nc142, nc143, nc144, nc145, nc146, nc147, nc148, 
        nc149, nc150, nc151, nc152, nc153, nc154, nc155, nc156, nc157, 
        nc158, nc159, nc160, nc161, nc162, nc163, nc164, nc165, nc166, 
        nc167, nc168, nc169, nc170, nc171}), .F_HM1_WRITE(), 
        .FAB_CHRGVBUS(), .FAB_DISCHRGVBUS(), .FAB_DMPULLDOWN(), 
        .FAB_DPPULLDOWN(), .FAB_DRVVBUS(), .FAB_IDPULLUP(), 
        .FAB_OPMODE({nc172, nc173}), .FAB_SUSPENDM(), .FAB_TERMSEL(), 
        .FAB_TXVALID(), .FAB_VCONTROL({nc174, nc175, nc176, nc177}), 
        .FAB_VCONTROLLOADM(), .FAB_XCVRSEL({nc178, nc179}), 
        .FAB_XDATAOUT({nc180, nc181, nc182, nc183, nc184, nc185, nc186, 
        nc187}), .FACC_GLMUX_SEL(), .FIC32_0_MASTER({nc188, nc189}), 
        .FIC32_1_MASTER({nc190, nc191}), .FPGA_RESET_N(
        MSS_RESET_N_M2F_c), .GTX_CLK(), .H2F_INTERRUPT({nc192, nc193, 
        nc194, nc195, nc196, nc197, nc198, nc199, nc200, nc201, nc202, 
        nc203, nc204, nc205, nc206, nc207}), .H2F_NMI(), .H2FCALIB(), 
        .I2C0_SCL_MGPIO31B_H2F_A(), .I2C0_SCL_MGPIO31B_H2F_B(), 
        .I2C0_SDA_MGPIO30B_H2F_A(), .I2C0_SDA_MGPIO30B_H2F_B(), 
        .I2C1_SCL_MGPIO1A_H2F_A(), .I2C1_SCL_MGPIO1A_H2F_B(
        GPIO_1_M2F_c), .I2C1_SDA_MGPIO0A_H2F_A(), 
        .I2C1_SDA_MGPIO0A_H2F_B(GPIO_0_M2F_c), .MDCF(), .MDOENF(), 
        .MDOF(), .MMUART0_CTS_MGPIO19B_H2F_A(), 
        .MMUART0_CTS_MGPIO19B_H2F_B(), .MMUART0_DCD_MGPIO22B_H2F_A(), 
        .MMUART0_DCD_MGPIO22B_H2F_B(), .MMUART0_DSR_MGPIO20B_H2F_A(), 
        .MMUART0_DSR_MGPIO20B_H2F_B(), .MMUART0_DTR_MGPIO18B_H2F_A(), 
        .MMUART0_DTR_MGPIO18B_H2F_B(), .MMUART0_RI_MGPIO21B_H2F_A(), 
        .MMUART0_RI_MGPIO21B_H2F_B(), .MMUART0_RTS_MGPIO17B_H2F_A(), 
        .MMUART0_RTS_MGPIO17B_H2F_B(), .MMUART0_RXD_MGPIO28B_H2F_A(), 
        .MMUART0_RXD_MGPIO28B_H2F_B(), .MMUART0_SCK_MGPIO29B_H2F_A(), 
        .MMUART0_SCK_MGPIO29B_H2F_B(), .MMUART0_TXD_MGPIO27B_H2F_A(), 
        .MMUART0_TXD_MGPIO27B_H2F_B(), .MMUART1_DTR_MGPIO12B_H2F_A(), 
        .MMUART1_RTS_MGPIO11B_H2F_A(), .MMUART1_RTS_MGPIO11B_H2F_B(), 
        .MMUART1_RXD_MGPIO26B_H2F_A(), .MMUART1_RXD_MGPIO26B_H2F_B(), 
        .MMUART1_SCK_MGPIO25B_H2F_A(), .MMUART1_SCK_MGPIO25B_H2F_B(), 
        .MMUART1_TXD_MGPIO24B_H2F_A(), .MMUART1_TXD_MGPIO24B_H2F_B(), 
        .MPLL_LOCK(), .PER2_FABRIC_PADDR({\FIC_2_APB_M_PADDR_c[16] , 
        \FIC_2_APB_M_PADDR_c[15] , \FIC_2_APB_M_PADDR_c[14] , 
        \FIC_2_APB_M_PADDR_c[13] , \FIC_2_APB_M_PADDR_c[12] , 
        \FIC_2_APB_M_PADDR_c[11] , \FIC_2_APB_M_PADDR_c[10] , 
        \FIC_2_APB_M_PADDR_c[9] , \FIC_2_APB_M_PADDR_c[8] , 
        \FIC_2_APB_M_PADDR_c[7] , \FIC_2_APB_M_PADDR_c[6] , 
        \FIC_2_APB_M_PADDR_c[5] , \FIC_2_APB_M_PADDR_c[4] , 
        \FIC_2_APB_M_PADDR_c[3] , \FIC_2_APB_M_PADDR_c[2] }), 
        .PER2_FABRIC_PENABLE(FIC_2_APB_M_PENABLE_c), .PER2_FABRIC_PSEL(
        FIC_2_APB_M_PSEL_c), .PER2_FABRIC_PWDATA({
        \FIC_2_APB_M_PWDATA_c[31] , \FIC_2_APB_M_PWDATA_c[30] , 
        \FIC_2_APB_M_PWDATA_c[29] , \FIC_2_APB_M_PWDATA_c[28] , 
        \FIC_2_APB_M_PWDATA_c[27] , \FIC_2_APB_M_PWDATA_c[26] , 
        \FIC_2_APB_M_PWDATA_c[25] , \FIC_2_APB_M_PWDATA_c[24] , 
        \FIC_2_APB_M_PWDATA_c[23] , \FIC_2_APB_M_PWDATA_c[22] , 
        \FIC_2_APB_M_PWDATA_c[21] , \FIC_2_APB_M_PWDATA_c[20] , 
        \FIC_2_APB_M_PWDATA_c[19] , \FIC_2_APB_M_PWDATA_c[18] , 
        \FIC_2_APB_M_PWDATA_c[17] , \FIC_2_APB_M_PWDATA_c[16] , 
        \FIC_2_APB_M_PWDATA_c[15] , \FIC_2_APB_M_PWDATA_c[14] , 
        \FIC_2_APB_M_PWDATA_c[13] , \FIC_2_APB_M_PWDATA_c[12] , 
        \FIC_2_APB_M_PWDATA_c[11] , \FIC_2_APB_M_PWDATA_c[10] , 
        \FIC_2_APB_M_PWDATA_c[9] , \FIC_2_APB_M_PWDATA_c[8] , 
        \FIC_2_APB_M_PWDATA_c[7] , \FIC_2_APB_M_PWDATA_c[6] , 
        \FIC_2_APB_M_PWDATA_c[5] , \FIC_2_APB_M_PWDATA_c[4] , 
        \FIC_2_APB_M_PWDATA_c[3] , \FIC_2_APB_M_PWDATA_c[2] , 
        \FIC_2_APB_M_PWDATA_c[1] , \FIC_2_APB_M_PWDATA_c[0] }), 
        .PER2_FABRIC_PWRITE(FIC_2_APB_M_PWRITE_c), .RTC_MATCH(), 
        .SLEEPDEEP(), .SLEEPHOLDACK(), .SLEEPING(), .SMBALERT_NO0(), 
        .SMBALERT_NO1(), .SMBSUS_NO0(), .SMBSUS_NO1(), .SPI0_CLK_OUT(), 
        .SPI0_SDI_MGPIO5A_H2F_A(), .SPI0_SDI_MGPIO5A_H2F_B(), 
        .SPI0_SDO_MGPIO6A_H2F_A(), .SPI0_SDO_MGPIO6A_H2F_B(), 
        .SPI0_SS0_MGPIO7A_H2F_A(), .SPI0_SS0_MGPIO7A_H2F_B(), 
        .SPI0_SS1_MGPIO8A_H2F_A(), .SPI0_SS1_MGPIO8A_H2F_B(
        GPIO_8_M2F_c), .SPI0_SS2_MGPIO9A_H2F_A(), 
        .SPI0_SS2_MGPIO9A_H2F_B(GPIO_9_M2F_c), 
        .SPI0_SS3_MGPIO10A_H2F_A(), .SPI0_SS3_MGPIO10A_H2F_B(
        GPIO_10_M2F_c), .SPI0_SS4_MGPIO19A_H2F_A(), 
        .SPI0_SS5_MGPIO20A_H2F_A(), .SPI0_SS6_MGPIO21A_H2F_A(), 
        .SPI0_SS7_MGPIO22A_H2F_A(), .SPI1_CLK_OUT(), 
        .SPI1_SDI_MGPIO11A_H2F_A(), .SPI1_SDI_MGPIO11A_H2F_B(), 
        .SPI1_SDO_MGPIO12A_H2F_A(), .SPI1_SDO_MGPIO12A_H2F_B(), 
        .SPI1_SS0_MGPIO13A_H2F_A(), .SPI1_SS0_MGPIO13A_H2F_B(), 
        .SPI1_SS1_MGPIO14A_H2F_A(), .SPI1_SS1_MGPIO14A_H2F_B(), 
        .SPI1_SS2_MGPIO15A_H2F_A(), .SPI1_SS2_MGPIO15A_H2F_B(), 
        .SPI1_SS3_MGPIO16A_H2F_A(), .SPI1_SS3_MGPIO16A_H2F_B(), 
        .SPI1_SS4_MGPIO17A_H2F_A(), .SPI1_SS5_MGPIO18A_H2F_A(), 
        .SPI1_SS6_MGPIO23A_H2F_A(), .SPI1_SS7_MGPIO24A_H2F_A(), .TCGF({
        nc208, nc209, nc210, nc211, nc212, nc213, nc214, nc215, nc216, 
        nc217}), .TRACECLK(), .TRACEDATA({nc218, nc219, nc220, nc221}), 
        .TX_CLK(), .TX_ENF(), .TX_ERRF(), .TXCTL_EN_RIF(), .TXD_RIF({
        nc222, nc223, nc224, nc225}), .TXDF({nc226, nc227, nc228, 
        nc229, nc230, nc231, nc232, nc233}), .TXEV(), .WDOGTIMEOUT(), 
        .F_ARREADY_HREADYOUT1(MDDR_DDR_AXI_S_ARREADY_c), 
        .F_AWREADY_HREADYOUT0(MDDR_DDR_AXI_S_AWREADY_c), .F_BID({
        \MDDR_DDR_AXI_S_BID_c[3] , \MDDR_DDR_AXI_S_BID_c[2] , 
        \MDDR_DDR_AXI_S_BID_c[1] , \MDDR_DDR_AXI_S_BID_c[0] }), 
        .F_BRESP_HRESP0({\MDDR_DDR_AXI_S_BRESP_c[1] , 
        \MDDR_DDR_AXI_S_BRESP_c[0] }), .F_BVALID(
        MDDR_DDR_AXI_S_BVALID_c), .F_RDATA_HRDATA01({
        \MDDR_DDR_AXI_S_RDATA_c[63] , \MDDR_DDR_AXI_S_RDATA_c[62] , 
        \MDDR_DDR_AXI_S_RDATA_c[61] , \MDDR_DDR_AXI_S_RDATA_c[60] , 
        \MDDR_DDR_AXI_S_RDATA_c[59] , \MDDR_DDR_AXI_S_RDATA_c[58] , 
        \MDDR_DDR_AXI_S_RDATA_c[57] , \MDDR_DDR_AXI_S_RDATA_c[56] , 
        \MDDR_DDR_AXI_S_RDATA_c[55] , \MDDR_DDR_AXI_S_RDATA_c[54] , 
        \MDDR_DDR_AXI_S_RDATA_c[53] , \MDDR_DDR_AXI_S_RDATA_c[52] , 
        \MDDR_DDR_AXI_S_RDATA_c[51] , \MDDR_DDR_AXI_S_RDATA_c[50] , 
        \MDDR_DDR_AXI_S_RDATA_c[49] , \MDDR_DDR_AXI_S_RDATA_c[48] , 
        \MDDR_DDR_AXI_S_RDATA_c[47] , \MDDR_DDR_AXI_S_RDATA_c[46] , 
        \MDDR_DDR_AXI_S_RDATA_c[45] , \MDDR_DDR_AXI_S_RDATA_c[44] , 
        \MDDR_DDR_AXI_S_RDATA_c[43] , \MDDR_DDR_AXI_S_RDATA_c[42] , 
        \MDDR_DDR_AXI_S_RDATA_c[41] , \MDDR_DDR_AXI_S_RDATA_c[40] , 
        \MDDR_DDR_AXI_S_RDATA_c[39] , \MDDR_DDR_AXI_S_RDATA_c[38] , 
        \MDDR_DDR_AXI_S_RDATA_c[37] , \MDDR_DDR_AXI_S_RDATA_c[36] , 
        \MDDR_DDR_AXI_S_RDATA_c[35] , \MDDR_DDR_AXI_S_RDATA_c[34] , 
        \MDDR_DDR_AXI_S_RDATA_c[33] , \MDDR_DDR_AXI_S_RDATA_c[32] , 
        \MDDR_DDR_AXI_S_RDATA_c[31] , \MDDR_DDR_AXI_S_RDATA_c[30] , 
        \MDDR_DDR_AXI_S_RDATA_c[29] , \MDDR_DDR_AXI_S_RDATA_c[28] , 
        \MDDR_DDR_AXI_S_RDATA_c[27] , \MDDR_DDR_AXI_S_RDATA_c[26] , 
        \MDDR_DDR_AXI_S_RDATA_c[25] , \MDDR_DDR_AXI_S_RDATA_c[24] , 
        \MDDR_DDR_AXI_S_RDATA_c[23] , \MDDR_DDR_AXI_S_RDATA_c[22] , 
        \MDDR_DDR_AXI_S_RDATA_c[21] , \MDDR_DDR_AXI_S_RDATA_c[20] , 
        \MDDR_DDR_AXI_S_RDATA_c[19] , \MDDR_DDR_AXI_S_RDATA_c[18] , 
        \MDDR_DDR_AXI_S_RDATA_c[17] , \MDDR_DDR_AXI_S_RDATA_c[16] , 
        \MDDR_DDR_AXI_S_RDATA_c[15] , \MDDR_DDR_AXI_S_RDATA_c[14] , 
        \MDDR_DDR_AXI_S_RDATA_c[13] , \MDDR_DDR_AXI_S_RDATA_c[12] , 
        \MDDR_DDR_AXI_S_RDATA_c[11] , \MDDR_DDR_AXI_S_RDATA_c[10] , 
        \MDDR_DDR_AXI_S_RDATA_c[9] , \MDDR_DDR_AXI_S_RDATA_c[8] , 
        \MDDR_DDR_AXI_S_RDATA_c[7] , \MDDR_DDR_AXI_S_RDATA_c[6] , 
        \MDDR_DDR_AXI_S_RDATA_c[5] , \MDDR_DDR_AXI_S_RDATA_c[4] , 
        \MDDR_DDR_AXI_S_RDATA_c[3] , \MDDR_DDR_AXI_S_RDATA_c[2] , 
        \MDDR_DDR_AXI_S_RDATA_c[1] , \MDDR_DDR_AXI_S_RDATA_c[0] }), 
        .F_RID({\MDDR_DDR_AXI_S_RID_c[3] , \MDDR_DDR_AXI_S_RID_c[2] , 
        \MDDR_DDR_AXI_S_RID_c[1] , \MDDR_DDR_AXI_S_RID_c[0] }), 
        .F_RLAST(MDDR_DDR_AXI_S_RLAST_c), .F_RRESP_HRESP1({
        \MDDR_DDR_AXI_S_RRESP_c[1] , \MDDR_DDR_AXI_S_RRESP_c[0] }), 
        .F_RVALID(MDDR_DDR_AXI_S_RVALID_c), .F_WREADY(
        MDDR_DDR_AXI_S_WREADY_c), .MDDR_FABRIC_PRDATA({
        \MDDR_APB_S_PRDATA_c[15] , \MDDR_APB_S_PRDATA_c[14] , 
        \MDDR_APB_S_PRDATA_c[13] , \MDDR_APB_S_PRDATA_c[12] , 
        \MDDR_APB_S_PRDATA_c[11] , \MDDR_APB_S_PRDATA_c[10] , 
        \MDDR_APB_S_PRDATA_c[9] , \MDDR_APB_S_PRDATA_c[8] , 
        \MDDR_APB_S_PRDATA_c[7] , \MDDR_APB_S_PRDATA_c[6] , 
        \MDDR_APB_S_PRDATA_c[5] , \MDDR_APB_S_PRDATA_c[4] , 
        \MDDR_APB_S_PRDATA_c[3] , \MDDR_APB_S_PRDATA_c[2] , 
        \MDDR_APB_S_PRDATA_c[1] , \MDDR_APB_S_PRDATA_c[0] }), 
        .MDDR_FABRIC_PREADY(MDDR_APB_S_PREADY_c), .MDDR_FABRIC_PSLVERR(
        MDDR_APB_S_PSLVERR_c), .REV_ARADDR({nc234, nc235, nc236, nc237, 
        nc238, nc239, nc240, nc241, nc242, nc243, nc244, nc245, nc246, 
        nc247, nc248, nc249, nc250, nc251, nc252, nc253, nc254, nc255, 
        nc256, nc257, nc258, nc259, nc260, nc261, nc262, nc263, nc264, 
        nc265}), .REV_ARBURST({nc266, nc267}), .REV_ARID({nc268, nc269, 
        nc270, nc271}), .REV_ARLEN({nc272, nc273, nc274, nc275}), 
        .REV_ARLOCK({nc276, nc277}), .REV_ARSIZE({nc278, nc279}), 
        .REV_AWADDR({nc280, nc281, nc282, nc283, nc284, nc285, nc286, 
        nc287, nc288, nc289, nc290, nc291, nc292, nc293, nc294, nc295, 
        nc296, nc297, nc298, nc299, nc300, nc301, nc302, nc303, nc304, 
        nc305, nc306, nc307, nc308, nc309, nc310, nc311}), .REV_AWLOCK({
        nc312, nc313}), .REV_AWSIZE({nc314, nc315}), .REV_RREADY(), 
        .REV_WID({nc316, nc317, nc318, nc319}), .REV_WSTRB({nc320, 
        nc321, nc322, nc323, nc324, nc325, nc326, nc327}), 
        .CAN_RXBUS_F2H_SCP(VCC_net_1), .CAN_TX_EBL_F2H_SCP(VCC_net_1), 
        .CAN_TXBUS_F2H_SCP(VCC_net_1), .CLK_BASE(MCCC_CLK_BASE_c), 
        .COLF(VCC_net_1), .CRSF(VCC_net_1), .F2_DMAREADY({VCC_net_1, 
        VCC_net_1}), .F2H_INTERRUPT({GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1}), .F2HCALIB(VCC_net_1), 
        .F_DMAREADY({VCC_net_1, VCC_net_1}), .F_FM0_ADDR({
        \FIC_0_AHB_S_HADDR_c[31] , \FIC_0_AHB_S_HADDR_c[30] , 
        \FIC_0_AHB_S_HADDR_c[29] , \FIC_0_AHB_S_HADDR_c[28] , 
        \FIC_0_AHB_S_HADDR_c[27] , \FIC_0_AHB_S_HADDR_c[26] , 
        \FIC_0_AHB_S_HADDR_c[25] , \FIC_0_AHB_S_HADDR_c[24] , 
        \FIC_0_AHB_S_HADDR_c[23] , \FIC_0_AHB_S_HADDR_c[22] , 
        \FIC_0_AHB_S_HADDR_c[21] , \FIC_0_AHB_S_HADDR_c[20] , 
        \FIC_0_AHB_S_HADDR_c[19] , \FIC_0_AHB_S_HADDR_c[18] , 
        \FIC_0_AHB_S_HADDR_c[17] , \FIC_0_AHB_S_HADDR_c[16] , 
        \FIC_0_AHB_S_HADDR_c[15] , \FIC_0_AHB_S_HADDR_c[14] , 
        \FIC_0_AHB_S_HADDR_c[13] , \FIC_0_AHB_S_HADDR_c[12] , 
        \FIC_0_AHB_S_HADDR_c[11] , \FIC_0_AHB_S_HADDR_c[10] , 
        \FIC_0_AHB_S_HADDR_c[9] , \FIC_0_AHB_S_HADDR_c[8] , 
        \FIC_0_AHB_S_HADDR_c[7] , \FIC_0_AHB_S_HADDR_c[6] , 
        \FIC_0_AHB_S_HADDR_c[5] , \FIC_0_AHB_S_HADDR_c[4] , 
        \FIC_0_AHB_S_HADDR_c[3] , \FIC_0_AHB_S_HADDR_c[2] , 
        \FIC_0_AHB_S_HADDR_c[1] , \FIC_0_AHB_S_HADDR_c[0] }), 
        .F_FM0_ENABLE(GND_net_1), .F_FM0_MASTLOCK(
        FIC_0_AHB_S_HMASTLOCK_c), .F_FM0_READY(FIC_0_AHB_S_HREADY_c), 
        .F_FM0_SEL(FIC_0_AHB_S_HSEL_c), .F_FM0_SIZE({
        \FIC_0_AHB_S_HSIZE_c[1] , \FIC_0_AHB_S_HSIZE_c[0] }), 
        .F_FM0_TRANS1(\FIC_0_AHB_S_HTRANS_c[1] ), .F_FM0_WDATA({
        \FIC_0_AHB_S_HWDATA_c[31] , \FIC_0_AHB_S_HWDATA_c[30] , 
        \FIC_0_AHB_S_HWDATA_c[29] , \FIC_0_AHB_S_HWDATA_c[28] , 
        \FIC_0_AHB_S_HWDATA_c[27] , \FIC_0_AHB_S_HWDATA_c[26] , 
        \FIC_0_AHB_S_HWDATA_c[25] , \FIC_0_AHB_S_HWDATA_c[24] , 
        \FIC_0_AHB_S_HWDATA_c[23] , \FIC_0_AHB_S_HWDATA_c[22] , 
        \FIC_0_AHB_S_HWDATA_c[21] , \FIC_0_AHB_S_HWDATA_c[20] , 
        \FIC_0_AHB_S_HWDATA_c[19] , \FIC_0_AHB_S_HWDATA_c[18] , 
        \FIC_0_AHB_S_HWDATA_c[17] , \FIC_0_AHB_S_HWDATA_c[16] , 
        \FIC_0_AHB_S_HWDATA_c[15] , \FIC_0_AHB_S_HWDATA_c[14] , 
        \FIC_0_AHB_S_HWDATA_c[13] , \FIC_0_AHB_S_HWDATA_c[12] , 
        \FIC_0_AHB_S_HWDATA_c[11] , \FIC_0_AHB_S_HWDATA_c[10] , 
        \FIC_0_AHB_S_HWDATA_c[9] , \FIC_0_AHB_S_HWDATA_c[8] , 
        \FIC_0_AHB_S_HWDATA_c[7] , \FIC_0_AHB_S_HWDATA_c[6] , 
        \FIC_0_AHB_S_HWDATA_c[5] , \FIC_0_AHB_S_HWDATA_c[4] , 
        \FIC_0_AHB_S_HWDATA_c[3] , \FIC_0_AHB_S_HWDATA_c[2] , 
        \FIC_0_AHB_S_HWDATA_c[1] , \FIC_0_AHB_S_HWDATA_c[0] }), 
        .F_FM0_WRITE(FIC_0_AHB_S_HWRITE_c), .F_FM1_ADDR({GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1}), .F_FM1_ENABLE(GND_net_1), .F_FM1_MASTLOCK(
        GND_net_1), .F_FM1_READY(VCC_net_1), .F_FM1_SEL(GND_net_1), 
        .F_FM1_SIZE({GND_net_1, GND_net_1}), .F_FM1_TRANS1(GND_net_1), 
        .F_FM1_WDATA({GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1}), .F_FM1_WRITE(GND_net_1), 
        .F_HM0_RDATA({GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1}), .F_HM0_READY(VCC_net_1), 
        .F_HM0_RESP(GND_net_1), .F_HM1_RDATA({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .F_HM1_READY(VCC_net_1), .F_HM1_RESP(GND_net_1), .FAB_AVALID(
        VCC_net_1), .FAB_HOSTDISCON(VCC_net_1), .FAB_IDDIG(VCC_net_1), 
        .FAB_LINESTATE({VCC_net_1, VCC_net_1}), .FAB_M3_RESET_N(
        M3_RESET_N_c), .FAB_PLL_LOCK(MCCC_CLK_BASE_PLL_LOCK_c), 
        .FAB_RXACTIVE(VCC_net_1), .FAB_RXERROR(VCC_net_1), 
        .FAB_RXVALID(VCC_net_1), .FAB_RXVALIDH(GND_net_1), 
        .FAB_SESSEND(VCC_net_1), .FAB_TXREADY(VCC_net_1), 
        .FAB_VBUSVALID(VCC_net_1), .FAB_VSTATUS({VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1}), .FAB_XDATAIN({VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .GTX_CLKPF(VCC_net_1), .I2C0_BCLK(VCC_net_1), 
        .I2C0_SCL_F2H_SCP(VCC_net_1), .I2C0_SDA_F2H_SCP(VCC_net_1), 
        .I2C1_BCLK(VCC_net_1), .I2C1_SCL_F2H_SCP(VCC_net_1), 
        .I2C1_SDA_F2H_SCP(VCC_net_1), .MDIF(VCC_net_1), 
        .MGPIO0A_F2H_GPIN(VCC_net_1), .MGPIO10A_F2H_GPIN(VCC_net_1), 
        .MGPIO11A_F2H_GPIN(GPIO_11_F2M_c), .MGPIO11B_F2H_GPIN(
        VCC_net_1), .MGPIO12A_F2H_GPIN(GPIO_12_F2M_c), 
        .MGPIO13A_F2H_GPIN(VCC_net_1), .MGPIO14A_F2H_GPIN(VCC_net_1), 
        .MGPIO15A_F2H_GPIN(VCC_net_1), .MGPIO16A_F2H_GPIN(VCC_net_1), 
        .MGPIO17B_F2H_GPIN(VCC_net_1), .MGPIO18B_F2H_GPIN(VCC_net_1), 
        .MGPIO19B_F2H_GPIN(VCC_net_1), .MGPIO1A_F2H_GPIN(VCC_net_1), 
        .MGPIO20B_F2H_GPIN(VCC_net_1), .MGPIO21B_F2H_GPIN(VCC_net_1), 
        .MGPIO22B_F2H_GPIN(VCC_net_1), .MGPIO24B_F2H_GPIN(VCC_net_1), 
        .MGPIO25B_F2H_GPIN(VCC_net_1), .MGPIO26B_F2H_GPIN(VCC_net_1), 
        .MGPIO27B_F2H_GPIN(VCC_net_1), .MGPIO28B_F2H_GPIN(VCC_net_1), 
        .MGPIO29B_F2H_GPIN(VCC_net_1), .MGPIO2A_F2H_GPIN(VCC_net_1), 
        .MGPIO30B_F2H_GPIN(VCC_net_1), .MGPIO31B_F2H_GPIN(VCC_net_1), 
        .MGPIO3A_F2H_GPIN(VCC_net_1), .MGPIO4A_F2H_GPIN(VCC_net_1), 
        .MGPIO5A_F2H_GPIN(VCC_net_1), .MGPIO6A_F2H_GPIN(VCC_net_1), 
        .MGPIO7A_F2H_GPIN(VCC_net_1), .MGPIO8A_F2H_GPIN(VCC_net_1), 
        .MGPIO9A_F2H_GPIN(VCC_net_1), .MMUART0_CTS_F2H_SCP(VCC_net_1), 
        .MMUART0_DCD_F2H_SCP(VCC_net_1), .MMUART0_DSR_F2H_SCP(
        VCC_net_1), .MMUART0_DTR_F2H_SCP(VCC_net_1), 
        .MMUART0_RI_F2H_SCP(VCC_net_1), .MMUART0_RTS_F2H_SCP(VCC_net_1)
        , .MMUART0_RXD_F2H_SCP(VCC_net_1), .MMUART0_SCK_F2H_SCP(
        VCC_net_1), .MMUART0_TXD_F2H_SCP(VCC_net_1), 
        .MMUART1_CTS_F2H_SCP(VCC_net_1), .MMUART1_DCD_F2H_SCP(
        VCC_net_1), .MMUART1_DSR_F2H_SCP(VCC_net_1), 
        .MMUART1_RI_F2H_SCP(VCC_net_1), .MMUART1_RTS_F2H_SCP(VCC_net_1)
        , .MMUART1_RXD_F2H_SCP(VCC_net_1), .MMUART1_SCK_F2H_SCP(
        VCC_net_1), .MMUART1_TXD_F2H_SCP(VCC_net_1), 
        .PER2_FABRIC_PRDATA({\FIC_2_APB_M_PRDATA_c[31] , 
        \FIC_2_APB_M_PRDATA_c[30] , \FIC_2_APB_M_PRDATA_c[29] , 
        \FIC_2_APB_M_PRDATA_c[28] , \FIC_2_APB_M_PRDATA_c[27] , 
        \FIC_2_APB_M_PRDATA_c[26] , \FIC_2_APB_M_PRDATA_c[25] , 
        \FIC_2_APB_M_PRDATA_c[24] , \FIC_2_APB_M_PRDATA_c[23] , 
        \FIC_2_APB_M_PRDATA_c[22] , \FIC_2_APB_M_PRDATA_c[21] , 
        \FIC_2_APB_M_PRDATA_c[20] , \FIC_2_APB_M_PRDATA_c[19] , 
        \FIC_2_APB_M_PRDATA_c[18] , \FIC_2_APB_M_PRDATA_c[17] , 
        \FIC_2_APB_M_PRDATA_c[16] , \FIC_2_APB_M_PRDATA_c[15] , 
        \FIC_2_APB_M_PRDATA_c[14] , \FIC_2_APB_M_PRDATA_c[13] , 
        \FIC_2_APB_M_PRDATA_c[12] , \FIC_2_APB_M_PRDATA_c[11] , 
        \FIC_2_APB_M_PRDATA_c[10] , \FIC_2_APB_M_PRDATA_c[9] , 
        \FIC_2_APB_M_PRDATA_c[8] , \FIC_2_APB_M_PRDATA_c[7] , 
        \FIC_2_APB_M_PRDATA_c[6] , \FIC_2_APB_M_PRDATA_c[5] , 
        \FIC_2_APB_M_PRDATA_c[4] , \FIC_2_APB_M_PRDATA_c[3] , 
        \FIC_2_APB_M_PRDATA_c[2] , \FIC_2_APB_M_PRDATA_c[1] , 
        \FIC_2_APB_M_PRDATA_c[0] }), .PER2_FABRIC_PREADY(
        FIC_2_APB_M_PREADY_c), .PER2_FABRIC_PSLVERR(
        FIC_2_APB_M_PSLVERR_c), .RCGF({VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1}), .RX_CLKPF(VCC_net_1), .RX_DVF(
        VCC_net_1), .RX_ERRF(VCC_net_1), .RX_EV(VCC_net_1), .RXDF({
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1}), .SLEEPHOLDREQ(GND_net_1), 
        .SMBALERT_NI0(VCC_net_1), .SMBALERT_NI1(VCC_net_1), 
        .SMBSUS_NI0(VCC_net_1), .SMBSUS_NI1(VCC_net_1), .SPI0_CLK_IN(
        VCC_net_1), .SPI0_SDI_F2H_SCP(VCC_net_1), .SPI0_SDO_F2H_SCP(
        VCC_net_1), .SPI0_SS0_F2H_SCP(VCC_net_1), .SPI0_SS1_F2H_SCP(
        VCC_net_1), .SPI0_SS2_F2H_SCP(VCC_net_1), .SPI0_SS3_F2H_SCP(
        VCC_net_1), .SPI1_CLK_IN(VCC_net_1), .SPI1_SDI_F2H_SCP(
        VCC_net_1), .SPI1_SDO_F2H_SCP(VCC_net_1), .SPI1_SS0_F2H_SCP(
        VCC_net_1), .SPI1_SS1_F2H_SCP(VCC_net_1), .SPI1_SS2_F2H_SCP(
        VCC_net_1), .SPI1_SS3_F2H_SCP(VCC_net_1), .TX_CLKPF(VCC_net_1), 
        .USER_MSS_GPIO_RESET_N(VCC_net_1), .USER_MSS_RESET_N(VCC_net_1)
        , .XCLK_FAB(VCC_net_1), .CLK_MDDR_APB(MDDR_APB_S_PCLK_c), 
        .F_ARADDR_HADDR1({\MDDR_DDR_AXI_S_ARADDR_c[31] , 
        \MDDR_DDR_AXI_S_ARADDR_c[30] , \MDDR_DDR_AXI_S_ARADDR_c[29] , 
        \MDDR_DDR_AXI_S_ARADDR_c[28] , \MDDR_DDR_AXI_S_ARADDR_c[27] , 
        \MDDR_DDR_AXI_S_ARADDR_c[26] , \MDDR_DDR_AXI_S_ARADDR_c[25] , 
        \MDDR_DDR_AXI_S_ARADDR_c[24] , \MDDR_DDR_AXI_S_ARADDR_c[23] , 
        \MDDR_DDR_AXI_S_ARADDR_c[22] , \MDDR_DDR_AXI_S_ARADDR_c[21] , 
        \MDDR_DDR_AXI_S_ARADDR_c[20] , \MDDR_DDR_AXI_S_ARADDR_c[19] , 
        \MDDR_DDR_AXI_S_ARADDR_c[18] , \MDDR_DDR_AXI_S_ARADDR_c[17] , 
        \MDDR_DDR_AXI_S_ARADDR_c[16] , \MDDR_DDR_AXI_S_ARADDR_c[15] , 
        \MDDR_DDR_AXI_S_ARADDR_c[14] , \MDDR_DDR_AXI_S_ARADDR_c[13] , 
        \MDDR_DDR_AXI_S_ARADDR_c[12] , \MDDR_DDR_AXI_S_ARADDR_c[11] , 
        \MDDR_DDR_AXI_S_ARADDR_c[10] , \MDDR_DDR_AXI_S_ARADDR_c[9] , 
        \MDDR_DDR_AXI_S_ARADDR_c[8] , \MDDR_DDR_AXI_S_ARADDR_c[7] , 
        \MDDR_DDR_AXI_S_ARADDR_c[6] , \MDDR_DDR_AXI_S_ARADDR_c[5] , 
        \MDDR_DDR_AXI_S_ARADDR_c[4] , \MDDR_DDR_AXI_S_ARADDR_c[3] , 
        \MDDR_DDR_AXI_S_ARADDR_c[2] , \MDDR_DDR_AXI_S_ARADDR_c[1] , 
        \MDDR_DDR_AXI_S_ARADDR_c[0] }), .F_ARBURST_HTRANS1({
        \MDDR_DDR_AXI_S_ARBURST_c[1] , \MDDR_DDR_AXI_S_ARBURST_c[0] }), 
        .F_ARID_HSEL1({\MDDR_DDR_AXI_S_ARID_c[3] , 
        \MDDR_DDR_AXI_S_ARID_c[2] , \MDDR_DDR_AXI_S_ARID_c[1] , 
        \MDDR_DDR_AXI_S_ARID_c[0] }), .F_ARLEN_HBURST1({
        \MDDR_DDR_AXI_S_ARLEN_c[3] , \MDDR_DDR_AXI_S_ARLEN_c[2] , 
        \MDDR_DDR_AXI_S_ARLEN_c[1] , \MDDR_DDR_AXI_S_ARLEN_c[0] }), 
        .F_ARLOCK_HMASTLOCK1({\MDDR_DDR_AXI_S_ARLOCK_c[1] , 
        \MDDR_DDR_AXI_S_ARLOCK_c[0] }), .F_ARSIZE_HSIZE1({
        \MDDR_DDR_AXI_S_ARSIZE_c[1] , \MDDR_DDR_AXI_S_ARSIZE_c[0] }), 
        .F_ARVALID_HWRITE1(MDDR_DDR_AXI_S_ARVALID_c), .F_AWADDR_HADDR0({
        \MDDR_DDR_AXI_S_AWADDR_c[31] , \MDDR_DDR_AXI_S_AWADDR_c[30] , 
        \MDDR_DDR_AXI_S_AWADDR_c[29] , \MDDR_DDR_AXI_S_AWADDR_c[28] , 
        \MDDR_DDR_AXI_S_AWADDR_c[27] , \MDDR_DDR_AXI_S_AWADDR_c[26] , 
        \MDDR_DDR_AXI_S_AWADDR_c[25] , \MDDR_DDR_AXI_S_AWADDR_c[24] , 
        \MDDR_DDR_AXI_S_AWADDR_c[23] , \MDDR_DDR_AXI_S_AWADDR_c[22] , 
        \MDDR_DDR_AXI_S_AWADDR_c[21] , \MDDR_DDR_AXI_S_AWADDR_c[20] , 
        \MDDR_DDR_AXI_S_AWADDR_c[19] , \MDDR_DDR_AXI_S_AWADDR_c[18] , 
        \MDDR_DDR_AXI_S_AWADDR_c[17] , \MDDR_DDR_AXI_S_AWADDR_c[16] , 
        \MDDR_DDR_AXI_S_AWADDR_c[15] , \MDDR_DDR_AXI_S_AWADDR_c[14] , 
        \MDDR_DDR_AXI_S_AWADDR_c[13] , \MDDR_DDR_AXI_S_AWADDR_c[12] , 
        \MDDR_DDR_AXI_S_AWADDR_c[11] , \MDDR_DDR_AXI_S_AWADDR_c[10] , 
        \MDDR_DDR_AXI_S_AWADDR_c[9] , \MDDR_DDR_AXI_S_AWADDR_c[8] , 
        \MDDR_DDR_AXI_S_AWADDR_c[7] , \MDDR_DDR_AXI_S_AWADDR_c[6] , 
        \MDDR_DDR_AXI_S_AWADDR_c[5] , \MDDR_DDR_AXI_S_AWADDR_c[4] , 
        \MDDR_DDR_AXI_S_AWADDR_c[3] , \MDDR_DDR_AXI_S_AWADDR_c[2] , 
        \MDDR_DDR_AXI_S_AWADDR_c[1] , \MDDR_DDR_AXI_S_AWADDR_c[0] }), 
        .F_AWBURST_HTRANS0({\MDDR_DDR_AXI_S_AWBURST_c[1] , 
        \MDDR_DDR_AXI_S_AWBURST_c[0] }), .F_AWID_HSEL0({
        \MDDR_DDR_AXI_S_AWID_c[3] , \MDDR_DDR_AXI_S_AWID_c[2] , 
        \MDDR_DDR_AXI_S_AWID_c[1] , \MDDR_DDR_AXI_S_AWID_c[0] }), 
        .F_AWLEN_HBURST0({\MDDR_DDR_AXI_S_AWLEN_c[3] , 
        \MDDR_DDR_AXI_S_AWLEN_c[2] , \MDDR_DDR_AXI_S_AWLEN_c[1] , 
        \MDDR_DDR_AXI_S_AWLEN_c[0] }), .F_AWLOCK_HMASTLOCK0({
        \MDDR_DDR_AXI_S_AWLOCK_c[1] , \MDDR_DDR_AXI_S_AWLOCK_c[0] }), 
        .F_AWSIZE_HSIZE0({\MDDR_DDR_AXI_S_AWSIZE_c[1] , 
        \MDDR_DDR_AXI_S_AWSIZE_c[0] }), .F_AWVALID_HWRITE0(
        MDDR_DDR_AXI_S_AWVALID_c), .F_BREADY(MDDR_DDR_AXI_S_BREADY_c), 
        .F_RMW_AXI(MDDR_DDR_AXI_S_RMW_c), .F_RREADY(
        MDDR_DDR_AXI_S_RREADY_c), .F_WDATA_HWDATA01({
        \MDDR_DDR_AXI_S_WDATA_c[63] , \MDDR_DDR_AXI_S_WDATA_c[62] , 
        \MDDR_DDR_AXI_S_WDATA_c[61] , \MDDR_DDR_AXI_S_WDATA_c[60] , 
        \MDDR_DDR_AXI_S_WDATA_c[59] , \MDDR_DDR_AXI_S_WDATA_c[58] , 
        \MDDR_DDR_AXI_S_WDATA_c[57] , \MDDR_DDR_AXI_S_WDATA_c[56] , 
        \MDDR_DDR_AXI_S_WDATA_c[55] , \MDDR_DDR_AXI_S_WDATA_c[54] , 
        \MDDR_DDR_AXI_S_WDATA_c[53] , \MDDR_DDR_AXI_S_WDATA_c[52] , 
        \MDDR_DDR_AXI_S_WDATA_c[51] , \MDDR_DDR_AXI_S_WDATA_c[50] , 
        \MDDR_DDR_AXI_S_WDATA_c[49] , \MDDR_DDR_AXI_S_WDATA_c[48] , 
        \MDDR_DDR_AXI_S_WDATA_c[47] , \MDDR_DDR_AXI_S_WDATA_c[46] , 
        \MDDR_DDR_AXI_S_WDATA_c[45] , \MDDR_DDR_AXI_S_WDATA_c[44] , 
        \MDDR_DDR_AXI_S_WDATA_c[43] , \MDDR_DDR_AXI_S_WDATA_c[42] , 
        \MDDR_DDR_AXI_S_WDATA_c[41] , \MDDR_DDR_AXI_S_WDATA_c[40] , 
        \MDDR_DDR_AXI_S_WDATA_c[39] , \MDDR_DDR_AXI_S_WDATA_c[38] , 
        \MDDR_DDR_AXI_S_WDATA_c[37] , \MDDR_DDR_AXI_S_WDATA_c[36] , 
        \MDDR_DDR_AXI_S_WDATA_c[35] , \MDDR_DDR_AXI_S_WDATA_c[34] , 
        \MDDR_DDR_AXI_S_WDATA_c[33] , \MDDR_DDR_AXI_S_WDATA_c[32] , 
        \MDDR_DDR_AXI_S_WDATA_c[31] , \MDDR_DDR_AXI_S_WDATA_c[30] , 
        \MDDR_DDR_AXI_S_WDATA_c[29] , \MDDR_DDR_AXI_S_WDATA_c[28] , 
        \MDDR_DDR_AXI_S_WDATA_c[27] , \MDDR_DDR_AXI_S_WDATA_c[26] , 
        \MDDR_DDR_AXI_S_WDATA_c[25] , \MDDR_DDR_AXI_S_WDATA_c[24] , 
        \MDDR_DDR_AXI_S_WDATA_c[23] , \MDDR_DDR_AXI_S_WDATA_c[22] , 
        \MDDR_DDR_AXI_S_WDATA_c[21] , \MDDR_DDR_AXI_S_WDATA_c[20] , 
        \MDDR_DDR_AXI_S_WDATA_c[19] , \MDDR_DDR_AXI_S_WDATA_c[18] , 
        \MDDR_DDR_AXI_S_WDATA_c[17] , \MDDR_DDR_AXI_S_WDATA_c[16] , 
        \MDDR_DDR_AXI_S_WDATA_c[15] , \MDDR_DDR_AXI_S_WDATA_c[14] , 
        \MDDR_DDR_AXI_S_WDATA_c[13] , \MDDR_DDR_AXI_S_WDATA_c[12] , 
        \MDDR_DDR_AXI_S_WDATA_c[11] , \MDDR_DDR_AXI_S_WDATA_c[10] , 
        \MDDR_DDR_AXI_S_WDATA_c[9] , \MDDR_DDR_AXI_S_WDATA_c[8] , 
        \MDDR_DDR_AXI_S_WDATA_c[7] , \MDDR_DDR_AXI_S_WDATA_c[6] , 
        \MDDR_DDR_AXI_S_WDATA_c[5] , \MDDR_DDR_AXI_S_WDATA_c[4] , 
        \MDDR_DDR_AXI_S_WDATA_c[3] , \MDDR_DDR_AXI_S_WDATA_c[2] , 
        \MDDR_DDR_AXI_S_WDATA_c[1] , \MDDR_DDR_AXI_S_WDATA_c[0] }), 
        .F_WID_HREADY01({\MDDR_DDR_AXI_S_WID_c[3] , 
        \MDDR_DDR_AXI_S_WID_c[2] , \MDDR_DDR_AXI_S_WID_c[1] , 
        \MDDR_DDR_AXI_S_WID_c[0] }), .F_WLAST(MDDR_DDR_AXI_S_WLAST_c), 
        .F_WSTRB({\MDDR_DDR_AXI_S_WSTRB_c[7] , 
        \MDDR_DDR_AXI_S_WSTRB_c[6] , \MDDR_DDR_AXI_S_WSTRB_c[5] , 
        \MDDR_DDR_AXI_S_WSTRB_c[4] , \MDDR_DDR_AXI_S_WSTRB_c[3] , 
        \MDDR_DDR_AXI_S_WSTRB_c[2] , \MDDR_DDR_AXI_S_WSTRB_c[1] , 
        \MDDR_DDR_AXI_S_WSTRB_c[0] }), .F_WVALID(
        MDDR_DDR_AXI_S_WVALID_c), .FPGA_MDDR_ARESET_N(
        MDDR_DDR_CORE_RESET_N_c), .MDDR_FABRIC_PADDR({
        \MDDR_APB_S_PADDR_c[10] , \MDDR_APB_S_PADDR_c[9] , 
        \MDDR_APB_S_PADDR_c[8] , \MDDR_APB_S_PADDR_c[7] , 
        \MDDR_APB_S_PADDR_c[6] , \MDDR_APB_S_PADDR_c[5] , 
        \MDDR_APB_S_PADDR_c[4] , \MDDR_APB_S_PADDR_c[3] , 
        \MDDR_APB_S_PADDR_c[2] }), .MDDR_FABRIC_PENABLE(
        MDDR_APB_S_PENABLE_c), .MDDR_FABRIC_PSEL(MDDR_APB_S_PSEL_c), 
        .MDDR_FABRIC_PWDATA({\MDDR_APB_S_PWDATA_c[15] , 
        \MDDR_APB_S_PWDATA_c[14] , \MDDR_APB_S_PWDATA_c[13] , 
        \MDDR_APB_S_PWDATA_c[12] , \MDDR_APB_S_PWDATA_c[11] , 
        \MDDR_APB_S_PWDATA_c[10] , \MDDR_APB_S_PWDATA_c[9] , 
        \MDDR_APB_S_PWDATA_c[8] , \MDDR_APB_S_PWDATA_c[7] , 
        \MDDR_APB_S_PWDATA_c[6] , \MDDR_APB_S_PWDATA_c[5] , 
        \MDDR_APB_S_PWDATA_c[4] , \MDDR_APB_S_PWDATA_c[3] , 
        \MDDR_APB_S_PWDATA_c[2] , \MDDR_APB_S_PWDATA_c[1] , 
        \MDDR_APB_S_PWDATA_c[0] }), .MDDR_FABRIC_PWRITE(
        MDDR_APB_S_PWRITE_c), .PRESET_N(MDDR_APB_S_PRESET_N_c), 
        .CAN_RXBUS_USBA_DATA1_MGPIO3A_IN(GND_net_1), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN(GND_net_1), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_IN(GND_net_1), .DM_IN({GND_net_1, 
        GND_net_1, GND_net_1, MDDR_DM_RDQS_1_PAD_Y, 
        MDDR_DM_RDQS_0_PAD_Y}), .DRAM_DQ_IN({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, MDDR_DQ_15_PAD_Y, 
        MDDR_DQ_14_PAD_Y, MDDR_DQ_13_PAD_Y, MDDR_DQ_12_PAD_Y, 
        MDDR_DQ_11_PAD_Y, MDDR_DQ_10_PAD_Y, MDDR_DQ_9_PAD_Y, 
        MDDR_DQ_8_PAD_Y, MDDR_DQ_7_PAD_Y, MDDR_DQ_6_PAD_Y, 
        MDDR_DQ_5_PAD_Y, MDDR_DQ_4_PAD_Y, MDDR_DQ_3_PAD_Y, 
        MDDR_DQ_2_PAD_Y, MDDR_DQ_1_PAD_Y, MDDR_DQ_0_PAD_Y}), 
        .DRAM_DQS_IN({GND_net_1, GND_net_1, GND_net_1, 
        MDDR_DQS_1_PAD_Y, MDDR_DQS_0_PAD_Y}), .DRAM_FIFO_WE_IN({
        GND_net_1, GND_net_1, MDDR_DQS_TMATCH_0_IN_PAD_Y}), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_IN(GND_net_1), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_IN(GND_net_1), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_IN(GND_net_1), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_IN(GND_net_1), .MGPIO0B_IN(
        GND_net_1), .MGPIO10B_IN(GND_net_1), .MGPIO1B_IN(GND_net_1), 
        .MGPIO25A_IN(GND_net_1), .MGPIO26A_IN(GND_net_1), .MGPIO27A_IN(
        GND_net_1), .MGPIO28A_IN(GND_net_1), .MGPIO29A_IN(GND_net_1), 
        .MGPIO2B_IN(GND_net_1), .MGPIO30A_IN(GND_net_1), .MGPIO31A_IN(
        GND_net_1), .MGPIO3B_IN(GND_net_1), .MGPIO4B_IN(GND_net_1), 
        .MGPIO5B_IN(GND_net_1), .MGPIO6B_IN(GND_net_1), .MGPIO7B_IN(
        GND_net_1), .MGPIO8B_IN(GND_net_1), .MGPIO9B_IN(GND_net_1), 
        .MMUART0_CTS_USBC_DATA7_MGPIO19B_IN(GND_net_1), 
        .MMUART0_DCD_MGPIO22B_IN(GND_net_1), .MMUART0_DSR_MGPIO20B_IN(
        GND_net_1), .MMUART0_DTR_USBC_DATA6_MGPIO18B_IN(GND_net_1), 
        .MMUART0_RI_MGPIO21B_IN(GND_net_1), 
        .MMUART0_RTS_USBC_DATA5_MGPIO17B_IN(GND_net_1), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_IN(MMUART_0_RXD_PAD_Y), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_IN(GND_net_1), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_IN(GND_net_1), 
        .MMUART1_CTS_MGPIO13B_IN(GND_net_1), .MMUART1_DCD_MGPIO16B_IN(
        GND_net_1), .MMUART1_DSR_MGPIO14B_IN(GND_net_1), 
        .MMUART1_DTR_MGPIO12B_IN(GND_net_1), .MMUART1_RI_MGPIO15B_IN(
        GND_net_1), .MMUART1_RTS_MGPIO11B_IN(GND_net_1), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_IN(GND_net_1), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_IN(GND_net_1), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_IN(GND_net_1), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN(GND_net_1), 
        .RGMII_MDC_RMII_MDC_IN(GND_net_1), 
        .RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN(GND_net_1), 
        .RGMII_RX_CLK_IN(GND_net_1), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN(GND_net_1), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN(GND_net_1), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN(GND_net_1), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN(GND_net_1), 
        .RGMII_RXD3_USBB_DATA4_IN(GND_net_1), .RGMII_TX_CLK_IN(
        GND_net_1), .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN(GND_net_1), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_IN(GND_net_1), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_IN(GND_net_1), 
        .RGMII_TXD2_USBB_DATA5_IN(GND_net_1), 
        .RGMII_TXD3_USBB_DATA6_IN(GND_net_1), .SPI0_SCK_USBA_XCLK_IN(
        SPI_0_CLK_PAD_Y), .SPI0_SDI_USBA_DIR_MGPIO5A_IN(SPI_0_DI_PAD_Y)
        , .SPI0_SDO_USBA_STP_MGPIO6A_IN(GND_net_1), 
        .SPI0_SS0_USBA_NXT_MGPIO7A_IN(SPI_0_SS0_PAD_Y), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_IN(GND_net_1), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_IN(GND_net_1), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_IN(GND_net_1), 
        .SPI0_SS4_MGPIO19A_IN(GND_net_1), .SPI0_SS5_MGPIO20A_IN(
        GND_net_1), .SPI0_SS6_MGPIO21A_IN(GND_net_1), 
        .SPI0_SS7_MGPIO22A_IN(GND_net_1), .SPI1_SCK_IN(GND_net_1), 
        .SPI1_SDI_MGPIO11A_IN(GND_net_1), .SPI1_SDO_MGPIO12A_IN(
        GND_net_1), .SPI1_SS0_MGPIO13A_IN(GND_net_1), 
        .SPI1_SS1_MGPIO14A_IN(GND_net_1), .SPI1_SS2_MGPIO15A_IN(
        GND_net_1), .SPI1_SS3_MGPIO16A_IN(GND_net_1), 
        .SPI1_SS4_MGPIO17A_IN(GND_net_1), .SPI1_SS5_MGPIO18A_IN(
        GND_net_1), .SPI1_SS6_MGPIO23A_IN(GND_net_1), 
        .SPI1_SS7_MGPIO24A_IN(GND_net_1), .USBC_XCLK_IN(GND_net_1), 
        .USBD_DATA0_IN(GND_net_1), .USBD_DATA1_IN(GND_net_1), 
        .USBD_DATA2_IN(GND_net_1), .USBD_DATA3_IN(GND_net_1), 
        .USBD_DATA4_IN(GND_net_1), .USBD_DATA5_IN(GND_net_1), 
        .USBD_DATA6_IN(GND_net_1), .USBD_DATA7_MGPIO23B_IN(GND_net_1), 
        .USBD_DIR_IN(GND_net_1), .USBD_NXT_IN(GND_net_1), .USBD_STP_IN(
        GND_net_1), .USBD_XCLK_IN(GND_net_1), 
        .CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT(), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT(), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT(), .DRAM_ADDR({
        \DRAM_ADDR_net_0[15] , \DRAM_ADDR_net_0[14] , 
        \DRAM_ADDR_net_0[13] , \DRAM_ADDR_net_0[12] , 
        \DRAM_ADDR_net_0[11] , \DRAM_ADDR_net_0[10] , 
        \DRAM_ADDR_net_0[9] , \DRAM_ADDR_net_0[8] , 
        \DRAM_ADDR_net_0[7] , \DRAM_ADDR_net_0[6] , 
        \DRAM_ADDR_net_0[5] , \DRAM_ADDR_net_0[4] , 
        \DRAM_ADDR_net_0[3] , \DRAM_ADDR_net_0[2] , 
        \DRAM_ADDR_net_0[1] , \DRAM_ADDR_net_0[0] }), .DRAM_BA({
        \DRAM_BA_net_0[2] , \DRAM_BA_net_0[1] , \DRAM_BA_net_0[0] }), 
        .DRAM_CASN(MSS_ADLIB_INST_DRAM_CASN), .DRAM_CKE(
        MSS_ADLIB_INST_DRAM_CKE), .DRAM_CLK(MSS_ADLIB_INST_DRAM_CLK), 
        .DRAM_CSN(MSS_ADLIB_INST_DRAM_CSN), .DRAM_DM_RDQS_OUT({nc328, 
        nc329, nc330, \DRAM_DM_RDQS_OUT_net_0[1] , 
        \DRAM_DM_RDQS_OUT_net_0[0] }), .DRAM_DQ_OUT({nc331, nc332, 
        nc333, nc334, nc335, nc336, nc337, nc338, nc339, nc340, nc341, 
        nc342, nc343, nc344, nc345, nc346, nc347, nc348, nc349, nc350, 
        \DRAM_DQ_OUT_net_0[15] , \DRAM_DQ_OUT_net_0[14] , 
        \DRAM_DQ_OUT_net_0[13] , \DRAM_DQ_OUT_net_0[12] , 
        \DRAM_DQ_OUT_net_0[11] , \DRAM_DQ_OUT_net_0[10] , 
        \DRAM_DQ_OUT_net_0[9] , \DRAM_DQ_OUT_net_0[8] , 
        \DRAM_DQ_OUT_net_0[7] , \DRAM_DQ_OUT_net_0[6] , 
        \DRAM_DQ_OUT_net_0[5] , \DRAM_DQ_OUT_net_0[4] , 
        \DRAM_DQ_OUT_net_0[3] , \DRAM_DQ_OUT_net_0[2] , 
        \DRAM_DQ_OUT_net_0[1] , \DRAM_DQ_OUT_net_0[0] }), 
        .DRAM_DQS_OUT({nc351, nc352, nc353, \DRAM_DQS_OUT_net_0[1] , 
        \DRAM_DQS_OUT_net_0[0] }), .DRAM_FIFO_WE_OUT({nc354, nc355, 
        \DRAM_FIFO_WE_OUT_net_0[0] }), .DRAM_ODT(
        MSS_ADLIB_INST_DRAM_ODT), .DRAM_RASN(MSS_ADLIB_INST_DRAM_RASN), 
        .DRAM_RSTN(MSS_ADLIB_INST_DRAM_RSTN), .DRAM_WEN(
        MSS_ADLIB_INST_DRAM_WEN), .I2C0_SCL_USBC_DATA1_MGPIO31B_OUT(), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_OUT(), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_OUT(), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_OUT(), .MGPIO0B_OUT(), 
        .MGPIO10B_OUT(), .MGPIO1B_OUT(), .MGPIO25A_OUT(), 
        .MGPIO26A_OUT(), .MGPIO27A_OUT(), .MGPIO28A_OUT(), 
        .MGPIO29A_OUT(), .MGPIO2B_OUT(), .MGPIO30A_OUT(), 
        .MGPIO31A_OUT(), .MGPIO3B_OUT(), .MGPIO4B_OUT(), .MGPIO5B_OUT()
        , .MGPIO6B_OUT(), .MGPIO7B_OUT(), .MGPIO8B_OUT(), .MGPIO9B_OUT(
        ), .MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT(), 
        .MMUART0_DCD_MGPIO22B_OUT(), .MMUART0_DSR_MGPIO20B_OUT(), 
        .MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT(), 
        .MMUART0_RI_MGPIO21B_OUT(), 
        .MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT(), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_OUT(), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_OUT(), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_OUT(
        MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OUT), 
        .MMUART1_CTS_MGPIO13B_OUT(), .MMUART1_DCD_MGPIO16B_OUT(), 
        .MMUART1_DSR_MGPIO14B_OUT(), .MMUART1_DTR_MGPIO12B_OUT(), 
        .MMUART1_RI_MGPIO15B_OUT(), .MMUART1_RTS_MGPIO11B_OUT(), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT(), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT(), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT(), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT(), 
        .RGMII_MDC_RMII_MDC_OUT(), 
        .RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT(), .RGMII_RX_CLK_OUT(), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT(), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT(), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT(), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT(), 
        .RGMII_RXD3_USBB_DATA4_OUT(), .RGMII_TX_CLK_OUT(), 
        .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT(), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT(), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_OUT(), 
        .RGMII_TXD2_USBB_DATA5_OUT(), .RGMII_TXD3_USBB_DATA6_OUT(), 
        .SPI0_SCK_USBA_XCLK_OUT(MSS_ADLIB_INST_SPI0_SCK_USBA_XCLK_OUT), 
        .SPI0_SDI_USBA_DIR_MGPIO5A_OUT(), 
        .SPI0_SDO_USBA_STP_MGPIO6A_OUT(
        MSS_ADLIB_INST_SPI0_SDO_USBA_STP_MGPIO6A_OUT), 
        .SPI0_SS0_USBA_NXT_MGPIO7A_OUT(
        MSS_ADLIB_INST_SPI0_SS0_USBA_NXT_MGPIO7A_OUT), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_OUT(), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_OUT(), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_OUT(), .SPI0_SS4_MGPIO19A_OUT(), 
        .SPI0_SS5_MGPIO20A_OUT(), .SPI0_SS6_MGPIO21A_OUT(), 
        .SPI0_SS7_MGPIO22A_OUT(), .SPI1_SCK_OUT(), 
        .SPI1_SDI_MGPIO11A_OUT(), .SPI1_SDO_MGPIO12A_OUT(), 
        .SPI1_SS0_MGPIO13A_OUT(), .SPI1_SS1_MGPIO14A_OUT(), 
        .SPI1_SS2_MGPIO15A_OUT(), .SPI1_SS3_MGPIO16A_OUT(), 
        .SPI1_SS4_MGPIO17A_OUT(), .SPI1_SS5_MGPIO18A_OUT(), 
        .SPI1_SS6_MGPIO23A_OUT(), .SPI1_SS7_MGPIO24A_OUT(), 
        .USBC_XCLK_OUT(), .USBD_DATA0_OUT(), .USBD_DATA1_OUT(), 
        .USBD_DATA2_OUT(), .USBD_DATA3_OUT(), .USBD_DATA4_OUT(), 
        .USBD_DATA5_OUT(), .USBD_DATA6_OUT(), .USBD_DATA7_MGPIO23B_OUT(
        ), .USBD_DIR_OUT(), .USBD_NXT_OUT(), .USBD_STP_OUT(), 
        .USBD_XCLK_OUT(), .CAN_RXBUS_USBA_DATA1_MGPIO3A_OE(), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE(), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_OE(), .DM_OE({nc356, nc357, 
        nc358, \DM_OE_net_0[1] , \DM_OE_net_0[0] }), .DRAM_DQ_OE({
        nc359, nc360, nc361, nc362, nc363, nc364, nc365, nc366, nc367, 
        nc368, nc369, nc370, nc371, nc372, nc373, nc374, nc375, nc376, 
        nc377, nc378, \DRAM_DQ_OE_net_0[15] , \DRAM_DQ_OE_net_0[14] , 
        \DRAM_DQ_OE_net_0[13] , \DRAM_DQ_OE_net_0[12] , 
        \DRAM_DQ_OE_net_0[11] , \DRAM_DQ_OE_net_0[10] , 
        \DRAM_DQ_OE_net_0[9] , \DRAM_DQ_OE_net_0[8] , 
        \DRAM_DQ_OE_net_0[7] , \DRAM_DQ_OE_net_0[6] , 
        \DRAM_DQ_OE_net_0[5] , \DRAM_DQ_OE_net_0[4] , 
        \DRAM_DQ_OE_net_0[3] , \DRAM_DQ_OE_net_0[2] , 
        \DRAM_DQ_OE_net_0[1] , \DRAM_DQ_OE_net_0[0] }), .DRAM_DQS_OE({
        nc379, nc380, nc381, \DRAM_DQS_OE_net_0[1] , 
        \DRAM_DQS_OE_net_0[0] }), .I2C0_SCL_USBC_DATA1_MGPIO31B_OE(), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_OE(), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_OE(), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_OE(), .MGPIO0B_OE(), .MGPIO10B_OE(
        ), .MGPIO1B_OE(), .MGPIO25A_OE(), .MGPIO26A_OE(), .MGPIO27A_OE(
        ), .MGPIO28A_OE(), .MGPIO29A_OE(), .MGPIO2B_OE(), .MGPIO30A_OE(
        ), .MGPIO31A_OE(), .MGPIO3B_OE(), .MGPIO4B_OE(), .MGPIO5B_OE(), 
        .MGPIO6B_OE(), .MGPIO7B_OE(), .MGPIO8B_OE(), .MGPIO9B_OE(), 
        .MMUART0_CTS_USBC_DATA7_MGPIO19B_OE(), 
        .MMUART0_DCD_MGPIO22B_OE(), .MMUART0_DSR_MGPIO20B_OE(), 
        .MMUART0_DTR_USBC_DATA6_MGPIO18B_OE(), .MMUART0_RI_MGPIO21B_OE(
        ), .MMUART0_RTS_USBC_DATA5_MGPIO17B_OE(), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_OE(), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_OE(), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_OE(
        MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OE), 
        .MMUART1_CTS_MGPIO13B_OE(), .MMUART1_DCD_MGPIO16B_OE(), 
        .MMUART1_DSR_MGPIO14B_OE(), .MMUART1_DTR_MGPIO12B_OE(), 
        .MMUART1_RI_MGPIO15B_OE(), .MMUART1_RTS_MGPIO11B_OE(), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_OE(), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_OE(), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_OE(), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE(), .RGMII_MDC_RMII_MDC_OE(
        ), .RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE(), .RGMII_RX_CLK_OE(), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE(), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE(), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE(), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE(), 
        .RGMII_RXD3_USBB_DATA4_OE(), .RGMII_TX_CLK_OE(), 
        .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE(), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_OE(), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_OE(), .RGMII_TXD2_USBB_DATA5_OE(
        ), .RGMII_TXD3_USBB_DATA6_OE(), .SPI0_SCK_USBA_XCLK_OE(
        MSS_ADLIB_INST_SPI0_SCK_USBA_XCLK_OE), 
        .SPI0_SDI_USBA_DIR_MGPIO5A_OE(), .SPI0_SDO_USBA_STP_MGPIO6A_OE(
        MSS_ADLIB_INST_SPI0_SDO_USBA_STP_MGPIO6A_OE), 
        .SPI0_SS0_USBA_NXT_MGPIO7A_OE(
        MSS_ADLIB_INST_SPI0_SS0_USBA_NXT_MGPIO7A_OE), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_OE(), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_OE(), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_OE(), .SPI0_SS4_MGPIO19A_OE(), 
        .SPI0_SS5_MGPIO20A_OE(), .SPI0_SS6_MGPIO21A_OE(), 
        .SPI0_SS7_MGPIO22A_OE(), .SPI1_SCK_OE(), .SPI1_SDI_MGPIO11A_OE(
        ), .SPI1_SDO_MGPIO12A_OE(), .SPI1_SS0_MGPIO13A_OE(), 
        .SPI1_SS1_MGPIO14A_OE(), .SPI1_SS2_MGPIO15A_OE(), 
        .SPI1_SS3_MGPIO16A_OE(), .SPI1_SS4_MGPIO17A_OE(), 
        .SPI1_SS5_MGPIO18A_OE(), .SPI1_SS6_MGPIO23A_OE(), 
        .SPI1_SS7_MGPIO24A_OE(), .USBC_XCLK_OE(), .USBD_DATA0_OE(), 
        .USBD_DATA1_OE(), .USBD_DATA2_OE(), .USBD_DATA3_OE(), 
        .USBD_DATA4_OE(), .USBD_DATA5_OE(), .USBD_DATA6_OE(), 
        .USBD_DATA7_MGPIO23B_OE(), .USBD_DIR_OE(), .USBD_NXT_OE(), 
        .USBD_STP_OE(), .USBD_XCLK_OE());
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[12]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[12]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[12] ));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[10]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[10]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[10] ));
    OUTBUF \MDDR_DDR_AXI_S_BRESP_obuf[1]  (.D(
        \MDDR_DDR_AXI_S_BRESP_c[1] ), .PAD(MDDR_DDR_AXI_S_BRESP[1]));
    OUTBUF MDDR_DDR_AXI_S_AWREADY_obuf (.D(MDDR_DDR_AXI_S_AWREADY_c), 
        .PAD(MDDR_DDR_AXI_S_AWREADY));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[21]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[21]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[21] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[62]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[62] ), .PAD(MDDR_DDR_AXI_S_RDATA[62]));
    INBUF \MDDR_APB_S_PADDR_ibuf[7]  (.PAD(MDDR_APB_S_PADDR[7]), .Y(
        \MDDR_APB_S_PADDR_c[7] ));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[4]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[4]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[4] ));
    INBUF \MDDR_APB_S_PWDATA_ibuf[10]  (.PAD(MDDR_APB_S_PWDATA[10]), 
        .Y(\MDDR_APB_S_PWDATA_c[10] ));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[10]  (.PAD(FIC_2_APB_M_PRDATA[10]), 
        .Y(\FIC_2_APB_M_PRDATA_c[10] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[8]  (.PAD(MDDR_DDR_AXI_S_WDATA[8])
        , .Y(\MDDR_DDR_AXI_S_WDATA_c[8] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[55]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[55] ), .PAD(MDDR_DDR_AXI_S_RDATA[55]));
    OUTBUF \MDDR_APB_S_PRDATA_obuf[10]  (.D(\MDDR_APB_S_PRDATA_c[10] ), 
        .PAD(MDDR_APB_S_PRDATA[10]));
    OUTBUF GPIO_3_M2F_obuf (.D(GPIO_3_M2F_c), .PAD(GPIO_3_M2F));
    INBUF #( .IOSTD("SSTL15I") )  MDDR_DQS_TMATCH_0_IN_PAD (.PAD(
        MDDR_DQS_TMATCH_0_IN), .Y(MDDR_DQS_TMATCH_0_IN_PAD_Y));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[46]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[46]), .Y(\MDDR_DDR_AXI_S_WDATA_c[46] ));
    OUTBUF \MDDR_DDR_AXI_S_RID_obuf[3]  (.D(\MDDR_DDR_AXI_S_RID_c[3] ), 
        .PAD(MDDR_DDR_AXI_S_RID[3]));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[58]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[58] ), .PAD(MDDR_DDR_AXI_S_RDATA[58]));
    INBUF \MDDR_DDR_AXI_S_AWLEN_ibuf[1]  (.PAD(MDDR_DDR_AXI_S_AWLEN[1])
        , .Y(\MDDR_DDR_AXI_S_AWLEN_c[1] ));
    OUTBUF \MDDR_DDR_AXI_S_BRESP_obuf[0]  (.D(
        \MDDR_DDR_AXI_S_BRESP_c[0] ), .PAD(MDDR_DDR_AXI_S_BRESP[0]));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[29]  (.PAD(FIC_2_APB_M_PRDATA[29]), 
        .Y(\FIC_2_APB_M_PRDATA_c[29] ));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[19]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[19]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[19] ));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[17]  (.D(
        \FIC_0_AHB_S_HRDATA_c[17] ), .PAD(FIC_0_AHB_S_HRDATA[17]));
    OUTBUF \MDDR_DDR_AXI_S_RRESP_obuf[1]  (.D(
        \MDDR_DDR_AXI_S_RRESP_c[1] ), .PAD(MDDR_DDR_AXI_S_RRESP[1]));
    INBUF MDDR_DDR_AXI_S_BREADY_ibuf (.PAD(MDDR_DDR_AXI_S_BREADY), .Y(
        MDDR_DDR_AXI_S_BREADY_c));
    INBUF \MDDR_APB_S_PWDATA_ibuf[13]  (.PAD(MDDR_APB_S_PWDATA[13]), 
        .Y(\MDDR_APB_S_PWDATA_c[13] ));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[19]  (.PAD(FIC_2_APB_M_PRDATA[19]), 
        .Y(\FIC_2_APB_M_PRDATA_c[19] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[51]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[51]), .Y(\MDDR_DDR_AXI_S_WDATA_c[51] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[37]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[37]), .Y(\MDDR_DDR_AXI_S_WDATA_c[37] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[32]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[32]), .Y(\MDDR_DDR_AXI_S_WDATA_c[32] ));
    OUTBUF \MDDR_DDR_AXI_S_BID_obuf[0]  (.D(\MDDR_DDR_AXI_S_BID_c[0] ), 
        .PAD(MDDR_DDR_AXI_S_BID[0]));
    INBUF \MDDR_DDR_AXI_S_ARBURST_ibuf[0]  (.PAD(
        MDDR_DDR_AXI_S_ARBURST[0]), .Y(\MDDR_DDR_AXI_S_ARBURST_c[0] ));
    OUTBUF FIC_2_APB_M_PRESET_N_obuf (.D(FIC_2_APB_M_PRESET_N_c), .PAD(
        FIC_2_APB_M_PRESET_N));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[22]  (.D(
        \FIC_0_AHB_S_HRDATA_c[22] ), .PAD(FIC_0_AHB_S_HRDATA[22]));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[8]  (.PAD(FIC_0_AHB_S_HADDR[8]), .Y(
        \FIC_0_AHB_S_HADDR_c[8] ));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[8]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[8]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[8] ));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[31]  (.PAD(FIC_0_AHB_S_HWDATA[31]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[31] ));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[9]  (.D(\FIC_0_AHB_S_HRDATA_c[9] ), 
        .PAD(FIC_0_AHB_S_HRDATA[9]));
    OUTBUF \MDDR_DDR_AXI_S_RRESP_obuf[0]  (.D(
        \MDDR_DDR_AXI_S_RRESP_c[0] ), .PAD(MDDR_DDR_AXI_S_RRESP[0]));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[19]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[19] ), .PAD(MDDR_DDR_AXI_S_RDATA[19]));
    OUTBUF MDDR_DDR_AXI_S_BVALID_obuf (.D(MDDR_DDR_AXI_S_BVALID_c), 
        .PAD(MDDR_DDR_AXI_S_BVALID));
    INBUF \MDDR_APB_S_PWDATA_ibuf[8]  (.PAD(MDDR_APB_S_PWDATA[8]), .Y(
        \MDDR_APB_S_PWDATA_c[8] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[36]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[36] ), .PAD(MDDR_DDR_AXI_S_RDATA[36]));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[4]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[4]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[4] ));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[0]  (.PAD(FIC_2_APB_M_PRDATA[0]), 
        .Y(\FIC_2_APB_M_PRDATA_c[0] ));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[28]  (.D(
        \FIC_0_AHB_S_HRDATA_c[28] ), .PAD(FIC_0_AHB_S_HRDATA[28]));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[19]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[19]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[19] ));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[20]  (.PAD(FIC_0_AHB_S_HADDR[20]), 
        .Y(\FIC_0_AHB_S_HADDR_c[20] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[14]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[14]), .Y(\MDDR_DDR_AXI_S_WDATA_c[14] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[45]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[45]), .Y(\MDDR_DDR_AXI_S_WDATA_c[45] ));
    OUTBUF GPIO_9_M2F_obuf (.D(GPIO_9_M2F_c), .PAD(GPIO_9_M2F));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_7_PAD (.PAD(MDDR_DQ[7]), .D(
        \DRAM_DQ_OUT_net_0[7] ), .E(\DRAM_DQ_OE_net_0[7] ), .Y(
        MDDR_DQ_7_PAD_Y));
    OUTBUF GPIO_2_M2F_obuf (.D(GPIO_2_M2F_c), .PAD(GPIO_2_M2F));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[19]  (.PAD(FIC_0_AHB_S_HADDR[19]), 
        .Y(\FIC_0_AHB_S_HADDR_c[19] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[35]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[35] ), .PAD(MDDR_DDR_AXI_S_RDATA[35]));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[0]  (.D(\FIC_2_APB_M_PWDATA_c[0] ), 
        .PAD(FIC_2_APB_M_PWDATA[0]));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[28]  (.PAD(FIC_0_AHB_S_HADDR[28]), 
        .Y(\FIC_0_AHB_S_HADDR_c[28] ));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[27]  (.PAD(FIC_0_AHB_S_HWDATA[27]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[27] ));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_DQS_TMATCH_0_OUT_PAD (.D(
        \DRAM_FIFO_WE_OUT_net_0[0] ), .PAD(MDDR_DQS_TMATCH_0_OUT));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[38]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[38] ), .PAD(MDDR_DDR_AXI_S_RDATA[38]));
    INBUF \MDDR_DDR_AXI_S_WID_ibuf[0]  (.PAD(MDDR_DDR_AXI_S_WID[0]), 
        .Y(\MDDR_DDR_AXI_S_WID_c[0] ));
    OUTBUF \MDDR_APB_S_PRDATA_obuf[8]  (.D(\MDDR_APB_S_PRDATA_c[8] ), 
        .PAD(MDDR_APB_S_PRDATA[8]));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[30]  (.D(
        \FIC_2_APB_M_PWDATA_c[30] ), .PAD(FIC_2_APB_M_PWDATA[30]));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[12]  (.PAD(FIC_0_AHB_S_HWDATA[12]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[12] ));
    OUTBUF \MDDR_APB_S_PRDATA_obuf[14]  (.D(\MDDR_APB_S_PRDATA_c[14] ), 
        .PAD(MDDR_APB_S_PRDATA[14]));
    OUTBUF MDDR_DDR_AXI_S_ARREADY_obuf (.D(MDDR_DDR_AXI_S_ARREADY_c), 
        .PAD(MDDR_DDR_AXI_S_ARREADY));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[48]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[48]), .Y(\MDDR_DDR_AXI_S_WDATA_c[48] ));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_6_PAD (.D(
        \DRAM_ADDR_net_0[6] ), .PAD(MDDR_ADDR[6]));
    INBUF \MDDR_DDR_AXI_S_AWLEN_ibuf[3]  (.PAD(MDDR_DDR_AXI_S_AWLEN[3])
        , .Y(\MDDR_DDR_AXI_S_AWLEN_c[3] ));
    OUTBUF GPIO_10_M2F_obuf (.D(GPIO_10_M2F_c), .PAD(GPIO_10_M2F));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[9]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[9]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[9] ));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[30]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[30]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[30] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[43]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[43]), .Y(\MDDR_DDR_AXI_S_WDATA_c[43] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[7]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[7] ), .PAD(MDDR_DDR_AXI_S_RDATA[7]));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[59]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[59] ), .PAD(MDDR_DDR_AXI_S_RDATA[59]));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[21]  (.D(
        \FIC_0_AHB_S_HRDATA_c[21] ), .PAD(FIC_0_AHB_S_HRDATA[21]));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_4_PAD (.PAD(MDDR_DQ[4]), .D(
        \DRAM_DQ_OUT_net_0[4] ), .E(\DRAM_DQ_OE_net_0[4] ), .Y(
        MDDR_DQ_4_PAD_Y));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[13]  (.PAD(FIC_0_AHB_S_HWDATA[13]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[13] ));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[23]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[23]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[23] ));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_CAS_N_PAD (.D(
        MSS_ADLIB_INST_DRAM_CASN), .PAD(MDDR_CAS_N));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[31]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[31]), .Y(\MDDR_DDR_AXI_S_WDATA_c[31] ));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[14]  (.PAD(FIC_0_AHB_S_HWDATA[14]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[14] ));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[14]  (.PAD(FIC_0_AHB_S_HADDR[14]), 
        .Y(\FIC_0_AHB_S_HADDR_c[14] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[54]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[54]), .Y(\MDDR_DDR_AXI_S_WDATA_c[54] ));
    INBUF \MDDR_APB_S_PWDATA_ibuf[7]  (.PAD(MDDR_APB_S_PWDATA[7]), .Y(
        \MDDR_APB_S_PWDATA_c[7] ));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[11]  (.PAD(FIC_0_AHB_S_HADDR[11]), 
        .Y(\FIC_0_AHB_S_HADDR_c[11] ));
    OUTBUF \FIC_2_APB_M_PADDR_obuf[12]  (.D(\FIC_2_APB_M_PADDR_c[12] ), 
        .PAD(FIC_2_APB_M_PADDR[12]));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[29]  (.D(
        \FIC_0_AHB_S_HRDATA_c[29] ), .PAD(FIC_0_AHB_S_HRDATA[29]));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[40]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[40] ), .PAD(MDDR_DDR_AXI_S_RDATA[40]));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[2]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[2] ), .PAD(MDDR_DDR_AXI_S_RDATA[2]));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_BA_2_PAD (.D(
        \DRAM_BA_net_0[2] ), .PAD(MDDR_BA[2]));
    TRIBUFF SPI_0_DO_PAD (.D(
        MSS_ADLIB_INST_SPI0_SDO_USBA_STP_MGPIO6A_OUT), .E(
        MSS_ADLIB_INST_SPI0_SDO_USBA_STP_MGPIO6A_OE), .PAD(SPI_0_DO));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[30]  (.PAD(FIC_0_AHB_S_HWDATA[30]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[30] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[63]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[63] ), .PAD(MDDR_DDR_AXI_S_RDATA[63]));
    INBUF \MDDR_APB_S_PADDR_ibuf[5]  (.PAD(MDDR_APB_S_PADDR[5]), .Y(
        \MDDR_APB_S_PADDR_c[5] ));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_2_PAD (.PAD(MDDR_DQ[2]), .D(
        \DRAM_DQ_OUT_net_0[2] ), .E(\DRAM_DQ_OE_net_0[2] ), .Y(
        MDDR_DQ_2_PAD_Y));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[16]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[16]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[16] ));
    OUTBUF \MDDR_DDR_AXI_S_RID_obuf[2]  (.D(\MDDR_DDR_AXI_S_RID_c[2] ), 
        .PAD(MDDR_DDR_AXI_S_RID[2]));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[0]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[0] ), .PAD(MDDR_DDR_AXI_S_RDATA[0]));
    INBUF \MDDR_APB_S_PWDATA_ibuf[4]  (.PAD(MDDR_APB_S_PWDATA[4]), .Y(
        \MDDR_APB_S_PWDATA_c[4] ));
    INBUF FIC_0_AHB_S_HREADY_ibuf (.PAD(FIC_0_AHB_S_HREADY), .Y(
        FIC_0_AHB_S_HREADY_c));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[25]  (.PAD(FIC_0_AHB_S_HADDR[25]), 
        .Y(\FIC_0_AHB_S_HADDR_c[25] ));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[3]  (.PAD(FIC_0_AHB_S_HWDATA[3]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[3] ));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_9_PAD (.D(
        \DRAM_ADDR_net_0[9] ), .PAD(MDDR_ADDR[9]));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[8]  (.PAD(FIC_0_AHB_S_HWDATA[8]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[8] ));
    OUTBUF \MDDR_APB_S_PRDATA_obuf[7]  (.D(\MDDR_APB_S_PRDATA_c[7] ), 
        .PAD(MDDR_APB_S_PRDATA[7]));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_5_PAD (.PAD(MDDR_DQ[5]), .D(
        \DRAM_DQ_OUT_net_0[5] ), .E(\DRAM_DQ_OE_net_0[5] ), .Y(
        MDDR_DQ_5_PAD_Y));
    INBUF \MDDR_DDR_AXI_S_AWID_ibuf[0]  (.PAD(MDDR_DDR_AXI_S_AWID[0]), 
        .Y(\MDDR_DDR_AXI_S_AWID_c[0] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[41]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[41] ), .PAD(MDDR_DDR_AXI_S_RDATA[41]));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_15_PAD (.D(
        \DRAM_ADDR_net_0[15] ), .PAD(MDDR_ADDR[15]));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_6_PAD (.PAD(MDDR_DQ[6]), .D(
        \DRAM_DQ_OUT_net_0[6] ), .E(\DRAM_DQ_OE_net_0[6] ), .Y(
        MDDR_DQ_6_PAD_Y));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[22]  (.D(
        \FIC_2_APB_M_PWDATA_c[22] ), .PAD(FIC_2_APB_M_PWDATA[22]));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[9]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[9]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[9] ));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[16]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[16]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[16] ));
    INBUF \MDDR_DDR_AXI_S_ARSIZE_ibuf[1]  (.PAD(
        MDDR_DDR_AXI_S_ARSIZE[1]), .Y(\MDDR_DDR_AXI_S_ARSIZE_c[1] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[27]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[27] ), .PAD(MDDR_DDR_AXI_S_RDATA[27]));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[30]  (.D(
        \FIC_0_AHB_S_HRDATA_c[30] ), .PAD(FIC_0_AHB_S_HRDATA[30]));
    OUTBUF \MDDR_APB_S_PRDATA_obuf[4]  (.D(\MDDR_APB_S_PRDATA_c[4] ), 
        .PAD(MDDR_APB_S_PRDATA[4]));
    OUTBUF \FIC_2_APB_M_PADDR_obuf[9]  (.D(\FIC_2_APB_M_PADDR_c[9] ), 
        .PAD(FIC_2_APB_M_PADDR[9]));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[28]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[28]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[28] ));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[26]  (.D(
        \FIC_2_APB_M_PWDATA_c[26] ), .PAD(FIC_2_APB_M_PWDATA[26]));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[12]  (.D(
        \FIC_2_APB_M_PWDATA_c[12] ), .PAD(FIC_2_APB_M_PWDATA[12]));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[39]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[39] ), .PAD(MDDR_DDR_AXI_S_RDATA[39]));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_10_PAD (.D(
        \DRAM_ADDR_net_0[10] ), .PAD(MDDR_ADDR[10]));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_3_PAD (.D(
        \DRAM_ADDR_net_0[3] ), .PAD(MDDR_ADDR[3]));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[4]  (.PAD(FIC_0_AHB_S_HWDATA[4]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[4] ));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[15]  (.D(
        \FIC_0_AHB_S_HRDATA_c[15] ), .PAD(FIC_0_AHB_S_HRDATA[15]));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[34]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[34]), .Y(\MDDR_DDR_AXI_S_WDATA_c[34] ));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[16]  (.D(
        \FIC_2_APB_M_PWDATA_c[16] ), .PAD(FIC_2_APB_M_PWDATA[16]));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[1]  (.PAD(FIC_0_AHB_S_HWDATA[1]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[1] ));
    OUTBUF MDDR_APB_S_PREADY_obuf (.D(MDDR_APB_S_PREADY_c), .PAD(
        MDDR_APB_S_PREADY));
    OUTBUF FIC_2_APB_M_PWRITE_obuf (.D(FIC_2_APB_M_PWRITE_c), .PAD(
        FIC_2_APB_M_PWRITE));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[20]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[20]), .Y(\MDDR_DDR_AXI_S_WDATA_c[20] ));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[11]  (.PAD(FIC_0_AHB_S_HWDATA[11]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[11] ));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[14]  (.D(
        \FIC_0_AHB_S_HRDATA_c[14] ), .PAD(FIC_0_AHB_S_HRDATA[14]));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[2]  (.PAD(FIC_0_AHB_S_HWDATA[2]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[2] ));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[17]  (.PAD(FIC_0_AHB_S_HADDR[17]), 
        .Y(\FIC_0_AHB_S_HADDR_c[17] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[47]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[47]), .Y(\MDDR_DDR_AXI_S_WDATA_c[47] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[42]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[42]), .Y(\MDDR_DDR_AXI_S_WDATA_c[42] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[1]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[1] ), .PAD(MDDR_DDR_AXI_S_RDATA[1]));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_CS_N_PAD (.D(
        MSS_ADLIB_INST_DRAM_CSN), .PAD(MDDR_CS_N));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[25]  (.D(
        \FIC_2_APB_M_PWDATA_c[25] ), .PAD(FIC_2_APB_M_PWDATA[25]));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[12]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[12]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[12] ));
    OUTBUF \FIC_2_APB_M_PADDR_obuf[15]  (.D(\FIC_2_APB_M_PADDR_c[15] ), 
        .PAD(FIC_2_APB_M_PADDR[15]));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[22]  (.PAD(FIC_2_APB_M_PRDATA[22]), 
        .Y(\FIC_2_APB_M_PRDATA_c[22] ));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[13]  (.PAD(FIC_0_AHB_S_HADDR[13]), 
        .Y(\FIC_0_AHB_S_HADDR_c[13] ));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[7]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[7]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[7] ));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[27]  (.PAD(FIC_2_APB_M_PRDATA[27]), 
        .Y(\FIC_2_APB_M_PRDATA_c[27] ));
    OUTBUF GPIO_1_M2F_obuf (.D(GPIO_1_M2F_c), .PAD(GPIO_1_M2F));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[25]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[25]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[25] ));
    OUTBUF \FIC_2_APB_M_PADDR_obuf[11]  (.D(\FIC_2_APB_M_PADDR_c[11] ), 
        .PAD(FIC_2_APB_M_PADDR[11]));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[46]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[46] ), .PAD(MDDR_DDR_AXI_S_RDATA[46]));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[15]  (.D(
        \FIC_2_APB_M_PWDATA_c[15] ), .PAD(FIC_2_APB_M_PWDATA[15]));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[12]  (.PAD(FIC_2_APB_M_PRDATA[12]), 
        .Y(\FIC_2_APB_M_PRDATA_c[12] ));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[19]  (.PAD(FIC_0_AHB_S_HWDATA[19]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[19] ));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[6]  (.PAD(FIC_0_AHB_S_HWDATA[6]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[6] ));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[17]  (.PAD(FIC_2_APB_M_PRDATA[17]), 
        .Y(\FIC_2_APB_M_PRDATA_c[17] ));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[23]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[23]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[23] ));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_1_PAD (.PAD(MDDR_DQ[1]), .D(
        \DRAM_DQ_OUT_net_0[1] ), .E(\DRAM_DQ_OE_net_0[1] ), .Y(
        MDDR_DQ_1_PAD_Y));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[24]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[24] ), .PAD(MDDR_DDR_AXI_S_RDATA[24]));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[14]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[14]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[14] ));
    OUTBUF GPIO_0_M2F_obuf (.D(GPIO_0_M2F_c), .PAD(GPIO_0_M2F));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[45]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[45] ), .PAD(MDDR_DDR_AXI_S_RDATA[45]));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_14_PAD (.D(
        \DRAM_ADDR_net_0[14] ), .PAD(MDDR_ADDR[14]));
    INBUF \MDDR_DDR_AXI_S_ARLEN_ibuf[0]  (.PAD(MDDR_DDR_AXI_S_ARLEN[0])
        , .Y(\MDDR_DDR_AXI_S_ARLEN_c[0] ));
    OUTBUF \MDDR_APB_S_PRDATA_obuf[13]  (.D(\MDDR_APB_S_PRDATA_c[13] ), 
        .PAD(MDDR_APB_S_PRDATA[13]));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[63]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[63]), .Y(\MDDR_DDR_AXI_S_WDATA_c[63] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[48]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[48] ), .PAD(MDDR_DDR_AXI_S_RDATA[48]));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DM_RDQS_0_PAD (.PAD(
        MDDR_DM_RDQS[0]), .D(\DRAM_DM_RDQS_OUT_net_0[0] ), .E(
        \DM_OE_net_0[0] ), .Y(MDDR_DM_RDQS_0_PAD_Y));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[27]  (.D(
        \FIC_0_AHB_S_HRDATA_c[27] ), .PAD(FIC_0_AHB_S_HRDATA[27]));
    INBUF \MDDR_DDR_AXI_S_AWID_ibuf[1]  (.PAD(MDDR_DDR_AXI_S_AWID[1]), 
        .Y(\MDDR_DDR_AXI_S_AWID_c[1] ));
    INBUF \MDDR_DDR_AXI_S_AWBURST_ibuf[1]  (.PAD(
        MDDR_DDR_AXI_S_AWBURST[1]), .Y(\MDDR_DDR_AXI_S_AWBURST_c[1] ));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[16]  (.PAD(FIC_0_AHB_S_HADDR[16]), 
        .Y(\FIC_0_AHB_S_HADDR_c[16] ));
    INBUF MDDR_DDR_AXI_S_RREADY_ibuf (.PAD(MDDR_DDR_AXI_S_RREADY), .Y(
        MDDR_DDR_AXI_S_RREADY_c));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[17]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[17] ), .PAD(MDDR_DDR_AXI_S_RDATA[17]));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[3]  (.PAD(FIC_2_APB_M_PRDATA[3]), 
        .Y(\FIC_2_APB_M_PRDATA_c[3] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[3]  (.PAD(MDDR_DDR_AXI_S_WDATA[3])
        , .Y(\MDDR_DDR_AXI_S_WDATA_c[3] ));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[31]  (.PAD(FIC_2_APB_M_PRDATA[31]), 
        .Y(\FIC_2_APB_M_PRDATA_c[31] ));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[17]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[17]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[17] ));
    OUTBUF_DIFF #( .IOSTD("SSTL15I") )  MDDR_CLK_PAD (.D(
        MSS_ADLIB_INST_DRAM_CLK), .PADP(MDDR_CLK), .PADN(MDDR_CLK_N));
    OUTBUF \MDDR_APB_S_PRDATA_obuf[11]  (.D(\MDDR_APB_S_PRDATA_c[11] ), 
        .PAD(MDDR_APB_S_PRDATA[11]));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[22]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[22] ), .PAD(MDDR_DDR_AXI_S_RDATA[22]));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[16]  (.D(
        \FIC_0_AHB_S_HRDATA_c[16] ), .PAD(FIC_0_AHB_S_HRDATA[16]));
    INBUF MDDR_DDR_AXI_S_WVALID_ibuf (.PAD(MDDR_DDR_AXI_S_WVALID), .Y(
        MDDR_DDR_AXI_S_WVALID_c));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[60]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[60] ), .PAD(MDDR_DDR_AXI_S_RDATA[60]));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[7]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[7]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[7] ));
    BIBUF_DIFF #( .IOSTD("SSTL15I") )  MDDR_DQS_0_PAD (.D(
        \DRAM_DQS_OUT_net_0[0] ), .E(\DRAM_DQS_OE_net_0[0] ), .PADP(
        MDDR_DQS[0]), .PADN(MDDR_DQS_N[0]), .Y(MDDR_DQS_0_PAD_Y));
    OUTBUF FIC_2_APB_M_PENABLE_obuf (.D(FIC_2_APB_M_PENABLE_c), .PAD(
        FIC_2_APB_M_PENABLE));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[29]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[29]), .Y(\MDDR_DDR_AXI_S_WDATA_c[29] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[41]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[41]), .Y(\MDDR_DDR_AXI_S_WDATA_c[41] ));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[3]  (.D(\FIC_2_APB_M_PWDATA_c[3] ), 
        .PAD(FIC_2_APB_M_PWDATA[3]));
    INBUF \MDDR_DDR_AXI_S_ARID_ibuf[3]  (.PAD(MDDR_DDR_AXI_S_ARID[3]), 
        .Y(\MDDR_DDR_AXI_S_ARID_c[3] ));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[0]  (.PAD(FIC_0_AHB_S_HADDR[0]), .Y(
        \FIC_0_AHB_S_HADDR_c[0] ));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[10]  (.PAD(FIC_0_AHB_S_HWDATA[10]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[10] ));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[2]  (.PAD(FIC_0_AHB_S_HADDR[2]), .Y(
        \FIC_0_AHB_S_HADDR_c[2] ));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[0]  (.D(\FIC_0_AHB_S_HRDATA_c[0] ), 
        .PAD(FIC_0_AHB_S_HRDATA[0]));
    OUTBUF \FIC_2_APB_M_PADDR_obuf[10]  (.D(\FIC_2_APB_M_PADDR_c[10] ), 
        .PAD(FIC_2_APB_M_PADDR[10]));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[10]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[10]), .Y(\MDDR_DDR_AXI_S_WDATA_c[10] ));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[21]  (.D(
        \FIC_2_APB_M_PWDATA_c[21] ), .PAD(FIC_2_APB_M_PWDATA[21]));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[26]  (.PAD(FIC_2_APB_M_PRDATA[26]), 
        .Y(\FIC_2_APB_M_PRDATA_c[26] ));
    INBUF \FIC_0_AHB_S_HTRANS_ibuf[1]  (.PAD(FIC_0_AHB_S_HTRANS[1]), 
        .Y(\FIC_0_AHB_S_HTRANS_c[1] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[9]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[9] ), .PAD(MDDR_DDR_AXI_S_RDATA[9]));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[25]  (.PAD(FIC_2_APB_M_PRDATA[25]), 
        .Y(\FIC_2_APB_M_PRDATA_c[25] ));
    INBUF \MDDR_DDR_AXI_S_AWBURST_ibuf[0]  (.PAD(
        MDDR_DDR_AXI_S_AWBURST[0]), .Y(\MDDR_DDR_AXI_S_AWBURST_c[0] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[61]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[61] ), .PAD(MDDR_DDR_AXI_S_RDATA[61]));
    INBUF MDDR_DDR_AXI_S_ARVALID_ibuf (.PAD(MDDR_DDR_AXI_S_ARVALID), 
        .Y(MDDR_DDR_AXI_S_ARVALID_c));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[1]  (.PAD(FIC_2_APB_M_PRDATA[1]), 
        .Y(\FIC_2_APB_M_PRDATA_c[1] ));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[12]  (.PAD(FIC_0_AHB_S_HADDR[12]), 
        .Y(\FIC_0_AHB_S_HADDR_c[12] ));
    INBUF FIC_2_APB_M_PREADY_ibuf (.PAD(FIC_2_APB_M_PREADY), .Y(
        FIC_2_APB_M_PREADY_c));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[27]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[27]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[27] ));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[7]  (.PAD(FIC_2_APB_M_PRDATA[7]), 
        .Y(\FIC_2_APB_M_PRDATA_c[7] ));
    OUTBUF \MDDR_DDR_AXI_S_BID_obuf[1]  (.D(\MDDR_DDR_AXI_S_BID_c[1] ), 
        .PAD(MDDR_DDR_AXI_S_BID[1]));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[57]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[57] ), .PAD(MDDR_DDR_AXI_S_RDATA[57]));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[16]  (.PAD(FIC_0_AHB_S_HWDATA[16]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[16] ));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[9]  (.PAD(FIC_0_AHB_S_HADDR[9]), .Y(
        \FIC_0_AHB_S_HADDR_c[9] ));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_12_PAD (.D(
        \DRAM_ADDR_net_0[12] ), .PAD(MDDR_ADDR[12]));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[11]  (.D(
        \FIC_2_APB_M_PWDATA_c[11] ), .PAD(FIC_2_APB_M_PWDATA[11]));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[16]  (.PAD(FIC_2_APB_M_PRDATA[16]), 
        .Y(\FIC_2_APB_M_PRDATA_c[16] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[6]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[6] ), .PAD(MDDR_DDR_AXI_S_RDATA[6]));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[15]  (.PAD(FIC_2_APB_M_PRDATA[15]), 
        .Y(\FIC_2_APB_M_PRDATA_c[15] ));
    OUTBUF MDDR_DDR_AXI_S_RLAST_obuf (.D(MDDR_DDR_AXI_S_RLAST_c), .PAD(
        MDDR_DDR_AXI_S_RLAST));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[22]  (.PAD(FIC_0_AHB_S_HWDATA[22]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[22] ));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[6]  (.PAD(FIC_0_AHB_S_HADDR[6]), .Y(
        \FIC_0_AHB_S_HADDR_c[6] ));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[5]  (.PAD(FIC_0_AHB_S_HADDR[5]), .Y(
        \FIC_0_AHB_S_HADDR_c[5] ));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_0_PAD (.D(
        \DRAM_ADDR_net_0[0] ), .PAD(MDDR_ADDR[0]));
    OUTBUF \FIC_2_APB_M_PADDR_obuf[6]  (.D(\FIC_2_APB_M_PADDR_c[6] ), 
        .PAD(FIC_2_APB_M_PADDR[6]));
    OUTBUF \FIC_2_APB_M_PADDR_obuf[3]  (.D(\FIC_2_APB_M_PADDR_c[3] ), 
        .PAD(FIC_2_APB_M_PADDR[3]));
    INBUF \MDDR_DDR_AXI_S_WSTRB_ibuf[0]  (.PAD(MDDR_DDR_AXI_S_WSTRB[0])
        , .Y(\MDDR_DDR_AXI_S_WSTRB_c[0] ));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[1]  (.D(\FIC_2_APB_M_PWDATA_c[1] ), 
        .PAD(FIC_2_APB_M_PWDATA[1]));
    OUTBUF \FIC_0_AHB_S_HRDATA_obuf[10]  (.D(
        \FIC_0_AHB_S_HRDATA_c[10] ), .PAD(FIC_0_AHB_S_HRDATA[10]));
    INBUF \MDDR_APB_S_PWDATA_ibuf[3]  (.PAD(MDDR_APB_S_PWDATA[3]), .Y(
        \MDDR_APB_S_PWDATA_c[3] ));
    OUTBUF \MDDR_DDR_AXI_S_RID_obuf[0]  (.D(\MDDR_DDR_AXI_S_RID_c[0] ), 
        .PAD(MDDR_DDR_AXI_S_RID[0]));
    INBUF MDDR_APB_S_PWRITE_ibuf (.PAD(MDDR_APB_S_PWRITE), .Y(
        MDDR_APB_S_PWRITE_c));
    INBUF MDDR_APB_S_PENABLE_ibuf (.PAD(MDDR_APB_S_PENABLE), .Y(
        MDDR_APB_S_PENABLE_c));
    INBUF FIC_0_AHB_S_HSEL_ibuf (.PAD(FIC_0_AHB_S_HSEL), .Y(
        FIC_0_AHB_S_HSEL_c));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[25]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[25]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[25] ));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[7]  (.D(\FIC_2_APB_M_PWDATA_c[7] ), 
        .PAD(FIC_2_APB_M_PWDATA[7]));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[8]  (.PAD(FIC_2_APB_M_PRDATA[8]), 
        .Y(\FIC_2_APB_M_PRDATA_c[8] ));
    OUTBUF \FIC_2_APB_M_PADDR_obuf[16]  (.D(\FIC_2_APB_M_PADDR_c[16] ), 
        .PAD(FIC_2_APB_M_PADDR[16]));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[5]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[5] ), .PAD(MDDR_DDR_AXI_S_RDATA[5]));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[23]  (.PAD(FIC_0_AHB_S_HWDATA[23]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[23] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[14]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[14] ), .PAD(MDDR_DDR_AXI_S_RDATA[14]));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[6]  (.PAD(FIC_2_APB_M_PRDATA[6]), 
        .Y(\FIC_2_APB_M_PRDATA_c[6] ));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[24]  (.PAD(FIC_0_AHB_S_HWDATA[24]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[24] ));
    INBUF \MDDR_DDR_AXI_S_WSTRB_ibuf[1]  (.PAD(MDDR_DDR_AXI_S_WSTRB[1])
        , .Y(\MDDR_DDR_AXI_S_WSTRB_c[1] ));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[5]  (.PAD(FIC_2_APB_M_PRDATA[5]), 
        .Y(\FIC_2_APB_M_PRDATA_c[5] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[50]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[50]), .Y(\MDDR_DDR_AXI_S_WDATA_c[50] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[49]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[49] ), .PAD(MDDR_DDR_AXI_S_RDATA[49]));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[8]  (.D(\FIC_2_APB_M_PWDATA_c[8] ), 
        .PAD(FIC_2_APB_M_PWDATA[8]));
    INBUF \FIC_0_AHB_S_HWDATA_ibuf[9]  (.PAD(FIC_0_AHB_S_HWDATA[9]), 
        .Y(\FIC_0_AHB_S_HWDATA_c[9] ));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[3]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[3]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[3] ));
    INBUF \MDDR_DDR_AXI_S_WID_ibuf[1]  (.PAD(MDDR_DDR_AXI_S_WID[1]), 
        .Y(\MDDR_DDR_AXI_S_WID_c[1] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[62]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[62]), .Y(\MDDR_DDR_AXI_S_WDATA_c[62] ));
    OUTBUF \MDDR_APB_S_PRDATA_obuf[3]  (.D(\MDDR_APB_S_PRDATA_c[3] ), 
        .PAD(MDDR_APB_S_PRDATA[3]));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[9]  (.PAD(FIC_2_APB_M_PRDATA[9]), 
        .Y(\FIC_2_APB_M_PRDATA_c[9] ));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_3_PAD (.PAD(MDDR_DQ[3]), .D(
        \DRAM_DQ_OUT_net_0[3] ), .E(\DRAM_DQ_OE_net_0[3] ), .Y(
        MDDR_DQ_3_PAD_Y));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[44]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[44]), .Y(\MDDR_DDR_AXI_S_WDATA_c[44] ));
    INBUF \MDDR_APB_S_PWDATA_ibuf[15]  (.PAD(MDDR_APB_S_PWDATA[15]), 
        .Y(\MDDR_APB_S_PWDATA_c[15] ));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[6]  (.D(\FIC_2_APB_M_PWDATA_c[6] ), 
        .PAD(FIC_2_APB_M_PWDATA[6]));
    INBUF \MDDR_DDR_AXI_S_WSTRB_ibuf[7]  (.PAD(MDDR_DDR_AXI_S_WSTRB[7])
        , .Y(\MDDR_DDR_AXI_S_WSTRB_c[7] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[12]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[12] ), .PAD(MDDR_DDR_AXI_S_RDATA[12]));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[2]  (.PAD(FIC_2_APB_M_PRDATA[2]), 
        .Y(\FIC_2_APB_M_PRDATA_c[2] ));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[11]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[11]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[11] ));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[5]  (.D(\FIC_2_APB_M_PWDATA_c[5] ), 
        .PAD(FIC_2_APB_M_PWDATA[5]));
    INBUF \MDDR_DDR_AXI_S_ARID_ibuf[2]  (.PAD(MDDR_DDR_AXI_S_ARID[2]), 
        .Y(\MDDR_DDR_AXI_S_ARID_c[2] ));
    INBUF \MDDR_APB_S_PADDR_ibuf[4]  (.PAD(MDDR_APB_S_PADDR[4]), .Y(
        \MDDR_APB_S_PADDR_c[4] ));
    INBUF \MDDR_DDR_AXI_S_WDATA_ibuf[19]  (.PAD(
        MDDR_DDR_AXI_S_WDATA[19]), .Y(\MDDR_DDR_AXI_S_WDATA_c[19] ));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[22]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[22]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[22] ));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[20]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[20]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[20] ));
    INBUF \MDDR_APB_S_PWDATA_ibuf[14]  (.PAD(MDDR_APB_S_PWDATA[14]), 
        .Y(\MDDR_APB_S_PWDATA_c[14] ));
    INBUF \MDDR_DDR_AXI_S_AWSIZE_ibuf[0]  (.PAD(
        MDDR_DDR_AXI_S_AWSIZE[0]), .Y(\MDDR_DDR_AXI_S_AWSIZE_c[0] ));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[14]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[14]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[14] ));
    INBUF \MDDR_DDR_AXI_S_WSTRB_ibuf[3]  (.PAD(MDDR_DDR_AXI_S_WSTRB[3])
        , .Y(\MDDR_DDR_AXI_S_WSTRB_c[3] ));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_8_PAD (.D(
        \DRAM_ADDR_net_0[8] ), .PAD(MDDR_ADDR[8]));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[9]  (.D(\FIC_2_APB_M_PWDATA_c[9] ), 
        .PAD(FIC_2_APB_M_PWDATA[9]));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_WE_N_PAD (.D(
        MSS_ADLIB_INST_DRAM_WEN), .PAD(MDDR_WE_N));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[18]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[18]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[18] ));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[2]  (.D(\FIC_2_APB_M_PWDATA_c[2] ), 
        .PAD(FIC_2_APB_M_PWDATA[2]));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[3]  (.PAD(FIC_0_AHB_S_HADDR[3]), .Y(
        \FIC_0_AHB_S_HADDR_c[3] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[37]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[37] ), .PAD(MDDR_DDR_AXI_S_RDATA[37]));
    INBUF \FIC_0_AHB_S_HSIZE_ibuf[0]  (.PAD(FIC_0_AHB_S_HSIZE[0]), .Y(
        \FIC_0_AHB_S_HSIZE_c[0] ));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[27]  (.D(
        \FIC_2_APB_M_PWDATA_c[27] ), .PAD(FIC_2_APB_M_PWDATA[27]));
    INBUF \FIC_0_AHB_S_HADDR_ibuf[31]  (.PAD(FIC_0_AHB_S_HADDR[31]), 
        .Y(\FIC_0_AHB_S_HADDR_c[31] ));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[54]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[54] ), .PAD(MDDR_DDR_AXI_S_RDATA[54]));
    INBUF \MDDR_APB_S_PADDR_ibuf[3]  (.PAD(MDDR_APB_S_PADDR[3]), .Y(
        \MDDR_APB_S_PADDR_c[3] ));
    INBUF \MDDR_APB_S_PWDATA_ibuf[1]  (.PAD(MDDR_APB_S_PWDATA[1]), .Y(
        \MDDR_APB_S_PWDATA_c[1] ));
    INBUF \FIC_2_APB_M_PRDATA_ibuf[28]  (.PAD(FIC_2_APB_M_PRDATA[28]), 
        .Y(\FIC_2_APB_M_PRDATA_c[28] ));
    OUTBUF FIC_2_APB_M_PCLK_obuf (.D(FIC_2_APB_M_PCLK_c), .PAD(
        FIC_2_APB_M_PCLK));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[23]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[23] ), .PAD(MDDR_DDR_AXI_S_RDATA[23]));
    INBUF \MDDR_DDR_AXI_S_AWLEN_ibuf[2]  (.PAD(MDDR_DDR_AXI_S_AWLEN[2])
        , .Y(\MDDR_DDR_AXI_S_AWLEN_c[2] ));
    INBUF \MDDR_DDR_AXI_S_ARADDR_ibuf[29]  (.PAD(
        MDDR_DDR_AXI_S_ARADDR[29]), .Y(\MDDR_DDR_AXI_S_ARADDR_c[29] ));
    INBUF \MDDR_DDR_AXI_S_AWADDR_ibuf[10]  (.PAD(
        MDDR_DDR_AXI_S_AWADDR[10]), .Y(\MDDR_DDR_AXI_S_AWADDR_c[10] ));
    INBUF \MDDR_APB_S_PWDATA_ibuf[5]  (.PAD(MDDR_APB_S_PWDATA[5]), .Y(
        \MDDR_APB_S_PWDATA_c[5] ));
    OUTBUF \FIC_2_APB_M_PWDATA_obuf[17]  (.D(
        \FIC_2_APB_M_PWDATA_c[17] ), .PAD(FIC_2_APB_M_PWDATA[17]));
    OUTBUF \MDDR_DDR_AXI_S_RDATA_obuf[4]  (.D(
        \MDDR_DDR_AXI_S_RDATA_c[4] ), .PAD(MDDR_DDR_AXI_S_RDATA[4]));
    
endmodule
