//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Wed Mar 23 12:27:19 2016
// Version: v11.7 11.7.0.119
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

// CodeShadowing_LPDDR_top
module CodeShadowing_LPDDR_top(
    // Inputs
    DEVRST_N,
    GPIO_11_F2M,
    GPIO_12_F2M,
    MDDR_DQS_TMATCH_0_IN,
    MMUART_1_RXD,
    SPI_0_DI,
    // Outputs
    GPIO_0_M2F,
    GPIO_10_M2F,
    GPIO_1_M2F,
    GPIO_2_M2F,
    GPIO_3_M2F,
    GPIO_4_M2F,
    GPIO_8_M2F,
    GPIO_9_M2F,
    MDDR_ADDR,
    MDDR_BA,
    MDDR_CAS_N,
    MDDR_CKE,
    MDDR_CLK,
    MDDR_CLK_N,
    MDDR_CS_N,
    MDDR_DQS_TMATCH_0_OUT,
    MDDR_ODT,
    MDDR_RAS_N,
    MDDR_RESET_N,
    MDDR_WE_N,
    MMUART_1_TXD,
    SPI_0_DO,
    // Inouts
    MDDR_DM_RDQS,
    MDDR_DQ,
    MDDR_DQS,
    SPI_0_CLK,
    SPI_0_SS0
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input         DEVRST_N;
input         GPIO_11_F2M;
input         GPIO_12_F2M;
input         MDDR_DQS_TMATCH_0_IN;
input         MMUART_1_RXD;
input         SPI_0_DI;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output        GPIO_0_M2F;
output        GPIO_10_M2F;
output        GPIO_1_M2F;
output        GPIO_2_M2F;
output        GPIO_3_M2F;
output        GPIO_4_M2F;
output        GPIO_8_M2F;
output        GPIO_9_M2F;
output [15:0] MDDR_ADDR;
output [2:0]  MDDR_BA;
output        MDDR_CAS_N;
output        MDDR_CKE;
output        MDDR_CLK;
output        MDDR_CLK_N;
output        MDDR_CS_N;
output        MDDR_DQS_TMATCH_0_OUT;
output        MDDR_ODT;
output        MDDR_RAS_N;
output        MDDR_RESET_N;
output        MDDR_WE_N;
output        MMUART_1_TXD;
output        SPI_0_DO;
//--------------------------------------------------------------------
// Inout
//--------------------------------------------------------------------
inout  [1:0]  MDDR_DM_RDQS;
inout  [15:0] MDDR_DQ;
inout  [1:0]  MDDR_DQS;
inout         SPI_0_CLK;
inout         SPI_0_SS0;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire          DEVRST_N;
wire          GPIO_0_M2F_net_0;
wire          GPIO_1_M2F_net_0;
wire          GPIO_2_M2F_net_0;
wire          GPIO_3_M2F_net_0;
wire          GPIO_4_M2F_net_0;
wire          GPIO_8_M2F_net_0;
wire          GPIO_9_M2F_net_0;
wire          GPIO_10_M2F_net_0;
wire          GPIO_11_F2M;
wire          GPIO_12_F2M;
wire   [15:0] MDDR_ADDR_net_0;
wire   [2:0]  MDDR_BA_net_0;
wire          MDDR_CAS_N_net_0;
wire          MDDR_CKE_net_0;
wire          MDDR_CLK_net_0;
wire          MDDR_CLK_N_net_0;
wire          MDDR_CS_N_net_0;
wire   [1:0]  MDDR_DM_RDQS;
wire   [15:0] MDDR_DQ;
wire   [1:0]  MDDR_DQS;
wire          MDDR_DQS_TMATCH_0_IN;
wire          MDDR_DQS_TMATCH_0_OUT_net_0;
wire          MDDR_ODT_net_0;
wire          MDDR_RAS_N_net_0;
wire          MDDR_RESET_N_net_0;
wire          MDDR_WE_N_net_0;
wire          MMUART_1_RXD;
wire          MMUART_1_TXD_net_0;
wire          SPI_0_CLK;
wire          SPI_0_DI;
wire          SPI_0_DO_net_0;
wire          SPI_0_SS0;
wire          SPI_0_DO_net_1;
wire          MDDR_DQS_TMATCH_0_OUT_net_1;
wire          MDDR_CAS_N_net_1;
wire          MDDR_CLK_net_1;
wire          MDDR_CLK_N_net_1;
wire          MDDR_CKE_net_1;
wire          MDDR_CS_N_net_1;
wire          MDDR_ODT_net_1;
wire          MDDR_RAS_N_net_1;
wire          MDDR_RESET_N_net_1;
wire          MDDR_WE_N_net_1;
wire          GPIO_0_M2F_net_1;
wire          GPIO_1_M2F_net_1;
wire          GPIO_2_M2F_net_1;
wire          GPIO_3_M2F_net_1;
wire          GPIO_4_M2F_net_1;
wire          GPIO_8_M2F_net_1;
wire          GPIO_9_M2F_net_1;
wire          GPIO_10_M2F_net_1;
wire          MMUART_1_TXD_net_1;
wire   [15:0] MDDR_ADDR_net_1;
wire   [2:0]  MDDR_BA_net_1;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire          VCC_net;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign VCC_net = 1'b1;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign SPI_0_DO_net_1              = SPI_0_DO_net_0;
assign SPI_0_DO                    = SPI_0_DO_net_1;
assign MDDR_DQS_TMATCH_0_OUT_net_1 = MDDR_DQS_TMATCH_0_OUT_net_0;
assign MDDR_DQS_TMATCH_0_OUT       = MDDR_DQS_TMATCH_0_OUT_net_1;
assign MDDR_CAS_N_net_1            = MDDR_CAS_N_net_0;
assign MDDR_CAS_N                  = MDDR_CAS_N_net_1;
assign MDDR_CLK_net_1              = MDDR_CLK_net_0;
assign MDDR_CLK                    = MDDR_CLK_net_1;
assign MDDR_CLK_N_net_1            = MDDR_CLK_N_net_0;
assign MDDR_CLK_N                  = MDDR_CLK_N_net_1;
assign MDDR_CKE_net_1              = MDDR_CKE_net_0;
assign MDDR_CKE                    = MDDR_CKE_net_1;
assign MDDR_CS_N_net_1             = MDDR_CS_N_net_0;
assign MDDR_CS_N                   = MDDR_CS_N_net_1;
assign MDDR_ODT_net_1              = MDDR_ODT_net_0;
assign MDDR_ODT                    = MDDR_ODT_net_1;
assign MDDR_RAS_N_net_1            = MDDR_RAS_N_net_0;
assign MDDR_RAS_N                  = MDDR_RAS_N_net_1;
assign MDDR_RESET_N_net_1          = MDDR_RESET_N_net_0;
assign MDDR_RESET_N                = MDDR_RESET_N_net_1;
assign MDDR_WE_N_net_1             = MDDR_WE_N_net_0;
assign MDDR_WE_N                   = MDDR_WE_N_net_1;
assign GPIO_0_M2F_net_1            = GPIO_0_M2F_net_0;
assign GPIO_0_M2F                  = GPIO_0_M2F_net_1;
assign GPIO_1_M2F_net_1            = GPIO_1_M2F_net_0;
assign GPIO_1_M2F                  = GPIO_1_M2F_net_1;
assign GPIO_2_M2F_net_1            = GPIO_2_M2F_net_0;
assign GPIO_2_M2F                  = GPIO_2_M2F_net_1;
assign GPIO_3_M2F_net_1            = GPIO_3_M2F_net_0;
assign GPIO_3_M2F                  = GPIO_3_M2F_net_1;
assign GPIO_4_M2F_net_1            = GPIO_4_M2F_net_0;
assign GPIO_4_M2F                  = GPIO_4_M2F_net_1;
assign GPIO_8_M2F_net_1            = GPIO_8_M2F_net_0;
assign GPIO_8_M2F                  = GPIO_8_M2F_net_1;
assign GPIO_9_M2F_net_1            = GPIO_9_M2F_net_0;
assign GPIO_9_M2F                  = GPIO_9_M2F_net_1;
assign GPIO_10_M2F_net_1           = GPIO_10_M2F_net_0;
assign GPIO_10_M2F                 = GPIO_10_M2F_net_1;
assign MMUART_1_TXD_net_1          = MMUART_1_TXD_net_0;
assign MMUART_1_TXD                = MMUART_1_TXD_net_1;
assign MDDR_ADDR_net_1             = MDDR_ADDR_net_0;
assign MDDR_ADDR[15:0]             = MDDR_ADDR_net_1;
assign MDDR_BA_net_1               = MDDR_BA_net_0;
assign MDDR_BA[2:0]                = MDDR_BA_net_1;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------CodeShadowing_LPDDR
CodeShadowing_LPDDR CodeShadowing_LPDDR_0(
        // Inputs
        .SPI_0_DI              ( SPI_0_DI ),
        .MMUART_1_RXD          ( MMUART_1_RXD ),
        .MDDR_DQS_TMATCH_0_IN  ( MDDR_DQS_TMATCH_0_IN ),
        .FAB_RESET_N           ( VCC_net ),
        .DEVRST_N              ( DEVRST_N ),
        .GPIO_11_F2M           ( GPIO_11_F2M ),
        .GPIO_12_F2M           ( GPIO_12_F2M ),
        // Outputs
        .SPI_0_DO              ( SPI_0_DO_net_0 ),
        .MMUART_1_TXD          ( MMUART_1_TXD_net_0 ),
        .MDDR_DQS_TMATCH_0_OUT ( MDDR_DQS_TMATCH_0_OUT_net_0 ),
        .MDDR_CAS_N            ( MDDR_CAS_N_net_0 ),
        .MDDR_CLK              ( MDDR_CLK_net_0 ),
        .MDDR_CLK_N            ( MDDR_CLK_N_net_0 ),
        .MDDR_CKE              ( MDDR_CKE_net_0 ),
        .MDDR_CS_N             ( MDDR_CS_N_net_0 ),
        .MDDR_ODT              ( MDDR_ODT_net_0 ),
        .MDDR_RAS_N            ( MDDR_RAS_N_net_0 ),
        .MDDR_RESET_N          ( MDDR_RESET_N_net_0 ),
        .MDDR_WE_N             ( MDDR_WE_N_net_0 ),
        .POWER_ON_RESET_N      (  ),
        .INIT_DONE             (  ),
        .DDR_READY             (  ),
        .FAB_CCC_GL0           (  ),
        .FAB_CCC_LOCK          (  ),
        .MSS_READY             (  ),
        .GPIO_0_M2F            ( GPIO_0_M2F_net_0 ),
        .GPIO_1_M2F            ( GPIO_1_M2F_net_0 ),
        .GPIO_2_M2F            ( GPIO_2_M2F_net_0 ),
        .GPIO_3_M2F            ( GPIO_3_M2F_net_0 ),
        .GPIO_4_M2F            ( GPIO_4_M2F_net_0 ),
        .GPIO_8_M2F            ( GPIO_8_M2F_net_0 ),
        .GPIO_9_M2F            ( GPIO_9_M2F_net_0 ),
        .GPIO_10_M2F           ( GPIO_10_M2F_net_0 ),
        .MDDR_ADDR             ( MDDR_ADDR_net_0 ),
        .MDDR_BA               ( MDDR_BA_net_0 ),
        // Inouts
        .SPI_0_CLK             ( SPI_0_CLK ),
        .SPI_0_SS0             ( SPI_0_SS0 ),
        .MDDR_DM_RDQS          ( MDDR_DM_RDQS ),
        .MDDR_DQ               ( MDDR_DQ ),
        .MDDR_DQS              ( MDDR_DQS ) 
        );


endmodule
