`timescale 1 ns/100 ps
// Version: v11.7 11.7.0.119


module MSS_075(
       CAN_RXBUS_MGPIO3A_H2F_A,
       CAN_RXBUS_MGPIO3A_H2F_B,
       CAN_TX_EBL_MGPIO4A_H2F_A,
       CAN_TX_EBL_MGPIO4A_H2F_B,
       CAN_TXBUS_MGPIO2A_H2F_A,
       CAN_TXBUS_MGPIO2A_H2F_B,
       CLK_CONFIG_APB,
       COMMS_INT,
       CONFIG_PRESET_N,
       EDAC_ERROR,
       F_FM0_RDATA,
       F_FM0_READYOUT,
       F_FM0_RESP,
       F_HM0_ADDR,
       F_HM0_ENABLE,
       F_HM0_SEL,
       F_HM0_SIZE,
       F_HM0_TRANS1,
       F_HM0_WDATA,
       F_HM0_WRITE,
       FAB_CHRGVBUS,
       FAB_DISCHRGVBUS,
       FAB_DMPULLDOWN,
       FAB_DPPULLDOWN,
       FAB_DRVVBUS,
       FAB_IDPULLUP,
       FAB_OPMODE,
       FAB_SUSPENDM,
       FAB_TERMSEL,
       FAB_TXVALID,
       FAB_VCONTROL,
       FAB_VCONTROLLOADM,
       FAB_XCVRSEL,
       FAB_XDATAOUT,
       FACC_GLMUX_SEL,
       FIC32_0_MASTER,
       FIC32_1_MASTER,
       FPGA_RESET_N,
       GTX_CLK,
       H2F_INTERRUPT,
       H2F_NMI,
       H2FCALIB,
       I2C0_SCL_MGPIO31B_H2F_A,
       I2C0_SCL_MGPIO31B_H2F_B,
       I2C0_SDA_MGPIO30B_H2F_A,
       I2C0_SDA_MGPIO30B_H2F_B,
       I2C1_SCL_MGPIO1A_H2F_A,
       I2C1_SCL_MGPIO1A_H2F_B,
       I2C1_SDA_MGPIO0A_H2F_A,
       I2C1_SDA_MGPIO0A_H2F_B,
       MDCF,
       MDOENF,
       MDOF,
       MMUART0_CTS_MGPIO19B_H2F_A,
       MMUART0_CTS_MGPIO19B_H2F_B,
       MMUART0_DCD_MGPIO22B_H2F_A,
       MMUART0_DCD_MGPIO22B_H2F_B,
       MMUART0_DSR_MGPIO20B_H2F_A,
       MMUART0_DSR_MGPIO20B_H2F_B,
       MMUART0_DTR_MGPIO18B_H2F_A,
       MMUART0_DTR_MGPIO18B_H2F_B,
       MMUART0_RI_MGPIO21B_H2F_A,
       MMUART0_RI_MGPIO21B_H2F_B,
       MMUART0_RTS_MGPIO17B_H2F_A,
       MMUART0_RTS_MGPIO17B_H2F_B,
       MMUART0_RXD_MGPIO28B_H2F_A,
       MMUART0_RXD_MGPIO28B_H2F_B,
       MMUART0_SCK_MGPIO29B_H2F_A,
       MMUART0_SCK_MGPIO29B_H2F_B,
       MMUART0_TXD_MGPIO27B_H2F_A,
       MMUART0_TXD_MGPIO27B_H2F_B,
       MMUART1_DTR_MGPIO12B_H2F_A,
       MMUART1_RTS_MGPIO11B_H2F_A,
       MMUART1_RTS_MGPIO11B_H2F_B,
       MMUART1_RXD_MGPIO26B_H2F_A,
       MMUART1_RXD_MGPIO26B_H2F_B,
       MMUART1_SCK_MGPIO25B_H2F_A,
       MMUART1_SCK_MGPIO25B_H2F_B,
       MMUART1_TXD_MGPIO24B_H2F_A,
       MMUART1_TXD_MGPIO24B_H2F_B,
       MPLL_LOCK,
       PER2_FABRIC_PADDR,
       PER2_FABRIC_PENABLE,
       PER2_FABRIC_PSEL,
       PER2_FABRIC_PWDATA,
       PER2_FABRIC_PWRITE,
       RTC_MATCH,
       SLEEPDEEP,
       SLEEPHOLDACK,
       SLEEPING,
       SMBALERT_NO0,
       SMBALERT_NO1,
       SMBSUS_NO0,
       SMBSUS_NO1,
       SPI0_CLK_OUT,
       SPI0_SDI_MGPIO5A_H2F_A,
       SPI0_SDI_MGPIO5A_H2F_B,
       SPI0_SDO_MGPIO6A_H2F_A,
       SPI0_SDO_MGPIO6A_H2F_B,
       SPI0_SS0_MGPIO7A_H2F_A,
       SPI0_SS0_MGPIO7A_H2F_B,
       SPI0_SS1_MGPIO8A_H2F_A,
       SPI0_SS1_MGPIO8A_H2F_B,
       SPI0_SS2_MGPIO9A_H2F_A,
       SPI0_SS2_MGPIO9A_H2F_B,
       SPI0_SS3_MGPIO10A_H2F_A,
       SPI0_SS3_MGPIO10A_H2F_B,
       SPI0_SS4_MGPIO19A_H2F_A,
       SPI0_SS5_MGPIO20A_H2F_A,
       SPI0_SS6_MGPIO21A_H2F_A,
       SPI0_SS7_MGPIO22A_H2F_A,
       SPI1_CLK_OUT,
       SPI1_SDI_MGPIO11A_H2F_A,
       SPI1_SDI_MGPIO11A_H2F_B,
       SPI1_SDO_MGPIO12A_H2F_A,
       SPI1_SDO_MGPIO12A_H2F_B,
       SPI1_SS0_MGPIO13A_H2F_A,
       SPI1_SS0_MGPIO13A_H2F_B,
       SPI1_SS1_MGPIO14A_H2F_A,
       SPI1_SS1_MGPIO14A_H2F_B,
       SPI1_SS2_MGPIO15A_H2F_A,
       SPI1_SS2_MGPIO15A_H2F_B,
       SPI1_SS3_MGPIO16A_H2F_A,
       SPI1_SS3_MGPIO16A_H2F_B,
       SPI1_SS4_MGPIO17A_H2F_A,
       SPI1_SS5_MGPIO18A_H2F_A,
       SPI1_SS6_MGPIO23A_H2F_A,
       SPI1_SS7_MGPIO24A_H2F_A,
       TCGF,
       TRACECLK,
       TRACEDATA,
       TX_CLK,
       TX_ENF,
       TX_ERRF,
       TXCTL_EN_RIF,
       TXD_RIF,
       TXDF,
       TXEV,
       WDOGTIMEOUT,
       F_ARREADY_HREADYOUT1,
       F_AWREADY_HREADYOUT0,
       F_BID,
       F_BRESP_HRESP0,
       F_BVALID,
       F_RDATA_HRDATA01,
       F_RID,
       F_RLAST,
       F_RRESP_HRESP1,
       F_RVALID,
       F_WREADY,
       MDDR_FABRIC_PRDATA,
       MDDR_FABRIC_PREADY,
       MDDR_FABRIC_PSLVERR,
       CAN_RXBUS_F2H_SCP,
       CAN_TX_EBL_F2H_SCP,
       CAN_TXBUS_F2H_SCP,
       COLF,
       CRSF,
       F2_DMAREADY,
       F2H_INTERRUPT,
       F2HCALIB,
       F_DMAREADY,
       F_FM0_ADDR,
       F_FM0_ENABLE,
       F_FM0_MASTLOCK,
       F_FM0_READY,
       F_FM0_SEL,
       F_FM0_SIZE,
       F_FM0_TRANS1,
       F_FM0_WDATA,
       F_FM0_WRITE,
       F_HM0_RDATA,
       F_HM0_READY,
       F_HM0_RESP,
       FAB_AVALID,
       FAB_HOSTDISCON,
       FAB_IDDIG,
       FAB_LINESTATE,
       FAB_M3_RESET_N,
       FAB_PLL_LOCK,
       FAB_RXACTIVE,
       FAB_RXERROR,
       FAB_RXVALID,
       FAB_RXVALIDH,
       FAB_SESSEND,
       FAB_TXREADY,
       FAB_VBUSVALID,
       FAB_VSTATUS,
       FAB_XDATAIN,
       GTX_CLKPF,
       I2C0_BCLK,
       I2C0_SCL_F2H_SCP,
       I2C0_SDA_F2H_SCP,
       I2C1_BCLK,
       I2C1_SCL_F2H_SCP,
       I2C1_SDA_F2H_SCP,
       MDIF,
       MGPIO0A_F2H_GPIN,
       MGPIO10A_F2H_GPIN,
       MGPIO11A_F2H_GPIN,
       MGPIO11B_F2H_GPIN,
       MGPIO12A_F2H_GPIN,
       MGPIO13A_F2H_GPIN,
       MGPIO14A_F2H_GPIN,
       MGPIO15A_F2H_GPIN,
       MGPIO16A_F2H_GPIN,
       MGPIO17B_F2H_GPIN,
       MGPIO18B_F2H_GPIN,
       MGPIO19B_F2H_GPIN,
       MGPIO1A_F2H_GPIN,
       MGPIO20B_F2H_GPIN,
       MGPIO21B_F2H_GPIN,
       MGPIO22B_F2H_GPIN,
       MGPIO24B_F2H_GPIN,
       MGPIO25B_F2H_GPIN,
       MGPIO26B_F2H_GPIN,
       MGPIO27B_F2H_GPIN,
       MGPIO28B_F2H_GPIN,
       MGPIO29B_F2H_GPIN,
       MGPIO2A_F2H_GPIN,
       MGPIO30B_F2H_GPIN,
       MGPIO31B_F2H_GPIN,
       MGPIO3A_F2H_GPIN,
       MGPIO4A_F2H_GPIN,
       MGPIO5A_F2H_GPIN,
       MGPIO6A_F2H_GPIN,
       MGPIO7A_F2H_GPIN,
       MGPIO8A_F2H_GPIN,
       MGPIO9A_F2H_GPIN,
       MMUART0_CTS_F2H_SCP,
       MMUART0_DCD_F2H_SCP,
       MMUART0_DSR_F2H_SCP,
       MMUART0_DTR_F2H_SCP,
       MMUART0_RI_F2H_SCP,
       MMUART0_RTS_F2H_SCP,
       MMUART0_RXD_F2H_SCP,
       MMUART0_SCK_F2H_SCP,
       MMUART0_TXD_F2H_SCP,
       MMUART1_CTS_F2H_SCP,
       MMUART1_DCD_F2H_SCP,
       MMUART1_DSR_F2H_SCP,
       MMUART1_RI_F2H_SCP,
       MMUART1_RTS_F2H_SCP,
       MMUART1_RXD_F2H_SCP,
       MMUART1_SCK_F2H_SCP,
       MMUART1_TXD_F2H_SCP,
       PER2_FABRIC_PRDATA,
       PER2_FABRIC_PREADY,
       PER2_FABRIC_PSLVERR,
       RCGF,
       RX_CLKPF,
       RX_DVF,
       RX_ERRF,
       RX_EV,
       RXDF,
       SLEEPHOLDREQ,
       SMBALERT_NI0,
       SMBALERT_NI1,
       SMBSUS_NI0,
       SMBSUS_NI1,
       SPI0_CLK_IN,
       SPI0_SDI_F2H_SCP,
       SPI0_SDO_F2H_SCP,
       SPI0_SS0_F2H_SCP,
       SPI0_SS1_F2H_SCP,
       SPI0_SS2_F2H_SCP,
       SPI0_SS3_F2H_SCP,
       SPI1_CLK_IN,
       SPI1_SDI_F2H_SCP,
       SPI1_SDO_F2H_SCP,
       SPI1_SS0_F2H_SCP,
       SPI1_SS1_F2H_SCP,
       SPI1_SS2_F2H_SCP,
       SPI1_SS3_F2H_SCP,
       TX_CLKPF,
       USER_MSS_GPIO_RESET_N,
       USER_MSS_RESET_N,
       XCLK_FAB,
       CLK_BASE,
       CLK_MDDR_APB,
       F_ARADDR_HADDR1,
       F_ARBURST_HTRANS1,
       F_ARID_HSEL1,
       F_ARLEN_HBURST1,
       F_ARLOCK_HMASTLOCK1,
       F_ARSIZE_HSIZE1,
       F_ARVALID_HWRITE1,
       F_AWADDR_HADDR0,
       F_AWBURST_HTRANS0,
       F_AWID_HSEL0,
       F_AWLEN_HBURST0,
       F_AWLOCK_HMASTLOCK0,
       F_AWSIZE_HSIZE0,
       F_AWVALID_HWRITE0,
       F_BREADY,
       F_RMW_AXI,
       F_RREADY,
       F_WDATA_HWDATA01,
       F_WID_HREADY01,
       F_WLAST,
       F_WSTRB,
       F_WVALID,
       FPGA_MDDR_ARESET_N,
       MDDR_FABRIC_PADDR,
       MDDR_FABRIC_PENABLE,
       MDDR_FABRIC_PSEL,
       MDDR_FABRIC_PWDATA,
       MDDR_FABRIC_PWRITE,
       PRESET_N,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_IN,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_IN,
       DM_IN,
       DRAM_DQ_IN,
       DRAM_DQS_IN,
       DRAM_FIFO_WE_IN,
       I2C0_SCL_USBC_DATA1_MGPIO31B_IN,
       I2C0_SDA_USBC_DATA0_MGPIO30B_IN,
       I2C1_SCL_USBA_DATA4_MGPIO1A_IN,
       I2C1_SDA_USBA_DATA3_MGPIO0A_IN,
       MGPIO0B_IN,
       MGPIO10B_IN,
       MGPIO1B_IN,
       MGPIO25A_IN,
       MGPIO26A_IN,
       MGPIO27A_IN,
       MGPIO28A_IN,
       MGPIO29A_IN,
       MGPIO2B_IN,
       MGPIO30A_IN,
       MGPIO31A_IN,
       MGPIO3B_IN,
       MGPIO4B_IN,
       MGPIO5B_IN,
       MGPIO6B_IN,
       MGPIO7B_IN,
       MGPIO8B_IN,
       MGPIO9B_IN,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_IN,
       MMUART0_DCD_MGPIO22B_IN,
       MMUART0_DSR_MGPIO20B_IN,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_IN,
       MMUART0_RI_MGPIO21B_IN,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_IN,
       MMUART0_RXD_USBC_STP_MGPIO28B_IN,
       MMUART0_SCK_USBC_NXT_MGPIO29B_IN,
       MMUART0_TXD_USBC_DIR_MGPIO27B_IN,
       MMUART1_CTS_MGPIO13B_IN,
       MMUART1_DCD_MGPIO16B_IN,
       MMUART1_DSR_MGPIO14B_IN,
       MMUART1_DTR_MGPIO12B_IN,
       MMUART1_RI_MGPIO15B_IN,
       MMUART1_RTS_MGPIO11B_IN,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_IN,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_IN,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_IN,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN,
       RGMII_MDC_RMII_MDC_IN,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN,
       RGMII_RX_CLK_IN,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN,
       RGMII_RXD3_USBB_DATA4_IN,
       RGMII_TX_CLK_IN,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_IN,
       RGMII_TXD1_RMII_TXD1_USBB_STP_IN,
       RGMII_TXD2_USBB_DATA5_IN,
       RGMII_TXD3_USBB_DATA6_IN,
       SPI0_SCK_USBA_XCLK_IN,
       SPI0_SDI_USBA_DIR_MGPIO5A_IN,
       SPI0_SDO_USBA_STP_MGPIO6A_IN,
       SPI0_SS0_USBA_NXT_MGPIO7A_IN,
       SPI0_SS1_USBA_DATA5_MGPIO8A_IN,
       SPI0_SS2_USBA_DATA6_MGPIO9A_IN,
       SPI0_SS3_USBA_DATA7_MGPIO10A_IN,
       SPI0_SS4_MGPIO19A_IN,
       SPI0_SS5_MGPIO20A_IN,
       SPI0_SS6_MGPIO21A_IN,
       SPI0_SS7_MGPIO22A_IN,
       SPI1_SCK_IN,
       SPI1_SDI_MGPIO11A_IN,
       SPI1_SDO_MGPIO12A_IN,
       SPI1_SS0_MGPIO13A_IN,
       SPI1_SS1_MGPIO14A_IN,
       SPI1_SS2_MGPIO15A_IN,
       SPI1_SS3_MGPIO16A_IN,
       SPI1_SS4_MGPIO17A_IN,
       SPI1_SS5_MGPIO18A_IN,
       SPI1_SS6_MGPIO23A_IN,
       SPI1_SS7_MGPIO24A_IN,
       USBC_XCLK_IN,
       USBD_DATA0_IN,
       USBD_DATA1_IN,
       USBD_DATA2_IN,
       USBD_DATA3_IN,
       USBD_DATA4_IN,
       USBD_DATA5_IN,
       USBD_DATA6_IN,
       USBD_DATA7_MGPIO23B_IN,
       USBD_DIR_IN,
       USBD_NXT_IN,
       USBD_STP_IN,
       USBD_XCLK_IN,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT,
       DRAM_ADDR,
       DRAM_BA,
       DRAM_CASN,
       DRAM_CKE,
       DRAM_CLK,
       DRAM_CSN,
       DRAM_DM_RDQS_OUT,
       DRAM_DQ_OUT,
       DRAM_DQS_OUT,
       DRAM_FIFO_WE_OUT,
       DRAM_ODT,
       DRAM_RASN,
       DRAM_RSTN,
       DRAM_WEN,
       I2C0_SCL_USBC_DATA1_MGPIO31B_OUT,
       I2C0_SDA_USBC_DATA0_MGPIO30B_OUT,
       I2C1_SCL_USBA_DATA4_MGPIO1A_OUT,
       I2C1_SDA_USBA_DATA3_MGPIO0A_OUT,
       MGPIO0B_OUT,
       MGPIO10B_OUT,
       MGPIO1B_OUT,
       MGPIO25A_OUT,
       MGPIO26A_OUT,
       MGPIO27A_OUT,
       MGPIO28A_OUT,
       MGPIO29A_OUT,
       MGPIO2B_OUT,
       MGPIO30A_OUT,
       MGPIO31A_OUT,
       MGPIO3B_OUT,
       MGPIO4B_OUT,
       MGPIO5B_OUT,
       MGPIO6B_OUT,
       MGPIO7B_OUT,
       MGPIO8B_OUT,
       MGPIO9B_OUT,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT,
       MMUART0_DCD_MGPIO22B_OUT,
       MMUART0_DSR_MGPIO20B_OUT,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT,
       MMUART0_RI_MGPIO21B_OUT,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT,
       MMUART0_RXD_USBC_STP_MGPIO28B_OUT,
       MMUART0_SCK_USBC_NXT_MGPIO29B_OUT,
       MMUART0_TXD_USBC_DIR_MGPIO27B_OUT,
       MMUART1_CTS_MGPIO13B_OUT,
       MMUART1_DCD_MGPIO16B_OUT,
       MMUART1_DSR_MGPIO14B_OUT,
       MMUART1_DTR_MGPIO12B_OUT,
       MMUART1_RI_MGPIO15B_OUT,
       MMUART1_RTS_MGPIO11B_OUT,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT,
       RGMII_MDC_RMII_MDC_OUT,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT,
       RGMII_RX_CLK_OUT,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT,
       RGMII_RXD3_USBB_DATA4_OUT,
       RGMII_TX_CLK_OUT,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT,
       RGMII_TXD1_RMII_TXD1_USBB_STP_OUT,
       RGMII_TXD2_USBB_DATA5_OUT,
       RGMII_TXD3_USBB_DATA6_OUT,
       SPI0_SCK_USBA_XCLK_OUT,
       SPI0_SDI_USBA_DIR_MGPIO5A_OUT,
       SPI0_SDO_USBA_STP_MGPIO6A_OUT,
       SPI0_SS0_USBA_NXT_MGPIO7A_OUT,
       SPI0_SS1_USBA_DATA5_MGPIO8A_OUT,
       SPI0_SS2_USBA_DATA6_MGPIO9A_OUT,
       SPI0_SS3_USBA_DATA7_MGPIO10A_OUT,
       SPI0_SS4_MGPIO19A_OUT,
       SPI0_SS5_MGPIO20A_OUT,
       SPI0_SS6_MGPIO21A_OUT,
       SPI0_SS7_MGPIO22A_OUT,
       SPI1_SCK_OUT,
       SPI1_SDI_MGPIO11A_OUT,
       SPI1_SDO_MGPIO12A_OUT,
       SPI1_SS0_MGPIO13A_OUT,
       SPI1_SS1_MGPIO14A_OUT,
       SPI1_SS2_MGPIO15A_OUT,
       SPI1_SS3_MGPIO16A_OUT,
       SPI1_SS4_MGPIO17A_OUT,
       SPI1_SS5_MGPIO18A_OUT,
       SPI1_SS6_MGPIO23A_OUT,
       SPI1_SS7_MGPIO24A_OUT,
       USBC_XCLK_OUT,
       USBD_DATA0_OUT,
       USBD_DATA1_OUT,
       USBD_DATA2_OUT,
       USBD_DATA3_OUT,
       USBD_DATA4_OUT,
       USBD_DATA5_OUT,
       USBD_DATA6_OUT,
       USBD_DATA7_MGPIO23B_OUT,
       USBD_DIR_OUT,
       USBD_NXT_OUT,
       USBD_STP_OUT,
       USBD_XCLK_OUT,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_OE,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_OE,
       DM_OE,
       DRAM_DQ_OE,
       DRAM_DQS_OE,
       I2C0_SCL_USBC_DATA1_MGPIO31B_OE,
       I2C0_SDA_USBC_DATA0_MGPIO30B_OE,
       I2C1_SCL_USBA_DATA4_MGPIO1A_OE,
       I2C1_SDA_USBA_DATA3_MGPIO0A_OE,
       MGPIO0B_OE,
       MGPIO10B_OE,
       MGPIO1B_OE,
       MGPIO25A_OE,
       MGPIO26A_OE,
       MGPIO27A_OE,
       MGPIO28A_OE,
       MGPIO29A_OE,
       MGPIO2B_OE,
       MGPIO30A_OE,
       MGPIO31A_OE,
       MGPIO3B_OE,
       MGPIO4B_OE,
       MGPIO5B_OE,
       MGPIO6B_OE,
       MGPIO7B_OE,
       MGPIO8B_OE,
       MGPIO9B_OE,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_OE,
       MMUART0_DCD_MGPIO22B_OE,
       MMUART0_DSR_MGPIO20B_OE,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_OE,
       MMUART0_RI_MGPIO21B_OE,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_OE,
       MMUART0_RXD_USBC_STP_MGPIO28B_OE,
       MMUART0_SCK_USBC_NXT_MGPIO29B_OE,
       MMUART0_TXD_USBC_DIR_MGPIO27B_OE,
       MMUART1_CTS_MGPIO13B_OE,
       MMUART1_DCD_MGPIO16B_OE,
       MMUART1_DSR_MGPIO14B_OE,
       MMUART1_DTR_MGPIO12B_OE,
       MMUART1_RI_MGPIO15B_OE,
       MMUART1_RTS_MGPIO11B_OE,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_OE,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_OE,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_OE,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE,
       RGMII_MDC_RMII_MDC_OE,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE,
       RGMII_RX_CLK_OE,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE,
       RGMII_RXD3_USBB_DATA4_OE,
       RGMII_TX_CLK_OE,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_OE,
       RGMII_TXD1_RMII_TXD1_USBB_STP_OE,
       RGMII_TXD2_USBB_DATA5_OE,
       RGMII_TXD3_USBB_DATA6_OE,
       SPI0_SCK_USBA_XCLK_OE,
       SPI0_SDI_USBA_DIR_MGPIO5A_OE,
       SPI0_SDO_USBA_STP_MGPIO6A_OE,
       SPI0_SS0_USBA_NXT_MGPIO7A_OE,
       SPI0_SS1_USBA_DATA5_MGPIO8A_OE,
       SPI0_SS2_USBA_DATA6_MGPIO9A_OE,
       SPI0_SS3_USBA_DATA7_MGPIO10A_OE,
       SPI0_SS4_MGPIO19A_OE,
       SPI0_SS5_MGPIO20A_OE,
       SPI0_SS6_MGPIO21A_OE,
       SPI0_SS7_MGPIO22A_OE,
       SPI1_SCK_OE,
       SPI1_SDI_MGPIO11A_OE,
       SPI1_SDO_MGPIO12A_OE,
       SPI1_SS0_MGPIO13A_OE,
       SPI1_SS1_MGPIO14A_OE,
       SPI1_SS2_MGPIO15A_OE,
       SPI1_SS3_MGPIO16A_OE,
       SPI1_SS4_MGPIO17A_OE,
       SPI1_SS5_MGPIO18A_OE,
       SPI1_SS6_MGPIO23A_OE,
       SPI1_SS7_MGPIO24A_OE,
       USBC_XCLK_OE,
       USBD_DATA0_OE,
       USBD_DATA1_OE,
       USBD_DATA2_OE,
       USBD_DATA3_OE,
       USBD_DATA4_OE,
       USBD_DATA5_OE,
       USBD_DATA6_OE,
       USBD_DATA7_MGPIO23B_OE,
       USBD_DIR_OE,
       USBD_NXT_OE,
       USBD_STP_OE,
       USBD_XCLK_OE
    );
output CAN_RXBUS_MGPIO3A_H2F_A;
output CAN_RXBUS_MGPIO3A_H2F_B;
output CAN_TX_EBL_MGPIO4A_H2F_A;
output CAN_TX_EBL_MGPIO4A_H2F_B;
output CAN_TXBUS_MGPIO2A_H2F_A;
output CAN_TXBUS_MGPIO2A_H2F_B;
output CLK_CONFIG_APB;
output COMMS_INT;
output CONFIG_PRESET_N;
output [7:0] EDAC_ERROR;
output [31:0] F_FM0_RDATA;
output F_FM0_READYOUT;
output F_FM0_RESP;
output [31:0] F_HM0_ADDR;
output F_HM0_ENABLE;
output F_HM0_SEL;
output [1:0] F_HM0_SIZE;
output F_HM0_TRANS1;
output [31:0] F_HM0_WDATA;
output F_HM0_WRITE;
output FAB_CHRGVBUS;
output FAB_DISCHRGVBUS;
output FAB_DMPULLDOWN;
output FAB_DPPULLDOWN;
output FAB_DRVVBUS;
output FAB_IDPULLUP;
output [1:0] FAB_OPMODE;
output FAB_SUSPENDM;
output FAB_TERMSEL;
output FAB_TXVALID;
output [3:0] FAB_VCONTROL;
output FAB_VCONTROLLOADM;
output [1:0] FAB_XCVRSEL;
output [7:0] FAB_XDATAOUT;
output FACC_GLMUX_SEL;
output [1:0] FIC32_0_MASTER;
output [1:0] FIC32_1_MASTER;
output FPGA_RESET_N;
output GTX_CLK;
output [15:0] H2F_INTERRUPT;
output H2F_NMI;
output H2FCALIB;
output I2C0_SCL_MGPIO31B_H2F_A;
output I2C0_SCL_MGPIO31B_H2F_B;
output I2C0_SDA_MGPIO30B_H2F_A;
output I2C0_SDA_MGPIO30B_H2F_B;
output I2C1_SCL_MGPIO1A_H2F_A;
output I2C1_SCL_MGPIO1A_H2F_B;
output I2C1_SDA_MGPIO0A_H2F_A;
output I2C1_SDA_MGPIO0A_H2F_B;
output MDCF;
output MDOENF;
output MDOF;
output MMUART0_CTS_MGPIO19B_H2F_A;
output MMUART0_CTS_MGPIO19B_H2F_B;
output MMUART0_DCD_MGPIO22B_H2F_A;
output MMUART0_DCD_MGPIO22B_H2F_B;
output MMUART0_DSR_MGPIO20B_H2F_A;
output MMUART0_DSR_MGPIO20B_H2F_B;
output MMUART0_DTR_MGPIO18B_H2F_A;
output MMUART0_DTR_MGPIO18B_H2F_B;
output MMUART0_RI_MGPIO21B_H2F_A;
output MMUART0_RI_MGPIO21B_H2F_B;
output MMUART0_RTS_MGPIO17B_H2F_A;
output MMUART0_RTS_MGPIO17B_H2F_B;
output MMUART0_RXD_MGPIO28B_H2F_A;
output MMUART0_RXD_MGPIO28B_H2F_B;
output MMUART0_SCK_MGPIO29B_H2F_A;
output MMUART0_SCK_MGPIO29B_H2F_B;
output MMUART0_TXD_MGPIO27B_H2F_A;
output MMUART0_TXD_MGPIO27B_H2F_B;
output MMUART1_DTR_MGPIO12B_H2F_A;
output MMUART1_RTS_MGPIO11B_H2F_A;
output MMUART1_RTS_MGPIO11B_H2F_B;
output MMUART1_RXD_MGPIO26B_H2F_A;
output MMUART1_RXD_MGPIO26B_H2F_B;
output MMUART1_SCK_MGPIO25B_H2F_A;
output MMUART1_SCK_MGPIO25B_H2F_B;
output MMUART1_TXD_MGPIO24B_H2F_A;
output MMUART1_TXD_MGPIO24B_H2F_B;
output MPLL_LOCK;
output [15:2] PER2_FABRIC_PADDR;
output PER2_FABRIC_PENABLE;
output PER2_FABRIC_PSEL;
output [31:0] PER2_FABRIC_PWDATA;
output PER2_FABRIC_PWRITE;
output RTC_MATCH;
output SLEEPDEEP;
output SLEEPHOLDACK;
output SLEEPING;
output SMBALERT_NO0;
output SMBALERT_NO1;
output SMBSUS_NO0;
output SMBSUS_NO1;
output SPI0_CLK_OUT;
output SPI0_SDI_MGPIO5A_H2F_A;
output SPI0_SDI_MGPIO5A_H2F_B;
output SPI0_SDO_MGPIO6A_H2F_A;
output SPI0_SDO_MGPIO6A_H2F_B;
output SPI0_SS0_MGPIO7A_H2F_A;
output SPI0_SS0_MGPIO7A_H2F_B;
output SPI0_SS1_MGPIO8A_H2F_A;
output SPI0_SS1_MGPIO8A_H2F_B;
output SPI0_SS2_MGPIO9A_H2F_A;
output SPI0_SS2_MGPIO9A_H2F_B;
output SPI0_SS3_MGPIO10A_H2F_A;
output SPI0_SS3_MGPIO10A_H2F_B;
output SPI0_SS4_MGPIO19A_H2F_A;
output SPI0_SS5_MGPIO20A_H2F_A;
output SPI0_SS6_MGPIO21A_H2F_A;
output SPI0_SS7_MGPIO22A_H2F_A;
output SPI1_CLK_OUT;
output SPI1_SDI_MGPIO11A_H2F_A;
output SPI1_SDI_MGPIO11A_H2F_B;
output SPI1_SDO_MGPIO12A_H2F_A;
output SPI1_SDO_MGPIO12A_H2F_B;
output SPI1_SS0_MGPIO13A_H2F_A;
output SPI1_SS0_MGPIO13A_H2F_B;
output SPI1_SS1_MGPIO14A_H2F_A;
output SPI1_SS1_MGPIO14A_H2F_B;
output SPI1_SS2_MGPIO15A_H2F_A;
output SPI1_SS2_MGPIO15A_H2F_B;
output SPI1_SS3_MGPIO16A_H2F_A;
output SPI1_SS3_MGPIO16A_H2F_B;
output SPI1_SS4_MGPIO17A_H2F_A;
output SPI1_SS5_MGPIO18A_H2F_A;
output SPI1_SS6_MGPIO23A_H2F_A;
output SPI1_SS7_MGPIO24A_H2F_A;
output [9:0] TCGF;
output TRACECLK;
output [3:0] TRACEDATA;
output TX_CLK;
output TX_ENF;
output TX_ERRF;
output TXCTL_EN_RIF;
output [3:0] TXD_RIF;
output [7:0] TXDF;
output TXEV;
output WDOGTIMEOUT;
output F_ARREADY_HREADYOUT1;
output F_AWREADY_HREADYOUT0;
output [3:0] F_BID;
output [1:0] F_BRESP_HRESP0;
output F_BVALID;
output [63:0] F_RDATA_HRDATA01;
output [3:0] F_RID;
output F_RLAST;
output [1:0] F_RRESP_HRESP1;
output F_RVALID;
output F_WREADY;
output [15:0] MDDR_FABRIC_PRDATA;
output MDDR_FABRIC_PREADY;
output MDDR_FABRIC_PSLVERR;
input  CAN_RXBUS_F2H_SCP;
input  CAN_TX_EBL_F2H_SCP;
input  CAN_TXBUS_F2H_SCP;
input  COLF;
input  CRSF;
input  [1:0] F2_DMAREADY;
input  [15:0] F2H_INTERRUPT;
input  F2HCALIB;
input  [1:0] F_DMAREADY;
input  [31:0] F_FM0_ADDR;
input  F_FM0_ENABLE;
input  F_FM0_MASTLOCK;
input  F_FM0_READY;
input  F_FM0_SEL;
input  [1:0] F_FM0_SIZE;
input  F_FM0_TRANS1;
input  [31:0] F_FM0_WDATA;
input  F_FM0_WRITE;
input  [31:0] F_HM0_RDATA;
input  F_HM0_READY;
input  F_HM0_RESP;
input  FAB_AVALID;
input  FAB_HOSTDISCON;
input  FAB_IDDIG;
input  [1:0] FAB_LINESTATE;
input  FAB_M3_RESET_N;
input  FAB_PLL_LOCK;
input  FAB_RXACTIVE;
input  FAB_RXERROR;
input  FAB_RXVALID;
input  FAB_RXVALIDH;
input  FAB_SESSEND;
input  FAB_TXREADY;
input  FAB_VBUSVALID;
input  [7:0] FAB_VSTATUS;
input  [7:0] FAB_XDATAIN;
input  GTX_CLKPF;
input  I2C0_BCLK;
input  I2C0_SCL_F2H_SCP;
input  I2C0_SDA_F2H_SCP;
input  I2C1_BCLK;
input  I2C1_SCL_F2H_SCP;
input  I2C1_SDA_F2H_SCP;
input  MDIF;
input  MGPIO0A_F2H_GPIN;
input  MGPIO10A_F2H_GPIN;
input  MGPIO11A_F2H_GPIN;
input  MGPIO11B_F2H_GPIN;
input  MGPIO12A_F2H_GPIN;
input  MGPIO13A_F2H_GPIN;
input  MGPIO14A_F2H_GPIN;
input  MGPIO15A_F2H_GPIN;
input  MGPIO16A_F2H_GPIN;
input  MGPIO17B_F2H_GPIN;
input  MGPIO18B_F2H_GPIN;
input  MGPIO19B_F2H_GPIN;
input  MGPIO1A_F2H_GPIN;
input  MGPIO20B_F2H_GPIN;
input  MGPIO21B_F2H_GPIN;
input  MGPIO22B_F2H_GPIN;
input  MGPIO24B_F2H_GPIN;
input  MGPIO25B_F2H_GPIN;
input  MGPIO26B_F2H_GPIN;
input  MGPIO27B_F2H_GPIN;
input  MGPIO28B_F2H_GPIN;
input  MGPIO29B_F2H_GPIN;
input  MGPIO2A_F2H_GPIN;
input  MGPIO30B_F2H_GPIN;
input  MGPIO31B_F2H_GPIN;
input  MGPIO3A_F2H_GPIN;
input  MGPIO4A_F2H_GPIN;
input  MGPIO5A_F2H_GPIN;
input  MGPIO6A_F2H_GPIN;
input  MGPIO7A_F2H_GPIN;
input  MGPIO8A_F2H_GPIN;
input  MGPIO9A_F2H_GPIN;
input  MMUART0_CTS_F2H_SCP;
input  MMUART0_DCD_F2H_SCP;
input  MMUART0_DSR_F2H_SCP;
input  MMUART0_DTR_F2H_SCP;
input  MMUART0_RI_F2H_SCP;
input  MMUART0_RTS_F2H_SCP;
input  MMUART0_RXD_F2H_SCP;
input  MMUART0_SCK_F2H_SCP;
input  MMUART0_TXD_F2H_SCP;
input  MMUART1_CTS_F2H_SCP;
input  MMUART1_DCD_F2H_SCP;
input  MMUART1_DSR_F2H_SCP;
input  MMUART1_RI_F2H_SCP;
input  MMUART1_RTS_F2H_SCP;
input  MMUART1_RXD_F2H_SCP;
input  MMUART1_SCK_F2H_SCP;
input  MMUART1_TXD_F2H_SCP;
input  [31:0] PER2_FABRIC_PRDATA;
input  PER2_FABRIC_PREADY;
input  PER2_FABRIC_PSLVERR;
input  [9:0] RCGF;
input  RX_CLKPF;
input  RX_DVF;
input  RX_ERRF;
input  RX_EV;
input  [7:0] RXDF;
input  SLEEPHOLDREQ;
input  SMBALERT_NI0;
input  SMBALERT_NI1;
input  SMBSUS_NI0;
input  SMBSUS_NI1;
input  SPI0_CLK_IN;
input  SPI0_SDI_F2H_SCP;
input  SPI0_SDO_F2H_SCP;
input  SPI0_SS0_F2H_SCP;
input  SPI0_SS1_F2H_SCP;
input  SPI0_SS2_F2H_SCP;
input  SPI0_SS3_F2H_SCP;
input  SPI1_CLK_IN;
input  SPI1_SDI_F2H_SCP;
input  SPI1_SDO_F2H_SCP;
input  SPI1_SS0_F2H_SCP;
input  SPI1_SS1_F2H_SCP;
input  SPI1_SS2_F2H_SCP;
input  SPI1_SS3_F2H_SCP;
input  TX_CLKPF;
input  USER_MSS_GPIO_RESET_N;
input  USER_MSS_RESET_N;
input  XCLK_FAB;
input  CLK_BASE;
input  CLK_MDDR_APB;
input  [31:0] F_ARADDR_HADDR1;
input  [1:0] F_ARBURST_HTRANS1;
input  [3:0] F_ARID_HSEL1;
input  [3:0] F_ARLEN_HBURST1;
input  [1:0] F_ARLOCK_HMASTLOCK1;
input  [1:0] F_ARSIZE_HSIZE1;
input  F_ARVALID_HWRITE1;
input  [31:0] F_AWADDR_HADDR0;
input  [1:0] F_AWBURST_HTRANS0;
input  [3:0] F_AWID_HSEL0;
input  [3:0] F_AWLEN_HBURST0;
input  [1:0] F_AWLOCK_HMASTLOCK0;
input  [1:0] F_AWSIZE_HSIZE0;
input  F_AWVALID_HWRITE0;
input  F_BREADY;
input  F_RMW_AXI;
input  F_RREADY;
input  [63:0] F_WDATA_HWDATA01;
input  [3:0] F_WID_HREADY01;
input  F_WLAST;
input  [7:0] F_WSTRB;
input  F_WVALID;
input  FPGA_MDDR_ARESET_N;
input  [10:2] MDDR_FABRIC_PADDR;
input  MDDR_FABRIC_PENABLE;
input  MDDR_FABRIC_PSEL;
input  [15:0] MDDR_FABRIC_PWDATA;
input  MDDR_FABRIC_PWRITE;
input  PRESET_N;
input  CAN_RXBUS_USBA_DATA1_MGPIO3A_IN;
input  CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN;
input  CAN_TXBUS_USBA_DATA0_MGPIO2A_IN;
input  [2:0] DM_IN;
input  [17:0] DRAM_DQ_IN;
input  [2:0] DRAM_DQS_IN;
input  [1:0] DRAM_FIFO_WE_IN;
input  I2C0_SCL_USBC_DATA1_MGPIO31B_IN;
input  I2C0_SDA_USBC_DATA0_MGPIO30B_IN;
input  I2C1_SCL_USBA_DATA4_MGPIO1A_IN;
input  I2C1_SDA_USBA_DATA3_MGPIO0A_IN;
input  MGPIO0B_IN;
input  MGPIO10B_IN;
input  MGPIO1B_IN;
input  MGPIO25A_IN;
input  MGPIO26A_IN;
input  MGPIO27A_IN;
input  MGPIO28A_IN;
input  MGPIO29A_IN;
input  MGPIO2B_IN;
input  MGPIO30A_IN;
input  MGPIO31A_IN;
input  MGPIO3B_IN;
input  MGPIO4B_IN;
input  MGPIO5B_IN;
input  MGPIO6B_IN;
input  MGPIO7B_IN;
input  MGPIO8B_IN;
input  MGPIO9B_IN;
input  MMUART0_CTS_USBC_DATA7_MGPIO19B_IN;
input  MMUART0_DCD_MGPIO22B_IN;
input  MMUART0_DSR_MGPIO20B_IN;
input  MMUART0_DTR_USBC_DATA6_MGPIO18B_IN;
input  MMUART0_RI_MGPIO21B_IN;
input  MMUART0_RTS_USBC_DATA5_MGPIO17B_IN;
input  MMUART0_RXD_USBC_STP_MGPIO28B_IN;
input  MMUART0_SCK_USBC_NXT_MGPIO29B_IN;
input  MMUART0_TXD_USBC_DIR_MGPIO27B_IN;
input  MMUART1_CTS_MGPIO13B_IN;
input  MMUART1_DCD_MGPIO16B_IN;
input  MMUART1_DSR_MGPIO14B_IN;
input  MMUART1_DTR_MGPIO12B_IN;
input  MMUART1_RI_MGPIO15B_IN;
input  MMUART1_RTS_MGPIO11B_IN;
input  MMUART1_RXD_USBC_DATA3_MGPIO26B_IN;
input  MMUART1_SCK_USBC_DATA4_MGPIO25B_IN;
input  MMUART1_TXD_USBC_DATA2_MGPIO24B_IN;
input  RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN;
input  RGMII_MDC_RMII_MDC_IN;
input  RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN;
input  RGMII_RX_CLK_IN;
input  RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN;
input  RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN;
input  RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN;
input  RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN;
input  RGMII_RXD3_USBB_DATA4_IN;
input  RGMII_TX_CLK_IN;
input  RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN;
input  RGMII_TXD0_RMII_TXD0_USBB_DIR_IN;
input  RGMII_TXD1_RMII_TXD1_USBB_STP_IN;
input  RGMII_TXD2_USBB_DATA5_IN;
input  RGMII_TXD3_USBB_DATA6_IN;
input  SPI0_SCK_USBA_XCLK_IN;
input  SPI0_SDI_USBA_DIR_MGPIO5A_IN;
input  SPI0_SDO_USBA_STP_MGPIO6A_IN;
input  SPI0_SS0_USBA_NXT_MGPIO7A_IN;
input  SPI0_SS1_USBA_DATA5_MGPIO8A_IN;
input  SPI0_SS2_USBA_DATA6_MGPIO9A_IN;
input  SPI0_SS3_USBA_DATA7_MGPIO10A_IN;
input  SPI0_SS4_MGPIO19A_IN;
input  SPI0_SS5_MGPIO20A_IN;
input  SPI0_SS6_MGPIO21A_IN;
input  SPI0_SS7_MGPIO22A_IN;
input  SPI1_SCK_IN;
input  SPI1_SDI_MGPIO11A_IN;
input  SPI1_SDO_MGPIO12A_IN;
input  SPI1_SS0_MGPIO13A_IN;
input  SPI1_SS1_MGPIO14A_IN;
input  SPI1_SS2_MGPIO15A_IN;
input  SPI1_SS3_MGPIO16A_IN;
input  SPI1_SS4_MGPIO17A_IN;
input  SPI1_SS5_MGPIO18A_IN;
input  SPI1_SS6_MGPIO23A_IN;
input  SPI1_SS7_MGPIO24A_IN;
input  USBC_XCLK_IN;
input  USBD_DATA0_IN;
input  USBD_DATA1_IN;
input  USBD_DATA2_IN;
input  USBD_DATA3_IN;
input  USBD_DATA4_IN;
input  USBD_DATA5_IN;
input  USBD_DATA6_IN;
input  USBD_DATA7_MGPIO23B_IN;
input  USBD_DIR_IN;
input  USBD_NXT_IN;
input  USBD_STP_IN;
input  USBD_XCLK_IN;
output CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT;
output CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT;
output CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT;
output [15:0] DRAM_ADDR;
output [2:0] DRAM_BA;
output DRAM_CASN;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CSN;
output [2:0] DRAM_DM_RDQS_OUT;
output [17:0] DRAM_DQ_OUT;
output [2:0] DRAM_DQS_OUT;
output [1:0] DRAM_FIFO_WE_OUT;
output DRAM_ODT;
output DRAM_RASN;
output DRAM_RSTN;
output DRAM_WEN;
output I2C0_SCL_USBC_DATA1_MGPIO31B_OUT;
output I2C0_SDA_USBC_DATA0_MGPIO30B_OUT;
output I2C1_SCL_USBA_DATA4_MGPIO1A_OUT;
output I2C1_SDA_USBA_DATA3_MGPIO0A_OUT;
output MGPIO0B_OUT;
output MGPIO10B_OUT;
output MGPIO1B_OUT;
output MGPIO25A_OUT;
output MGPIO26A_OUT;
output MGPIO27A_OUT;
output MGPIO28A_OUT;
output MGPIO29A_OUT;
output MGPIO2B_OUT;
output MGPIO30A_OUT;
output MGPIO31A_OUT;
output MGPIO3B_OUT;
output MGPIO4B_OUT;
output MGPIO5B_OUT;
output MGPIO6B_OUT;
output MGPIO7B_OUT;
output MGPIO8B_OUT;
output MGPIO9B_OUT;
output MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT;
output MMUART0_DCD_MGPIO22B_OUT;
output MMUART0_DSR_MGPIO20B_OUT;
output MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT;
output MMUART0_RI_MGPIO21B_OUT;
output MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT;
output MMUART0_RXD_USBC_STP_MGPIO28B_OUT;
output MMUART0_SCK_USBC_NXT_MGPIO29B_OUT;
output MMUART0_TXD_USBC_DIR_MGPIO27B_OUT;
output MMUART1_CTS_MGPIO13B_OUT;
output MMUART1_DCD_MGPIO16B_OUT;
output MMUART1_DSR_MGPIO14B_OUT;
output MMUART1_DTR_MGPIO12B_OUT;
output MMUART1_RI_MGPIO15B_OUT;
output MMUART1_RTS_MGPIO11B_OUT;
output MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT;
output MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT;
output MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT;
output RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT;
output RGMII_MDC_RMII_MDC_OUT;
output RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT;
output RGMII_RX_CLK_OUT;
output RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT;
output RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT;
output RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT;
output RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT;
output RGMII_RXD3_USBB_DATA4_OUT;
output RGMII_TX_CLK_OUT;
output RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT;
output RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT;
output RGMII_TXD1_RMII_TXD1_USBB_STP_OUT;
output RGMII_TXD2_USBB_DATA5_OUT;
output RGMII_TXD3_USBB_DATA6_OUT;
output SPI0_SCK_USBA_XCLK_OUT;
output SPI0_SDI_USBA_DIR_MGPIO5A_OUT;
output SPI0_SDO_USBA_STP_MGPIO6A_OUT;
output SPI0_SS0_USBA_NXT_MGPIO7A_OUT;
output SPI0_SS1_USBA_DATA5_MGPIO8A_OUT;
output SPI0_SS2_USBA_DATA6_MGPIO9A_OUT;
output SPI0_SS3_USBA_DATA7_MGPIO10A_OUT;
output SPI0_SS4_MGPIO19A_OUT;
output SPI0_SS5_MGPIO20A_OUT;
output SPI0_SS6_MGPIO21A_OUT;
output SPI0_SS7_MGPIO22A_OUT;
output SPI1_SCK_OUT;
output SPI1_SDI_MGPIO11A_OUT;
output SPI1_SDO_MGPIO12A_OUT;
output SPI1_SS0_MGPIO13A_OUT;
output SPI1_SS1_MGPIO14A_OUT;
output SPI1_SS2_MGPIO15A_OUT;
output SPI1_SS3_MGPIO16A_OUT;
output SPI1_SS4_MGPIO17A_OUT;
output SPI1_SS5_MGPIO18A_OUT;
output SPI1_SS6_MGPIO23A_OUT;
output SPI1_SS7_MGPIO24A_OUT;
output USBC_XCLK_OUT;
output USBD_DATA0_OUT;
output USBD_DATA1_OUT;
output USBD_DATA2_OUT;
output USBD_DATA3_OUT;
output USBD_DATA4_OUT;
output USBD_DATA5_OUT;
output USBD_DATA6_OUT;
output USBD_DATA7_MGPIO23B_OUT;
output USBD_DIR_OUT;
output USBD_NXT_OUT;
output USBD_STP_OUT;
output USBD_XCLK_OUT;
output CAN_RXBUS_USBA_DATA1_MGPIO3A_OE;
output CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE;
output CAN_TXBUS_USBA_DATA0_MGPIO2A_OE;
output [2:0] DM_OE;
output [17:0] DRAM_DQ_OE;
output [2:0] DRAM_DQS_OE;
output I2C0_SCL_USBC_DATA1_MGPIO31B_OE;
output I2C0_SDA_USBC_DATA0_MGPIO30B_OE;
output I2C1_SCL_USBA_DATA4_MGPIO1A_OE;
output I2C1_SDA_USBA_DATA3_MGPIO0A_OE;
output MGPIO0B_OE;
output MGPIO10B_OE;
output MGPIO1B_OE;
output MGPIO25A_OE;
output MGPIO26A_OE;
output MGPIO27A_OE;
output MGPIO28A_OE;
output MGPIO29A_OE;
output MGPIO2B_OE;
output MGPIO30A_OE;
output MGPIO31A_OE;
output MGPIO3B_OE;
output MGPIO4B_OE;
output MGPIO5B_OE;
output MGPIO6B_OE;
output MGPIO7B_OE;
output MGPIO8B_OE;
output MGPIO9B_OE;
output MMUART0_CTS_USBC_DATA7_MGPIO19B_OE;
output MMUART0_DCD_MGPIO22B_OE;
output MMUART0_DSR_MGPIO20B_OE;
output MMUART0_DTR_USBC_DATA6_MGPIO18B_OE;
output MMUART0_RI_MGPIO21B_OE;
output MMUART0_RTS_USBC_DATA5_MGPIO17B_OE;
output MMUART0_RXD_USBC_STP_MGPIO28B_OE;
output MMUART0_SCK_USBC_NXT_MGPIO29B_OE;
output MMUART0_TXD_USBC_DIR_MGPIO27B_OE;
output MMUART1_CTS_MGPIO13B_OE;
output MMUART1_DCD_MGPIO16B_OE;
output MMUART1_DSR_MGPIO14B_OE;
output MMUART1_DTR_MGPIO12B_OE;
output MMUART1_RI_MGPIO15B_OE;
output MMUART1_RTS_MGPIO11B_OE;
output MMUART1_RXD_USBC_DATA3_MGPIO26B_OE;
output MMUART1_SCK_USBC_DATA4_MGPIO25B_OE;
output MMUART1_TXD_USBC_DATA2_MGPIO24B_OE;
output RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE;
output RGMII_MDC_RMII_MDC_OE;
output RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE;
output RGMII_RX_CLK_OE;
output RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE;
output RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE;
output RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE;
output RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE;
output RGMII_RXD3_USBB_DATA4_OE;
output RGMII_TX_CLK_OE;
output RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE;
output RGMII_TXD0_RMII_TXD0_USBB_DIR_OE;
output RGMII_TXD1_RMII_TXD1_USBB_STP_OE;
output RGMII_TXD2_USBB_DATA5_OE;
output RGMII_TXD3_USBB_DATA6_OE;
output SPI0_SCK_USBA_XCLK_OE;
output SPI0_SDI_USBA_DIR_MGPIO5A_OE;
output SPI0_SDO_USBA_STP_MGPIO6A_OE;
output SPI0_SS0_USBA_NXT_MGPIO7A_OE;
output SPI0_SS1_USBA_DATA5_MGPIO8A_OE;
output SPI0_SS2_USBA_DATA6_MGPIO9A_OE;
output SPI0_SS3_USBA_DATA7_MGPIO10A_OE;
output SPI0_SS4_MGPIO19A_OE;
output SPI0_SS5_MGPIO20A_OE;
output SPI0_SS6_MGPIO21A_OE;
output SPI0_SS7_MGPIO22A_OE;
output SPI1_SCK_OE;
output SPI1_SDI_MGPIO11A_OE;
output SPI1_SDO_MGPIO12A_OE;
output SPI1_SS0_MGPIO13A_OE;
output SPI1_SS1_MGPIO14A_OE;
output SPI1_SS2_MGPIO15A_OE;
output SPI1_SS3_MGPIO16A_OE;
output SPI1_SS4_MGPIO17A_OE;
output SPI1_SS5_MGPIO18A_OE;
output SPI1_SS6_MGPIO23A_OE;
output SPI1_SS7_MGPIO24A_OE;
output USBC_XCLK_OE;
output USBD_DATA0_OE;
output USBD_DATA1_OE;
output USBD_DATA2_OE;
output USBD_DATA3_OE;
output USBD_DATA4_OE;
output USBD_DATA5_OE;
output USBD_DATA6_OE;
output USBD_DATA7_MGPIO23B_OE;
output USBD_DIR_OE;
output USBD_NXT_OE;
output USBD_STP_OE;
output USBD_XCLK_OE;

    parameter INIT = 'h0 ;
    parameter ACT_UBITS = 'hFFFFFFFFFFFFFF ;
    parameter MEMORYFILE = "" ;
    parameter RTC_MAIN_XTL_FREQ = 0.0 ;
    parameter RTC_MAIN_XTL_MODE = "1" ;
    parameter DDR_CLK_FREQ = 0.0 ;
    
endmodule


module RCOSC_25_50MHZ(
       CLKOUT
    );
output CLKOUT;

    parameter FREQUENCY = 50.0 ;
    
endmodule


module MDDR_Config_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_Z8(
       HW_Boot_Engine_0_APB_IF_PWDATA,
       HW_Boot_Engine_0_APB_IF_PADDR_0,
       HW_Boot_Engine_0_APB_IF_PADDR_1,
       HW_Boot_Engine_0_APB_IF_PADDR_2,
       HW_Boot_Engine_0_APB_IF_PADDR_3,
       HW_Boot_Engine_0_APB_IF_PADDR_4,
       HW_Boot_Engine_0_APB_IF_PADDR_5,
       HW_Boot_Engine_0_APB_IF_PADDR_6,
       HW_Boot_Engine_0_APB_IF_PADDR_7,
       HW_Boot_Engine_0_APB_IF_PADDR_8,
       HW_Boot_Engine_0_APB_IF_PADDR_10,
       HW_Boot_Engine_0_APB_IF_PADDR_11,
       HW_Boot_Engine_0_APB_IF_PADDR_13,
       MDDR_Config_0_DRAM_Ready,
       MSS_HPMS_READY,
       CORECONFIGP_0_APB_S_PCLK,
       HW_Boot_Engine_0_APB_IF_PWRITE,
       HW_Boot_Engine_0_APB_IF_PENABLE,
       HW_Boot_Engine_0_APB_IF_PSELx,
       HW_Boot_Engine_0_APB_IF_PREADY
    );
output [15:0] HW_Boot_Engine_0_APB_IF_PWDATA;
output HW_Boot_Engine_0_APB_IF_PADDR_0;
output HW_Boot_Engine_0_APB_IF_PADDR_1;
output HW_Boot_Engine_0_APB_IF_PADDR_2;
output HW_Boot_Engine_0_APB_IF_PADDR_3;
output HW_Boot_Engine_0_APB_IF_PADDR_4;
output HW_Boot_Engine_0_APB_IF_PADDR_5;
output HW_Boot_Engine_0_APB_IF_PADDR_6;
output HW_Boot_Engine_0_APB_IF_PADDR_7;
output HW_Boot_Engine_0_APB_IF_PADDR_8;
output HW_Boot_Engine_0_APB_IF_PADDR_10;
output HW_Boot_Engine_0_APB_IF_PADDR_11;
output HW_Boot_Engine_0_APB_IF_PADDR_13;
output MDDR_Config_0_DRAM_Ready;
input  MSS_HPMS_READY;
input  CORECONFIGP_0_APB_S_PCLK;
output HW_Boot_Engine_0_APB_IF_PWRITE;
output HW_Boot_Engine_0_APB_IF_PENABLE;
output HW_Boot_Engine_0_APB_IF_PSELx;
input  HW_Boot_Engine_0_APB_IF_PREADY;

    wire \apb_fsm_current_state[5]_net_1 , \i[0]_net_1 , \i_s[0] , 
        VCC_net_1, \PWDATA_5[11] , N_463_i_0, GND_net_1, N_256_mux, 
        \PWDATA_5[13] , \PWDATA_5[14] , \PWDATA_5[15] , PWDATA_5_0, 
        \PWDATA_5[1] , \PWDATA_5[2] , \PWDATA_5[3] , \PWDATA_5[4] , 
        \PWDATA_5[5] , \PWDATA_5[6] , \PWDATA_5[7] , \PWDATA_5[8] , 
        \PWDATA_5[9] , \PWDATA_5[10] , 
        \apb_fsm_current_state[0]_net_1 , N_263_mux, N_744_i_0, 
        un1_DRAM_Ready_1_sqmuxa_i_0, \apb_fsm_current_state[1]_net_1 , 
        N_266_mux_i_0, \apb_fsm_current_state[2]_net_1 , i_0_sqmuxa, 
        \apb_fsm_current_state[3]_net_1 , N_443_i_0, 
        \apb_fsm_current_state[4]_net_1 , N_43_i_0, 
        DRAM_Ready_0_sqmuxa, \apb_fsm_current_state[6]_net_1 , 
        N_447_i_0, \PADDR_int_lm[2] , N_382_i_0, \PADDR_int_lm[3] , 
        \PADDR_int_lm[4] , \PADDR_int_lm[5] , \PADDR_int_lm[6] , 
        \PADDR_int_lm[7] , \PADDR_int_lm[8] , \PADDR_int_lm[9] , 
        \PADDR_int_lm[10] , \HW_Boot_Engine_0_APB_IF_PADDR[11] , 
        \PADDR_int_lm[11] , \PADDR_int_lm[12] , \PADDR_int_lm[13] , 
        \HW_Boot_Engine_0_APB_IF_PADDR[14] , \PADDR_int_lm[14] , 
        \PADDR_int_lm[15] , \count_delay[0]_net_1 , \count_delay_s[0] , 
        \count_delay[1]_net_1 , \count_delay_s[1] , 
        \count_delay[2]_net_1 , \count_delay_s[2] , 
        \count_delay[3]_net_1 , \count_delay_s[3] , 
        \count_delay[4]_net_1 , \count_delay_s[4] , 
        \count_delay[5]_net_1 , \count_delay_s[5] , 
        \count_delay[6]_net_1 , \count_delay_s[6] , 
        \count_delay[7]_net_1 , \count_delay_s[7] , 
        \count_delay[8]_net_1 , \count_delay_s[8] , 
        \count_delay[9]_net_1 , \count_delay_s[9] , 
        \count_delay[10]_net_1 , \count_delay_s[10] , 
        \count_delay[11]_net_1 , \count_delay_s[11]_net_1 , 
        N_251_mux_i_0, \i[1]_net_1 , \i_s[1] , \i[2]_net_1 , \i_s[2] , 
        \i[3]_net_1 , \i_s[3] , \i[4]_net_1 , \i_s[4] , \i[5]_net_1 , 
        \i_s[5] , \i[6]_net_1 , \i_s[6]_net_1 , count_delay_cry_cy, 
        N_233_mux, \count_delay_cry[0]_net_1 , 
        \count_delay_cry[1]_net_1 , \count_delay_cry[2]_net_1 , 
        \count_delay_cry[3]_net_1 , \count_delay_cry[4]_net_1 , 
        \count_delay_cry[5]_net_1 , \count_delay_cry[6]_net_1 , 
        \count_delay_cry[7]_net_1 , \count_delay_cry[8]_net_1 , 
        \count_delay_cry[9]_net_1 , \count_delay_cry[10]_net_1 , 
        i_s_306_FCO, \i_cry[1]_net_1 , \i_cry[2]_net_1 , 
        \i_cry[3]_net_1 , \i_cry[4]_net_1 , \i_cry[5]_net_1 , 
        PADDR_int_s_307_FCO, \PADDR_int_cry[3]_net_1 , 
        \PADDR_int_s[3] , \PADDR_int_cry[4]_net_1 , \PADDR_int_s[4] , 
        \PADDR_int_cry[5]_net_1 , \PADDR_int_s[5] , 
        \PADDR_int_cry[6]_net_1 , \PADDR_int_s[6] , 
        \PADDR_int_cry[7]_net_1 , \PADDR_int_s[7] , 
        \PADDR_int_cry[8]_net_1 , \PADDR_int_s[8] , 
        \PADDR_int_cry[9]_net_1 , \PADDR_int_s[9] , 
        \PADDR_int_cry[10]_net_1 , \PADDR_int_s[10] , 
        \PADDR_int_cry[11]_net_1 , \PADDR_int_s[11] , 
        \PADDR_int_cry[12]_net_1 , \PADDR_int_s[12] , 
        \PADDR_int_cry[13]_net_1 , \PADDR_int_s[13] , 
        \PADDR_int_s[15]_net_1 , \PADDR_int_cry[14]_net_1 , 
        \PADDR_int_s[14] , N_64_i, N_477, N_15_1, m187_am_1_1, 
        m187_am_1, m183_1, m78_2, \PWDATA_RNO_0[1]_net_1 , 
        \PWDATA_RNO_1[4]_net_1 , m193_1, \PWDATA_RNO_3[4]_net_1 , 
        N_194, N_192, N_494, m78_1_0, m78_1, N_473, N_465, N_69_0, 
        N_481, m123_ns_1, N_498, N_67_0, m141_ns_1, N_513, m148_ns_1, 
        N_8_0, N_519, N_468, m128_ns_1, N_501, m163_ns_1, N_529, N_530, 
        m213_ns_1, N_214, N_198, m199_ns_1, N_200, N_68_0, m104_ns_1, 
        \PWDATA_RNO_1[10]_net_1 , \PWDATA_RNO_2[10]_net_1 , 
        \PWDATA_RNO_3[10]_net_1 , \PWDATA_RNO_4[10]_net_1 , 
        \PWDATA_RNO_1[1]_net_1 , \PWDATA_RNO_2[6]_net_1 , 
        \PWDATA_RNO_3[6]_net_1 , N_207, \PWDATA_RNO_3[3]_net_1 , 
        \PWDATA_RNO_4[3]_net_1 , N_511, \PWDATA_RNO_4[0]_net_1 , 
        \PWDATA_RNO_5[0]_net_1 , N_479, \PWDATA_RNO_2[9]_net_1 , 
        \PWDATA_RNO_3[9]_net_1 , N_526, m173_0, N_35_0, N_254, m32_5, 
        un58lt11, N_228, N_470, N_81_i, N_505, N_460, N_515, m32_7, 
        N_476, N_185, N_480, N_531, i15_mux, N_492, N_471, N_264_mux, 
        N_504, N_509, N_171, N_528, N_221, i15_mux_1, N_216, N_205, 
        N_182, N_469, N_250_mux, i14_mux_3, N_517, N_522, N_217, N_490, 
        N_533;
    
    CFG3 #( .INIT(8'h20) )  \PWDATA_RNO_3[0]  (.A(\i[3]_net_1 ), .B(
        \i[5]_net_1 ), .C(N_469), .Y(m78_1));
    CFG4 #( .INIT(16'hD580) )  \PWDATA_RNO[5]  (.A(\i[6]_net_1 ), .B(
        \i[3]_net_1 ), .C(N_528), .D(N_200), .Y(\PWDATA_5[5] ));
    CFG2 #( .INIT(4'h1) )  \i_RNIVLGT_2[1]  (.A(\i[2]_net_1 ), .B(
        \i[1]_net_1 ), .Y(N_8_0));
    CFG4 #( .INIT(16'h4454) )  \PWDATA_RNO_2[3]  (.A(\i[0]_net_1 ), .B(
        \i[4]_net_1 ), .C(\i[1]_net_1 ), .D(\i[2]_net_1 ), .Y(
        m141_ns_1));
    CFG3 #( .INIT(8'hE2) )  \PWDATA_RNO[4]  (.A(N_194), .B(
        \i[6]_net_1 ), .C(N_533), .Y(\PWDATA_5[4] ));
    CFG2 #( .INIT(4'hD) )  \PADDR_int_lm_0[11]  (.A(N_15_1), .B(
        \PADDR_int_s[11] ), .Y(\PADDR_int_lm[11] ));
    CFG4 #( .INIT(16'h03C1) )  \PWDATA_RNO_2[2]  (.A(\i[1]_net_1 ), .B(
        \i[5]_net_1 ), .C(\i[0]_net_1 ), .D(\i[4]_net_1 ), .Y(
        m128_ns_1));
    ARI1 #( .INIT(20'h4AA00) )  \PADDR_int_s[15]  (.A(VCC_net_1), .B(
        HW_Boot_Engine_0_APB_IF_PADDR_13), .C(GND_net_1), .D(GND_net_1)
        , .FCI(\PADDR_int_cry[14]_net_1 ), .S(\PADDR_int_s[15]_net_1 ), 
        .Y(), .FCO());
    ARI1 #( .INIT(20'h42A00) )  \count_delay_cry[5]  (.A(VCC_net_1), 
        .B(\count_delay[5]_net_1 ), .C(N_233_mux), .D(
        \apb_fsm_current_state[3]_net_1 ), .FCI(
        \count_delay_cry[4]_net_1 ), .S(\count_delay_s[5] ), .Y(), 
        .FCO(\count_delay_cry[5]_net_1 ));
    CFG4 #( .INIT(16'hFAFB) )  \PWDATA_RNO_0[1]  (.A(m183_1), .B(
        \i[3]_net_1 ), .C(m78_2), .D(m187_am_1), .Y(
        \PWDATA_RNO_0[1]_net_1 ));
    SLE \count_delay[4]  (.D(\count_delay_s[4] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_43_i_0), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\count_delay[4]_net_1 ));
    CFG3 #( .INIT(8'h60) )  \i_RNIVC1R1[0]  (.A(\i[0]_net_1 ), .B(
        \i[4]_net_1 ), .C(N_8_0), .Y(N_531));
    SLE \i[0]  (.D(\i_s[0] ), .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(
        N_251_mux_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(\i[0]_net_1 ));
    CFG3 #( .INIT(8'hB8) )  \PADDR_int_lm_0[7]  (.A(\PADDR_int_s[7] ), 
        .B(N_15_1), .C(\apb_fsm_current_state[3]_net_1 ), .Y(
        \PADDR_int_lm[7] ));
    ARI1 #( .INIT(20'h42A00) )  \count_delay_cry[7]  (.A(VCC_net_1), 
        .B(\count_delay[7]_net_1 ), .C(N_233_mux), .D(
        \apb_fsm_current_state[3]_net_1 ), .FCI(
        \count_delay_cry[6]_net_1 ), .S(\count_delay_s[7] ), .Y(), 
        .FCO(\count_delay_cry[7]_net_1 ));
    CFG3 #( .INIT(8'hE4) )  \PWDATA_RNO_7[0]  (.A(\i[4]_net_1 ), .B(
        N_465), .C(N_468), .Y(N_469));
    CFG3 #( .INIT(8'h90) )  \PWDATA_RNO_0[11]  (.A(\i[0]_net_1 ), .B(
        \i[4]_net_1 ), .C(N_468), .Y(N_492));
    CFG4 #( .INIT(16'h2F2C) )  \PWDATA_RNO_0[4]  (.A(
        \PWDATA_RNO_1[4]_net_1 ), .B(\i[3]_net_1 ), .C(m193_1), .D(
        \PWDATA_RNO_3[4]_net_1 ), .Y(N_194));
    SLE \PADDR_int[3]  (.D(\PADDR_int_lm[3] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_382_i_0), .ALn(MSS_HPMS_READY)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(HW_Boot_Engine_0_APB_IF_PADDR_1));
    CFG4 #( .INIT(16'hA2F2) )  \apb_fsm_current_state_RNO[6]  (.A(
        \apb_fsm_current_state[6]_net_1 ), .B(
        HW_Boot_Engine_0_APB_IF_PREADY), .C(
        \apb_fsm_current_state[3]_net_1 ), .D(N_233_mux), .Y(N_447_i_0)
        );
    CFG4 #( .INIT(16'h8000) )  \count_delay_RNILAVA1[10]  (.A(
        \count_delay[10]_net_1 ), .B(\count_delay[8]_net_1 ), .C(
        \count_delay[7]_net_1 ), .D(\count_delay[5]_net_1 ), .Y(m32_5));
    CFG4 #( .INIT(16'h40B2) )  \PWDATA_RNO_0[12]  (.A(\i[0]_net_1 ), 
        .B(\i[4]_net_1 ), .C(\i[1]_net_1 ), .D(\i[2]_net_1 ), .Y(N_171)
        );
    ARI1 #( .INIT(20'h42A00) )  \count_delay_cry[2]  (.A(VCC_net_1), 
        .B(\count_delay[2]_net_1 ), .C(N_233_mux), .D(
        \apb_fsm_current_state[3]_net_1 ), .FCI(
        \count_delay_cry[1]_net_1 ), .S(\count_delay_s[2] ), .Y(), 
        .FCO(\count_delay_cry[2]_net_1 ));
    CLKINT \apb_fsm_current_state_RNI41G[5]  (.A(
        \apb_fsm_current_state[5]_net_1 ), .Y(MDDR_Config_0_DRAM_Ready)
        );
    CFG3 #( .INIT(8'hFE) )  \apb_fsm_current_state_RNI2PF1[2]  (.A(
        \apb_fsm_current_state[0]_net_1 ), .B(
        \apb_fsm_current_state[3]_net_1 ), .C(
        \apb_fsm_current_state[2]_net_1 ), .Y(N_382_i_0));
    CFG3 #( .INIT(8'hB8) )  \PWDATA_RNO_4[3]  (.A(N_494), .B(
        \i[5]_net_1 ), .C(N_509), .Y(\PWDATA_RNO_4[3]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \PADDR_int_cry[3]  (.A(VCC_net_1), .B(
        HW_Boot_Engine_0_APB_IF_PADDR_1), .C(GND_net_1), .D(GND_net_1), 
        .FCI(PADDR_int_s_307_FCO), .S(\PADDR_int_s[3] ), .Y(), .FCO(
        \PADDR_int_cry[3]_net_1 ));
    CFG4 #( .INIT(16'h3222) )  \PWDATA_RNO_3[5]  (.A(\i[3]_net_1 ), .B(
        \i[5]_net_1 ), .C(\i[4]_net_1 ), .D(N_68_0), .Y(m199_ns_1));
    CFG3 #( .INIT(8'hFE) )  PENABLE_RNO (.A(
        \apb_fsm_current_state[4]_net_1 ), .B(
        \apb_fsm_current_state[1]_net_1 ), .C(
        \apb_fsm_current_state[6]_net_1 ), .Y(N_744_i_0));
    SLE \PWDATA[8]  (.D(\PWDATA_5[8] ), .CLK(CORECONFIGP_0_APB_S_PCLK), 
        .EN(N_463_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_APB_IF_PWDATA[8]));
    CFG4 #( .INIT(16'h5140) )  \PWDATA_RNO[9]  (.A(\i[6]_net_1 ), .B(
        \i[3]_net_1 ), .C(N_526), .D(N_522), .Y(\PWDATA_5[9] ));
    CFG4 #( .INIT(16'h5140) )  \PWDATA_RNO[8]  (.A(\i[6]_net_1 ), .B(
        \i[3]_net_1 ), .C(N_217), .D(N_214), .Y(\PWDATA_5[8] ));
    ARI1 #( .INIT(20'h4AA00) )  \PADDR_int_cry[12]  (.A(VCC_net_1), .B(
        HW_Boot_Engine_0_APB_IF_PADDR_10), .C(GND_net_1), .D(GND_net_1)
        , .FCI(\PADDR_int_cry[11]_net_1 ), .S(\PADDR_int_s[12] ), .Y(), 
        .FCO(\PADDR_int_cry[12]_net_1 ));
    CFG3 #( .INIT(8'hE2) )  \PWDATA_RNO_1[6]  (.A(
        \PWDATA_RNO_2[6]_net_1 ), .B(\i[3]_net_1 ), .C(
        \PWDATA_RNO_3[6]_net_1 ), .Y(N_207));
    SLE \PADDR_int[14]  (.D(\PADDR_int_lm[14] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_382_i_0), .ALn(MSS_HPMS_READY)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\HW_Boot_Engine_0_APB_IF_PADDR[14] ));
    CFG4 #( .INIT(16'h2301) )  \PWDATA_RNO_1[7]  (.A(\i[5]_net_1 ), .B(
        \i[4]_net_1 ), .C(N_515), .D(N_81_i), .Y(N_517));
    CFG4 #( .INIT(16'h0950) )  \PWDATA_RNO_5[10]  (.A(\i[5]_net_1 ), 
        .B(\i[0]_net_1 ), .C(\i[1]_net_1 ), .D(\i[2]_net_1 ), .Y(
        i15_mux_1));
    CFG2 #( .INIT(4'h2) )  \PWDATA_RNO_4[6]  (.A(N_67_0), .B(
        \i[0]_net_1 ), .Y(N_470));
    CFG4 #( .INIT(16'hA5FB) )  \PWDATA_RNO_3[1]  (.A(\i[1]_net_1 ), .B(
        \i[2]_net_1 ), .C(\i[4]_net_1 ), .D(m187_am_1_1), .Y(m187_am_1)
        );
    ARI1 #( .INIT(20'h42A00) )  \count_delay_cry[0]  (.A(VCC_net_1), 
        .B(\count_delay[0]_net_1 ), .C(N_233_mux), .D(
        \apb_fsm_current_state[3]_net_1 ), .FCI(count_delay_cry_cy), 
        .S(\count_delay_s[0] ), .Y(), .FCO(\count_delay_cry[0]_net_1 ));
    SLE \count_delay[0]  (.D(\count_delay_s[0] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_43_i_0), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\count_delay[0]_net_1 ));
    CFG4 #( .INIT(16'h2034) )  \PWDATA_RNO_5[3]  (.A(\i[0]_net_1 ), .B(
        \i[4]_net_1 ), .C(\i[1]_net_1 ), .D(\i[2]_net_1 ), .Y(N_504));
    CFG3 #( .INIT(8'h10) )  \PWDATA_RNO_3[9]  (.A(\i[0]_net_1 ), .B(
        \i[4]_net_1 ), .C(N_67_0), .Y(\PWDATA_RNO_3[9]_net_1 ));
    CFG3 #( .INIT(8'hE4) )  \PWDATA_RNO_3[6]  (.A(\i[5]_net_1 ), .B(
        N_205), .C(N_494), .Y(\PWDATA_RNO_3[6]_net_1 ));
    GND GND (.Y(GND_net_1));
    SLE \count_delay[9]  (.D(\count_delay_s[9] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_43_i_0), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\count_delay[9]_net_1 ));
    SLE \PWDATA[10]  (.D(\PWDATA_5[10] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_463_i_0), .ALn(MSS_HPMS_READY)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(HW_Boot_Engine_0_APB_IF_PWDATA[10]));
    CFG4 #( .INIT(16'h4073) )  \PWDATA_RNO_1[2]  (.A(\i[4]_net_1 ), .B(
        \i[5]_net_1 ), .C(N_481), .D(m123_ns_1), .Y(N_498));
    SLE \PADDR_int[10]  (.D(\PADDR_int_lm[10] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_382_i_0), .ALn(MSS_HPMS_READY)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(HW_Boot_Engine_0_APB_IF_PADDR_8));
    CFG3 #( .INIT(8'h1D) )  PWRITE_RNO_0 (.A(
        \apb_fsm_current_state[0]_net_1 ), .B(
        \apb_fsm_current_state[3]_net_1 ), .C(N_233_mux), .Y(N_490));
    CFG1 #( .INIT(2'h1) )  \i_RNO[0]  (.A(\i[0]_net_1 ), .Y(\i_s[0] ));
    CFG4 #( .INIT(16'h0001) )  PWRITE_RNO (.A(
        \apb_fsm_current_state[4]_net_1 ), .B(N_490), .C(
        MDDR_Config_0_DRAM_Ready), .D(\apb_fsm_current_state[6]_net_1 )
        , .Y(N_263_mux));
    SLE \PWDATA[4]  (.D(\PWDATA_5[4] ), .CLK(CORECONFIGP_0_APB_S_PCLK), 
        .EN(N_463_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_APB_IF_PWDATA[4]));
    SLE \PADDR_int[7]  (.D(\PADDR_int_lm[7] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_382_i_0), .ALn(MSS_HPMS_READY)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(HW_Boot_Engine_0_APB_IF_PADDR_5));
    CFG3 #( .INIT(8'h5E) )  \i_RNIDV8C1[1]  (.A(\i[2]_net_1 ), .B(
        \i[0]_net_1 ), .C(\i[1]_net_1 ), .Y(N_465));
    SLE \PADDR_int[4]  (.D(\PADDR_int_lm[4] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_382_i_0), .ALn(MSS_HPMS_READY)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(HW_Boot_Engine_0_APB_IF_PADDR_2));
    CFG4 #( .INIT(16'h5140) )  \PWDATA_RNO[7]  (.A(\i[6]_net_1 ), .B(
        \i[3]_net_1 ), .C(N_519), .D(N_517), .Y(\PWDATA_5[7] ));
    SLE \PWDATA[7]  (.D(\PWDATA_5[7] ), .CLK(CORECONFIGP_0_APB_S_PCLK), 
        .EN(N_463_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_APB_IF_PWDATA[7]));
    ARI1 #( .INIT(20'h4AA00) )  \PADDR_int_cry[7]  (.A(VCC_net_1), .B(
        HW_Boot_Engine_0_APB_IF_PADDR_5), .C(GND_net_1), .D(GND_net_1), 
        .FCI(\PADDR_int_cry[6]_net_1 ), .S(\PADDR_int_s[7] ), .Y(), 
        .FCO(\PADDR_int_cry[7]_net_1 ));
    SLE \PWDATA[0]  (.D(PWDATA_5_0), .CLK(CORECONFIGP_0_APB_S_PCLK), 
        .EN(N_463_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_APB_IF_PWDATA[0]));
    ARI1 #( .INIT(20'h4AA00) )  \PADDR_int_cry[4]  (.A(VCC_net_1), .B(
        HW_Boot_Engine_0_APB_IF_PADDR_2), .C(GND_net_1), .D(GND_net_1), 
        .FCI(\PADDR_int_cry[3]_net_1 ), .S(\PADDR_int_s[4] ), .Y(), 
        .FCO(\PADDR_int_cry[4]_net_1 ));
    CFG3 #( .INIT(8'h1B) )  \PWDATA_RNO_8[0]  (.A(\i[0]_net_1 ), .B(
        N_468), .C(\i[5]_net_1 ), .Y(i15_mux));
    SLE \PWDATA[13]  (.D(\PWDATA_5[13] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_463_i_0), .ALn(MSS_HPMS_READY)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(HW_Boot_Engine_0_APB_IF_PWDATA[13]));
    CFG4 #( .INIT(16'hFFF4) )  \PWDATA_RNO_0[0]  (.A(\i[3]_net_1 ), .B(
        m78_1_0), .C(m78_1), .D(m78_2), .Y(N_473));
    CFG4 #( .INIT(16'h0062) )  \PWDATA_RNO_1[14]  (.A(\i[3]_net_1 ), 
        .B(\i[5]_net_1 ), .C(\i[0]_net_1 ), .D(\i[4]_net_1 ), .Y(
        m163_ns_1));
    CFG4 #( .INIT(16'h5140) )  \PWDATA_RNO[2]  (.A(\i[6]_net_1 ), .B(
        \i[3]_net_1 ), .C(N_501), .D(N_498), .Y(\PWDATA_5[2] ));
    CFG4 #( .INIT(16'h01F2) )  \PWDATA_RNO_5[1]  (.A(\i[0]_net_1 ), .B(
        \i[4]_net_1 ), .C(\i[1]_net_1 ), .D(\i[2]_net_1 ), .Y(N_182));
    SLE \PADDR_int[12]  (.D(\PADDR_int_lm[12] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_382_i_0), .ALn(MSS_HPMS_READY)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(HW_Boot_Engine_0_APB_IF_PADDR_10));
    ARI1 #( .INIT(20'h4AA00) )  \PADDR_int_cry[11]  (.A(VCC_net_1), .B(
        \HW_Boot_Engine_0_APB_IF_PADDR[11] ), .C(GND_net_1), .D(
        GND_net_1), .FCI(\PADDR_int_cry[10]_net_1 ), .S(
        \PADDR_int_s[11] ), .Y(), .FCO(\PADDR_int_cry[11]_net_1 ));
    CFG4 #( .INIT(16'h7520) )  \PWDATA_RNO[6]  (.A(\i[6]_net_1 ), .B(
        \i[3]_net_1 ), .C(i14_mux_3), .D(N_207), .Y(\PWDATA_5[6] ));
    CFG4 #( .INIT(16'hA820) )  \PWDATA_RNO[11]  (.A(N_254), .B(
        \i[3]_net_1 ), .C(N_477), .D(N_492), .Y(\PWDATA_5[11] ));
    CFG4 #( .INIT(16'h8000) )  \i_RNIAO1R1[6]  (.A(\i[5]_net_1 ), .B(
        \i[4]_net_1 ), .C(\i[6]_net_1 ), .D(\i[3]_net_1 ), .Y(
        N_233_mux));
    CFG4 #( .INIT(16'hC480) )  \PWDATA_RNO[13]  (.A(\i[3]_net_1 ), .B(
        N_254), .C(N_221), .D(N_480), .Y(\PWDATA_5[13] ));
    SLE PSEL (.D(VCC_net_1), .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(
        \apb_fsm_current_state[0]_net_1 ), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_APB_IF_PSELx));
    CFG2 #( .INIT(4'hE) )  \apb_fsm_current_state_RNI39S35[0]  (.A(
        N_15_1), .B(\apb_fsm_current_state[0]_net_1 ), .Y(N_463_i_0));
    CFG3 #( .INIT(8'hE2) )  \PWDATA_RNO_1[0]  (.A(
        \PWDATA_RNO_4[0]_net_1 ), .B(\i[3]_net_1 ), .C(
        \PWDATA_RNO_5[0]_net_1 ), .Y(N_479));
    SLE \PADDR_int[13]  (.D(\PADDR_int_lm[13] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_382_i_0), .ALn(MSS_HPMS_READY)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(HW_Boot_Engine_0_APB_IF_PADDR_11));
    CFG3 #( .INIT(8'h10) )  \i_RNIVC1R1_1[0]  (.A(\i[0]_net_1 ), .B(
        \i[4]_net_1 ), .C(N_468), .Y(N_480));
    CFG4 #( .INIT(16'h5132) )  \PWDATA_RNO_2[9]  (.A(\i[0]_net_1 ), .B(
        \i[4]_net_1 ), .C(\i[1]_net_1 ), .D(\i[2]_net_1 ), .Y(
        \PWDATA_RNO_2[9]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \PWDATA_RNO_0[5]  (.A(N_477), .B(
        \i[5]_net_1 ), .Y(N_528));
    CFG4 #( .INIT(16'h7520) )  \PWDATA_RNO[3]  (.A(\i[6]_net_1 ), .B(
        \i[3]_net_1 ), .C(N_513), .D(N_511), .Y(\PWDATA_5[3] ));
    SLE \count_delay[3]  (.D(\count_delay_s[3] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_43_i_0), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\count_delay[3]_net_1 ));
    SLE \apb_fsm_current_state[2]  (.D(i_0_sqmuxa), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(VCC_net_1), .ALn(MSS_HPMS_READY)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\apb_fsm_current_state[2]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \PADDR_int_lm_0[4]  (.A(N_15_1), .B(
        \PADDR_int_s[4] ), .Y(\PADDR_int_lm[4] ));
    CFG2 #( .INIT(4'h8) )  \PWDATA_RNO_4[1]  (.A(N_481), .B(
        \i[4]_net_1 ), .Y(N_185));
    ARI1 #( .INIT(20'h4AA00) )  \PADDR_int_cry[14]  (.A(VCC_net_1), .B(
        \HW_Boot_Engine_0_APB_IF_PADDR[14] ), .C(GND_net_1), .D(
        GND_net_1), .FCI(\PADDR_int_cry[13]_net_1 ), .S(
        \PADDR_int_s[14] ), .Y(), .FCO(\PADDR_int_cry[14]_net_1 ));
    VCC VCC (.Y(VCC_net_1));
    CFG2 #( .INIT(4'h8) )  \PADDR_int_lm_0[3]  (.A(N_15_1), .B(
        \PADDR_int_s[3] ), .Y(\PADDR_int_lm[3] ));
    SLE \count_delay[11]  (.D(\count_delay_s[11]_net_1 ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_43_i_0), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\count_delay[11]_net_1 ));
    CFG4 #( .INIT(16'h1810) )  \PWDATA_RNO_0[7]  (.A(\i[4]_net_1 ), .B(
        \i[0]_net_1 ), .C(m148_ns_1), .D(N_8_0), .Y(N_519));
    CFG2 #( .INIT(4'h8) )  \PADDR_int_lm_0[14]  (.A(N_15_1), .B(
        \PADDR_int_s[14] ), .Y(\PADDR_int_lm[14] ));
    ARI1 #( .INIT(20'h42A00) )  \count_delay_s[11]  (.A(VCC_net_1), .B(
        \count_delay[11]_net_1 ), .C(N_233_mux), .D(
        \apb_fsm_current_state[3]_net_1 ), .FCI(
        \count_delay_cry[10]_net_1 ), .S(\count_delay_s[11]_net_1 ), 
        .Y(), .FCO());
    CFG4 #( .INIT(16'h3538) )  \PWDATA_RNO_6[1]  (.A(\i[2]_net_1 ), .B(
        \i[5]_net_1 ), .C(\i[0]_net_1 ), .D(\i[4]_net_1 ), .Y(
        m187_am_1_1));
    SLE \PADDR_int[6]  (.D(\PADDR_int_lm[6] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_382_i_0), .ALn(MSS_HPMS_READY)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(HW_Boot_Engine_0_APB_IF_PADDR_4));
    CFG3 #( .INIT(8'h80) )  \i_RNIM89C1[3]  (.A(\i[4]_net_1 ), .B(
        \i[3]_net_1 ), .C(\i[5]_net_1 ), .Y(N_228));
    CFG4 #( .INIT(16'h0138) )  \PWDATA_RNO_5[6]  (.A(\i[0]_net_1 ), .B(
        \i[4]_net_1 ), .C(\i[1]_net_1 ), .D(\i[2]_net_1 ), .Y(N_205));
    CFG2 #( .INIT(4'h4) )  \apb_fsm_current_state_RNO_0[1]  (.A(
        HW_Boot_Engine_0_APB_IF_PREADY), .B(
        \apb_fsm_current_state[1]_net_1 ), .Y(N_35_0));
    ARI1 #( .INIT(20'h4AA00) )  \PADDR_int_cry[6]  (.A(VCC_net_1), .B(
        HW_Boot_Engine_0_APB_IF_PADDR_4), .C(GND_net_1), .D(GND_net_1), 
        .FCI(\PADDR_int_cry[5]_net_1 ), .S(\PADDR_int_s[6] ), .Y(), 
        .FCO(\PADDR_int_cry[6]_net_1 ));
    CFG3 #( .INIT(8'hE2) )  \PWDATA_RNO[0]  (.A(N_473), .B(
        \i[6]_net_1 ), .C(N_479), .Y(PWDATA_5_0));
    SLE PENABLE (.D(N_744_i_0), .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(
        un1_DRAM_Ready_1_sqmuxa_i_0), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_APB_IF_PENABLE));
    CFG4 #( .INIT(16'h5D58) )  \PWDATA_RNO[10]  (.A(m104_ns_1), .B(
        \PWDATA_RNO_1[10]_net_1 ), .C(\i[6]_net_1 ), .D(
        \PWDATA_RNO_2[10]_net_1 ), .Y(\PWDATA_5[10] ));
    CFG3 #( .INIT(8'h8B) )  \PADDR_int_lm_0[5]  (.A(\PADDR_int_s[5] ), 
        .B(N_15_1), .C(\apb_fsm_current_state[0]_net_1 ), .Y(
        \PADDR_int_lm[5] ));
    CFG3 #( .INIT(8'h20) )  \PWDATA_RNO_3[4]  (.A(\i[0]_net_1 ), .B(
        \i[4]_net_1 ), .C(N_8_0), .Y(\PWDATA_RNO_3[4]_net_1 ));
    SLE \PWDATA[1]  (.D(\PWDATA_5[1] ), .CLK(CORECONFIGP_0_APB_S_PCLK), 
        .EN(N_463_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_APB_IF_PWDATA[1]));
    CFG2 #( .INIT(4'h8) )  \PADDR_int_lm_0[8]  (.A(N_15_1), .B(
        \PADDR_int_s[8] ), .Y(\PADDR_int_lm[8] ));
    ARI1 #( .INIT(20'h42A00) )  \count_delay_cry[1]  (.A(VCC_net_1), 
        .B(\count_delay[1]_net_1 ), .C(N_233_mux), .D(
        \apb_fsm_current_state[3]_net_1 ), .FCI(
        \count_delay_cry[0]_net_1 ), .S(\count_delay_s[1] ), .Y(), 
        .FCO(\count_delay_cry[1]_net_1 ));
    CFG4 #( .INIT(16'hB1A0) )  \PWDATA_RNO_1[9]  (.A(\i[4]_net_1 ), .B(
        \i[5]_net_1 ), .C(N_505), .D(N_468), .Y(N_522));
    CFG3 #( .INIT(8'h8B) )  PENABLE_RNO_0 (.A(N_264_mux), .B(
        \apb_fsm_current_state[4]_net_1 ), .C(N_460), .Y(
        un1_DRAM_Ready_1_sqmuxa_i_0));
    CFG4 #( .INIT(16'h0010) )  \PWDATA_RNO_3[10]  (.A(\i[0]_net_1 ), 
        .B(\i[5]_net_1 ), .C(N_8_0), .D(\i[4]_net_1 ), .Y(
        \PWDATA_RNO_3[10]_net_1 ));
    CFG2 #( .INIT(4'h2) )  \i_RNI5SGT[6]  (.A(\i[3]_net_1 ), .B(
        \i[6]_net_1 ), .Y(m173_0));
    CFG4 #( .INIT(16'h201C) )  \PWDATA_RNO_6[3]  (.A(\i[0]_net_1 ), .B(
        \i[4]_net_1 ), .C(\i[1]_net_1 ), .D(\i[2]_net_1 ), .Y(N_509));
    CFG4 #( .INIT(16'h139B) )  \PWDATA_RNO_2[4]  (.A(\i[3]_net_1 ), .B(
        \i[5]_net_1 ), .C(N_192), .D(N_494), .Y(m193_1));
    CFG4 #( .INIT(16'hBCB0) )  \PWDATA_RNO_1[5]  (.A(N_198), .B(
        \i[3]_net_1 ), .C(m199_ns_1), .D(N_494), .Y(N_200));
    SLE \count_delay[6]  (.D(\count_delay_s[6] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_43_i_0), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\count_delay[6]_net_1 ));
    CFG3 #( .INIT(8'h08) )  \i_RNIVC1R1_3[0]  (.A(N_64_i), .B(
        \i[0]_net_1 ), .C(\i[4]_net_1 ), .Y(N_477));
    CFG4 #( .INIT(16'h193B) )  \PWDATA_RNO_0[10]  (.A(\i[6]_net_1 ), 
        .B(\i[3]_net_1 ), .C(\PWDATA_RNO_3[10]_net_1 ), .D(
        \PWDATA_RNO_4[10]_net_1 ), .Y(m104_ns_1));
    CFG3 #( .INIT(8'h20) )  \PWDATA_RNO_2[1]  (.A(\i[3]_net_1 ), .B(
        \i[5]_net_1 ), .C(N_182), .Y(m183_1));
    CFG4 #( .INIT(16'hFFFE) )  un58lto3 (.A(\count_delay[3]_net_1 ), 
        .B(\count_delay[2]_net_1 ), .C(\count_delay[1]_net_1 ), .D(
        \count_delay[0]_net_1 ), .Y(un58lt11));
    SLE \i[2]  (.D(\i_s[2] ), .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(
        N_251_mux_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(\i[2]_net_1 ));
    CFG4 #( .INIT(16'h8000) )  \count_delay_RNI8M962[4]  (.A(
        \count_delay[6]_net_1 ), .B(\count_delay[4]_net_1 ), .C(
        HW_Boot_Engine_0_APB_IF_PREADY), .D(m32_5), .Y(m32_7));
    SLE \count_delay[1]  (.D(\count_delay_s[1] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_43_i_0), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\count_delay[1]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \apb_fsm_current_state_RNO[5]  (.A(
        N_264_mux), .B(\apb_fsm_current_state[4]_net_1 ), .Y(
        DRAM_Ready_0_sqmuxa));
    CFG2 #( .INIT(4'h8) )  \i_RNIDV8C1_0[0]  (.A(N_64_i), .B(
        \i[0]_net_1 ), .Y(N_81_i));
    CFG2 #( .INIT(4'h1) )  \i_RNI7UGT[6]  (.A(\i[5]_net_1 ), .B(
        \i[6]_net_1 ), .Y(N_254));
    CFG4 #( .INIT(16'hF960) )  \PWDATA_RNO_0[6]  (.A(\i[5]_net_1 ), .B(
        \i[4]_net_1 ), .C(N_505), .D(N_477), .Y(i14_mux_3));
    SLE \apb_fsm_current_state[0]  (.D(GND_net_1), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(VCC_net_1), .ALn(MSS_HPMS_READY)
        , .ADn(GND_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\apb_fsm_current_state[0]_net_1 ));
    CFG3 #( .INIT(8'hE2) )  \PWDATA_RNO[1]  (.A(
        \PWDATA_RNO_0[1]_net_1 ), .B(\i[6]_net_1 ), .C(
        \PWDATA_RNO_1[1]_net_1 ), .Y(\PWDATA_5[1] ));
    CFG4 #( .INIT(16'hFFEA) )  \apb_fsm_current_state_RNO[1]  (.A(
        \apb_fsm_current_state[0]_net_1 ), .B(
        \apb_fsm_current_state[2]_net_1 ), .C(N_250_mux), .D(N_35_0), 
        .Y(N_266_mux_i_0));
    CFG2 #( .INIT(4'h2) )  \i_RNIDV8C1_1[0]  (.A(N_64_i), .B(
        \i[0]_net_1 ), .Y(N_505));
    CFG4 #( .INIT(16'hD002) )  \PWDATA_RNO_1[8]  (.A(\i[1]_net_1 ), .B(
        \i[5]_net_1 ), .C(\i[4]_net_1 ), .D(m213_ns_1), .Y(N_214));
    CFG2 #( .INIT(4'h2) )  \PWDATA_RNO_2[10]  (.A(i15_mux_1), .B(
        \i[4]_net_1 ), .Y(\PWDATA_RNO_2[10]_net_1 ));
    SLE \apb_fsm_current_state[6]  (.D(N_447_i_0), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(VCC_net_1), .ALn(MSS_HPMS_READY)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\apb_fsm_current_state[6]_net_1 ));
    ARI1 #( .INIT(20'h42A00) )  \count_delay_cry[6]  (.A(VCC_net_1), 
        .B(\count_delay[6]_net_1 ), .C(N_233_mux), .D(
        \apb_fsm_current_state[3]_net_1 ), .FCI(
        \count_delay_cry[5]_net_1 ), .S(\count_delay_s[6] ), .Y(), 
        .FCO(\count_delay_cry[6]_net_1 ));
    ARI1 #( .INIT(20'h42A00) )  \count_delay_cry[4]  (.A(VCC_net_1), 
        .B(\count_delay[4]_net_1 ), .C(N_233_mux), .D(
        \apb_fsm_current_state[3]_net_1 ), .FCI(
        \count_delay_cry[3]_net_1 ), .S(\count_delay_s[4] ), .Y(), 
        .FCO(\count_delay_cry[4]_net_1 ));
    SLE \i[6]  (.D(\i_s[6]_net_1 ), .CLK(CORECONFIGP_0_APB_S_PCLK), 
        .EN(N_251_mux_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \i[6]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \i_cry[1]  (.A(VCC_net_1), .B(
        \i[1]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(i_s_306_FCO), 
        .S(\i_s[1] ), .Y(), .FCO(\i_cry[1]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \i_cry[2]  (.A(VCC_net_1), .B(
        \i[2]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \i_cry[1]_net_1 ), .S(\i_s[2] ), .Y(), .FCO(\i_cry[2]_net_1 ));
    SLE \i[4]  (.D(\i_s[4] ), .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(
        N_251_mux_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(\i[4]_net_1 ));
    SLE PWRITE (.D(\apb_fsm_current_state[0]_net_1 ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_263_mux), .ALn(MSS_HPMS_READY)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(HW_Boot_Engine_0_APB_IF_PWRITE));
    CFG4 #( .INIT(16'h2080) )  \PWDATA_RNO_4[10]  (.A(\i[0]_net_1 ), 
        .B(\i[5]_net_1 ), .C(N_64_i), .D(\i[4]_net_1 ), .Y(
        \PWDATA_RNO_4[10]_net_1 ));
    SLE \PADDR_int[11]  (.D(\PADDR_int_lm[11] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_382_i_0), .ALn(MSS_HPMS_READY)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\HW_Boot_Engine_0_APB_IF_PADDR[11] ));
    CFG2 #( .INIT(4'h2) )  \i_RNIVLGT_1[1]  (.A(\i[2]_net_1 ), .B(
        \i[1]_net_1 ), .Y(N_67_0));
    ARI1 #( .INIT(20'h4AA00) )  \i_s[6]  (.A(VCC_net_1), .B(
        \i[6]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \i_cry[5]_net_1 ), .S(\i_s[6]_net_1 ), .Y(), .FCO());
    SLE \apb_fsm_current_state[3]  (.D(N_443_i_0), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(VCC_net_1), .ALn(MSS_HPMS_READY)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\apb_fsm_current_state[3]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \PADDR_int_cry[10]  (.A(VCC_net_1), .B(
        HW_Boot_Engine_0_APB_IF_PADDR_8), .C(GND_net_1), .D(GND_net_1), 
        .FCI(\PADDR_int_cry[9]_net_1 ), .S(\PADDR_int_s[10] ), .Y(), 
        .FCO(\PADDR_int_cry[10]_net_1 ));
    SLE \PADDR_int[9]  (.D(\PADDR_int_lm[9] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_382_i_0), .ALn(MSS_HPMS_READY)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(HW_Boot_Engine_0_APB_IF_PADDR_7));
    CFG3 #( .INIT(8'h01) )  \i_RNIG29C1[2]  (.A(\i[0]_net_1 ), .B(
        \i[4]_net_1 ), .C(\i[2]_net_1 ), .Y(N_494));
    SLE \PWDATA[6]  (.D(\PWDATA_5[6] ), .CLK(CORECONFIGP_0_APB_S_PCLK), 
        .EN(N_463_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_APB_IF_PWDATA[6]));
    CFG3 #( .INIT(8'h4F) )  \PWDATA_RNO_3[7]  (.A(\i[2]_net_1 ), .B(
        \i[0]_net_1 ), .C(\i[1]_net_1 ), .Y(N_515));
    ARI1 #( .INIT(20'h42A00) )  \count_delay_cry[8]  (.A(VCC_net_1), 
        .B(\count_delay[8]_net_1 ), .C(N_233_mux), .D(
        \apb_fsm_current_state[3]_net_1 ), .FCI(
        \count_delay_cry[7]_net_1 ), .S(\count_delay_s[8] ), .Y(), 
        .FCO(\count_delay_cry[8]_net_1 ));
    CFG4 #( .INIT(16'h7824) )  \PWDATA_RNO_6[0]  (.A(\i[0]_net_1 ), .B(
        \i[4]_net_1 ), .C(\i[1]_net_1 ), .D(\i[2]_net_1 ), .Y(N_69_0));
    CFG4 #( .INIT(16'h6004) )  \PWDATA_RNO_1[4]  (.A(\i[0]_net_1 ), .B(
        \i[4]_net_1 ), .C(\i[1]_net_1 ), .D(\i[2]_net_1 ), .Y(
        \PWDATA_RNO_1[4]_net_1 ));
    CFG4 #( .INIT(16'h6F09) )  \PWDATA_RNO_4[0]  (.A(\i[5]_net_1 ), .B(
        \i[4]_net_1 ), .C(i15_mux), .D(N_81_i), .Y(
        \PWDATA_RNO_4[0]_net_1 ));
    CFG4 #( .INIT(16'h01FA) )  \PWDATA_RNO_2[5]  (.A(\i[0]_net_1 ), .B(
        \i[4]_net_1 ), .C(\i[1]_net_1 ), .D(\i[2]_net_1 ), .Y(N_198));
    ARI1 #( .INIT(20'h4AA00) )  \PADDR_int_cry[9]  (.A(VCC_net_1), .B(
        HW_Boot_Engine_0_APB_IF_PADDR_7), .C(GND_net_1), .D(GND_net_1), 
        .FCI(\PADDR_int_cry[8]_net_1 ), .S(\PADDR_int_s[9] ), .Y(), 
        .FCO(\PADDR_int_cry[9]_net_1 ));
    SLE \PADDR_int[5]  (.D(\PADDR_int_lm[5] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_382_i_0), .ALn(MSS_HPMS_READY)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(HW_Boot_Engine_0_APB_IF_PADDR_3));
    CFG3 #( .INIT(8'hB8) )  \PADDR_int_lm_0[6]  (.A(\PADDR_int_s[6] ), 
        .B(N_15_1), .C(\apb_fsm_current_state[3]_net_1 ), .Y(
        \PADDR_int_lm[6] ));
    ARI1 #( .INIT(20'h4AA00) )  i_s_306 (.A(VCC_net_1), .B(
        \i[0]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(VCC_net_1), 
        .S(), .Y(), .FCO(i_s_306_FCO));
    SLE \apb_fsm_current_state[5]  (.D(VCC_net_1), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(DRAM_Ready_0_sqmuxa), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        \apb_fsm_current_state[5]_net_1 ));
    SLE \PADDR_int[15]  (.D(\PADDR_int_lm[15] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_382_i_0), .ALn(MSS_HPMS_READY)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(HW_Boot_Engine_0_APB_IF_PADDR_13));
    ARI1 #( .INIT(20'h4AA00) )  \PADDR_int_cry[5]  (.A(VCC_net_1), .B(
        HW_Boot_Engine_0_APB_IF_PADDR_3), .C(GND_net_1), .D(GND_net_1), 
        .FCI(\PADDR_int_cry[4]_net_1 ), .S(\PADDR_int_s[5] ), .Y(), 
        .FCO(\PADDR_int_cry[5]_net_1 ));
    SLE \count_delay[10]  (.D(\count_delay_s[10] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_43_i_0), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\count_delay[10]_net_1 ));
    CFG4 #( .INIT(16'h2E0C) )  \apb_fsm_current_state_RNI4DC35[2]  (.A(
        \apb_fsm_current_state[2]_net_1 ), .B(
        \apb_fsm_current_state[3]_net_1 ), .C(N_233_mux), .D(N_250_mux)
        , .Y(N_15_1));
    CFG4 #( .INIT(16'h3120) )  \PWDATA_RNO_1[1]  (.A(\i[5]_net_1 ), .B(
        \i[3]_net_1 ), .C(N_185), .D(N_480), .Y(
        \PWDATA_RNO_1[1]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \PADDR_int_cry[13]  (.A(VCC_net_1), .B(
        HW_Boot_Engine_0_APB_IF_PADDR_11), .C(GND_net_1), .D(GND_net_1)
        , .FCI(\PADDR_int_cry[12]_net_1 ), .S(\PADDR_int_s[13] ), .Y(), 
        .FCO(\PADDR_int_cry[13]_net_1 ));
    CFG3 #( .INIT(8'h42) )  \i_RNIVC1R1_0[0]  (.A(\i[0]_net_1 ), .B(
        \i[4]_net_1 ), .C(N_67_0), .Y(N_471));
    SLE \count_delay[5]  (.D(\count_delay_s[5] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_43_i_0), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\count_delay[5]_net_1 ));
    SLE \count_delay[8]  (.D(\count_delay_s[8] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_43_i_0), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\count_delay[8]_net_1 ));
    SLE \PWDATA[11]  (.D(\PWDATA_5[11] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_463_i_0), .ALn(MSS_HPMS_READY)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(HW_Boot_Engine_0_APB_IF_PWDATA[11]));
    ARI1 #( .INIT(20'h42A00) )  \count_delay_cry[9]  (.A(VCC_net_1), 
        .B(\count_delay[9]_net_1 ), .C(N_233_mux), .D(
        \apb_fsm_current_state[3]_net_1 ), .FCI(
        \count_delay_cry[8]_net_1 ), .S(\count_delay_s[9] ), .Y(), 
        .FCO(\count_delay_cry[9]_net_1 ));
    SLE \PWDATA[12]  (.D(N_256_mux), .CLK(CORECONFIGP_0_APB_S_PCLK), 
        .EN(N_463_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_APB_IF_PWDATA[12]));
    CFG3 #( .INIT(8'hE4) )  \PWDATA_RNO_0[9]  (.A(\i[5]_net_1 ), .B(
        \PWDATA_RNO_2[9]_net_1 ), .C(\PWDATA_RNO_3[9]_net_1 ), .Y(
        N_526));
    CFG3 #( .INIT(8'hCE) )  \apb_fsm_current_state_RNITJKV1[3]  (.A(
        \apb_fsm_current_state[3]_net_1 ), .B(i_0_sqmuxa), .C(
        N_233_mux), .Y(N_251_mux_i_0));
    CFG4 #( .INIT(16'h1180) )  \PWDATA_RNO_0[3]  (.A(\i[5]_net_1 ), .B(
        \i[4]_net_1 ), .C(N_67_0), .D(m141_ns_1), .Y(N_513));
    SLE \PADDR_int[8]  (.D(\PADDR_int_lm[8] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_382_i_0), .ALn(MSS_HPMS_READY)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(HW_Boot_Engine_0_APB_IF_PADDR_6));
    ARI1 #( .INIT(20'h47700) )  \count_delay_cry_cy[0]  (.A(VCC_net_1), 
        .B(\apb_fsm_current_state[3]_net_1 ), .C(N_233_mux), .D(
        GND_net_1), .FCI(VCC_net_1), .S(), .Y(), .FCO(
        count_delay_cry_cy));
    CFG4 #( .INIT(16'h4450) )  \PWDATA_RNO_3[8]  (.A(\i[0]_net_1 ), .B(
        N_64_i), .C(\i[2]_net_1 ), .D(\i[5]_net_1 ), .Y(m213_ns_1));
    CFG4 #( .INIT(16'h1505) )  \i_RNINNA73[6]  (.A(\i[6]_net_1 ), .B(
        \i[0]_net_1 ), .C(N_228), .D(N_8_0), .Y(N_250_mux));
    ARI1 #( .INIT(20'h4AA00) )  \i_cry[3]  (.A(VCC_net_1), .B(
        \i[3]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \i_cry[2]_net_1 ), .S(\i_s[3] ), .Y(), .FCO(\i_cry[3]_net_1 ));
    CFG3 #( .INIT(8'h0E) )  PENABLE_RNO_1 (.A(
        \apb_fsm_current_state[1]_net_1 ), .B(
        \apb_fsm_current_state[6]_net_1 ), .C(
        HW_Boot_Engine_0_APB_IF_PREADY), .Y(N_460));
    SLE \PWDATA[9]  (.D(\PWDATA_5[9] ), .CLK(CORECONFIGP_0_APB_S_PCLK), 
        .EN(N_463_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_APB_IF_PWDATA[9]));
    CFG2 #( .INIT(4'h8) )  \i_RNIDV8C1[0]  (.A(N_8_0), .B(\i[0]_net_1 )
        , .Y(N_481));
    ARI1 #( .INIT(20'h4AA00) )  \PADDR_int_cry[8]  (.A(VCC_net_1), .B(
        HW_Boot_Engine_0_APB_IF_PADDR_6), .C(GND_net_1), .D(GND_net_1), 
        .FCI(\PADDR_int_cry[7]_net_1 ), .S(\PADDR_int_s[8] ), .Y(), 
        .FCO(\PADDR_int_cry[8]_net_1 ));
    CFG4 #( .INIT(16'hC480) )  \i_RNI2LJJ4[3]  (.A(\i[5]_net_1 ), .B(
        \i[3]_net_1 ), .C(N_476), .D(N_531), .Y(N_533));
    CFG2 #( .INIT(4'h8) )  \PADDR_int_lm_0[12]  (.A(N_15_1), .B(
        \PADDR_int_s[12] ), .Y(\PADDR_int_lm[12] ));
    ARI1 #( .INIT(20'h4AA00) )  \i_cry[4]  (.A(VCC_net_1), .B(
        \i[4]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \i_cry[3]_net_1 ), .S(\i_s[4] ), .Y(), .FCO(\i_cry[4]_net_1 ));
    CFG4 #( .INIT(16'hA820) )  \PWDATA_RNO[15]  (.A(m173_0), .B(
        \i[5]_net_1 ), .C(N_480), .D(N_494), .Y(\PWDATA_5[15] ));
    SLE \i[5]  (.D(\i_s[5] ), .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(
        N_251_mux_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(\i[5]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \i_RNIVLGT[1]  (.A(\i[2]_net_1 ), .B(
        \i[1]_net_1 ), .Y(N_64_i));
    SLE \apb_fsm_current_state[1]  (.D(N_266_mux_i_0), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(VCC_net_1), .ALn(MSS_HPMS_READY)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\apb_fsm_current_state[1]_net_1 ));
    SLE \PWDATA[15]  (.D(\PWDATA_5[15] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_463_i_0), .ALn(MSS_HPMS_READY)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(HW_Boot_Engine_0_APB_IF_PWDATA[15]));
    CFG4 #( .INIT(16'h3402) )  \PWDATA_RNO_0[2]  (.A(\i[1]_net_1 ), .B(
        \i[2]_net_1 ), .C(\i[5]_net_1 ), .D(m128_ns_1), .Y(N_501));
    CFG4 #( .INIT(16'h7430) )  \PWDATA_RNO_5[0]  (.A(\i[4]_net_1 ), .B(
        \i[5]_net_1 ), .C(N_476), .D(N_81_i), .Y(
        \PWDATA_RNO_5[0]_net_1 ));
    SLE \PWDATA[5]  (.D(\PWDATA_5[5] ), .CLK(CORECONFIGP_0_APB_S_PCLK), 
        .EN(N_463_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_APB_IF_PWDATA[5]));
    CFG2 #( .INIT(4'h8) )  \PADDR_int_lm_0[13]  (.A(N_15_1), .B(
        \PADDR_int_s[13] ), .Y(\PADDR_int_lm[13] ));
    ARI1 #( .INIT(20'h42A00) )  \count_delay_cry[10]  (.A(VCC_net_1), 
        .B(\count_delay[10]_net_1 ), .C(N_233_mux), .D(
        \apb_fsm_current_state[3]_net_1 ), .FCI(
        \count_delay_cry[9]_net_1 ), .S(\count_delay_s[10] ), .Y(), 
        .FCO(\count_delay_cry[10]_net_1 ));
    CFG3 #( .INIT(8'h72) )  \PADDR_int_lm_0[2]  (.A(N_15_1), .B(
        HW_Boot_Engine_0_APB_IF_PADDR_0), .C(
        \apb_fsm_current_state[3]_net_1 ), .Y(\PADDR_int_lm[2] ));
    ARI1 #( .INIT(20'h4AA00) )  \i_cry[5]  (.A(VCC_net_1), .B(
        \i[5]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \i_cry[4]_net_1 ), .S(\i_s[5] ), .Y(), .FCO(\i_cry[5]_net_1 ));
    CFG4 #( .INIT(16'hC808) )  \PWDATA_RNO_0[14]  (.A(N_64_i), .B(
        m163_ns_1), .C(\i[3]_net_1 ), .D(N_529), .Y(N_530));
    CFG3 #( .INIT(8'h29) )  \PWDATA_RNO_4[5]  (.A(\i[2]_net_1 ), .B(
        \i[0]_net_1 ), .C(\i[1]_net_1 ), .Y(N_68_0));
    CFG3 #( .INIT(8'hE2) )  \PWDATA_RNO_1[3]  (.A(
        \PWDATA_RNO_3[3]_net_1 ), .B(\i[3]_net_1 ), .C(
        \PWDATA_RNO_4[3]_net_1 ), .Y(N_511));
    CFG4 #( .INIT(16'hAE0C) )  \apb_fsm_current_state_RNIPV1Q4[4]  (.A(
        \apb_fsm_current_state[3]_net_1 ), .B(
        \apb_fsm_current_state[4]_net_1 ), .C(N_264_mux), .D(N_233_mux)
        , .Y(N_43_i_0));
    CFG4 #( .INIT(16'h1FDF) )  \PWDATA_RNO_3[2]  (.A(\i[0]_net_1 ), .B(
        \i[4]_net_1 ), .C(\i[1]_net_1 ), .D(\i[2]_net_1 ), .Y(
        m123_ns_1));
    CFG3 #( .INIT(8'h40) )  \PWDATA_RNO[12]  (.A(\i[5]_net_1 ), .B(
        m173_0), .C(N_171), .Y(N_256_mux));
    SLE \i[3]  (.D(\i_s[3] ), .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(
        N_251_mux_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(\i[3]_net_1 ));
    SLE \apb_fsm_current_state[4]  (.D(N_43_i_0), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(VCC_net_1), .ALn(MSS_HPMS_READY)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\apb_fsm_current_state[4]_net_1 ));
    SLE \count_delay[2]  (.D(\count_delay_s[2] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_43_i_0), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\count_delay[2]_net_1 ));
    CFG4 #( .INIT(16'hB380) )  \PWDATA_RNO_3[3]  (.A(\i[4]_net_1 ), .B(
        \i[5]_net_1 ), .C(N_505), .D(N_504), .Y(
        \PWDATA_RNO_3[3]_net_1 ));
    CFG4 #( .INIT(16'h0DFA) )  \PWDATA_RNO_4[4]  (.A(\i[0]_net_1 ), .B(
        \i[4]_net_1 ), .C(\i[1]_net_1 ), .D(\i[2]_net_1 ), .Y(N_192));
    SLE \PWDATA[2]  (.D(\PWDATA_5[2] ), .CLK(CORECONFIGP_0_APB_S_PCLK), 
        .EN(N_463_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_APB_IF_PWDATA[2]));
    CFG3 #( .INIT(8'h70) )  \PWDATA_RNO_2[14]  (.A(\i[2]_net_1 ), .B(
        \i[0]_net_1 ), .C(\i[1]_net_1 ), .Y(N_529));
    CFG2 #( .INIT(4'h8) )  \PADDR_int_lm_0[15]  (.A(N_15_1), .B(
        \PADDR_int_s[15]_net_1 ), .Y(\PADDR_int_lm[15] ));
    SLE \PADDR_int[2]  (.D(\PADDR_int_lm[2] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_382_i_0), .ALn(MSS_HPMS_READY)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(HW_Boot_Engine_0_APB_IF_PADDR_0));
    SLE \i[1]  (.D(\i_s[1] ), .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(
        N_251_mux_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(\i[1]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \apb_fsm_current_state_RNIHS24[1]  (.A(
        HW_Boot_Engine_0_APB_IF_PREADY), .B(
        \apb_fsm_current_state[1]_net_1 ), .Y(i_0_sqmuxa));
    ARI1 #( .INIT(20'h42A00) )  \count_delay_cry[3]  (.A(VCC_net_1), 
        .B(\count_delay[3]_net_1 ), .C(N_233_mux), .D(
        \apb_fsm_current_state[3]_net_1 ), .FCI(
        \count_delay_cry[2]_net_1 ), .S(\count_delay_s[3] ), .Y(), 
        .FCO(\count_delay_cry[3]_net_1 ));
    CFG3 #( .INIT(8'h80) )  \i_RNI38IO2[3]  (.A(\i[3]_net_1 ), .B(
        \i[5]_net_1 ), .C(N_471), .Y(m78_2));
    CFG4 #( .INIT(16'h5D08) )  \PWDATA_RNO_2[0]  (.A(\i[5]_net_1 ), .B(
        \i[4]_net_1 ), .C(N_465), .D(N_69_0), .Y(m78_1_0));
    SLE \PWDATA[14]  (.D(\PWDATA_5[14] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_463_i_0), .ALn(MSS_HPMS_READY)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(HW_Boot_Engine_0_APB_IF_PWDATA[14]));
    CFG4 #( .INIT(16'h41BE) )  \PWDATA_RNO_2[8]  (.A(\i[0]_net_1 ), .B(
        \i[4]_net_1 ), .C(\i[1]_net_1 ), .D(\i[2]_net_1 ), .Y(N_216));
    SLE \count_delay[7]  (.D(\count_delay_s[7] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_43_i_0), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\count_delay[7]_net_1 ));
    CFG4 #( .INIT(16'h4032) )  \PWDATA_RNO_0[13]  (.A(\i[0]_net_1 ), 
        .B(\i[4]_net_1 ), .C(\i[1]_net_1 ), .D(\i[2]_net_1 ), .Y(N_221)
        );
    CFG3 #( .INIT(8'hE4) )  \PWDATA_RNO[14]  (.A(\i[6]_net_1 ), .B(
        N_530), .C(N_533), .Y(\PWDATA_5[14] ));
    CFG2 #( .INIT(4'h8) )  \PADDR_int_lm_0[10]  (.A(N_15_1), .B(
        \PADDR_int_s[10] ), .Y(\PADDR_int_lm[10] ));
    SLE \PWDATA[3]  (.D(\PWDATA_5[3] ), .CLK(CORECONFIGP_0_APB_S_PCLK), 
        .EN(N_463_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_APB_IF_PWDATA[3]));
    CFG4 #( .INIT(16'h7520) )  \PWDATA_RNO_1[10]  (.A(\i[5]_net_1 ), 
        .B(\i[4]_net_1 ), .C(N_481), .D(N_480), .Y(
        \PWDATA_RNO_1[10]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \i_RNIVLGT_0[1]  (.A(\i[2]_net_1 ), .B(
        \i[1]_net_1 ), .Y(N_468));
    CFG3 #( .INIT(8'h10) )  \i_RNIVC1R1_2[0]  (.A(\i[0]_net_1 ), .B(
        \i[4]_net_1 ), .C(N_8_0), .Y(N_476));
    CFG4 #( .INIT(16'hA280) )  \PWDATA_RNO_2[6]  (.A(\i[4]_net_1 ), .B(
        \i[5]_net_1 ), .C(N_481), .D(N_470), .Y(
        \PWDATA_RNO_2[6]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  PADDR_int_s_307 (.A(VCC_net_1), .B(
        HW_Boot_Engine_0_APB_IF_PADDR_0), .C(GND_net_1), .D(GND_net_1), 
        .FCI(VCC_net_1), .S(), .Y(), .FCO(PADDR_int_s_307_FCO));
    CFG4 #( .INIT(16'h8000) )  un58lto3_RNIA80U2 (.A(
        \count_delay[11]_net_1 ), .B(\count_delay[9]_net_1 ), .C(
        un58lt11), .D(m32_7), .Y(N_264_mux));
    CFG4 #( .INIT(16'h05EE) )  \PWDATA_RNO_2[7]  (.A(\i[0]_net_1 ), .B(
        N_468), .C(\i[2]_net_1 ), .D(\i[5]_net_1 ), .Y(m148_ns_1));
    CFG2 #( .INIT(4'h2) )  \PWDATA_RNO_0[8]  (.A(N_216), .B(
        \i[5]_net_1 ), .Y(N_217));
    CFG3 #( .INIT(8'hB8) )  \PADDR_int_lm_0[9]  (.A(\PADDR_int_s[9] ), 
        .B(N_15_1), .C(\apb_fsm_current_state[2]_net_1 ), .Y(
        \PADDR_int_lm[9] ));
    CFG4 #( .INIT(16'hA8EC) )  \apb_fsm_current_state_RNO[3]  (.A(
        \apb_fsm_current_state[6]_net_1 ), .B(
        \apb_fsm_current_state[2]_net_1 ), .C(
        HW_Boot_Engine_0_APB_IF_PREADY), .D(N_250_mux), .Y(N_443_i_0));
    
endmodule


module AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7(
       AHB_IF_0_DATAOUT,
       HW_Boot_Engine_0_AHB_IF_HTRANS,
       CoreAHBLite_0_AHBmslave4_HRDATA,
       SPI_to_MDDR_0_DATAOUT_0,
       SPI_to_MDDR_0_DATAOUT_1,
       SPI_to_MDDR_0_DATAOUT_2,
       SPI_to_MDDR_0_DATAOUT_3,
       SPI_to_MDDR_0_DATAOUT_4,
       SPI_to_MDDR_0_DATAOUT_5,
       SPI_to_MDDR_0_DATAOUT_6,
       SPI_to_MDDR_0_DATAOUT_7,
       SPI_to_MDDR_0_DATAOUT_18,
       HW_Boot_Engine_0_AHB_IF_HWDATA_2,
       HW_Boot_Engine_0_AHB_IF_HWDATA_3,
       HW_Boot_Engine_0_AHB_IF_HWDATA_4,
       HW_Boot_Engine_0_AHB_IF_HWDATA_5,
       HW_Boot_Engine_0_AHB_IF_HWDATA_6,
       HW_Boot_Engine_0_AHB_IF_HWDATA_7,
       HW_Boot_Engine_0_AHB_IF_HWDATA_18,
       HW_Boot_Engine_0_AHB_IF_HWDATA_0,
       HW_Boot_Engine_0_AHB_IF_HWDATA_1,
       SPI_to_MDDR_0_ADDR_0,
       SPI_to_MDDR_0_ADDR_1,
       SPI_to_MDDR_0_ADDR_2,
       SPI_to_MDDR_0_ADDR_10,
       SPI_to_MDDR_0_ADDR_14,
       SPI_to_MDDR_0_ADDR_28,
       HW_Boot_Engine_0_AHB_IF_HADDR_1,
       HW_Boot_Engine_0_AHB_IF_HADDR_2,
       HW_Boot_Engine_0_AHB_IF_HADDR_10,
       HW_Boot_Engine_0_AHB_IF_HADDR_14,
       HW_Boot_Engine_0_AHB_IF_HADDR_28,
       HW_Boot_Engine_0_AHB_IF_HADDR_0,
       ahb_fsm_current_state_5,
       AHB_IF_0_AHB_BUSY,
       AHB_IF_0_AHB_BUSY_i_0,
       MSS_HPMS_READY,
       CCC_0_GL0,
       HREADY_M_iv_i_0,
       HW_Boot_Engine_0_AHB_IF_HWRITE,
       SPI_to_MDDR_0_READ,
       SPI_to_MDDR_0_WRITE,
       N_95,
       HREADY_M_iv_i_0_d,
       HREADY_M_iv_i_0_1_0
    );
output [8:0] AHB_IF_0_DATAOUT;
output [1:1] HW_Boot_Engine_0_AHB_IF_HTRANS;
input  [8:0] CoreAHBLite_0_AHBmslave4_HRDATA;
input  SPI_to_MDDR_0_DATAOUT_0;
input  SPI_to_MDDR_0_DATAOUT_1;
input  SPI_to_MDDR_0_DATAOUT_2;
input  SPI_to_MDDR_0_DATAOUT_3;
input  SPI_to_MDDR_0_DATAOUT_4;
input  SPI_to_MDDR_0_DATAOUT_5;
input  SPI_to_MDDR_0_DATAOUT_6;
input  SPI_to_MDDR_0_DATAOUT_7;
input  SPI_to_MDDR_0_DATAOUT_18;
output HW_Boot_Engine_0_AHB_IF_HWDATA_2;
output HW_Boot_Engine_0_AHB_IF_HWDATA_3;
output HW_Boot_Engine_0_AHB_IF_HWDATA_4;
output HW_Boot_Engine_0_AHB_IF_HWDATA_5;
output HW_Boot_Engine_0_AHB_IF_HWDATA_6;
output HW_Boot_Engine_0_AHB_IF_HWDATA_7;
output HW_Boot_Engine_0_AHB_IF_HWDATA_18;
output HW_Boot_Engine_0_AHB_IF_HWDATA_0;
output HW_Boot_Engine_0_AHB_IF_HWDATA_1;
input  SPI_to_MDDR_0_ADDR_0;
input  SPI_to_MDDR_0_ADDR_1;
input  SPI_to_MDDR_0_ADDR_2;
input  SPI_to_MDDR_0_ADDR_10;
input  SPI_to_MDDR_0_ADDR_14;
input  SPI_to_MDDR_0_ADDR_28;
output HW_Boot_Engine_0_AHB_IF_HADDR_1;
output HW_Boot_Engine_0_AHB_IF_HADDR_2;
output HW_Boot_Engine_0_AHB_IF_HADDR_10;
output HW_Boot_Engine_0_AHB_IF_HADDR_14;
output HW_Boot_Engine_0_AHB_IF_HADDR_28;
output HW_Boot_Engine_0_AHB_IF_HADDR_0;
output ahb_fsm_current_state_5;
output AHB_IF_0_AHB_BUSY;
output AHB_IF_0_AHB_BUSY_i_0;
input  MSS_HPMS_READY;
input  CCC_0_GL0;
input  HREADY_M_iv_i_0;
output HW_Boot_Engine_0_AHB_IF_HWRITE;
input  SPI_to_MDDR_0_READ;
input  SPI_to_MDDR_0_WRITE;
input  N_95;
input  HREADY_M_iv_i_0_d;
input  HREADY_M_iv_i_0_1_0;

    wire VCC_net_1, \HW_Boot_Engine_0_AHB_IF_HRDATA[4] , N_111_i_0, 
        GND_net_1, \HW_Boot_Engine_0_AHB_IF_HRDATA[5] , 
        \DATAOUT_ldmx[6]_net_1 , \DATAOUT_ldmx[7]_net_1 , 
        \DATAOUT_ldmx[8]_net_1 , \HWDATA_ldmx[2]_net_1 , 
        \HWDATA_ldmx[3]_net_1 , \HWDATA_ldmx[4]_net_1 , 
        \HWDATA_ldmx[5]_net_1 , \HWDATA_ldmx[6]_net_1 , 
        \HWDATA_ldmx[7]_net_1 , \HWDATA_ldmx[10]_net_1 , 
        \DATAOUT_ldmx[0]_net_1 , \DATAOUT_ldmx[1]_net_1 , 
        \DATAOUT_ldmx[2]_net_1 , \DATAOUT_ldmx[3]_net_1 , 
        \HWDATA_int[0]_net_1 , N_121_i_0, \HWDATA_int[1]_net_1 , 
        \HWDATA_int[2]_net_1 , \HWDATA_int[3]_net_1 , 
        \HWDATA_int[4]_net_1 , \HWDATA_int[5]_net_1 , 
        \HWDATA_int[6]_net_1 , \HWDATA_int[7]_net_1 , \HWDATA_int[25] , 
        \HWDATA_ldmx[0]_net_1 , \HWDATA_ldmx[1]_net_1 , \HADDR_9[3] , 
        N_137_i_0, \HADDR_9[4] , \HADDR_9[12] , \HADDR_9[17] , 
        \HADDR_9[30] , \HADDR_int[2]_net_1 , N_117_i_0, 
        \HADDR_int[3]_net_1 , \HADDR_int[4]_net_1 , 
        \HADDR_int[12]_net_1 , \HADDR_int[17] , \HADDR_int[30]_net_1 , 
        \HADDR_9[2] , AHB_BUSY_6, N_139_i_0, N_115_i_0, 
        un1_ahb_fsm_current_state_7_0_net_1, N_143_i_0, N_129_i_0, 
        \ahb_fsm_current_state[0]_net_1 , N_119_i_0, 
        \ahb_fsm_current_state[1]_net_1 , 
        \ahb_fsm_current_state[2]_net_1 , 
        \ahb_fsm_current_state_ns[2]_net_1 , 
        \ahb_fsm_current_state[3]_net_1 , 
        \ahb_fsm_current_state[4]_net_1 , 
        \ahb_fsm_current_state_ns[4] , \ahb_fsm_current_state_ns[5] , 
        \ahb_fsm_current_state[6]_net_1 , N_150, N_138, N_140, 
        un1_ahb_fsm_current_state_9_i_1_net_1, \HADDR_int_m_0_0[2] , 
        \HADDR_int_m_0_0[15] , \HADDR_int_m_0_0[30] , 
        \HADDR_int_m_0_0[4] , \HADDR_int_m_0_0[3] , 
        un1_ahb_fsm_current_state_7_0_1_net_1, 
        \ahb_fsm_current_state_ns_i_1[0]_net_1 , \HADDR_int_m[12] ;
    
    SLE \ahb_fsm_current_state[2]  (.D(
        \ahb_fsm_current_state_ns[2]_net_1 ), .CLK(CCC_0_GL0), .EN(
        VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \ahb_fsm_current_state[2]_net_1 ));
    SLE \DATAOUT[6]  (.D(\DATAOUT_ldmx[6]_net_1 ), .CLK(CCC_0_GL0), 
        .EN(HREADY_M_iv_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[6]));
    SLE \ahb_fsm_current_state[1]  (.D(N_121_i_0), .CLK(CCC_0_GL0), 
        .EN(VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \ahb_fsm_current_state[1]_net_1 ));
    SLE HWRITE (.D(N_115_i_0), .CLK(CCC_0_GL0), .EN(
        un1_ahb_fsm_current_state_7_0_net_1), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(HW_Boot_Engine_0_AHB_IF_HWRITE));
    SLE \HADDR[4]  (.D(\HADDR_9[4] ), .CLK(CCC_0_GL0), .EN(N_137_i_0), 
        .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_AHB_IF_HADDR_2));
    CFG4 #( .INIT(16'hEAC0) )  \HADDR_RNO_0[4]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(ahb_fsm_current_state_5), 
        .C(\HADDR_int[4]_net_1 ), .D(SPI_to_MDDR_0_ADDR_2), .Y(
        \HADDR_int_m_0_0[4] ));
    CFG4 #( .INIT(16'h4F40) )  \DATAOUT_ldmx[7]  (.A(N_95), .B(
        CoreAHBLite_0_AHBmslave4_HRDATA[7]), .C(
        \ahb_fsm_current_state[6]_net_1 ), .D(AHB_IF_0_DATAOUT[7]), .Y(
        \DATAOUT_ldmx[7]_net_1 ));
    CFG3 #( .INIT(8'hBA) )  un1_ahb_fsm_current_state_7_0 (.A(
        un1_ahb_fsm_current_state_7_0_1_net_1), .B(HREADY_M_iv_i_0), 
        .C(ahb_fsm_current_state_5), .Y(
        un1_ahb_fsm_current_state_7_0_net_1));
    CFG3 #( .INIT(8'hFE) )  un1_ahb_fsm_current_state_7_0_1 (.A(
        \ahb_fsm_current_state[2]_net_1 ), .B(
        \ahb_fsm_current_state[1]_net_1 ), .C(
        \ahb_fsm_current_state[4]_net_1 ), .Y(
        un1_ahb_fsm_current_state_7_0_1_net_1));
    CFG3 #( .INIT(8'hD8) )  \HWDATA_ldmx[0]  (.A(
        \ahb_fsm_current_state[2]_net_1 ), .B(\HWDATA_int[0]_net_1 ), 
        .C(HW_Boot_Engine_0_AHB_IF_HWDATA_0), .Y(
        \HWDATA_ldmx[0]_net_1 ));
    SLE \HADDR[30]  (.D(\HADDR_9[30] ), .CLK(CCC_0_GL0), .EN(N_137_i_0)
        , .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_AHB_IF_HADDR_28));
    CFG2 #( .INIT(4'h2) )  \DATAOUT_RNO[5]  (.A(
        CoreAHBLite_0_AHBmslave4_HRDATA[5]), .B(N_95), .Y(
        \HW_Boot_Engine_0_AHB_IF_HRDATA[5] ));
    CFG4 #( .INIT(16'h4F40) )  \DATAOUT_ldmx[2]  (.A(N_95), .B(
        CoreAHBLite_0_AHBmslave4_HRDATA[2]), .C(
        \ahb_fsm_current_state[6]_net_1 ), .D(AHB_IF_0_DATAOUT[2]), .Y(
        \DATAOUT_ldmx[2]_net_1 ));
    SLE \DATAOUT[1]  (.D(\DATAOUT_ldmx[1]_net_1 ), .CLK(CCC_0_GL0), 
        .EN(HREADY_M_iv_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[1]));
    CFG4 #( .INIT(16'hFF08) )  \HADDR_RNO[2]  (.A(
        \ahb_fsm_current_state[2]_net_1 ), .B(\HADDR_int[2]_net_1 ), 
        .C(HREADY_M_iv_i_0), .D(\HADDR_int_m_0_0[2] ), .Y(\HADDR_9[2] )
        );
    CFG4 #( .INIT(16'h4F40) )  \DATAOUT_ldmx[0]  (.A(N_95), .B(
        CoreAHBLite_0_AHBmslave4_HRDATA[0]), .C(
        \ahb_fsm_current_state[6]_net_1 ), .D(AHB_IF_0_DATAOUT[0]), .Y(
        \DATAOUT_ldmx[0]_net_1 ));
    CFG2 #( .INIT(4'hE) )  HADDR_int_0_sqmuxa_i_o3 (.A(
        SPI_to_MDDR_0_WRITE), .B(SPI_to_MDDR_0_READ), .Y(N_140));
    CFG4 #( .INIT(16'h4405) )  \ahb_fsm_current_state_RNO[0]  (.A(
        \ahb_fsm_current_state_ns_i_1[0]_net_1 ), .B(HREADY_M_iv_i_0), 
        .C(N_140), .D(N_138), .Y(N_119_i_0));
    CFG4 #( .INIT(16'h0111) )  \HTRANS_1_RNO_0[1]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(
        \ahb_fsm_current_state[3]_net_1 ), .C(HREADY_M_iv_i_0_d), .D(
        HREADY_M_iv_i_0_1_0), .Y(N_129_i_0));
    SLE \HWDATA_int[5]  (.D(SPI_to_MDDR_0_DATAOUT_5), .CLK(CCC_0_GL0), 
        .EN(N_121_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HWDATA_int[5]_net_1 ));
    SLE \DATAOUT[0]  (.D(\DATAOUT_ldmx[0]_net_1 ), .CLK(CCC_0_GL0), 
        .EN(HREADY_M_iv_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[0]));
    CFG3 #( .INIT(8'h10) )  un1_ahb_fsm_current_state_0_sqmuxa_1_i_a3 
        (.A(SPI_to_MDDR_0_READ), .B(SPI_to_MDDR_0_WRITE), .C(
        \ahb_fsm_current_state[0]_net_1 ), .Y(N_150));
    CFG3 #( .INIT(8'hF8) )  \HADDR_9_iv[12]  (.A(SPI_to_MDDR_0_ADDR_10)
        , .B(\ahb_fsm_current_state[0]_net_1 ), .C(\HADDR_int_m[12] ), 
        .Y(\HADDR_9[12] ));
    VCC VCC (.Y(VCC_net_1));
    CFG3 #( .INIT(8'hF2) )  \ahb_fsm_current_state_ns[2]  (.A(
        \ahb_fsm_current_state[2]_net_1 ), .B(HREADY_M_iv_i_0), .C(
        \ahb_fsm_current_state[1]_net_1 ), .Y(
        \ahb_fsm_current_state_ns[2]_net_1 ));
    SLE \ahb_fsm_current_state[6]  (.D(ahb_fsm_current_state_5), .CLK(
        CCC_0_GL0), .EN(HREADY_M_iv_i_0), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\ahb_fsm_current_state[6]_net_1 ));
    SLE \ahb_fsm_current_state[0]  (.D(N_119_i_0), .CLK(CCC_0_GL0), 
        .EN(VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(GND_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \ahb_fsm_current_state[0]_net_1 ));
    SLE \HWDATA[10]  (.D(\HWDATA_ldmx[10]_net_1 ), .CLK(CCC_0_GL0), 
        .EN(HREADY_M_iv_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_AHB_IF_HWDATA_18));
    CFG3 #( .INIT(8'h15) )  \HTRANS_1_RNO[1]  (.A(
        \ahb_fsm_current_state[6]_net_1 ), .B(
        \ahb_fsm_current_state[2]_net_1 ), .C(HREADY_M_iv_i_0), .Y(
        N_143_i_0));
    SLE \DATAOUT[4]  (.D(\HW_Boot_Engine_0_AHB_IF_HRDATA[4] ), .CLK(
        CCC_0_GL0), .EN(N_111_i_0), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(AHB_IF_0_DATAOUT[4]));
    CFG4 #( .INIT(16'hFF08) )  \HADDR_RNO[15]  (.A(
        \ahb_fsm_current_state[2]_net_1 ), .B(\HADDR_int[17] ), .C(
        HREADY_M_iv_i_0), .D(\HADDR_int_m_0_0[15] ), .Y(\HADDR_9[17] ));
    CFG4 #( .INIT(16'h44F0) )  \DATAOUT_ldmx[8]  (.A(N_95), .B(
        CoreAHBLite_0_AHBmslave4_HRDATA[8]), .C(AHB_IF_0_DATAOUT[8]), 
        .D(\ahb_fsm_current_state[6]_net_1 ), .Y(
        \DATAOUT_ldmx[8]_net_1 ));
    CFG3 #( .INIT(8'h40) )  \ahb_fsm_current_state_ns_a5[4]  (.A(
        SPI_to_MDDR_0_WRITE), .B(\ahb_fsm_current_state[0]_net_1 ), .C(
        SPI_to_MDDR_0_READ), .Y(\ahb_fsm_current_state_ns[4] ));
    SLE \HWDATA[0]  (.D(\HWDATA_ldmx[0]_net_1 ), .CLK(CCC_0_GL0), .EN(
        HREADY_M_iv_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_AHB_IF_HWDATA_0));
    CFG2 #( .INIT(4'h8) )  \ahb_fsm_current_state_RNIKM6G[0]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(SPI_to_MDDR_0_WRITE), .Y(
        N_121_i_0));
    SLE \HWDATA_int[0]  (.D(SPI_to_MDDR_0_DATAOUT_0), .CLK(CCC_0_GL0), 
        .EN(N_121_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HWDATA_int[0]_net_1 ));
    SLE \HWDATA[4]  (.D(\HWDATA_ldmx[4]_net_1 ), .CLK(CCC_0_GL0), .EN(
        HREADY_M_iv_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_AHB_IF_HWDATA_4));
    CFG4 #( .INIT(16'h4F40) )  \DATAOUT_ldmx[1]  (.A(N_95), .B(
        CoreAHBLite_0_AHBmslave4_HRDATA[1]), .C(
        \ahb_fsm_current_state[6]_net_1 ), .D(AHB_IF_0_DATAOUT[1]), .Y(
        \DATAOUT_ldmx[1]_net_1 ));
    SLE \HWDATA_int[1]  (.D(SPI_to_MDDR_0_DATAOUT_1), .CLK(CCC_0_GL0), 
        .EN(N_121_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HWDATA_int[1]_net_1 ));
    CFG4 #( .INIT(16'hEAC0) )  \HADDR_RNO_0[3]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(ahb_fsm_current_state_5), 
        .C(\HADDR_int[3]_net_1 ), .D(SPI_to_MDDR_0_ADDR_1), .Y(
        \HADDR_int_m_0_0[3] ));
    SLE \HADDR[15]  (.D(\HADDR_9[17] ), .CLK(CCC_0_GL0), .EN(N_137_i_0)
        , .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_AHB_IF_HADDR_14));
    CFG3 #( .INIT(8'h13) )  AHB_BUSY_RNO (.A(HREADY_M_iv_i_0_d), .B(
        N_150), .C(HREADY_M_iv_i_0_1_0), .Y(N_139_i_0));
    CFG4 #( .INIT(16'hEAC0) )  \HADDR_RNO_0[2]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(ahb_fsm_current_state_5), 
        .C(\HADDR_int[2]_net_1 ), .D(SPI_to_MDDR_0_ADDR_0), .Y(
        \HADDR_int_m_0_0[2] ));
    SLE \ahb_fsm_current_state[3]  (.D(
        \ahb_fsm_current_state[2]_net_1 ), .CLK(CCC_0_GL0), .EN(
        HREADY_M_iv_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \ahb_fsm_current_state[3]_net_1 ));
    SLE \HADDR[3]  (.D(\HADDR_9[3] ), .CLK(CCC_0_GL0), .EN(N_137_i_0), 
        .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_AHB_IF_HADDR_1));
    GND GND (.Y(GND_net_1));
    CFG2 #( .INIT(4'h2) )  \DATAOUT_RNO[4]  (.A(
        CoreAHBLite_0_AHBmslave4_HRDATA[4]), .B(N_95), .Y(
        \HW_Boot_Engine_0_AHB_IF_HRDATA[4] ));
    CFG2 #( .INIT(4'hE) )  AHB_BUSY_6_0_o3 (.A(
        \ahb_fsm_current_state[6]_net_1 ), .B(
        \ahb_fsm_current_state[3]_net_1 ), .Y(N_138));
    CFG3 #( .INIT(8'hD8) )  \HWDATA_ldmx[5]  (.A(
        \ahb_fsm_current_state[2]_net_1 ), .B(\HWDATA_int[5]_net_1 ), 
        .C(HW_Boot_Engine_0_AHB_IF_HWDATA_5), .Y(
        \HWDATA_ldmx[5]_net_1 ));
    SLE \HWDATA_int[7]  (.D(SPI_to_MDDR_0_DATAOUT_7), .CLK(CCC_0_GL0), 
        .EN(N_121_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HWDATA_int[7]_net_1 ));
    SLE \HWDATA_int[3]  (.D(SPI_to_MDDR_0_DATAOUT_3), .CLK(CCC_0_GL0), 
        .EN(N_121_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HWDATA_int[3]_net_1 ));
    CFG4 #( .INIT(16'hFF08) )  \HADDR_RNO[3]  (.A(
        \ahb_fsm_current_state[2]_net_1 ), .B(\HADDR_int[3]_net_1 ), 
        .C(HREADY_M_iv_i_0), .D(\HADDR_int_m_0_0[3] ), .Y(\HADDR_9[3] )
        );
    CFG2 #( .INIT(4'h8) )  HADDR_int_0_sqmuxa_i_o3_RNIHV0B (.A(N_140), 
        .B(\ahb_fsm_current_state[0]_net_1 ), .Y(N_117_i_0));
    CFG4 #( .INIT(16'h0111) )  HWRITE_RNO (.A(ahb_fsm_current_state_5), 
        .B(\ahb_fsm_current_state[4]_net_1 ), .C(HREADY_M_iv_i_0), .D(
        \ahb_fsm_current_state[2]_net_1 ), .Y(N_115_i_0));
    SLE \HWDATA[3]  (.D(\HWDATA_ldmx[3]_net_1 ), .CLK(CCC_0_GL0), .EN(
        HREADY_M_iv_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_AHB_IF_HWDATA_3));
    SLE \ahb_fsm_current_state[5]  (.D(\ahb_fsm_current_state_ns[5] ), 
        .CLK(CCC_0_GL0), .EN(VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(ahb_fsm_current_state_5));
    CFG4 #( .INIT(16'h4F40) )  \DATAOUT_ldmx[6]  (.A(N_95), .B(
        CoreAHBLite_0_AHBmslave4_HRDATA[6]), .C(
        \ahb_fsm_current_state[6]_net_1 ), .D(AHB_IF_0_DATAOUT[6]), .Y(
        \DATAOUT_ldmx[6]_net_1 ));
    SLE \ahb_fsm_current_state[4]  (.D(\ahb_fsm_current_state_ns[4] ), 
        .CLK(CCC_0_GL0), .EN(VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\ahb_fsm_current_state[4]_net_1 ));
    SLE \HWDATA[5]  (.D(\HWDATA_ldmx[5]_net_1 ), .CLK(CCC_0_GL0), .EN(
        HREADY_M_iv_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_AHB_IF_HWDATA_5));
    SLE \HADDR_int[3]  (.D(SPI_to_MDDR_0_ADDR_1), .CLK(CCC_0_GL0), .EN(
        N_117_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[3]_net_1 ));
    SLE \HADDR_int[2]  (.D(SPI_to_MDDR_0_ADDR_0), .CLK(CCC_0_GL0), .EN(
        N_117_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[2]_net_1 ));
    CFG3 #( .INIT(8'hD8) )  \HWDATA_ldmx[6]  (.A(
        \ahb_fsm_current_state[2]_net_1 ), .B(\HWDATA_int[6]_net_1 ), 
        .C(HW_Boot_Engine_0_AHB_IF_HWDATA_6), .Y(
        \HWDATA_ldmx[6]_net_1 ));
    CFG3 #( .INIT(8'hFE) )  un1_ahb_fsm_current_state_9_i_1 (.A(
        \ahb_fsm_current_state[1]_net_1 ), .B(
        \ahb_fsm_current_state[4]_net_1 ), .C(
        \ahb_fsm_current_state[3]_net_1 ), .Y(
        un1_ahb_fsm_current_state_9_i_1_net_1));
    SLE \HADDR_int[15]  (.D(SPI_to_MDDR_0_ADDR_14), .CLK(CCC_0_GL0), 
        .EN(N_117_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[17] ));
    SLE \HADDR[12]  (.D(\HADDR_9[12] ), .CLK(CCC_0_GL0), .EN(N_137_i_0)
        , .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_AHB_IF_HADDR_10));
    CFG3 #( .INIT(8'hD8) )  \HWDATA_ldmx[10]  (.A(
        \ahb_fsm_current_state[2]_net_1 ), .B(\HWDATA_int[25] ), .C(
        HW_Boot_Engine_0_AHB_IF_HWDATA_18), .Y(\HWDATA_ldmx[10]_net_1 )
        );
    SLE \DATAOUT[8]  (.D(\DATAOUT_ldmx[8]_net_1 ), .CLK(CCC_0_GL0), 
        .EN(HREADY_M_iv_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[8]));
    CFG1 #( .INIT(2'h1) )  AHB_BUSY_RNI796A (.A(AHB_IF_0_AHB_BUSY), .Y(
        AHB_IF_0_AHB_BUSY_i_0));
    CFG3 #( .INIT(8'hD8) )  \HWDATA_ldmx[7]  (.A(
        \ahb_fsm_current_state[2]_net_1 ), .B(\HWDATA_int[7]_net_1 ), 
        .C(HW_Boot_Engine_0_AHB_IF_HWDATA_7), .Y(
        \HWDATA_ldmx[7]_net_1 ));
    CFG3 #( .INIT(8'hD8) )  \HWDATA_ldmx[2]  (.A(
        \ahb_fsm_current_state[2]_net_1 ), .B(\HWDATA_int[2]_net_1 ), 
        .C(HW_Boot_Engine_0_AHB_IF_HWDATA_2), .Y(
        \HWDATA_ldmx[2]_net_1 ));
    CFG4 #( .INIT(16'hEAC0) )  \HADDR_RNO_0[15]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(ahb_fsm_current_state_5), 
        .C(\HADDR_int[17] ), .D(SPI_to_MDDR_0_ADDR_14), .Y(
        \HADDR_int_m_0_0[15] ));
    SLE \DATAOUT[3]  (.D(\DATAOUT_ldmx[3]_net_1 ), .CLK(CCC_0_GL0), 
        .EN(HREADY_M_iv_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[3]));
    SLE \HWDATA[7]  (.D(\HWDATA_ldmx[7]_net_1 ), .CLK(CCC_0_GL0), .EN(
        HREADY_M_iv_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_AHB_IF_HWDATA_7));
    SLE \HWDATA_int[10]  (.D(SPI_to_MDDR_0_DATAOUT_18), .CLK(CCC_0_GL0)
        , .EN(N_121_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HWDATA_int[25] ));
    SLE \DATAOUT[7]  (.D(\DATAOUT_ldmx[7]_net_1 ), .CLK(CCC_0_GL0), 
        .EN(HREADY_M_iv_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[7]));
    CFG3 #( .INIT(8'hD8) )  \HWDATA_ldmx[4]  (.A(
        \ahb_fsm_current_state[2]_net_1 ), .B(\HWDATA_int[4]_net_1 ), 
        .C(HW_Boot_Engine_0_AHB_IF_HWDATA_4), .Y(
        \HWDATA_ldmx[4]_net_1 ));
    SLE \HWDATA[1]  (.D(\HWDATA_ldmx[1]_net_1 ), .CLK(CCC_0_GL0), .EN(
        HREADY_M_iv_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_AHB_IF_HWDATA_1));
    SLE \HADDR_int[30]  (.D(SPI_to_MDDR_0_ADDR_28), .CLK(CCC_0_GL0), 
        .EN(N_117_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[30]_net_1 ));
    SLE \HWDATA[6]  (.D(\HWDATA_ldmx[6]_net_1 ), .CLK(CCC_0_GL0), .EN(
        HREADY_M_iv_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_AHB_IF_HWDATA_6));
    SLE \HTRANS_1[1]  (.D(N_143_i_0), .CLK(CCC_0_GL0), .EN(N_129_i_0), 
        .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_AHB_IF_HTRANS[1]));
    CFG4 #( .INIT(16'hFF08) )  \HADDR_RNO[4]  (.A(
        \ahb_fsm_current_state[2]_net_1 ), .B(\HADDR_int[4]_net_1 ), 
        .C(HREADY_M_iv_i_0), .D(\HADDR_int_m_0_0[4] ), .Y(\HADDR_9[4] )
        );
    SLE \DATAOUT[2]  (.D(\DATAOUT_ldmx[2]_net_1 ), .CLK(CCC_0_GL0), 
        .EN(HREADY_M_iv_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[2]));
    CFG3 #( .INIT(8'hF2) )  \ahb_fsm_current_state_ns_o5[5]  (.A(
        ahb_fsm_current_state_5), .B(HREADY_M_iv_i_0), .C(
        \ahb_fsm_current_state[4]_net_1 ), .Y(
        \ahb_fsm_current_state_ns[5] ));
    CFG3 #( .INIT(8'hD8) )  \HWDATA_ldmx[3]  (.A(
        \ahb_fsm_current_state[2]_net_1 ), .B(\HWDATA_int[3]_net_1 ), 
        .C(HW_Boot_Engine_0_AHB_IF_HWDATA_3), .Y(
        \HWDATA_ldmx[3]_net_1 ));
    SLE \HWDATA[2]  (.D(\HWDATA_ldmx[2]_net_1 ), .CLK(CCC_0_GL0), .EN(
        HREADY_M_iv_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_AHB_IF_HWDATA_2));
    SLE \DATAOUT[5]  (.D(\HW_Boot_Engine_0_AHB_IF_HRDATA[5] ), .CLK(
        CCC_0_GL0), .EN(N_111_i_0), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(AHB_IF_0_DATAOUT[5]));
    CFG4 #( .INIT(16'hFFFE) )  \ahb_fsm_current_state_ns_i_1[0]  (.A(
        \ahb_fsm_current_state[4]_net_1 ), .B(
        \ahb_fsm_current_state[1]_net_1 ), .C(
        \ahb_fsm_current_state[2]_net_1 ), .D(ahb_fsm_current_state_5), 
        .Y(\ahb_fsm_current_state_ns_i_1[0]_net_1 ));
    SLE AHB_BUSY (.D(AHB_BUSY_6), .CLK(CCC_0_GL0), .EN(N_139_i_0), 
        .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AHB_IF_0_AHB_BUSY));
    CFG4 #( .INIT(16'h8C88) )  \HADDR_9_iv_RNO[12]  (.A(
        ahb_fsm_current_state_5), .B(\HADDR_int[12]_net_1 ), .C(
        HREADY_M_iv_i_0), .D(\ahb_fsm_current_state[2]_net_1 ), .Y(
        \HADDR_int_m[12] ));
    CFG4 #( .INIT(16'hFF08) )  \HADDR_RNO[30]  (.A(
        \ahb_fsm_current_state[2]_net_1 ), .B(\HADDR_int[30]_net_1 ), 
        .C(HREADY_M_iv_i_0), .D(\HADDR_int_m_0_0[30] ), .Y(
        \HADDR_9[30] ));
    CFG2 #( .INIT(4'h7) )  AHB_BUSY_6_0 (.A(HREADY_M_iv_i_0), .B(N_138)
        , .Y(AHB_BUSY_6));
    CFG2 #( .INIT(4'h8) )  \ahb_fsm_current_state_RNIEKKA1[6]  (.A(
        HREADY_M_iv_i_0), .B(\ahb_fsm_current_state[6]_net_1 ), .Y(
        N_111_i_0));
    CFG4 #( .INIT(16'hEAC0) )  \HADDR_RNO_0[30]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(ahb_fsm_current_state_5), 
        .C(\HADDR_int[30]_net_1 ), .D(SPI_to_MDDR_0_ADDR_28), .Y(
        \HADDR_int_m_0_0[30] ));
    SLE \HADDR[2]  (.D(\HADDR_9[2] ), .CLK(CCC_0_GL0), .EN(N_137_i_0), 
        .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_AHB_IF_HADDR_0));
    SLE \HWDATA_int[6]  (.D(SPI_to_MDDR_0_DATAOUT_6), .CLK(CCC_0_GL0), 
        .EN(N_121_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HWDATA_int[6]_net_1 ));
    SLE \HADDR_int[12]  (.D(SPI_to_MDDR_0_ADDR_10), .CLK(CCC_0_GL0), 
        .EN(N_117_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[12]_net_1 ));
    SLE \HWDATA_int[4]  (.D(SPI_to_MDDR_0_DATAOUT_4), .CLK(CCC_0_GL0), 
        .EN(N_121_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HWDATA_int[4]_net_1 ));
    CFG3 #( .INIT(8'hD8) )  \HWDATA_ldmx[1]  (.A(
        \ahb_fsm_current_state[2]_net_1 ), .B(\HWDATA_int[1]_net_1 ), 
        .C(HW_Boot_Engine_0_AHB_IF_HWDATA_1), .Y(
        \HWDATA_ldmx[1]_net_1 ));
    SLE \HADDR_int[4]  (.D(SPI_to_MDDR_0_ADDR_2), .CLK(CCC_0_GL0), .EN(
        N_117_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[4]_net_1 ));
    SLE \HWDATA_int[2]  (.D(SPI_to_MDDR_0_DATAOUT_2), .CLK(CCC_0_GL0), 
        .EN(N_121_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HWDATA_int[2]_net_1 ));
    CFG4 #( .INIT(16'h0111) )  
        un1_ahb_fsm_current_state_9_i_1_RNIF2VA2 (.A(N_150), .B(
        un1_ahb_fsm_current_state_9_i_1_net_1), .C(HREADY_M_iv_i_0_d), 
        .D(HREADY_M_iv_i_0_1_0), .Y(N_137_i_0));
    CFG4 #( .INIT(16'h4F40) )  \DATAOUT_ldmx[3]  (.A(N_95), .B(
        CoreAHBLite_0_AHBmslave4_HRDATA[3]), .C(
        \ahb_fsm_current_state[6]_net_1 ), .D(AHB_IF_0_DATAOUT[3]), .Y(
        \DATAOUT_ldmx[3]_net_1 ));
    
endmodule


module SPI_to_MDDR_Z9(
       SPI_to_MDDR_0_AXI_DATA,
       AHB_IF_0_DATAOUT,
       SPI_to_MDDR_0_ADDR_0,
       SPI_to_MDDR_0_ADDR_1,
       SPI_to_MDDR_0_ADDR_2,
       SPI_to_MDDR_0_ADDR_28,
       SPI_to_MDDR_0_ADDR_14,
       SPI_to_MDDR_0_ADDR_10,
       SPI_to_MDDR_0_DATAOUT_0,
       SPI_to_MDDR_0_DATAOUT_1,
       SPI_to_MDDR_0_DATAOUT_2,
       SPI_to_MDDR_0_DATAOUT_3,
       SPI_to_MDDR_0_DATAOUT_4,
       SPI_to_MDDR_0_DATAOUT_5,
       SPI_to_MDDR_0_DATAOUT_6,
       SPI_to_MDDR_0_DATAOUT_7,
       SPI_to_MDDR_0_DATAOUT_18,
       CCC_0_GL0,
       MSS_HPMS_READY,
       SPI_to_MDDR_0_READ,
       SPI_to_MDDR_0_WRITE,
       GPIO_0_M2F_0,
       SPI_to_MDDR_0_AXI_WRITE,
       AHB_IF_0_AHB_BUSY_i_0,
       AHB_IF_0_AHB_BUSY,
       AXI_IF_0_AXI_BUSY,
       DP_SW1_c
    );
output [63:0] SPI_to_MDDR_0_AXI_DATA;
input  [8:0] AHB_IF_0_DATAOUT;
output SPI_to_MDDR_0_ADDR_0;
output SPI_to_MDDR_0_ADDR_1;
output SPI_to_MDDR_0_ADDR_2;
output SPI_to_MDDR_0_ADDR_28;
output SPI_to_MDDR_0_ADDR_14;
output SPI_to_MDDR_0_ADDR_10;
output SPI_to_MDDR_0_DATAOUT_0;
output SPI_to_MDDR_0_DATAOUT_1;
output SPI_to_MDDR_0_DATAOUT_2;
output SPI_to_MDDR_0_DATAOUT_3;
output SPI_to_MDDR_0_DATAOUT_4;
output SPI_to_MDDR_0_DATAOUT_5;
output SPI_to_MDDR_0_DATAOUT_6;
output SPI_to_MDDR_0_DATAOUT_7;
output SPI_to_MDDR_0_DATAOUT_18;
input  CCC_0_GL0;
input  MSS_HPMS_READY;
output SPI_to_MDDR_0_READ;
output SPI_to_MDDR_0_WRITE;
output GPIO_0_M2F_0;
output SPI_to_MDDR_0_AXI_WRITE;
input  AHB_IF_0_AHB_BUSY_i_0;
input  AHB_IF_0_AHB_BUSY;
input  AXI_IF_0_AXI_BUSY;
input  DP_SW1_c;

    wire \nblocks[0]_net_1 , \nblocks_s[0] , \nbytes[2]_net_1 , 
        \nbytes_i_0[2] , \nbytes[1]_net_1 , \nbytes_i_0[1] , 
        \nbytes[0]_net_1 , \nbytes_i_0[0] , AXI_DATA_0_sqmuxa_reto, 
        VCC_net_1, AXI_DATA_0_sqmuxa, GND_net_1, \nbytes[4]_net_1 , 
        \nbytes_10[4] , \nbytes[5]_net_1 , \nbytes_10[5] , 
        \nbytes[6]_net_1 , \nbytes_10[6] , \nbytes[7]_net_1 , 
        \nbytes_10[7] , \nbytes[8]_net_1 , \nbytes_10[8] , 
        \nbytes[9]_net_1 , \nbytes_10[9] , \nbytes[10]_net_1 , 
        \nbytes_10[10] , \nbytes[11]_net_1 , \nbytes_10[11] , 
        \CMD_count[0]_net_1 , N_52_i_0, \CMD_count[1]_net_1 , N_50_i_0, 
        \CMD_count[2]_net_1 , N_48_i_0, \CMD[0]_net_1 , N_46_i_0, 
        \CMD[1]_net_1 , N_44_i_0, \CMD[2]_net_1 , \CMD_6[2] , 
        \CMD[3]_net_1 , \CMD_6[3] , \CMD[4]_net_1 , \CMD_6[4] , 
        \CMD[5]_net_1 , \CMD_6[5] , \CMD[6]_net_1 , \CMD_6[6] , 
        \CMD[7]_net_1 , \CMD_6[7] , \reg_count[0]_net_1 , N_320_i_0, 
        \reg_count[1]_net_1 , N_322_i_0, \reg_count[2]_net_1 , 
        N_324_i_0, \nbytes_10[0] , \nbytes_10[1] , N_34_i_0, 
        \nbytes[3]_net_1 , \nbytes_10[3] , \block_address[20]_net_1 , 
        un2_block_address_1_cry_10_S, CMD_count_0_sqmuxa_1, 
        \block_address[21]_net_1 , un2_block_address_1_cry_11_S, 
        \block_address[22]_net_1 , un2_block_address_1_cry_12_S, 
        \block_address[23]_net_1 , un2_block_address_1_s_13_S, N_869, 
        un1_M3_RESETn_0_sqmuxa_2_net_1, \DATAOUT_14[1] , 
        \DATAOUT_14[2] , \DATAOUT_14[3] , \DATAOUT_14[4] , 
        \DATAOUT_14[5] , \DATAOUT_14[6] , \DATAOUT_14[7] , N_315_i_0, 
        un1_READ_0_sqmuxa_2_net_1, N_853, N_849_i_0, 
        \AXI_DATA_reto[27] , \AXI_DATA_reto[28] , \AXI_DATA_reto[29] , 
        \AXI_DATA_reto[30] , \AXI_DATA_reto[31] , 
        \block_address[10]_net_1 , block_address_238_net_1, 
        \block_address[11]_net_1 , un2_block_address_1_cry_1_S, 
        \block_address[12]_net_1 , un2_block_address_1_cry_2_S, 
        \block_address[13]_net_1 , un2_block_address_1_cry_3_S, 
        \block_address[14]_net_1 , un2_block_address_1_cry_4_S, 
        \block_address[15]_net_1 , un2_block_address_1_cry_5_S, 
        \block_address[16]_net_1 , un2_block_address_1_cry_6_S, 
        \block_address[17]_net_1 , un2_block_address_1_cry_7_S, 
        \block_address[18]_net_1 , un2_block_address_1_cry_8_S, 
        \block_address[19]_net_1 , un2_block_address_1_cry_9_S, 
        \AXI_DATA_reto[12] , \AXI_DATA_reto[13] , \AXI_DATA_reto[14] , 
        \AXI_DATA_reto[15] , \AXI_DATA_reto[24] , \AXI_DATA_reto[25] , 
        \AXI_DATA_reto[26] , \AXI_DATA_reto[8] , \AXI_DATA_reto[9] , 
        \AXI_DATA_reto[10] , \AXI_DATA_reto[11] , \AXI_DATA_reto[38] , 
        \AXI_DATA_reto[39] , \AXI_DATA_reto[47] , \AXI_DATA_reto[32] , 
        \AXI_DATA_reto[33] , \AXI_DATA_reto[34] , \AXI_DATA_reto[35] , 
        \AXI_DATA_reto[36] , \AXI_DATA_reto[37] , \AXI_DATA_reto[48] , 
        \AXI_DATA_reto[49] , \AXI_DATA_reto[50] , \AXI_DATA_reto[51] , 
        \AXI_DATA_reto[52] , \AXI_DATA_reto[53] , \AXI_DATA_reto[54] , 
        \AXI_DATA_reto[55] , \AXI_DATA_reto[40] , \AXI_DATA_reto[41] , 
        \AXI_DATA_reto[42] , \AXI_DATA_reto[43] , \AXI_DATA_reto[44] , 
        \AXI_DATA_reto[45] , \AXI_DATA_reto[46] , \AXI_DATA_reto[56] , 
        \AXI_DATA_reto[57] , \AXI_DATA_reto[58] , \AXI_DATA_reto[59] , 
        \AXI_DATA_reto[60] , \AXI_DATA_reto[61] , \AXI_DATA_reto[62] , 
        \AXI_DATA_reto[63] , \AXI_DATA_reto[0] , \AXI_DATA_reto[1] , 
        \AXI_DATA_reto[2] , \AXI_DATA_reto[3] , \AXI_DATA_reto[4] , 
        \AXI_DATA_reto[5] , \AXI_DATA_reto[6] , \AXI_DATA_reto[7] , 
        \AXI_DATA_reto[19] , \AXI_DATA_reto[20] , \AXI_DATA_reto[21] , 
        \AXI_DATA_reto[22] , \AXI_DATA_reto[23] , \AXI_DATA_reto[16] , 
        \AXI_DATA_reto[17] , \AXI_DATA_reto[18] , AXI_DATA_rst_net_1, 
        N_385_1, N_311_i_0, \SPI_current_state[11]_net_1 , 
        SPI_current_state_1_sqmuxa_1, N_820_i_0, 
        un1_WRITE_0_sqmuxa_net_1, N_313_i_0, N_383_i_0, 
        un1_SPI_current_state_7_0_net_1, \SPI_current_state[10]_net_1 , 
        N_267_i_0, \SPI_current_state[8]_net_1 , 
        \SPI_current_state_ns[8]_net_1 , \SPI_current_state[9]_net_1 , 
        N_284_i_0, \SPI_current_state_ns[11] , 
        \SPI_current_state[12]_net_1 , 
        \SPI_current_state_ns[12]_net_1 , 
        \SPI_current_state[13]_net_1 , N_288_i_0, 
        \SPI_current_state[14]_net_1 , 
        \SPI_current_state_ns_a5[14]_net_1 , 
        \SPI_current_state[0]_net_1 , \SPI_current_state_ns[0]_net_1 , 
        \SPI_current_state[1]_net_1 , N_271_i_0, 
        \SPI_current_state[2]_net_1 , \SPI_current_state[4]_net_1 , 
        \SPI_current_state[3]_net_1 , \SPI_current_state_ns[3] , 
        \SPI_current_state[5]_net_1 , \SPI_current_state[6]_net_1 , 
        \SPI_current_state[7]_net_1 , \nblocks[1]_net_1 , 
        \nblocks_s[1] , \nblocks[2]_net_1 , \nblocks_s[2] , 
        \nblocks[3]_net_1 , \nblocks_s[3] , \nblocks[4]_net_1 , 
        \nblocks_s[4] , \nblocks[5]_net_1 , \nblocks_s[5] , 
        \nblocks[6]_net_1 , \nblocks_s[6] , \nblocks[7]_net_1 , 
        \nblocks_s[7]_net_1 , un1_nbytes_2_cry_0, 
        un1_nbytes_2_cry_0_0_Y, N_36, un1_nbytes_2_cry_1_net_1, 
        un1_nbytes_2_cry_1_S, un1_nbytes_2_cry_2_net_1, 
        un1_nbytes_2_cry_2_S, un1_nbytes_2_cry_3_net_1, 
        un1_nbytes_2_cry_3_S, N_765, N_63, un1_nbytes_2_cry_4_net_1, 
        un1_nbytes_2_cry_4_S, un1_nbytes_2_cry_5_net_1, 
        un1_nbytes_2_cry_5_S, un1_nbytes_2_cry_6_net_1, 
        un1_nbytes_2_cry_6_S, un1_nbytes_2_cry_7_net_1, 
        un1_nbytes_2_cry_7_S, un1_nbytes_2_cry_8_net_1, 
        un1_nbytes_2_cry_8_S, un1_nbytes_2_cry_9_net_1, 
        un1_nbytes_2_cry_9_S, un1_nbytes_2_s_11_S, 
        un1_nbytes_2_cry_10_net_1, un1_nbytes_2_cry_10_S, 
        un42_AXI_DATA_cry_0_net_1, un42_AXI_DATA_cry_0_Y, 
        un42_AXI_DATA_cry_1_net_1, un42_AXI_DATA_cry_1_S, 
        un42_AXI_DATA_cry_2_net_1, un42_AXI_DATA_cry_2_S, 
        un42_AXI_DATA_cry_3_net_1, un42_AXI_DATA_cry_3_S, 
        un42_AXI_DATA_cry_4_net_1, un42_AXI_DATA_cry_4_S, 
        un42_AXI_DATA_cry_5_net_1, un42_AXI_DATA_cry_5_S, 
        un42_AXI_DATA_cry_6_net_1, un42_AXI_DATA_cry_6_S, 
        un42_AXI_DATA_cry_7_net_1, un42_AXI_DATA_cry_7_S, 
        un42_AXI_DATA_cry_8_net_1, un42_AXI_DATA_cry_8_S, 
        un42_AXI_DATA_s_10_S, un42_AXI_DATA_cry_9_net_1, 
        un42_AXI_DATA_cry_9_S, un30_AXI_DATA_cry_0_net_1, 
        un30_AXI_DATA_cry_0_Y, un30_AXI_DATA_cry_1_net_1, 
        un30_AXI_DATA_cry_1_S, un30_AXI_DATA_cry_2_net_1, 
        un30_AXI_DATA_cry_2_S, un30_AXI_DATA_cry_3_net_1, 
        un30_AXI_DATA_cry_3_S, un30_AXI_DATA_cry_4_net_1, 
        un30_AXI_DATA_cry_4_S, un30_AXI_DATA_cry_5_net_1, 
        un30_AXI_DATA_cry_5_S, un30_AXI_DATA_cry_6_net_1, 
        un30_AXI_DATA_cry_6_S, un30_AXI_DATA_cry_7_net_1, 
        un30_AXI_DATA_cry_7_S, un30_AXI_DATA_cry_8_net_1, 
        un30_AXI_DATA_cry_8_S, un30_AXI_DATA_s_10_S, 
        un30_AXI_DATA_cry_9_net_1, un30_AXI_DATA_cry_9_S, 
        un18_AXI_DATA_cry_0_net_1, un18_AXI_DATA_cry_0_Y, 
        un18_AXI_DATA_cry_1_net_1, un18_AXI_DATA_cry_1_S, 
        un18_AXI_DATA_cry_2_net_1, un18_AXI_DATA_cry_2_S, 
        un18_AXI_DATA_cry_3_net_1, un18_AXI_DATA_cry_3_S, 
        un18_AXI_DATA_cry_4_net_1, un18_AXI_DATA_cry_4_S, 
        un18_AXI_DATA_cry_5_net_1, un18_AXI_DATA_cry_5_S, 
        un18_AXI_DATA_cry_6_net_1, un18_AXI_DATA_cry_6_S, 
        un18_AXI_DATA_cry_7_net_1, un18_AXI_DATA_cry_7_S, 
        un18_AXI_DATA_cry_8_net_1, un18_AXI_DATA_cry_8_S, 
        un18_AXI_DATA_s_10_S, un18_AXI_DATA_cry_9_net_1, 
        un18_AXI_DATA_cry_9_S, un36_AXI_DATA_cry_0_net_1, 
        un36_AXI_DATA_cry_0_Y, un36_AXI_DATA_cry_1_net_1, 
        un36_AXI_DATA_cry_1_S, un36_AXI_DATA_cry_2_net_1, 
        un36_AXI_DATA_cry_2_S, un36_AXI_DATA_cry_3_net_1, 
        un36_AXI_DATA_cry_3_S, un36_AXI_DATA_cry_4_net_1, 
        un36_AXI_DATA_cry_4_S, un36_AXI_DATA_cry_5_net_1, 
        un36_AXI_DATA_cry_5_S, un36_AXI_DATA_cry_6_net_1, 
        un36_AXI_DATA_cry_6_S, un36_AXI_DATA_cry_7_net_1, 
        un36_AXI_DATA_cry_7_S, un36_AXI_DATA_s_9_S, 
        un36_AXI_DATA_cry_8_net_1, un36_AXI_DATA_cry_8_S, 
        nblocks_s_305_FCO, \nblocks_cry[1]_net_1 , 
        \nblocks_cry[2]_net_1 , \nblocks_cry[3]_net_1 , 
        \nblocks_cry[4]_net_1 , \nblocks_cry[5]_net_1 , 
        \nblocks_cry[6]_net_1 , un2_block_address_1_s_1_308_FCO, 
        un2_block_address_1_cry_1_net_1, 
        un2_block_address_1_cry_2_net_1, 
        un2_block_address_1_cry_3_net_1, 
        un2_block_address_1_cry_4_net_1, 
        un2_block_address_1_cry_5_net_1, 
        un2_block_address_1_cry_6_net_1, 
        un2_block_address_1_cry_7_net_1, 
        un2_block_address_1_cry_8_net_1, 
        un2_block_address_1_cry_9_net_1, 
        un2_block_address_1_cry_10_net_1, 
        un2_block_address_1_cry_11_net_1, 
        un2_block_address_1_cry_12_net_1, un5_AXI_DATA_s_1_309_FCO, 
        un5_AXI_DATA_cry_1_net_1, un5_AXI_DATA_cry_1_S, 
        un5_AXI_DATA_cry_2_net_1, un5_AXI_DATA_cry_2_S, 
        un5_AXI_DATA_cry_3_net_1, un5_AXI_DATA_cry_3_S, 
        un5_AXI_DATA_cry_4_net_1, un5_AXI_DATA_cry_4_S, 
        un5_AXI_DATA_cry_5_net_1, un5_AXI_DATA_cry_5_S, 
        un5_AXI_DATA_cry_6_net_1, un5_AXI_DATA_cry_6_S, 
        un5_AXI_DATA_cry_7_net_1, un5_AXI_DATA_cry_7_S, 
        un5_AXI_DATA_cry_8_net_1, un5_AXI_DATA_cry_8_S, 
        un5_AXI_DATA_s_10_S, un5_AXI_DATA_cry_9_net_1, 
        un5_AXI_DATA_cry_9_S, un12_AXI_DATA_s_1_311_FCO, 
        un12_AXI_DATA_cry_1_net_1, un12_AXI_DATA_cry_1_S, 
        un12_AXI_DATA_cry_2_net_1, un12_AXI_DATA_cry_2_S, 
        un12_AXI_DATA_cry_3_net_1, un12_AXI_DATA_cry_3_S, 
        un12_AXI_DATA_cry_4_net_1, un12_AXI_DATA_cry_4_S, 
        un12_AXI_DATA_cry_5_net_1, un12_AXI_DATA_cry_5_S, 
        un12_AXI_DATA_cry_6_net_1, un12_AXI_DATA_cry_6_S, 
        un12_AXI_DATA_cry_7_net_1, un12_AXI_DATA_cry_7_S, 
        un12_AXI_DATA_s_9_S, un12_AXI_DATA_cry_8_net_1, 
        un12_AXI_DATA_cry_8_S, un24_AXI_DATA_s_1_312_FCO, 
        un24_AXI_DATA_cry_1_net_1, un24_AXI_DATA_cry_1_S, 
        un24_AXI_DATA_cry_2_net_1, un24_AXI_DATA_cry_2_S, 
        un24_AXI_DATA_cry_3_net_1, un24_AXI_DATA_cry_3_S, 
        un24_AXI_DATA_cry_4_net_1, un24_AXI_DATA_cry_4_S, 
        un24_AXI_DATA_cry_5_net_1, un24_AXI_DATA_cry_5_S, 
        un24_AXI_DATA_cry_6_net_1, un24_AXI_DATA_cry_6_S, 
        un24_AXI_DATA_s_8_S, un24_AXI_DATA_cry_7_net_1, 
        un24_AXI_DATA_cry_7_S, \read_byte_reto[56] , 
        \read_byte_reto[57] , \read_byte_reto[58] , 
        \read_byte_reto[59] , \read_byte_reto[60] , 
        \read_byte_reto[61] , \read_byte_reto[62] , 
        \read_byte_reto[63] , read_byte_read_byte_0_0_we, 
        \read_byte_reto[48] , \read_byte_reto[49] , 
        \read_byte_reto[50] , \read_byte_reto[51] , 
        \read_byte_reto[52] , \read_byte_reto[53] , 
        \read_byte_reto[54] , \read_byte_reto[55] , 
        read_byte_0_read_byte_0_0_we, \read_byte_reto[40] , 
        \read_byte_reto[41] , \read_byte_reto[42] , 
        \read_byte_reto[43] , \read_byte_reto[44] , 
        \read_byte_reto[45] , \read_byte_reto[46] , 
        \read_byte_reto[47] , read_byte_1_read_byte_0_0_we, 
        \read_byte_reto[32] , \read_byte_reto[33] , 
        \read_byte_reto[34] , \read_byte_reto[35] , 
        \read_byte_reto[36] , \read_byte_reto[37] , 
        \read_byte_reto[38] , \read_byte_reto[39] , 
        read_byte_2_read_byte_0_0_we, \read_byte_reto[24] , 
        \read_byte_reto[25] , \read_byte_reto[26] , 
        \read_byte_reto[27] , \read_byte_reto[28] , 
        \read_byte_reto[29] , \read_byte_reto[30] , 
        \read_byte_reto[31] , read_byte_3_read_byte_0_0_we, 
        \read_byte_reto[16] , \read_byte_reto[17] , 
        \read_byte_reto[18] , \read_byte_reto[19] , 
        \read_byte_reto[20] , \read_byte_reto[21] , 
        \read_byte_reto[22] , \read_byte_reto[23] , 
        read_byte_4_read_byte_0_0_we, \read_byte_reto[8] , 
        \read_byte_reto[9] , \read_byte_reto[10] , 
        \read_byte_reto[11] , \read_byte_reto[12] , 
        \read_byte_reto[13] , \read_byte_reto[14] , 
        \read_byte_reto[15] , \read_byte_reto[0] , \read_byte_reto[1] , 
        \read_byte_reto[2] , \read_byte_reto[3] , \read_byte_reto[4] , 
        \read_byte_reto[5] , \read_byte_reto[6] , \read_byte_reto[7] , 
        un1_RESETn_net_1, N_378, N_884, N_34_i_1, N_59, 
        un1_nbyteslto11_0_a2_5_net_1, un1_nbyteslto11_0_a2_6_net_1, 
        un41_i_a2_1_net_1, CMD_count_1_sqmuxa, un41_i_a2_7_1_net_1, 
        un41_i_a2_4_net_1, un41_i_a2_7_net_1, N_401, 
        un1_nbyteslto11_0_a2_3_net_1, WRITE_0_sqmuxa_0_a5_1_net_1, 
        N_336, N_335, N_328, un1_nbytes_1_sqmuxa_1_0_net_1, 
        un41_i_a2_2_net_1, WRITE_0_sqmuxa_0_a5_2_net_1, 
        \CMD_count_7_i_0[2]_net_1 , 
        \SPI_current_state_ns_0_a2_0_7_5[11]_net_1 , 
        \SPI_current_state_ns_0_a2_0_7_4[11]_net_1 , 
        \ADDR_17_i_0_a2_0[2] , N_852, N_360, N_379, N_389, N_339_i_0, 
        N_327, un1_READ_0_sqmuxa_2_1_net_1, 
        un1_READ_0_sqmuxa_2_0_net_1, un1_M3_RESETn_0_sqmuxa_2_0_net_1, 
        \SPI_current_state_ns_0_0[3]_net_1 , 
        \SPI_current_state_ns_i_0_0[13]_net_1 , 
        \ADDR_17_i_0_1[2]_net_1 , ADDR_17_1_327_i_1_net_1, 
        WRITE_0_sqmuxa_0_a5_3_net_1, un1_READ_0_sqmuxa_3_i_a5_1_net_1, 
        N_887, reg_count_1_sqmuxa, N_332, DATAOUT_14_iv_365_1_net_1, 
        \ADDR_17_i_0_2[2]_net_1 , nbytes_1_sqmuxa_1_net_1, N_309, 
        N_336_0, N_353, N_313_1, N_284_1, \reg_count_9_i_1[2]_net_1 , 
        \SPI_current_state_ns_0_RNO[3]_net_1 ;
    
    CFG4 #( .INIT(16'hCAC0) )  \SPI_current_state_ns_0_0[3]  (.A(
        \SPI_current_state[7]_net_1 ), .B(\SPI_current_state[3]_net_1 )
        , .C(AHB_IF_0_AHB_BUSY), .D(AHB_IF_0_DATAOUT[6]), .Y(
        \SPI_current_state_ns_0_0[3]_net_1 ));
    RAM1K18 read_byte_1_read_byte_0_0 (.A_DOUT({nc0, nc1, nc2, nc3, 
        nc4, nc5, nc6, nc7, nc8, nc9, \read_byte_reto[47] , 
        \read_byte_reto[46] , \read_byte_reto[45] , 
        \read_byte_reto[44] , \read_byte_reto[43] , 
        \read_byte_reto[42] , \read_byte_reto[41] , 
        \read_byte_reto[40] }), .B_DOUT({nc10, nc11, nc12, nc13, nc14, 
        nc15, nc16, nc17, nc18, nc19, nc20, nc21, nc22, nc23, nc24, 
        nc25, nc26, nc27}), .BUSY(), .A_CLK(CCC_0_GL0), .A_DOUT_CLK(
        VCC_net_1), .A_ARST_N(VCC_net_1), .A_DOUT_EN(VCC_net_1), 
        .A_BLK({VCC_net_1, VCC_net_1, VCC_net_1}), .A_DOUT_ARST_N(
        VCC_net_1), .A_DOUT_SRST_N(VCC_net_1), .A_DIN({GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1}), .A_ADDR({un30_AXI_DATA_s_10_S, 
        un30_AXI_DATA_cry_9_S, un30_AXI_DATA_cry_8_S, 
        un30_AXI_DATA_cry_7_S, un30_AXI_DATA_cry_6_S, 
        un30_AXI_DATA_cry_5_S, un30_AXI_DATA_cry_4_S, 
        un30_AXI_DATA_cry_3_S, un30_AXI_DATA_cry_2_S, 
        un30_AXI_DATA_cry_1_S, un30_AXI_DATA_cry_0_Y, GND_net_1, 
        GND_net_1, GND_net_1}), .A_WEN({GND_net_1, GND_net_1}), .B_CLK(
        CCC_0_GL0), .B_DOUT_CLK(VCC_net_1), .B_ARST_N(VCC_net_1), 
        .B_DOUT_EN(VCC_net_1), .B_BLK({VCC_net_1, VCC_net_1, VCC_net_1})
        , .B_DOUT_ARST_N(VCC_net_1), .B_DOUT_SRST_N(VCC_net_1), .B_DIN({
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        AHB_IF_0_DATAOUT[7], AHB_IF_0_DATAOUT[6], AHB_IF_0_DATAOUT[5], 
        AHB_IF_0_DATAOUT[4], AHB_IF_0_DATAOUT[3], AHB_IF_0_DATAOUT[2], 
        AHB_IF_0_DATAOUT[1], AHB_IF_0_DATAOUT[0]}), .B_ADDR({
        \nbytes[10]_net_1 , \nbytes[9]_net_1 , \nbytes[8]_net_1 , 
        \nbytes[7]_net_1 , \nbytes[6]_net_1 , \nbytes[5]_net_1 , 
        \nbytes[4]_net_1 , \nbytes[3]_net_1 , \nbytes[2]_net_1 , 
        \nbytes[1]_net_1 , \nbytes[0]_net_1 , GND_net_1, GND_net_1, 
        GND_net_1}), .B_WEN({GND_net_1, read_byte_1_read_byte_0_0_we}), 
        .A_EN(VCC_net_1), .A_DOUT_LAT(VCC_net_1), .A_WIDTH({GND_net_1, 
        VCC_net_1, VCC_net_1}), .A_WMODE(GND_net_1), .B_EN(VCC_net_1), 
        .B_DOUT_LAT(VCC_net_1), .B_WIDTH({GND_net_1, VCC_net_1, 
        VCC_net_1}), .B_WMODE(GND_net_1), .SII_LOCK(GND_net_1));
    SLE \AXI_DATA_ret_0[4]  (.D(SPI_to_MDDR_0_AXI_DATA[12]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[12] ));
    CFG4 #( .INIT(16'hC888) )  \SPI_current_state_ns_i_0_1[10]  (.A(
        N_59), .B(AXI_DATA_0_sqmuxa), .C(
        \SPI_current_state_ns_0_a2_0_7_5[11]_net_1 ), .D(
        \SPI_current_state_ns_0_a2_0_7_4[11]_net_1 ), .Y(N_284_1));
    SLE \AXI_DATA_ret_4[7]  (.D(SPI_to_MDDR_0_AXI_DATA[63]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[63] ));
    CFG4 #( .INIT(16'hD800) )  read_byte_1_read_byte_0_0_RNI83431 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[44] ), .C(
        \AXI_DATA_reto[44] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[44]));
    SLE \AXI_DATA_ret_6[0]  (.D(SPI_to_MDDR_0_AXI_DATA[16]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[16] ));
    SLE \SPI_current_state[2]  (.D(\SPI_current_state[4]_net_1 ), .CLK(
        CCC_0_GL0), .EN(AHB_IF_0_AHB_BUSY_i_0), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\SPI_current_state[2]_net_1 ));
    CFG4 #( .INIT(16'hD800) )  read_byte_4_read_byte_0_0_RNIHR241 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[22] ), .C(
        \AXI_DATA_reto[22] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[22]));
    CFG3 #( .INIT(8'h20) )  read_byte_0_read_byte_0_0_RNO (.A(
        MSS_HPMS_READY), .B(AHB_IF_0_AHB_BUSY), .C(
        \SPI_current_state[9]_net_1 ), .Y(read_byte_0_read_byte_0_0_we)
        );
    CFG3 #( .INIT(8'hD0) )  \nbytes_RNO[1]  (.A(N_765), .B(
        un1_nbytes_1_sqmuxa_1_0_net_1), .C(un1_nbytes_2_cry_1_S), .Y(
        \nbytes_10[1] ));
    ARI1 #( .INIT(20'h4AA00) )  un12_AXI_DATA_s_9 (.A(VCC_net_1), .B(
        \nbytes[10]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un12_AXI_DATA_cry_8_net_1), .S(un12_AXI_DATA_s_9_S), .Y(), 
        .FCO());
    CFG3 #( .INIT(8'hD0) )  \nbytes_RNO[9]  (.A(N_765), .B(
        un1_nbytes_1_sqmuxa_1_0_net_1), .C(un1_nbytes_2_cry_9_S), .Y(
        \nbytes_10[9] ));
    SLE \block_address[23]  (.D(un2_block_address_1_s_13_S), .CLK(
        CCC_0_GL0), .EN(CMD_count_0_sqmuxa_1), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\block_address[23]_net_1 ));
    CFG4 #( .INIT(16'hD800) )  \AXI_DATA_ret_0_RNIDOBC1[7]  (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[15] ), .C(
        \AXI_DATA_reto[15] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[15]));
    CFG2 #( .INIT(4'h1) )  WRITE_0_sqmuxa_0_a5_1 (.A(
        \SPI_current_state[0]_net_1 ), .B(\SPI_current_state[1]_net_1 )
        , .Y(WRITE_0_sqmuxa_0_a5_1_net_1));
    SLE \AXI_DATA_ret_1[2]  (.D(SPI_to_MDDR_0_AXI_DATA[34]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[34] ));
    CFG4 #( .INIT(16'hD800) )  \AXI_DATA_ret_4_RNIRUVG1[5]  (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[61] ), .C(
        \AXI_DATA_reto[61] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[61]));
    SLE AXI_DATA_ret_0 (.D(AXI_DATA_0_sqmuxa), .CLK(CCC_0_GL0), .EN(
        VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(AXI_DATA_0_sqmuxa_reto));
    ARI1 #( .INIT(20'h4AA00) )  un5_AXI_DATA_cry_8 (.A(VCC_net_1), .B(
        \nbytes[8]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un5_AXI_DATA_cry_7_net_1), .S(un5_AXI_DATA_cry_8_S), .Y(), 
        .FCO(un5_AXI_DATA_cry_8_net_1));
    CFG4 #( .INIT(16'hD800) )  read_byte_2_read_byte_0_0_RNI4AS01 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[32] ), .C(
        \AXI_DATA_reto[32] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[32]));
    CFG3 #( .INIT(8'hD0) )  \nbytes_RNO[3]  (.A(N_765), .B(
        un1_nbytes_1_sqmuxa_1_0_net_1), .C(un1_nbytes_2_cry_3_S), .Y(
        \nbytes_10[3] ));
    SLE \AXI_DATA_ret_5[5]  (.D(SPI_to_MDDR_0_AXI_DATA[5]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[5] ));
    SLE \nbytes[3]  (.D(\nbytes_10[3] ), .CLK(CCC_0_GL0), .EN(
        VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \nbytes[3]_net_1 ));
    CFG4 #( .INIT(16'hD800) )  read_byte_0_read_byte_0_0_RNI6MB51 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[50] ), .C(
        \AXI_DATA_reto[50] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[50]));
    CFG2 #( .INIT(4'h8) )  \DATAOUT_1_RNO[5]  (.A(
        \SPI_current_state[2]_net_1 ), .B(\CMD[5]_net_1 ), .Y(
        \DATAOUT_14[5] ));
    CFG4 #( .INIT(16'hEFCC) )  \SPI_current_state_ns[0]  (.A(
        AHB_IF_0_AHB_BUSY), .B(CMD_count_0_sqmuxa_1), .C(DP_SW1_c), .D(
        \SPI_current_state[0]_net_1 ), .Y(
        \SPI_current_state_ns[0]_net_1 ));
    SLE \AXI_DATA_ret_3[0]  (.D(SPI_to_MDDR_0_AXI_DATA[48]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[48] ));
    SLE \AXI_DATA_ret_0[3]  (.D(SPI_to_MDDR_0_AXI_DATA[11]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[11] ));
    ARI1 #( .INIT(20'h4AA00) )  un5_AXI_DATA_cry_3 (.A(VCC_net_1), .B(
        \nbytes[3]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un5_AXI_DATA_cry_2_net_1), .S(un5_AXI_DATA_cry_3_S), .Y(), 
        .FCO(un5_AXI_DATA_cry_3_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un12_AXI_DATA_cry_2 (.A(VCC_net_1), .B(
        \nbytes[3]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un12_AXI_DATA_cry_1_net_1), .S(un12_AXI_DATA_cry_2_S), .Y(), 
        .FCO(un12_AXI_DATA_cry_2_net_1));
    CFG4 #( .INIT(16'hFFFB) )  WRITE_RNO (.A(
        \SPI_current_state[2]_net_1 ), .B(WRITE_0_sqmuxa_0_a5_1_net_1), 
        .C(\SPI_current_state[9]_net_1 ), .D(
        \SPI_current_state[11]_net_1 ), .Y(N_820_i_0));
    ARI1 #( .INIT(20'h4AA00) )  un24_AXI_DATA_cry_5 (.A(VCC_net_1), .B(
        \nbytes[7]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un24_AXI_DATA_cry_4_net_1), .S(un24_AXI_DATA_cry_5_S), .Y(), 
        .FCO(un24_AXI_DATA_cry_5_net_1));
    SLE \DATAOUT_1[6]  (.D(\DATAOUT_14[6] ), .CLK(CCC_0_GL0), .EN(
        un1_M3_RESETn_0_sqmuxa_2_net_1), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(SPI_to_MDDR_0_DATAOUT_6));
    SLE \DATAOUT_1[5]  (.D(\DATAOUT_14[5] ), .CLK(CCC_0_GL0), .EN(
        un1_M3_RESETn_0_sqmuxa_2_net_1), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(SPI_to_MDDR_0_DATAOUT_5));
    SLE \DATAOUT_1[1]  (.D(\DATAOUT_14[1] ), .CLK(CCC_0_GL0), .EN(
        un1_M3_RESETn_0_sqmuxa_2_net_1), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(SPI_to_MDDR_0_DATAOUT_1));
    CFG4 #( .INIT(16'hEAC0) )  \CMD_6_0_iv_0[6]  (.A(
        \block_address[22]_net_1 ), .B(\block_address[14]_net_1 ), .C(
        N_379), .D(N_378), .Y(\CMD_6[6] ));
    SLE \CMD[6]  (.D(\CMD_6[6] ), .CLK(CCC_0_GL0), .EN(VCC_net_1), 
        .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\CMD[6]_net_1 ));
    SLE \nbytes[6]  (.D(\nbytes_10[6] ), .CLK(CCC_0_GL0), .EN(
        VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \nbytes[6]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un2_block_address_1_cry_6 (.A(
        VCC_net_1), .B(\block_address[16]_net_1 ), .C(GND_net_1), .D(
        GND_net_1), .FCI(un2_block_address_1_cry_5_net_1), .S(
        un2_block_address_1_cry_6_S), .Y(), .FCO(
        un2_block_address_1_cry_6_net_1));
    CFG4 #( .INIT(16'h8000) )  \SPI_current_state_ns_0_a2_0_7_5[11]  (
        .A(\nbytes[5]_net_1 ), .B(\nbytes[4]_net_1 ), .C(
        \nbytes[3]_net_1 ), .D(\nbytes[2]_net_1 ), .Y(
        \SPI_current_state_ns_0_a2_0_7_5[11]_net_1 ));
    CFG2 #( .INIT(4'hB) )  \CMD_count_7_i_o2[2]  (.A(AHB_IF_0_AHB_BUSY)
        , .B(\SPI_current_state[5]_net_1 ), .Y(N_335));
    CFG4 #( .INIT(16'hD800) )  \AXI_DATA_ret_5_RNIH6RH1[6]  (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[6] ), .C(
        \AXI_DATA_reto[6] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[6]));
    SLE \nbytes[4]  (.D(\nbytes_10[4] ), .CLK(CCC_0_GL0), .EN(
        VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \nbytes[4]_net_1 ));
    SLE \SPI_current_state[14]  (.D(VCC_net_1), .CLK(CCC_0_GL0), .EN(
        \SPI_current_state_ns_a5[14]_net_1 ), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\SPI_current_state[14]_net_1 ));
    CFG3 #( .INIT(8'h10) )  \CMD_6_0_iv_0_a2_1[7]  (.A(
        \CMD_count[2]_net_1 ), .B(\CMD_count[1]_net_1 ), .C(
        \CMD_count[0]_net_1 ), .Y(N_378));
    SLE \block_address[10]  (.D(block_address_238_net_1), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\block_address[10]_net_1 ));
    CFG4 #( .INIT(16'hD800) )  read_byte_1_read_byte_0_0_RNI4V331 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[40] ), .C(
        \AXI_DATA_reto[40] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[40]));
    ARI1 #( .INIT(20'h4AA00) )  \nblocks_cry[1]  (.A(VCC_net_1), .B(
        \nblocks[1]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        nblocks_s_305_FCO), .S(\nblocks_s[1] ), .Y(), .FCO(
        \nblocks_cry[1]_net_1 ));
    CFG4 #( .INIT(16'h000B) )  \ADDR_1_RNO[2]  (.A(
        \reg_count[0]_net_1 ), .B(N_339_i_0), .C(
        \ADDR_17_i_0_2[2]_net_1 ), .D(\ADDR_17_i_0_1[2]_net_1 ), .Y(
        N_315_i_0));
    ARI1 #( .INIT(20'h4AA00) )  un36_AXI_DATA_cry_3 (.A(VCC_net_1), .B(
        \nbytes[4]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un36_AXI_DATA_cry_2_net_1), .S(un36_AXI_DATA_cry_3_S), .Y(), 
        .FCO(un36_AXI_DATA_cry_3_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un30_AXI_DATA_cry_3 (.A(VCC_net_1), .B(
        \nbytes[3]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un30_AXI_DATA_cry_2_net_1), .S(un30_AXI_DATA_cry_3_S), .Y(), 
        .FCO(un30_AXI_DATA_cry_3_net_1));
    CFG3 #( .INIT(8'h20) )  read_byte_3_read_byte_0_0_RNO (.A(
        MSS_HPMS_READY), .B(AHB_IF_0_AHB_BUSY), .C(
        \SPI_current_state[9]_net_1 ), .Y(read_byte_3_read_byte_0_0_we)
        );
    SLE \AXI_DATA_ret_4[0]  (.D(SPI_to_MDDR_0_AXI_DATA[56]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[56] ));
    ARI1 #( .INIT(20'h4AA00) )  un5_AXI_DATA_cry_9 (.A(VCC_net_1), .B(
        \nbytes[9]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un5_AXI_DATA_cry_8_net_1), .S(un5_AXI_DATA_cry_9_S), .Y(), 
        .FCO(un5_AXI_DATA_cry_9_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un42_AXI_DATA_s_10 (.A(VCC_net_1), .B(
        \nbytes[10]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un42_AXI_DATA_cry_9_net_1), .S(un42_AXI_DATA_s_10_S), .Y(), 
        .FCO());
    ARI1 #( .INIT(20'h4AA00) )  un36_AXI_DATA_cry_7 (.A(VCC_net_1), .B(
        \nbytes[8]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un36_AXI_DATA_cry_6_net_1), .S(un36_AXI_DATA_cry_7_S), .Y(), 
        .FCO(un36_AXI_DATA_cry_7_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un18_AXI_DATA_cry_8 (.A(VCC_net_1), .B(
        \nbytes[8]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un18_AXI_DATA_cry_7_net_1), .S(un18_AXI_DATA_cry_8_S), .Y(), 
        .FCO(un18_AXI_DATA_cry_8_net_1));
    CFG4 #( .INIT(16'h0002) )  \ADDR_1_RNO[4]  (.A(
        SPI_current_state_1_sqmuxa_1), .B(ADDR_17_1_327_i_1_net_1), .C(
        \SPI_current_state[9]_net_1 ), .D(N_328), .Y(N_849_i_0));
    SLE \ADDR_1[3]  (.D(N_853), .CLK(CCC_0_GL0), .EN(
        un1_READ_0_sqmuxa_2_net_1), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(SPI_to_MDDR_0_ADDR_1));
    RAM1K18 read_byte_5_read_byte_0_0 (.A_DOUT({nc28, nc29, nc30, nc31, 
        nc32, nc33, nc34, nc35, nc36, nc37, \read_byte_reto[15] , 
        \read_byte_reto[14] , \read_byte_reto[13] , 
        \read_byte_reto[12] , \read_byte_reto[11] , 
        \read_byte_reto[10] , \read_byte_reto[9] , \read_byte_reto[8] })
        , .B_DOUT({nc38, nc39, nc40, nc41, nc42, nc43, nc44, nc45, 
        nc46, nc47, \read_byte_reto[7] , \read_byte_reto[6] , 
        \read_byte_reto[5] , \read_byte_reto[4] , \read_byte_reto[3] , 
        \read_byte_reto[2] , \read_byte_reto[1] , \read_byte_reto[0] })
        , .BUSY(), .A_CLK(CCC_0_GL0), .A_DOUT_CLK(VCC_net_1), 
        .A_ARST_N(VCC_net_1), .A_DOUT_EN(VCC_net_1), .A_BLK({VCC_net_1, 
        VCC_net_1, VCC_net_1}), .A_DOUT_ARST_N(VCC_net_1), 
        .A_DOUT_SRST_N(VCC_net_1), .A_DIN({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1}), .A_ADDR({un5_AXI_DATA_s_10_S, 
        un5_AXI_DATA_cry_9_S, un5_AXI_DATA_cry_8_S, 
        un5_AXI_DATA_cry_7_S, un5_AXI_DATA_cry_6_S, 
        un5_AXI_DATA_cry_5_S, un5_AXI_DATA_cry_4_S, 
        un5_AXI_DATA_cry_3_S, un5_AXI_DATA_cry_2_S, 
        un5_AXI_DATA_cry_1_S, \nbytes_i_0[0] , GND_net_1, GND_net_1, 
        GND_net_1}), .A_WEN({GND_net_1, GND_net_1}), .B_CLK(CCC_0_GL0), 
        .B_DOUT_CLK(VCC_net_1), .B_ARST_N(VCC_net_1), .B_DOUT_EN(
        VCC_net_1), .B_BLK({VCC_net_1, VCC_net_1, VCC_net_1}), 
        .B_DOUT_ARST_N(VCC_net_1), .B_DOUT_SRST_N(VCC_net_1), .B_DIN({
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        AHB_IF_0_DATAOUT[7], AHB_IF_0_DATAOUT[6], AHB_IF_0_DATAOUT[5], 
        AHB_IF_0_DATAOUT[4], AHB_IF_0_DATAOUT[3], AHB_IF_0_DATAOUT[2], 
        AHB_IF_0_DATAOUT[1], AHB_IF_0_DATAOUT[0]}), .B_ADDR({
        \nbytes[10]_net_1 , \nbytes[9]_net_1 , \nbytes[8]_net_1 , 
        \nbytes[7]_net_1 , \nbytes[6]_net_1 , \nbytes[5]_net_1 , 
        \nbytes[4]_net_1 , \nbytes[3]_net_1 , \nbytes[2]_net_1 , 
        \nbytes[1]_net_1 , \nbytes[0]_net_1 , GND_net_1, GND_net_1, 
        GND_net_1}), .B_WEN({GND_net_1, un1_RESETn_net_1}), .A_EN(
        VCC_net_1), .A_DOUT_LAT(VCC_net_1), .A_WIDTH({GND_net_1, 
        VCC_net_1, VCC_net_1}), .A_WMODE(VCC_net_1), .B_EN(VCC_net_1), 
        .B_DOUT_LAT(VCC_net_1), .B_WIDTH({GND_net_1, VCC_net_1, 
        VCC_net_1}), .B_WMODE(VCC_net_1), .SII_LOCK(GND_net_1));
    CFG4 #( .INIT(16'hD800) )  \AXI_DATA_ret_0_RNI9KBC1[3]  (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[11] ), .C(
        \AXI_DATA_reto[11] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[11]));
    ARI1 #( .INIT(20'h4AA00) )  un5_AXI_DATA_s_1_309 (.A(VCC_net_1), 
        .B(\nbytes[0]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        VCC_net_1), .S(), .Y(), .FCO(un5_AXI_DATA_s_1_309_FCO));
    ARI1 #( .INIT(20'h4AA00) )  un30_AXI_DATA_cry_7 (.A(VCC_net_1), .B(
        \nbytes[7]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un30_AXI_DATA_cry_6_net_1), .S(un30_AXI_DATA_cry_7_S), .Y(), 
        .FCO(un30_AXI_DATA_cry_7_net_1));
    CFG4 #( .INIT(16'hD800) )  read_byte_3_read_byte_0_0_RNINIGV (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[26] ), .C(
        \AXI_DATA_reto[26] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[26]));
    CFG4 #( .INIT(16'h3320) )  \nbytes_RNO[2]  (.A(N_63), .B(
        CMD_count_0_sqmuxa_1), .C(N_34_i_1), .D(un1_nbytes_2_cry_2_S), 
        .Y(N_34_i_0));
    SLE \AXI_DATA_ret_4[1]  (.D(SPI_to_MDDR_0_AXI_DATA[57]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[57] ));
    ARI1 #( .INIT(20'h4AA00) )  un12_AXI_DATA_cry_1 (.A(VCC_net_1), .B(
        \nbytes[2]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un12_AXI_DATA_s_1_311_FCO), .S(un12_AXI_DATA_cry_1_S), .Y(), 
        .FCO(un12_AXI_DATA_cry_1_net_1));
    SLE \DATAOUT_1[0]  (.D(N_869), .CLK(CCC_0_GL0), .EN(
        un1_M3_RESETn_0_sqmuxa_2_net_1), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(SPI_to_MDDR_0_DATAOUT_0));
    CFG3 #( .INIT(8'hFB) )  M3_RESETn_RNO (.A(AHB_IF_0_AHB_BUSY), .B(
        DP_SW1_c), .C(\SPI_current_state[14]_net_1 ), .Y(N_383_i_0));
    SLE \AXI_DATA_ret_5[4]  (.D(SPI_to_MDDR_0_AXI_DATA[4]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[4] ));
    CFG2 #( .INIT(4'h1) )  un1_nbyteslto11_0_a2_3 (.A(
        \nbytes[3]_net_1 ), .B(\nbytes[4]_net_1 ), .Y(
        un1_nbyteslto11_0_a2_3_net_1));
    CFG3 #( .INIT(8'hA8) )  CMD_count_1_sqmuxa_0_a5 (.A(
        \SPI_current_state[11]_net_1 ), .B(\nblocks[7]_net_1 ), .C(
        AXI_IF_0_AXI_BUSY), .Y(CMD_count_1_sqmuxa));
    CFG2 #( .INIT(4'h1) )  AXI_WRITE_RNO (.A(N_401), .B(
        AXI_IF_0_AXI_BUSY), .Y(N_267_i_0));
    SLE \nbytes[10]  (.D(\nbytes_10[10] ), .CLK(CCC_0_GL0), .EN(
        VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \nbytes[10]_net_1 ));
    CFG4 #( .INIT(16'hEAC0) )  \CMD_6_0_iv_0[5]  (.A(
        \block_address[21]_net_1 ), .B(\block_address[13]_net_1 ), .C(
        N_379), .D(N_378), .Y(\CMD_6[5] ));
    CFG4 #( .INIT(16'hD800) )  read_byte_4_read_byte_0_0_RNICM241 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[17] ), .C(
        \AXI_DATA_reto[17] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[17]));
    CFG4 #( .INIT(16'hD800) )  \AXI_DATA_ret_4_RNISVVG1[6]  (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[62] ), .C(
        \AXI_DATA_reto[62] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[62]));
    SLE \AXI_DATA_ret[1]  (.D(SPI_to_MDDR_0_AXI_DATA[25]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[25] ));
    CFG4 #( .INIT(16'h8000) )  \SPI_current_state_ns_0_a2_0_7_4[11]  (
        .A(\nbytes[9]_net_1 ), .B(\nbytes[8]_net_1 ), .C(
        \nbytes[7]_net_1 ), .D(\nbytes[6]_net_1 ), .Y(
        \SPI_current_state_ns_0_a2_0_7_4[11]_net_1 ));
    SLE \CMD[0]  (.D(N_46_i_0), .CLK(CCC_0_GL0), .EN(VCC_net_1), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\CMD[0]_net_1 ));
    CFG4 #( .INIT(16'hF0F8) )  ADDR_17_1_327_i_1 (.A(
        \SPI_current_state[0]_net_1 ), .B(DP_SW1_c), .C(N_852), .D(
        \reg_count[1]_net_1 ), .Y(ADDR_17_1_327_i_1_net_1));
    SLE \AXI_DATA_ret_1[5]  (.D(SPI_to_MDDR_0_AXI_DATA[37]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[37] ));
    ARI1 #( .INIT(20'h4AA00) )  un24_AXI_DATA_cry_7 (.A(VCC_net_1), .B(
        \nbytes[9]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un24_AXI_DATA_cry_6_net_1), .S(un24_AXI_DATA_cry_7_S), .Y(), 
        .FCO(un24_AXI_DATA_cry_7_net_1));
    CFG4 #( .INIT(16'hD800) )  read_byte_0_read_byte_0_0_RNI4KB51 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[48] ), .C(
        \AXI_DATA_reto[48] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[48]));
    SLE \block_address[12]  (.D(un2_block_address_1_cry_2_S), .CLK(
        CCC_0_GL0), .EN(CMD_count_0_sqmuxa_1), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\block_address[12]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un36_AXI_DATA_s_9 (.A(VCC_net_1), .B(
        \nbytes[10]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un36_AXI_DATA_cry_8_net_1), .S(un36_AXI_DATA_s_9_S), .Y(), 
        .FCO());
    SLE \CMD[3]  (.D(\CMD_6[3] ), .CLK(CCC_0_GL0), .EN(VCC_net_1), 
        .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\CMD[3]_net_1 ));
    SLE \AXI_DATA_ret_5[6]  (.D(SPI_to_MDDR_0_AXI_DATA[6]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[6] ));
    CFG4 #( .INIT(16'hD800) )  read_byte_0_read_byte_0_0_RNI9PB51 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[53] ), .C(
        \AXI_DATA_reto[53] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[53]));
    ARI1 #( .INIT(20'h4AA00) )  \nblocks_cry[3]  (.A(VCC_net_1), .B(
        \nblocks[3]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \nblocks_cry[2]_net_1 ), .S(\nblocks_s[3] ), .Y(), .FCO(
        \nblocks_cry[3]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \DATAOUT_1_RNO[6]  (.A(
        \SPI_current_state[2]_net_1 ), .B(\CMD[6]_net_1 ), .Y(
        \DATAOUT_14[6] ));
    CFG4 #( .INIT(16'hD800) )  \AXI_DATA_ret_5_RNIE3RH1[3]  (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[3] ), .C(
        \AXI_DATA_reto[3] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[3]));
    CFG4 #( .INIT(16'hFF31) )  \reg_count_9_i_1[2]  (.A(
        \reg_count[0]_net_1 ), .B(\reg_count[2]_net_1 ), .C(N_353), .D(
        CMD_count_0_sqmuxa_1), .Y(\reg_count_9_i_1[2]_net_1 ));
    CFG3 #( .INIT(8'hFE) )  \DATAOUT_14_i_1[24]  (.A(
        \reg_count[2]_net_1 ), .B(\reg_count[0]_net_1 ), .C(N_332), .Y(
        N_313_1));
    CFG4 #( .INIT(16'hD800) )  read_byte_2_read_byte_0_0_RNI5BS01 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[33] ), .C(
        \AXI_DATA_reto[33] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[33]));
    CFG4 #( .INIT(16'hD800) )  read_byte_4_read_byte_0_0_RNIEO241 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[19] ), .C(
        \AXI_DATA_reto[19] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[19]));
    CFG4 #( .INIT(16'h0023) )  \CMD_count_RNO[2]  (.A(
        \CMD_count[2]_net_1 ), .B(\CMD_count_7_i_0[2]_net_1 ), .C(
        N_335), .D(CMD_count_0_sqmuxa_1), .Y(N_48_i_0));
    SLE \AXI_DATA_ret_1[3]  (.D(SPI_to_MDDR_0_AXI_DATA[35]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[35] ));
    CFG4 #( .INIT(16'hD800) )  read_byte_3_read_byte_0_0_RNIQLGV (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[29] ), .C(
        \AXI_DATA_reto[29] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[29]));
    ARI1 #( .INIT(20'h4AA00) )  un5_AXI_DATA_s_10 (.A(VCC_net_1), .B(
        \nbytes[10]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un5_AXI_DATA_cry_9_net_1), .S(un5_AXI_DATA_s_10_S), .Y(), .FCO(
        ));
    SLE \nbytes[0]  (.D(\nbytes_10[0] ), .CLK(CCC_0_GL0), .EN(
        VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \nbytes[0]_net_1 ));
    SLE \CMD_count[1]  (.D(N_50_i_0), .CLK(CCC_0_GL0), .EN(VCC_net_1), 
        .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\CMD_count[1]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un1_nbytes_2_cry_2 (.A(VCC_net_1), .B(
        \nbytes[2]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_nbytes_2_cry_1_net_1), .S(un1_nbytes_2_cry_2_S), .Y(), 
        .FCO(un1_nbytes_2_cry_2_net_1));
    SLE \CMD_count[0]  (.D(N_52_i_0), .CLK(CCC_0_GL0), .EN(VCC_net_1), 
        .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\CMD_count[0]_net_1 ));
    SLE \AXI_DATA_ret[0]  (.D(SPI_to_MDDR_0_AXI_DATA[24]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[24] ));
    ARI1 #( .INIT(20'h4AA00) )  un1_nbytes_2_s_11 (.A(VCC_net_1), .B(
        \nbytes[11]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_nbytes_2_cry_10_net_1), .S(un1_nbytes_2_s_11_S), .Y(), 
        .FCO());
    GND GND (.Y(GND_net_1));
    CFG4 #( .INIT(16'hA0B3) )  \DATAOUT_14_0_iv[1]  (.A(
        \SPI_current_state[2]_net_1 ), .B(N_313_1), .C(\CMD[1]_net_1 ), 
        .D(\reg_count[1]_net_1 ), .Y(\DATAOUT_14[1] ));
    SLE M3_RESETn (.D(N_383_i_0), .CLK(CCC_0_GL0), .EN(
        un1_SPI_current_state_7_0_net_1), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(GPIO_0_M2F_0));
    SLE \AXI_DATA_ret_2[6]  (.D(SPI_to_MDDR_0_AXI_DATA[46]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[46] ));
    CFG4 #( .INIT(16'hEAC0) )  \CMD_6_0_iv_0[7]  (.A(
        \block_address[23]_net_1 ), .B(\block_address[15]_net_1 ), .C(
        N_379), .D(N_378), .Y(\CMD_6[7] ));
    CFG4 #( .INIT(16'h0004) )  un1_nbyteslto11_0_a2_6 (.A(
        \nbytes[2]_net_1 ), .B(un1_nbyteslto11_0_a2_3_net_1), .C(
        \nbytes[11]_net_1 ), .D(\nbytes[7]_net_1 ), .Y(
        un1_nbyteslto11_0_a2_6_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un12_AXI_DATA_s_1_311 (.A(VCC_net_1), 
        .B(\nbytes[1]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        VCC_net_1), .S(), .Y(), .FCO(un12_AXI_DATA_s_1_311_FCO));
    CFG4 #( .INIT(16'hD800) )  read_byte_1_read_byte_0_0_RNI50431 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[41] ), .C(
        \AXI_DATA_reto[41] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[41]));
    CFG4 #( .INIT(16'h0111) )  nbytes_1_sqmuxa_1 (.A(AXI_IF_0_AXI_BUSY)
        , .B(N_59), .C(\SPI_current_state_ns_0_a2_0_7_4[11]_net_1 ), 
        .D(\SPI_current_state_ns_0_a2_0_7_5[11]_net_1 ), .Y(
        nbytes_1_sqmuxa_1_net_1));
    CFG4 #( .INIT(16'hD800) )  read_byte_2_read_byte_0_0_RNI7DS01 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[35] ), .C(
        \AXI_DATA_reto[35] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[35]));
    ARI1 #( .INIT(20'h4AA00) )  un2_block_address_1_s_13 (.A(VCC_net_1)
        , .B(\block_address[23]_net_1 ), .C(GND_net_1), .D(GND_net_1), 
        .FCI(un2_block_address_1_cry_12_net_1), .S(
        un2_block_address_1_s_13_S), .Y(), .FCO());
    SLE \AXI_DATA_ret_1[0]  (.D(SPI_to_MDDR_0_AXI_DATA[32]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[32] ));
    SLE \AXI_DATA_ret_1[7]  (.D(SPI_to_MDDR_0_AXI_DATA[39]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[39] ));
    CFG4 #( .INIT(16'hD800) )  \AXI_DATA_ret_0_RNIBMBC1[5]  (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[13] ), .C(
        \AXI_DATA_reto[13] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[13]));
    CFG3 #( .INIT(8'h09) )  \reg_count_RNO[1]  (.A(N_336_0), .B(
        \reg_count[1]_net_1 ), .C(CMD_count_0_sqmuxa_1), .Y(N_322_i_0));
    CFG4 #( .INIT(16'h3B5F) )  \SPI_current_state_ns_i_0_0[13]  (.A(
        \SPI_current_state[9]_net_1 ), .B(
        \SPI_current_state[13]_net_1 ), .C(N_59), .D(AHB_IF_0_AHB_BUSY)
        , .Y(\SPI_current_state_ns_i_0_0[13]_net_1 ));
    SLE \nbytes[2]  (.D(N_34_i_0), .CLK(CCC_0_GL0), .EN(VCC_net_1), 
        .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\nbytes[2]_net_1 ));
    CFG4 #( .INIT(16'h00F4) )  un1_READ_0_sqmuxa_2_1 (.A(
        AHB_IF_0_DATAOUT[6]), .B(\SPI_current_state[7]_net_1 ), .C(
        N_328), .D(AHB_IF_0_AHB_BUSY), .Y(un1_READ_0_sqmuxa_2_1_net_1));
    SLE \SPI_current_state[6]  (.D(\SPI_current_state[5]_net_1 ), .CLK(
        CCC_0_GL0), .EN(AHB_IF_0_AHB_BUSY_i_0), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\SPI_current_state[6]_net_1 ));
    CFG4 #( .INIT(16'hD800) )  read_byte_0_read_byte_0_0_RNIBRB51 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[55] ), .C(
        \AXI_DATA_reto[55] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[55]));
    CFG4 #( .INIT(16'hD800) )  read_byte_1_read_byte_0_0_RNIA5431 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[46] ), .C(
        \AXI_DATA_reto[46] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[46]));
    ARI1 #( .INIT(20'h4AA00) )  un30_AXI_DATA_cry_9 (.A(VCC_net_1), .B(
        \nbytes[9]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un30_AXI_DATA_cry_8_net_1), .S(un30_AXI_DATA_cry_9_S), .Y(), 
        .FCO(un30_AXI_DATA_cry_9_net_1));
    SLE \AXI_DATA_ret[5]  (.D(SPI_to_MDDR_0_AXI_DATA[29]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[29] ));
    CFG3 #( .INIT(8'hB3) )  \SPI_current_state_ns[12]  (.A(
        AHB_IF_0_AHB_BUSY), .B(SPI_current_state_1_sqmuxa_1), .C(
        \SPI_current_state[12]_net_1 ), .Y(
        \SPI_current_state_ns[12]_net_1 ));
    CFG4 #( .INIT(16'hD800) )  read_byte_3_read_byte_0_0_RNIOJGV (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[27] ), .C(
        \AXI_DATA_reto[27] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[27]));
    ARI1 #( .INIT(20'h4AA00) )  nblocks_s_305 (.A(VCC_net_1), .B(
        \nblocks[0]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        VCC_net_1), .S(), .Y(), .FCO(nblocks_s_305_FCO));
    CFG4 #( .INIT(16'h0004) )  WRITE_0_sqmuxa_0_a5_3 (.A(
        \SPI_current_state[2]_net_1 ), .B(N_401), .C(
        \SPI_current_state[9]_net_1 ), .D(AHB_IF_0_AHB_BUSY), .Y(
        WRITE_0_sqmuxa_0_a5_3_net_1));
    CFG4 #( .INIT(16'hD800) )  read_byte_2_read_byte_0_0_RNI8ES01 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[36] ), .C(
        \AXI_DATA_reto[36] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[36]));
    SLE \block_address[14]  (.D(un2_block_address_1_cry_4_S), .CLK(
        CCC_0_GL0), .EN(CMD_count_0_sqmuxa_1), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\block_address[14]_net_1 ));
    SLE \AXI_DATA_ret_2[5]  (.D(SPI_to_MDDR_0_AXI_DATA[45]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[45] ));
    ARI1 #( .INIT(20'h4AA00) )  un2_block_address_1_cry_7 (.A(
        VCC_net_1), .B(\block_address[17]_net_1 ), .C(GND_net_1), .D(
        GND_net_1), .FCI(un2_block_address_1_cry_6_net_1), .S(
        un2_block_address_1_cry_7_S), .Y(), .FCO(
        un2_block_address_1_cry_7_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un18_AXI_DATA_cry_7 (.A(VCC_net_1), .B(
        \nbytes[7]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un18_AXI_DATA_cry_6_net_1), .S(un18_AXI_DATA_cry_7_S), .Y(), 
        .FCO(un18_AXI_DATA_cry_7_net_1));
    SLE \AXI_DATA_ret_1[1]  (.D(SPI_to_MDDR_0_AXI_DATA[33]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[33] ));
    CFG4 #( .INIT(16'hD800) )  read_byte_0_read_byte_0_0_RNI7NB51 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[51] ), .C(
        \AXI_DATA_reto[51] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[51]));
    SLE \SPI_current_state[1]  (.D(N_271_i_0), .CLK(CCC_0_GL0), .EN(
        VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SPI_current_state[1]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un24_AXI_DATA_cry_1 (.A(VCC_net_1), .B(
        \nbytes[3]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un24_AXI_DATA_s_1_312_FCO), .S(un24_AXI_DATA_cry_1_S), .Y(), 
        .FCO(un24_AXI_DATA_cry_1_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un1_nbytes_2_cry_9 (.A(VCC_net_1), .B(
        \nbytes[9]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_nbytes_2_cry_8_net_1), .S(un1_nbytes_2_cry_9_S), .Y(), 
        .FCO(un1_nbytes_2_cry_9_net_1));
    CFG4 #( .INIT(16'hC444) )  \SPI_current_state_ns_0_RNO[3]  (.A(
        N_59), .B(N_63), .C(un1_nbyteslto11_0_a2_5_net_1), .D(
        un1_nbyteslto11_0_a2_6_net_1), .Y(
        \SPI_current_state_ns_0_RNO[3]_net_1 ));
    SLE \CMD[7]  (.D(\CMD_6[7] ), .CLK(CCC_0_GL0), .EN(VCC_net_1), 
        .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\CMD[7]_net_1 ));
    SLE \AXI_DATA_ret_4[3]  (.D(SPI_to_MDDR_0_AXI_DATA[59]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[59] ));
    CFG3 #( .INIT(8'h10) )  un2_ADDR_1_0_a5 (.A(\reg_count[1]_net_1 ), 
        .B(\reg_count[2]_net_1 ), .C(\reg_count[0]_net_1 ), .Y(N_360));
    ARI1 #( .INIT(20'h4AA00) )  un12_AXI_DATA_cry_8 (.A(VCC_net_1), .B(
        \nbytes[9]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un12_AXI_DATA_cry_7_net_1), .S(un12_AXI_DATA_cry_8_S), .Y(), 
        .FCO(un12_AXI_DATA_cry_8_net_1));
    SLE \AXI_DATA_ret[6]  (.D(SPI_to_MDDR_0_AXI_DATA[30]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[30] ));
    CFG4 #( .INIT(16'hD800) )  read_byte_4_read_byte_0_0_RNIDN241 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[18] ), .C(
        \AXI_DATA_reto[18] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[18]));
    CFG2 #( .INIT(4'hE) )  READ_0_sqmuxa_2_0_o2 (.A(
        \SPI_current_state[5]_net_1 ), .B(\SPI_current_state[3]_net_1 )
        , .Y(N_328));
    SLE \nbytes[8]  (.D(\nbytes_10[8] ), .CLK(CCC_0_GL0), .EN(
        VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \nbytes[8]_net_1 ));
    CFG4 #( .INIT(16'hD800) )  \AXI_DATA_ret_0_RNIALBC1[4]  (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[12] ), .C(
        \AXI_DATA_reto[12] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[12]));
    SLE \reg_count[2]  (.D(N_324_i_0), .CLK(CCC_0_GL0), .EN(VCC_net_1), 
        .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\reg_count[2]_net_1 ));
    SLE \ADDR_1[15]  (.D(\SPI_current_state[11]_net_1 ), .CLK(
        CCC_0_GL0), .EN(un1_READ_0_sqmuxa_2_net_1), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(SPI_to_MDDR_0_ADDR_14));
    SLE \ADDR_1[12]  (.D(SPI_current_state_1_sqmuxa_1), .CLK(CCC_0_GL0)
        , .EN(un1_READ_0_sqmuxa_2_net_1), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(SPI_to_MDDR_0_ADDR_10));
    ARI1 #( .INIT(20'h4AA00) )  un36_AXI_DATA_cry_5 (.A(VCC_net_1), .B(
        \nbytes[6]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un36_AXI_DATA_cry_4_net_1), .S(un36_AXI_DATA_cry_5_S), .Y(), 
        .FCO(un36_AXI_DATA_cry_5_net_1));
    CFG4 #( .INIT(16'hFFFD) )  DATAOUT_14_iv_365_o5 (.A(
        \reg_count[2]_net_1 ), .B(\SPI_current_state[0]_net_1 ), .C(
        \reg_count[0]_net_1 ), .D(\reg_count[1]_net_1 ), .Y(N_884));
    CFG3 #( .INIT(8'h20) )  read_byte_read_byte_0_0_RNO (.A(
        MSS_HPMS_READY), .B(AHB_IF_0_AHB_BUSY), .C(
        \SPI_current_state[9]_net_1 ), .Y(read_byte_read_byte_0_0_we));
    ARI1 #( .INIT(20'h4AA00) )  un30_AXI_DATA_cry_5 (.A(VCC_net_1), .B(
        \nbytes[5]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un30_AXI_DATA_cry_4_net_1), .S(un30_AXI_DATA_cry_5_S), .Y(), 
        .FCO(un30_AXI_DATA_cry_5_net_1));
    CFG2 #( .INIT(4'hB) )  un1_M3_RESETn_0_sqmuxa_i (.A(N_332), .B(
        N_884), .Y(N_309));
    VCC VCC (.Y(VCC_net_1));
    CFG3 #( .INIT(8'hF7) )  ADDR_17_0_347_a4_0_0_a2 (.A(
        \SPI_current_state[11]_net_1 ), .B(\nblocks[7]_net_1 ), .C(
        AXI_IF_0_AXI_BUSY), .Y(SPI_current_state_1_sqmuxa_1));
    SLE \SPI_current_state[12]  (.D(\SPI_current_state_ns[12]_net_1 ), 
        .CLK(CCC_0_GL0), .EN(VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\SPI_current_state[12]_net_1 ));
    CFG4 #( .INIT(16'hD800) )  read_byte_3_read_byte_0_0_RNISNGV (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[31] ), .C(
        \AXI_DATA_reto[31] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[31]));
    SLE \nblocks[4]  (.D(\nblocks_s[4] ), .CLK(CCC_0_GL0), .EN(
        CMD_count_0_sqmuxa_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \nblocks[4]_net_1 ));
    ARI1 #( .INIT(20'h65500) )  un42_AXI_DATA_cry_1 (.A(VCC_net_1), .B(
        \nbytes[1]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un42_AXI_DATA_cry_0_net_1), .S(un42_AXI_DATA_cry_1_S), .Y(), 
        .FCO(un42_AXI_DATA_cry_1_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un2_block_address_1_cry_8 (.A(
        VCC_net_1), .B(\block_address[18]_net_1 ), .C(GND_net_1), .D(
        GND_net_1), .FCI(un2_block_address_1_cry_7_net_1), .S(
        un2_block_address_1_cry_8_S), .Y(), .FCO(
        un2_block_address_1_cry_8_net_1));
    CFG4 #( .INIT(16'hEAC0) )  \CMD_6_0_iv_0[4]  (.A(
        \block_address[20]_net_1 ), .B(\block_address[12]_net_1 ), .C(
        N_379), .D(N_378), .Y(\CMD_6[4] ));
    CFG3 #( .INIT(8'hD0) )  \nbytes_RNO[11]  (.A(N_765), .B(
        un1_nbytes_1_sqmuxa_1_0_net_1), .C(un1_nbytes_2_s_11_S), .Y(
        \nbytes_10[11] ));
    SLE \AXI_DATA_ret_2[0]  (.D(SPI_to_MDDR_0_AXI_DATA[40]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[40] ));
    SLE \AXI_DATA_ret_0[6]  (.D(SPI_to_MDDR_0_AXI_DATA[14]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[14] ));
    SLE \AXI_DATA_ret[4]  (.D(SPI_to_MDDR_0_AXI_DATA[28]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[28] ));
    CFG4 #( .INIT(16'hD800) )  read_byte_2_read_byte_0_0_RNI9FS01 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[37] ), .C(
        \AXI_DATA_reto[37] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[37]));
    ARI1 #( .INIT(20'h4AA00) )  un42_AXI_DATA_cry_7 (.A(VCC_net_1), .B(
        \nbytes[7]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un42_AXI_DATA_cry_6_net_1), .S(un42_AXI_DATA_cry_7_S), .Y(), 
        .FCO(un42_AXI_DATA_cry_7_net_1));
    CFG2 #( .INIT(4'h4) )  \SPI_current_state_ns_a5[14]  (.A(
        AHB_IF_0_AHB_BUSY), .B(\SPI_current_state[12]_net_1 ), .Y(
        \SPI_current_state_ns_a5[14]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un18_AXI_DATA_cry_4 (.A(VCC_net_1), .B(
        \nbytes[4]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un18_AXI_DATA_cry_3_net_1), .S(un18_AXI_DATA_cry_4_S), .Y(), 
        .FCO(un18_AXI_DATA_cry_4_net_1));
    CFG4 #( .INIT(16'h0001) )  un1_nbyteslto11_0_a2_5 (.A(
        \nbytes[9]_net_1 ), .B(\nbytes[8]_net_1 ), .C(
        \nbytes[6]_net_1 ), .D(\nbytes[5]_net_1 ), .Y(
        un1_nbyteslto11_0_a2_5_net_1));
    CFG2 #( .INIT(4'h1) )  un41_i_a2_1 (.A(
        \SPI_current_state[4]_net_1 ), .B(\SPI_current_state[6]_net_1 )
        , .Y(un41_i_a2_1_net_1));
    CFG2 #( .INIT(4'hD) )  un1_M3_RESETn_0_sqmuxa_i_o5 (.A(N_327), .B(
        AHB_IF_0_AHB_BUSY), .Y(N_332));
    ARI1 #( .INIT(20'h4AA00) )  un36_AXI_DATA_cry_6 (.A(VCC_net_1), .B(
        \nbytes[7]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un36_AXI_DATA_cry_5_net_1), .S(un36_AXI_DATA_cry_6_S), .Y(), 
        .FCO(un36_AXI_DATA_cry_6_net_1));
    CFG4 #( .INIT(16'h00EC) )  \ADDR_17_i_0_2[2]  (.A(
        \ADDR_17_i_0_a2_0[2] ), .B(N_328), .C(
        \SPI_current_state[1]_net_1 ), .D(AHB_IF_0_AHB_BUSY), .Y(
        \ADDR_17_i_0_2[2]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un30_AXI_DATA_cry_6 (.A(VCC_net_1), .B(
        \nbytes[6]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un30_AXI_DATA_cry_5_net_1), .S(un30_AXI_DATA_cry_6_S), .Y(), 
        .FCO(un30_AXI_DATA_cry_6_net_1));
    CFG2 #( .INIT(4'h8) )  un1_RESETn (.A(N_63), .B(MSS_HPMS_READY), 
        .Y(un1_RESETn_net_1));
    SLE \SPI_current_state[0]  (.D(\SPI_current_state_ns[0]_net_1 ), 
        .CLK(CCC_0_GL0), .EN(VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(
        GND_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\SPI_current_state[0]_net_1 ));
    CFG4 #( .INIT(16'h0405) )  \CMD_RNO[0]  (.A(\CMD_count[1]_net_1 ), 
        .B(\block_address[16]_net_1 ), .C(\CMD_count[2]_net_1 ), .D(
        \CMD_count[0]_net_1 ), .Y(N_46_i_0));
    CFG4 #( .INIT(16'hB3A0) )  \DATAOUT_14_0_iv[2]  (.A(
        \SPI_current_state[2]_net_1 ), .B(N_313_1), .C(\CMD[2]_net_1 ), 
        .D(\reg_count[1]_net_1 ), .Y(\DATAOUT_14[2] ));
    SLE \AXI_DATA_ret_3[6]  (.D(SPI_to_MDDR_0_AXI_DATA[54]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[54] ));
    CFG4 #( .INIT(16'hD800) )  read_byte_2_read_byte_0_0_RNIAGS01 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[38] ), .C(
        \AXI_DATA_reto[38] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[38]));
    SLE \block_address[20]  (.D(un2_block_address_1_cry_10_S), .CLK(
        CCC_0_GL0), .EN(CMD_count_0_sqmuxa_1), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\block_address[20]_net_1 ));
    CFG4 #( .INIT(16'hD800) )  read_byte_2_read_byte_0_0_RNI6CS01 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[34] ), .C(
        \AXI_DATA_reto[34] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[34]));
    CFG3 #( .INIT(8'hD0) )  \nbytes_RNO[4]  (.A(N_765), .B(
        un1_nbytes_1_sqmuxa_1_0_net_1), .C(un1_nbytes_2_cry_4_S), .Y(
        \nbytes_10[4] ));
    SLE \AXI_DATA_ret_2[1]  (.D(SPI_to_MDDR_0_AXI_DATA[41]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[41] ));
    CFG4 #( .INIT(16'hFF10) )  un1_M3_RESETn_0_sqmuxa_2_0 (.A(
        AHB_IF_0_DATAOUT[8]), .B(AHB_IF_0_AHB_BUSY), .C(
        \SPI_current_state[2]_net_1 ), .D(N_339_i_0), .Y(
        un1_M3_RESETn_0_sqmuxa_2_0_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un2_block_address_1_cry_3 (.A(
        VCC_net_1), .B(\block_address[13]_net_1 ), .C(GND_net_1), .D(
        GND_net_1), .FCI(un2_block_address_1_cry_2_net_1), .S(
        un2_block_address_1_cry_3_S), .Y(), .FCO(
        un2_block_address_1_cry_3_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un1_nbytes_2_cry_6 (.A(VCC_net_1), .B(
        \nbytes[6]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_nbytes_2_cry_5_net_1), .S(un1_nbytes_2_cry_6_S), .Y(), 
        .FCO(un1_nbytes_2_cry_6_net_1));
    CFG4 #( .INIT(16'hD800) )  read_byte_4_read_byte_0_0_RNIBL241 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[16] ), .C(
        \AXI_DATA_reto[16] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[16]));
    ARI1 #( .INIT(20'h4AA00) )  un42_AXI_DATA_cry_4 (.A(VCC_net_1), .B(
        \nbytes[4]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un42_AXI_DATA_cry_3_net_1), .S(un42_AXI_DATA_cry_4_S), .Y(), 
        .FCO(un42_AXI_DATA_cry_4_net_1));
    CFG3 #( .INIT(8'h20) )  read_byte_4_read_byte_0_0_RNO_0 (.A(
        MSS_HPMS_READY), .B(AHB_IF_0_AHB_BUSY), .C(
        \SPI_current_state[9]_net_1 ), .Y(read_byte_4_read_byte_0_0_we)
        );
    SLE \nbytes[5]  (.D(\nbytes_10[5] ), .CLK(CCC_0_GL0), .EN(
        VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \nbytes[5]_net_1 ));
    SLE \nblocks[0]  (.D(\nblocks_s[0] ), .CLK(CCC_0_GL0), .EN(
        CMD_count_0_sqmuxa_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \nblocks[0]_net_1 ));
    SLE \ADDR_1[4]  (.D(N_849_i_0), .CLK(CCC_0_GL0), .EN(
        un1_READ_0_sqmuxa_2_net_1), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(SPI_to_MDDR_0_ADDR_2));
    CFG4 #( .INIT(16'hD800) )  \AXI_DATA_ret_4_RNIMPVG1[0]  (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[56] ), .C(
        \AXI_DATA_reto[56] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[56]));
    SLE \ADDR_1[30]  (.D(VCC_net_1), .CLK(CCC_0_GL0), .EN(
        un1_READ_0_sqmuxa_2_net_1), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(SPI_to_MDDR_0_ADDR_28));
    ARI1 #( .INIT(20'h4AA00) )  un1_nbytes_2_cry_5 (.A(VCC_net_1), .B(
        \nbytes[5]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_nbytes_2_cry_4_net_1), .S(un1_nbytes_2_cry_5_S), .Y(), 
        .FCO(un1_nbytes_2_cry_5_net_1));
    SLE \block_address[15]  (.D(un2_block_address_1_cry_5_S), .CLK(
        CCC_0_GL0), .EN(CMD_count_0_sqmuxa_1), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\block_address[15]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un5_AXI_DATA_cry_2 (.A(VCC_net_1), .B(
        \nbytes[2]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un5_AXI_DATA_cry_1_net_1), .S(un5_AXI_DATA_cry_2_S), .Y(), 
        .FCO(un5_AXI_DATA_cry_2_net_1));
    CFG4 #( .INIT(16'hD800) )  \AXI_DATA_ret_4_RNIORVG1[2]  (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[58] ), .C(
        \AXI_DATA_reto[58] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[58]));
    ARI1 #( .INIT(20'h4AA00) )  un18_AXI_DATA_cry_6 (.A(VCC_net_1), .B(
        \nbytes[6]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un18_AXI_DATA_cry_5_net_1), .S(un18_AXI_DATA_cry_6_S), .Y(), 
        .FCO(un18_AXI_DATA_cry_6_net_1));
    CFG4 #( .INIT(16'hD800) )  \AXI_DATA_ret_0_RNI6HBC1[0]  (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[8] ), .C(
        \AXI_DATA_reto[8] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[8]));
    ARI1 #( .INIT(20'h4AA00) )  un30_AXI_DATA_s_10 (.A(VCC_net_1), .B(
        \nbytes[10]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un30_AXI_DATA_cry_9_net_1), .S(un30_AXI_DATA_s_10_S), .Y(), 
        .FCO());
    SLE \nblocks[6]  (.D(\nblocks_s[6] ), .CLK(CCC_0_GL0), .EN(
        CMD_count_0_sqmuxa_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \nblocks[6]_net_1 ));
    CFG4 #( .INIT(16'hD800) )  read_byte_1_read_byte_0_0_RNIB6431 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[47] ), .C(
        \AXI_DATA_reto[47] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[47]));
    CFG3 #( .INIT(8'hD0) )  \nbytes_RNO[6]  (.A(N_765), .B(
        un1_nbytes_1_sqmuxa_1_0_net_1), .C(un1_nbytes_2_cry_6_S), .Y(
        \nbytes_10[6] ));
    SLE \block_address[22]  (.D(un2_block_address_1_cry_12_S), .CLK(
        CCC_0_GL0), .EN(CMD_count_0_sqmuxa_1), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\block_address[22]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un24_AXI_DATA_cry_4 (.A(VCC_net_1), .B(
        \nbytes[6]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un24_AXI_DATA_cry_3_net_1), .S(un24_AXI_DATA_cry_4_S), .Y(), 
        .FCO(un24_AXI_DATA_cry_4_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un1_nbytes_2_cry_10 (.A(VCC_net_1), .B(
        \nbytes[10]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_nbytes_2_cry_9_net_1), .S(un1_nbytes_2_cry_10_S), .Y(), 
        .FCO(un1_nbytes_2_cry_10_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un12_AXI_DATA_cry_7 (.A(VCC_net_1), .B(
        \nbytes[8]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un12_AXI_DATA_cry_6_net_1), .S(un12_AXI_DATA_cry_7_S), .Y(), 
        .FCO(un12_AXI_DATA_cry_7_net_1));
    CFG3 #( .INIT(8'h04) )  reg_count_1_sqmuxa_0_o2_i_a2 (.A(
        \reg_count[1]_net_1 ), .B(\reg_count[2]_net_1 ), .C(
        \reg_count[0]_net_1 ), .Y(N_389));
    ARI1 #( .INIT(20'h4AA00) )  \nblocks_s[7]  (.A(VCC_net_1), .B(
        \nblocks[7]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \nblocks_cry[6]_net_1 ), .S(\nblocks_s[7]_net_1 ), .Y(), .FCO()
        );
    SLE \CMD_count[2]  (.D(N_48_i_0), .CLK(CCC_0_GL0), .EN(VCC_net_1), 
        .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\CMD_count[2]_net_1 ));
    CFG4 #( .INIT(16'hD800) )  \AXI_DATA_ret_0_RNICNBC1[6]  (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[14] ), .C(
        \AXI_DATA_reto[14] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[14]));
    ARI1 #( .INIT(20'h4AA00) )  un18_AXI_DATA_cry_3 (.A(VCC_net_1), .B(
        \nbytes[3]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un18_AXI_DATA_cry_2_net_1), .S(un18_AXI_DATA_cry_3_S), .Y(), 
        .FCO(un18_AXI_DATA_cry_3_net_1));
    CFG4 #( .INIT(16'hD800) )  read_byte_4_read_byte_0_0_RNIIS241 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[23] ), .C(
        \AXI_DATA_reto[23] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[23]));
    SLE \AXI_DATA_ret_6[6]  (.D(SPI_to_MDDR_0_AXI_DATA[22]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[22] ));
    CFG3 #( .INIT(8'h2A) )  \nbytes_RNO_0[2]  (.A(N_59), .B(
        un1_nbyteslto11_0_a2_5_net_1), .C(un1_nbyteslto11_0_a2_6_net_1)
        , .Y(N_34_i_1));
    CFG4 #( .INIT(16'hD800) )  \AXI_DATA_ret_4_RNIPSVG1[3]  (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[59] ), .C(
        \AXI_DATA_reto[59] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[59]));
    CFG4 #( .INIT(16'hD800) )  \AXI_DATA_ret_4_RNINQVG1[1]  (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[57] ), .C(
        \AXI_DATA_reto[57] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[57]));
    CFG4 #( .INIT(16'hD800) )  read_byte_0_read_byte_0_0_RNI8OB51 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[52] ), .C(
        \AXI_DATA_reto[52] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[52]));
    SLE \AXI_DATA_ret_4[4]  (.D(SPI_to_MDDR_0_AXI_DATA[60]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[60] ));
    SLE \DATAOUT_1[2]  (.D(\DATAOUT_14[2] ), .CLK(CCC_0_GL0), .EN(
        un1_M3_RESETn_0_sqmuxa_2_net_1), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(SPI_to_MDDR_0_DATAOUT_2));
    CFG2 #( .INIT(4'h2) )  AXI_DATA_0_sqmuxa_0_a2_0_a2 (.A(
        \SPI_current_state[10]_net_1 ), .B(AXI_IF_0_AXI_BUSY), .Y(
        AXI_DATA_0_sqmuxa));
    CFG3 #( .INIT(8'hF8) )  un1_WRITE_0_sqmuxa (.A(
        WRITE_0_sqmuxa_0_a5_2_net_1), .B(WRITE_0_sqmuxa_0_a5_3_net_1), 
        .C(un1_M3_RESETn_0_sqmuxa_2_net_1), .Y(
        un1_WRITE_0_sqmuxa_net_1));
    ARI1 #( .INIT(20'h4AA00) )  \nblocks_cry[5]  (.A(VCC_net_1), .B(
        \nblocks[5]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \nblocks_cry[4]_net_1 ), .S(\nblocks_s[5] ), .Y(), .FCO(
        \nblocks_cry[5]_net_1 ));
    SLE \AXI_DATA_ret_6[1]  (.D(SPI_to_MDDR_0_AXI_DATA[17]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[17] ));
    SLE \AXI_DATA_ret_1[4]  (.D(SPI_to_MDDR_0_AXI_DATA[36]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[36] ));
    SLE \SPI_current_state[5]  (.D(\SPI_current_state[2]_net_1 ), .CLK(
        CCC_0_GL0), .EN(AHB_IF_0_AHB_BUSY_i_0), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\SPI_current_state[5]_net_1 ));
    SLE \DATAOUT_1[4]  (.D(\DATAOUT_14[4] ), .CLK(CCC_0_GL0), .EN(
        un1_M3_RESETn_0_sqmuxa_2_net_1), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(SPI_to_MDDR_0_DATAOUT_4));
    SLE \AXI_DATA_ret_6[3]  (.D(SPI_to_MDDR_0_AXI_DATA[19]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[19] ));
    CFG4 #( .INIT(16'hD800) )  \AXI_DATA_ret_5_RNID2RH1[2]  (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[2] ), .C(
        \AXI_DATA_reto[2] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[2]));
    SLE \AXI_DATA_ret[3]  (.D(SPI_to_MDDR_0_AXI_DATA[27]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[27] ));
    CFG3 #( .INIT(8'h04) )  WRITE_0_sqmuxa_0_a5_2 (.A(
        \SPI_current_state[7]_net_1 ), .B(WRITE_0_sqmuxa_0_a5_1_net_1), 
        .C(\SPI_current_state[12]_net_1 ), .Y(
        WRITE_0_sqmuxa_0_a5_2_net_1));
    SLE \nbytes[9]  (.D(\nbytes_10[9] ), .CLK(CCC_0_GL0), .EN(
        VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \nbytes[9]_net_1 ));
    CFG2 #( .INIT(4'hB) )  \CMD_count_7_i_o2_1[0]  (.A(
        \CMD_count[2]_net_1 ), .B(\CMD_count[0]_net_1 ), .Y(N_336));
    CFG3 #( .INIT(8'h04) )  reg_count_1_sqmuxa_0_a5 (.A(N_389), .B(
        \SPI_current_state[1]_net_1 ), .C(AHB_IF_0_AHB_BUSY), .Y(
        reg_count_1_sqmuxa));
    SLE \AXI_DATA_ret_0[2]  (.D(SPI_to_MDDR_0_AXI_DATA[10]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[10] ));
    SLE \AXI_DATA_ret_3[4]  (.D(SPI_to_MDDR_0_AXI_DATA[52]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[52] ));
    SLE AXI_DATA_rst (.D(VCC_net_1), .CLK(CCC_0_GL0), .EN(VCC_net_1), 
        .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_DATA_rst_net_1));
    CFG4 #( .INIT(16'hEAC0) )  \CMD_6_0_iv_0[2]  (.A(
        \block_address[18]_net_1 ), .B(\block_address[10]_net_1 ), .C(
        N_379), .D(N_378), .Y(\CMD_6[2] ));
    CFG4 #( .INIT(16'hD800) )  \AXI_DATA_ret_0_RNI8JBC1[2]  (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[10] ), .C(
        \AXI_DATA_reto[10] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[10]));
    CFG2 #( .INIT(4'hB) )  \reg_count_9_i_o2[0]  (.A(N_332), .B(
        \reg_count[0]_net_1 ), .Y(N_336_0));
    CFG3 #( .INIT(8'hF8) )  un1_M3_RESETn_0_sqmuxa_i_o2 (.A(
        \SPI_current_state[0]_net_1 ), .B(DP_SW1_c), .C(
        \SPI_current_state[1]_net_1 ), .Y(N_327));
    SLE \nbytes[1]  (.D(\nbytes_10[1] ), .CLK(CCC_0_GL0), .EN(
        VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \nbytes[1]_net_1 ));
    SLE \AXI_DATA_ret_2[7]  (.D(SPI_to_MDDR_0_AXI_DATA[47]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[47] ));
    CFG3 #( .INIT(8'hAE) )  un1_READ_0_sqmuxa_3_i_a5_1 (.A(N_328), .B(
        \SPI_current_state[7]_net_1 ), .C(AHB_IF_0_DATAOUT[6]), .Y(
        N_385_1));
    CFG3 #( .INIT(8'hD0) )  \nbytes_RNO[5]  (.A(N_765), .B(
        un1_nbytes_1_sqmuxa_1_0_net_1), .C(un1_nbytes_2_cry_5_S), .Y(
        \nbytes_10[5] ));
    ARI1 #( .INIT(20'h4AA00) )  un2_block_address_1_s_1_308 (.A(
        VCC_net_1), .B(\block_address[10]_net_1 ), .C(GND_net_1), .D(
        GND_net_1), .FCI(VCC_net_1), .S(), .Y(), .FCO(
        un2_block_address_1_s_1_308_FCO));
    CFG4 #( .INIT(16'hD800) )  read_byte_3_read_byte_0_0_RNIRMGV (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[30] ), .C(
        \AXI_DATA_reto[30] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[30]));
    SLE \AXI_DATA_ret_6[7]  (.D(SPI_to_MDDR_0_AXI_DATA[23]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[23] ));
    CFG3 #( .INIT(8'hA8) )  \SPI_current_state_RNO[1]  (.A(N_884), .B(
        \SPI_current_state[1]_net_1 ), .C(N_339_i_0), .Y(N_271_i_0));
    SLE \SPI_current_state[7]  (.D(\SPI_current_state[6]_net_1 ), .CLK(
        CCC_0_GL0), .EN(AHB_IF_0_AHB_BUSY_i_0), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\SPI_current_state[7]_net_1 ));
    CFG1 #( .INIT(2'h1) )  \nblocks_RNO[0]  (.A(\nblocks[0]_net_1 ), 
        .Y(\nblocks_s[0] ));
    SLE \SPI_current_state[8]  (.D(\SPI_current_state_ns[8]_net_1 ), 
        .CLK(CCC_0_GL0), .EN(VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\SPI_current_state[8]_net_1 ));
    SLE \SPI_current_state[3]  (.D(\SPI_current_state_ns[3] ), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\SPI_current_state[3]_net_1 ));
    RAM1K18 read_byte_read_byte_0_0 (.A_DOUT({nc48, nc49, nc50, nc51, 
        nc52, nc53, nc54, nc55, nc56, nc57, \read_byte_reto[63] , 
        \read_byte_reto[62] , \read_byte_reto[61] , 
        \read_byte_reto[60] , \read_byte_reto[59] , 
        \read_byte_reto[58] , \read_byte_reto[57] , 
        \read_byte_reto[56] }), .B_DOUT({nc58, nc59, nc60, nc61, nc62, 
        nc63, nc64, nc65, nc66, nc67, nc68, nc69, nc70, nc71, nc72, 
        nc73, nc74, nc75}), .BUSY(), .A_CLK(CCC_0_GL0), .A_DOUT_CLK(
        VCC_net_1), .A_ARST_N(VCC_net_1), .A_DOUT_EN(VCC_net_1), 
        .A_BLK({VCC_net_1, VCC_net_1, VCC_net_1}), .A_DOUT_ARST_N(
        VCC_net_1), .A_DOUT_SRST_N(VCC_net_1), .A_DIN({GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1}), .A_ADDR({un42_AXI_DATA_s_10_S, 
        un42_AXI_DATA_cry_9_S, un42_AXI_DATA_cry_8_S, 
        un42_AXI_DATA_cry_7_S, un42_AXI_DATA_cry_6_S, 
        un42_AXI_DATA_cry_5_S, un42_AXI_DATA_cry_4_S, 
        un42_AXI_DATA_cry_3_S, un42_AXI_DATA_cry_2_S, 
        un42_AXI_DATA_cry_1_S, un42_AXI_DATA_cry_0_Y, GND_net_1, 
        GND_net_1, GND_net_1}), .A_WEN({GND_net_1, GND_net_1}), .B_CLK(
        CCC_0_GL0), .B_DOUT_CLK(VCC_net_1), .B_ARST_N(VCC_net_1), 
        .B_DOUT_EN(VCC_net_1), .B_BLK({VCC_net_1, VCC_net_1, VCC_net_1})
        , .B_DOUT_ARST_N(VCC_net_1), .B_DOUT_SRST_N(VCC_net_1), .B_DIN({
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        AHB_IF_0_DATAOUT[7], AHB_IF_0_DATAOUT[6], AHB_IF_0_DATAOUT[5], 
        AHB_IF_0_DATAOUT[4], AHB_IF_0_DATAOUT[3], AHB_IF_0_DATAOUT[2], 
        AHB_IF_0_DATAOUT[1], AHB_IF_0_DATAOUT[0]}), .B_ADDR({
        \nbytes[10]_net_1 , \nbytes[9]_net_1 , \nbytes[8]_net_1 , 
        \nbytes[7]_net_1 , \nbytes[6]_net_1 , \nbytes[5]_net_1 , 
        \nbytes[4]_net_1 , \nbytes[3]_net_1 , \nbytes[2]_net_1 , 
        \nbytes[1]_net_1 , \nbytes[0]_net_1 , GND_net_1, GND_net_1, 
        GND_net_1}), .B_WEN({GND_net_1, read_byte_read_byte_0_0_we}), 
        .A_EN(VCC_net_1), .A_DOUT_LAT(VCC_net_1), .A_WIDTH({GND_net_1, 
        VCC_net_1, VCC_net_1}), .A_WMODE(GND_net_1), .B_EN(VCC_net_1), 
        .B_DOUT_LAT(VCC_net_1), .B_WIDTH({GND_net_1, VCC_net_1, 
        VCC_net_1}), .B_WMODE(GND_net_1), .SII_LOCK(GND_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un12_AXI_DATA_cry_4 (.A(VCC_net_1), .B(
        \nbytes[5]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un12_AXI_DATA_cry_3_net_1), .S(un12_AXI_DATA_cry_4_S), .Y(), 
        .FCO(un12_AXI_DATA_cry_4_net_1));
    CFG2 #( .INIT(4'h8) )  \DATAOUT_1_RNO[7]  (.A(
        \SPI_current_state[2]_net_1 ), .B(\CMD[7]_net_1 ), .Y(
        \DATAOUT_14[7] ));
    SLE \SPI_current_state[10]  (.D(N_284_i_0), .CLK(CCC_0_GL0), .EN(
        VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SPI_current_state[10]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un2_block_address_1_cry_12 (.A(
        VCC_net_1), .B(\block_address[22]_net_1 ), .C(GND_net_1), .D(
        GND_net_1), .FCI(un2_block_address_1_cry_11_net_1), .S(
        un2_block_address_1_cry_12_S), .Y(), .FCO(
        un2_block_address_1_cry_12_net_1));
    ARI1 #( .INIT(20'h5DF20) )  un1_nbytes_2_cry_0_0 (.A(
        \nbytes[0]_net_1 ), .B(N_36), .C(AHB_IF_0_AHB_BUSY), .D(
        \SPI_current_state[9]_net_1 ), .FCI(GND_net_1), .S(), .Y(
        un1_nbytes_2_cry_0_0_Y), .FCO(un1_nbytes_2_cry_0));
    SLE \AXI_DATA_ret_0[0]  (.D(SPI_to_MDDR_0_AXI_DATA[8]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[8] ));
    SLE \ADDR_1[2]  (.D(N_315_i_0), .CLK(CCC_0_GL0), .EN(
        un1_READ_0_sqmuxa_2_net_1), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(SPI_to_MDDR_0_ADDR_0));
    SLE READ (.D(N_385_1), .CLK(CCC_0_GL0), .EN(N_311_i_0), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(SPI_to_MDDR_0_READ));
    CFG3 #( .INIT(8'hD0) )  \nbytes_RNO[10]  (.A(N_765), .B(
        un1_nbytes_1_sqmuxa_1_0_net_1), .C(un1_nbytes_2_cry_10_S), .Y(
        \nbytes_10[10] ));
    SLE \block_address[11]  (.D(un2_block_address_1_cry_1_S), .CLK(
        CCC_0_GL0), .EN(CMD_count_0_sqmuxa_1), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\block_address[11]_net_1 ));
    CFG4 #( .INIT(16'hD800) )  read_byte_4_read_byte_0_0_RNIGQ241 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[21] ), .C(
        \AXI_DATA_reto[21] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[21]));
    RAM1K18 read_byte_4_read_byte_0_0 (.A_DOUT({nc76, nc77, nc78, nc79, 
        nc80, nc81, nc82, nc83, nc84, nc85, \read_byte_reto[23] , 
        \read_byte_reto[22] , \read_byte_reto[21] , 
        \read_byte_reto[20] , \read_byte_reto[19] , 
        \read_byte_reto[18] , \read_byte_reto[17] , 
        \read_byte_reto[16] }), .B_DOUT({nc86, nc87, nc88, nc89, nc90, 
        nc91, nc92, nc93, nc94, nc95, nc96, nc97, nc98, nc99, nc100, 
        nc101, nc102, nc103}), .BUSY(), .A_CLK(CCC_0_GL0), .A_DOUT_CLK(
        VCC_net_1), .A_ARST_N(VCC_net_1), .A_DOUT_EN(VCC_net_1), 
        .A_BLK({VCC_net_1, VCC_net_1, VCC_net_1}), .A_DOUT_ARST_N(
        VCC_net_1), .A_DOUT_SRST_N(VCC_net_1), .A_DIN({GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1}), .A_ADDR({un12_AXI_DATA_s_9_S, 
        un12_AXI_DATA_cry_8_S, un12_AXI_DATA_cry_7_S, 
        un12_AXI_DATA_cry_6_S, un12_AXI_DATA_cry_5_S, 
        un12_AXI_DATA_cry_4_S, un12_AXI_DATA_cry_3_S, 
        un12_AXI_DATA_cry_2_S, un12_AXI_DATA_cry_1_S, \nbytes_i_0[1] , 
        \nbytes[0]_net_1 , GND_net_1, GND_net_1, GND_net_1}), .A_WEN({
        GND_net_1, GND_net_1}), .B_CLK(CCC_0_GL0), .B_DOUT_CLK(
        VCC_net_1), .B_ARST_N(VCC_net_1), .B_DOUT_EN(VCC_net_1), 
        .B_BLK({VCC_net_1, VCC_net_1, VCC_net_1}), .B_DOUT_ARST_N(
        VCC_net_1), .B_DOUT_SRST_N(VCC_net_1), .B_DIN({GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        AHB_IF_0_DATAOUT[7], AHB_IF_0_DATAOUT[6], AHB_IF_0_DATAOUT[5], 
        AHB_IF_0_DATAOUT[4], AHB_IF_0_DATAOUT[3], AHB_IF_0_DATAOUT[2], 
        AHB_IF_0_DATAOUT[1], AHB_IF_0_DATAOUT[0]}), .B_ADDR({
        \nbytes[10]_net_1 , \nbytes[9]_net_1 , \nbytes[8]_net_1 , 
        \nbytes[7]_net_1 , \nbytes[6]_net_1 , \nbytes[5]_net_1 , 
        \nbytes[4]_net_1 , \nbytes[3]_net_1 , \nbytes[2]_net_1 , 
        \nbytes[1]_net_1 , \nbytes[0]_net_1 , GND_net_1, GND_net_1, 
        GND_net_1}), .B_WEN({GND_net_1, read_byte_4_read_byte_0_0_we}), 
        .A_EN(VCC_net_1), .A_DOUT_LAT(VCC_net_1), .A_WIDTH({GND_net_1, 
        VCC_net_1, VCC_net_1}), .A_WMODE(GND_net_1), .B_EN(VCC_net_1), 
        .B_DOUT_LAT(VCC_net_1), .B_WIDTH({GND_net_1, VCC_net_1, 
        VCC_net_1}), .B_WMODE(GND_net_1), .SII_LOCK(GND_net_1));
    SLE \block_address[18]  (.D(un2_block_address_1_cry_8_S), .CLK(
        CCC_0_GL0), .EN(CMD_count_0_sqmuxa_1), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\block_address[18]_net_1 ));
    CFG3 #( .INIT(8'h40) )  \SPI_current_state_ns_i_o2_i_a2[1]  (.A(
        AHB_IF_0_AHB_BUSY), .B(DP_SW1_c), .C(
        \SPI_current_state[0]_net_1 ), .Y(N_339_i_0));
    SLE \AXI_DATA_ret_3[5]  (.D(SPI_to_MDDR_0_AXI_DATA[53]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[53] ));
    CFG3 #( .INIT(8'h0B) )  \ADDR_17_i_0_a2_0_0[2]  (.A(
        \reg_count[1]_net_1 ), .B(\reg_count[2]_net_1 ), .C(
        \reg_count[0]_net_1 ), .Y(\ADDR_17_i_0_a2_0[2] ));
    ARI1 #( .INIT(20'h4AA00) )  un5_AXI_DATA_cry_6 (.A(VCC_net_1), .B(
        \nbytes[6]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un5_AXI_DATA_cry_5_net_1), .S(un5_AXI_DATA_cry_6_S), .Y(), 
        .FCO(un5_AXI_DATA_cry_6_net_1));
    CFG4 #( .INIT(16'h0004) )  un1_READ_0_sqmuxa_3_i_a5_1_0 (.A(
        \SPI_current_state[8]_net_1 ), .B(un41_i_a2_1_net_1), .C(
        \SPI_current_state[14]_net_1 ), .D(
        \SPI_current_state[13]_net_1 ), .Y(
        un1_READ_0_sqmuxa_3_i_a5_1_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un18_AXI_DATA_s_10 (.A(VCC_net_1), .B(
        \nbytes[10]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un18_AXI_DATA_cry_9_net_1), .S(un18_AXI_DATA_s_10_S), .Y(), 
        .FCO());
    SLE \AXI_DATA_ret[7]  (.D(SPI_to_MDDR_0_AXI_DATA[31]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[31] ));
    SLE \AXI_DATA_ret_1[6]  (.D(SPI_to_MDDR_0_AXI_DATA[38]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[38] ));
    CFG3 #( .INIT(8'h20) )  read_byte_1_read_byte_0_0_RNO (.A(
        MSS_HPMS_READY), .B(AHB_IF_0_AHB_BUSY), .C(
        \SPI_current_state[9]_net_1 ), .Y(read_byte_1_read_byte_0_0_we)
        );
    CFG4 #( .INIT(16'hD800) )  \AXI_DATA_ret_4_RNIQTVG1[4]  (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[60] ), .C(
        \AXI_DATA_reto[60] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[60]));
    CFG4 #( .INIT(16'h0004) )  un41_i_a2_4 (.A(
        \SPI_current_state[0]_net_1 ), .B(un41_i_a2_2_net_1), .C(
        \SPI_current_state[8]_net_1 ), .D(\SPI_current_state[5]_net_1 )
        , .Y(un41_i_a2_4_net_1));
    CFG4 #( .INIT(16'hD800) )  read_byte_3_read_byte_0_0_RNILGGV (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[24] ), .C(
        \AXI_DATA_reto[24] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[24]));
    CFG3 #( .INIT(8'hD0) )  \nbytes_RNO[7]  (.A(N_765), .B(
        un1_nbytes_1_sqmuxa_1_0_net_1), .C(un1_nbytes_2_cry_7_S), .Y(
        \nbytes_10[7] ));
    CFG4 #( .INIT(16'h0082) )  \reg_count_RNO[0]  (.A(N_884), .B(
        \reg_count[0]_net_1 ), .C(N_332), .D(CMD_count_0_sqmuxa_1), .Y(
        N_320_i_0));
    ARI1 #( .INIT(20'h4AA00) )  un24_AXI_DATA_cry_3 (.A(VCC_net_1), .B(
        \nbytes[5]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un24_AXI_DATA_cry_2_net_1), .S(un24_AXI_DATA_cry_3_S), .Y(), 
        .FCO(un24_AXI_DATA_cry_3_net_1));
    RAM1K18 read_byte_0_read_byte_0_0 (.A_DOUT({nc104, nc105, nc106, 
        nc107, nc108, nc109, nc110, nc111, nc112, nc113, 
        \read_byte_reto[55] , \read_byte_reto[54] , 
        \read_byte_reto[53] , \read_byte_reto[52] , 
        \read_byte_reto[51] , \read_byte_reto[50] , 
        \read_byte_reto[49] , \read_byte_reto[48] }), .B_DOUT({nc114, 
        nc115, nc116, nc117, nc118, nc119, nc120, nc121, nc122, nc123, 
        nc124, nc125, nc126, nc127, nc128, nc129, nc130, nc131}), 
        .BUSY(), .A_CLK(CCC_0_GL0), .A_DOUT_CLK(VCC_net_1), .A_ARST_N(
        VCC_net_1), .A_DOUT_EN(VCC_net_1), .A_BLK({VCC_net_1, 
        VCC_net_1, VCC_net_1}), .A_DOUT_ARST_N(VCC_net_1), 
        .A_DOUT_SRST_N(VCC_net_1), .A_DIN({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1}), .A_ADDR({un36_AXI_DATA_s_9_S, 
        un36_AXI_DATA_cry_8_S, un36_AXI_DATA_cry_7_S, 
        un36_AXI_DATA_cry_6_S, un36_AXI_DATA_cry_5_S, 
        un36_AXI_DATA_cry_4_S, un36_AXI_DATA_cry_3_S, 
        un36_AXI_DATA_cry_2_S, un36_AXI_DATA_cry_1_S, 
        un36_AXI_DATA_cry_0_Y, \nbytes[0]_net_1 , GND_net_1, GND_net_1, 
        GND_net_1}), .A_WEN({GND_net_1, GND_net_1}), .B_CLK(CCC_0_GL0), 
        .B_DOUT_CLK(VCC_net_1), .B_ARST_N(VCC_net_1), .B_DOUT_EN(
        VCC_net_1), .B_BLK({VCC_net_1, VCC_net_1, VCC_net_1}), 
        .B_DOUT_ARST_N(VCC_net_1), .B_DOUT_SRST_N(VCC_net_1), .B_DIN({
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        AHB_IF_0_DATAOUT[7], AHB_IF_0_DATAOUT[6], AHB_IF_0_DATAOUT[5], 
        AHB_IF_0_DATAOUT[4], AHB_IF_0_DATAOUT[3], AHB_IF_0_DATAOUT[2], 
        AHB_IF_0_DATAOUT[1], AHB_IF_0_DATAOUT[0]}), .B_ADDR({
        \nbytes[10]_net_1 , \nbytes[9]_net_1 , \nbytes[8]_net_1 , 
        \nbytes[7]_net_1 , \nbytes[6]_net_1 , \nbytes[5]_net_1 , 
        \nbytes[4]_net_1 , \nbytes[3]_net_1 , \nbytes[2]_net_1 , 
        \nbytes[1]_net_1 , \nbytes[0]_net_1 , GND_net_1, GND_net_1, 
        GND_net_1}), .B_WEN({GND_net_1, read_byte_0_read_byte_0_0_we}), 
        .A_EN(VCC_net_1), .A_DOUT_LAT(VCC_net_1), .A_WIDTH({GND_net_1, 
        VCC_net_1, VCC_net_1}), .A_WMODE(GND_net_1), .B_EN(VCC_net_1), 
        .B_DOUT_LAT(VCC_net_1), .B_WIDTH({GND_net_1, VCC_net_1, 
        VCC_net_1}), .B_WMODE(GND_net_1), .SII_LOCK(GND_net_1));
    CFG4 #( .INIT(16'h3021) )  \CMD_count_RNO[1]  (.A(N_335), .B(
        CMD_count_0_sqmuxa_1), .C(\CMD_count[1]_net_1 ), .D(N_336), .Y(
        N_50_i_0));
    ARI1 #( .INIT(20'h4AA00) )  un1_nbytes_2_cry_7 (.A(VCC_net_1), .B(
        \nbytes[7]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_nbytes_2_cry_6_net_1), .S(un1_nbytes_2_cry_7_S), .Y(), 
        .FCO(un1_nbytes_2_cry_7_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un24_AXI_DATA_cry_2 (.A(VCC_net_1), .B(
        \nbytes[4]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un24_AXI_DATA_cry_1_net_1), .S(un24_AXI_DATA_cry_2_S), .Y(), 
        .FCO(un24_AXI_DATA_cry_2_net_1));
    CFG4 #( .INIT(16'hD800) )  \AXI_DATA_ret_0_RNI7IBC1[1]  (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[9] ), .C(
        \AXI_DATA_reto[9] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[9]));
    ARI1 #( .INIT(20'h65500) )  un42_AXI_DATA_cry_2 (.A(VCC_net_1), .B(
        \nbytes[2]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un42_AXI_DATA_cry_1_net_1), .S(un42_AXI_DATA_cry_2_S), .Y(), 
        .FCO(un42_AXI_DATA_cry_2_net_1));
    CFG3 #( .INIT(8'hD0) )  \nbytes_RNO[8]  (.A(N_765), .B(
        un1_nbytes_1_sqmuxa_1_0_net_1), .C(un1_nbytes_2_cry_8_S), .Y(
        \nbytes_10[8] ));
    SLE \CMD[1]  (.D(N_44_i_0), .CLK(CCC_0_GL0), .EN(VCC_net_1), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\CMD[1]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un42_AXI_DATA_cry_5 (.A(VCC_net_1), .B(
        \nbytes[5]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un42_AXI_DATA_cry_4_net_1), .S(un42_AXI_DATA_cry_5_S), .Y(), 
        .FCO(un42_AXI_DATA_cry_5_net_1));
    CFG3 #( .INIT(8'h13) )  \CMD_count_7_i_0[2]  (.A(
        \CMD_count[0]_net_1 ), .B(\CMD_count[2]_net_1 ), .C(
        \CMD_count[1]_net_1 ), .Y(\CMD_count_7_i_0[2]_net_1 ));
    CFG4 #( .INIT(16'hD800) )  read_byte_0_read_byte_0_0_RNIAQB51 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[54] ), .C(
        \AXI_DATA_reto[54] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[54]));
    ARI1 #( .INIT(20'h4AA00) )  \nblocks_cry[4]  (.A(VCC_net_1), .B(
        \nblocks[4]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \nblocks_cry[3]_net_1 ), .S(\nblocks_s[4] ), .Y(), .FCO(
        \nblocks_cry[4]_net_1 ));
    SLE \DATAOUT_1[7]  (.D(\DATAOUT_14[7] ), .CLK(CCC_0_GL0), .EN(
        un1_M3_RESETn_0_sqmuxa_2_net_1), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(SPI_to_MDDR_0_DATAOUT_7));
    CFG4 #( .INIT(16'hFFF8) )  \SPI_current_state_ns_0[3]  (.A(N_389), 
        .B(\SPI_current_state[1]_net_1 ), .C(
        \SPI_current_state_ns_0_RNO[3]_net_1 ), .D(
        \SPI_current_state_ns_0_0[3]_net_1 ), .Y(
        \SPI_current_state_ns[3] ));
    ARI1 #( .INIT(20'h4AA00) )  un2_block_address_1_cry_4 (.A(
        VCC_net_1), .B(\block_address[14]_net_1 ), .C(GND_net_1), .D(
        GND_net_1), .FCI(un2_block_address_1_cry_3_net_1), .S(
        un2_block_address_1_cry_4_S), .Y(), .FCO(
        un2_block_address_1_cry_4_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un24_AXI_DATA_s_8 (.A(VCC_net_1), .B(
        \nbytes[10]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un24_AXI_DATA_cry_7_net_1), .S(un24_AXI_DATA_s_8_S), .Y(), 
        .FCO());
    ARI1 #( .INIT(20'h4AA00) )  un24_AXI_DATA_s_1_312 (.A(VCC_net_1), 
        .B(\nbytes[2]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        VCC_net_1), .S(), .Y(), .FCO(un24_AXI_DATA_s_1_312_FCO));
    SLE \block_address[13]  (.D(un2_block_address_1_cry_3_S), .CLK(
        CCC_0_GL0), .EN(CMD_count_0_sqmuxa_1), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\block_address[13]_net_1 ));
    SLE \SPI_current_state[9]  (.D(\SPI_current_state[8]_net_1 ), .CLK(
        CCC_0_GL0), .EN(AHB_IF_0_AHB_BUSY_i_0), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\SPI_current_state[9]_net_1 ));
    SLE \DATAOUT_1[3]  (.D(\DATAOUT_14[3] ), .CLK(CCC_0_GL0), .EN(
        un1_M3_RESETn_0_sqmuxa_2_net_1), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(SPI_to_MDDR_0_DATAOUT_3));
    ARI1 #( .INIT(20'h4AA00) )  un12_AXI_DATA_cry_6 (.A(VCC_net_1), .B(
        \nbytes[7]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un12_AXI_DATA_cry_5_net_1), .S(un12_AXI_DATA_cry_6_S), .Y(), 
        .FCO(un12_AXI_DATA_cry_6_net_1));
    CFG4 #( .INIT(16'hA0AC) )  \SPI_current_state_ns[8]  (.A(
        \SPI_current_state[8]_net_1 ), .B(\SPI_current_state[7]_net_1 )
        , .C(AHB_IF_0_AHB_BUSY), .D(AHB_IF_0_DATAOUT[6]), .Y(
        \SPI_current_state_ns[8]_net_1 ));
    RAM1K18 read_byte_2_read_byte_0_0 (.A_DOUT({nc132, nc133, nc134, 
        nc135, nc136, nc137, nc138, nc139, nc140, nc141, 
        \read_byte_reto[39] , \read_byte_reto[38] , 
        \read_byte_reto[37] , \read_byte_reto[36] , 
        \read_byte_reto[35] , \read_byte_reto[34] , 
        \read_byte_reto[33] , \read_byte_reto[32] }), .B_DOUT({nc142, 
        nc143, nc144, nc145, nc146, nc147, nc148, nc149, nc150, nc151, 
        nc152, nc153, nc154, nc155, nc156, nc157, nc158, nc159}), 
        .BUSY(), .A_CLK(CCC_0_GL0), .A_DOUT_CLK(VCC_net_1), .A_ARST_N(
        VCC_net_1), .A_DOUT_EN(VCC_net_1), .A_BLK({VCC_net_1, 
        VCC_net_1, VCC_net_1}), .A_DOUT_ARST_N(VCC_net_1), 
        .A_DOUT_SRST_N(VCC_net_1), .A_DIN({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1}), .A_ADDR({un24_AXI_DATA_s_8_S, 
        un24_AXI_DATA_cry_7_S, un24_AXI_DATA_cry_6_S, 
        un24_AXI_DATA_cry_5_S, un24_AXI_DATA_cry_4_S, 
        un24_AXI_DATA_cry_3_S, un24_AXI_DATA_cry_2_S, 
        un24_AXI_DATA_cry_1_S, \nbytes_i_0[2] , \nbytes[1]_net_1 , 
        \nbytes[0]_net_1 , GND_net_1, GND_net_1, GND_net_1}), .A_WEN({
        GND_net_1, GND_net_1}), .B_CLK(CCC_0_GL0), .B_DOUT_CLK(
        VCC_net_1), .B_ARST_N(VCC_net_1), .B_DOUT_EN(VCC_net_1), 
        .B_BLK({VCC_net_1, VCC_net_1, VCC_net_1}), .B_DOUT_ARST_N(
        VCC_net_1), .B_DOUT_SRST_N(VCC_net_1), .B_DIN({GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        AHB_IF_0_DATAOUT[7], AHB_IF_0_DATAOUT[6], AHB_IF_0_DATAOUT[5], 
        AHB_IF_0_DATAOUT[4], AHB_IF_0_DATAOUT[3], AHB_IF_0_DATAOUT[2], 
        AHB_IF_0_DATAOUT[1], AHB_IF_0_DATAOUT[0]}), .B_ADDR({
        \nbytes[10]_net_1 , \nbytes[9]_net_1 , \nbytes[8]_net_1 , 
        \nbytes[7]_net_1 , \nbytes[6]_net_1 , \nbytes[5]_net_1 , 
        \nbytes[4]_net_1 , \nbytes[3]_net_1 , \nbytes[2]_net_1 , 
        \nbytes[1]_net_1 , \nbytes[0]_net_1 , GND_net_1, GND_net_1, 
        GND_net_1}), .B_WEN({GND_net_1, read_byte_2_read_byte_0_0_we}), 
        .A_EN(VCC_net_1), .A_DOUT_LAT(VCC_net_1), .A_WIDTH({GND_net_1, 
        VCC_net_1, VCC_net_1}), .A_WMODE(GND_net_1), .B_EN(VCC_net_1), 
        .B_DOUT_LAT(VCC_net_1), .B_WIDTH({GND_net_1, VCC_net_1, 
        VCC_net_1}), .B_WMODE(GND_net_1), .SII_LOCK(GND_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un2_block_address_1_cry_5 (.A(
        VCC_net_1), .B(\block_address[15]_net_1 ), .C(GND_net_1), .D(
        GND_net_1), .FCI(un2_block_address_1_cry_4_net_1), .S(
        un2_block_address_1_cry_5_S), .Y(), .FCO(
        un2_block_address_1_cry_5_net_1));
    SLE \AXI_DATA_ret_2[2]  (.D(SPI_to_MDDR_0_AXI_DATA[42]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[42] ));
    CFG4 #( .INIT(16'h2300) )  ADDR_17_1_327_i_a6_1 (.A(
        \reg_count[0]_net_1 ), .B(\reg_count[1]_net_1 ), .C(
        \reg_count[2]_net_1 ), .D(\SPI_current_state[1]_net_1 ), .Y(
        N_852));
    ARI1 #( .INIT(20'h4AA00) )  un42_AXI_DATA_cry_3 (.A(VCC_net_1), .B(
        \nbytes[3]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un42_AXI_DATA_cry_2_net_1), .S(un42_AXI_DATA_cry_3_S), .Y(), 
        .FCO(un42_AXI_DATA_cry_3_net_1));
    SLE AXI_WRITE (.D(\SPI_current_state[10]_net_1 ), .CLK(CCC_0_GL0), 
        .EN(N_267_i_0), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        SPI_to_MDDR_0_AXI_WRITE));
    SLE \nbytes[11]  (.D(\nbytes_10[11] ), .CLK(CCC_0_GL0), .EN(
        VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \nbytes[11]_net_1 ));
    SLE \block_address[17]  (.D(un2_block_address_1_cry_7_S), .CLK(
        CCC_0_GL0), .EN(CMD_count_0_sqmuxa_1), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\block_address[17]_net_1 ));
    ARI1 #( .INIT(20'h65500) )  un36_AXI_DATA_cry_1 (.A(VCC_net_1), .B(
        \nbytes[2]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un36_AXI_DATA_cry_0_net_1), .S(un36_AXI_DATA_cry_1_S), .Y(), 
        .FCO(un36_AXI_DATA_cry_1_net_1));
    RAM1K18 read_byte_3_read_byte_0_0 (.A_DOUT({nc160, nc161, nc162, 
        nc163, nc164, nc165, nc166, nc167, nc168, nc169, 
        \read_byte_reto[31] , \read_byte_reto[30] , 
        \read_byte_reto[29] , \read_byte_reto[28] , 
        \read_byte_reto[27] , \read_byte_reto[26] , 
        \read_byte_reto[25] , \read_byte_reto[24] }), .B_DOUT({nc170, 
        nc171, nc172, nc173, nc174, nc175, nc176, nc177, nc178, nc179, 
        nc180, nc181, nc182, nc183, nc184, nc185, nc186, nc187}), 
        .BUSY(), .A_CLK(CCC_0_GL0), .A_DOUT_CLK(VCC_net_1), .A_ARST_N(
        VCC_net_1), .A_DOUT_EN(VCC_net_1), .A_BLK({VCC_net_1, 
        VCC_net_1, VCC_net_1}), .A_DOUT_ARST_N(VCC_net_1), 
        .A_DOUT_SRST_N(VCC_net_1), .A_DIN({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1}), .A_ADDR({un18_AXI_DATA_s_10_S, 
        un18_AXI_DATA_cry_9_S, un18_AXI_DATA_cry_8_S, 
        un18_AXI_DATA_cry_7_S, un18_AXI_DATA_cry_6_S, 
        un18_AXI_DATA_cry_5_S, un18_AXI_DATA_cry_4_S, 
        un18_AXI_DATA_cry_3_S, un18_AXI_DATA_cry_2_S, 
        un18_AXI_DATA_cry_1_S, un18_AXI_DATA_cry_0_Y, GND_net_1, 
        GND_net_1, GND_net_1}), .A_WEN({GND_net_1, GND_net_1}), .B_CLK(
        CCC_0_GL0), .B_DOUT_CLK(VCC_net_1), .B_ARST_N(VCC_net_1), 
        .B_DOUT_EN(VCC_net_1), .B_BLK({VCC_net_1, VCC_net_1, VCC_net_1})
        , .B_DOUT_ARST_N(VCC_net_1), .B_DOUT_SRST_N(VCC_net_1), .B_DIN({
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        AHB_IF_0_DATAOUT[7], AHB_IF_0_DATAOUT[6], AHB_IF_0_DATAOUT[5], 
        AHB_IF_0_DATAOUT[4], AHB_IF_0_DATAOUT[3], AHB_IF_0_DATAOUT[2], 
        AHB_IF_0_DATAOUT[1], AHB_IF_0_DATAOUT[0]}), .B_ADDR({
        \nbytes[10]_net_1 , \nbytes[9]_net_1 , \nbytes[8]_net_1 , 
        \nbytes[7]_net_1 , \nbytes[6]_net_1 , \nbytes[5]_net_1 , 
        \nbytes[4]_net_1 , \nbytes[3]_net_1 , \nbytes[2]_net_1 , 
        \nbytes[1]_net_1 , \nbytes[0]_net_1 , GND_net_1, GND_net_1, 
        GND_net_1}), .B_WEN({GND_net_1, read_byte_3_read_byte_0_0_we}), 
        .A_EN(VCC_net_1), .A_DOUT_LAT(VCC_net_1), .A_WIDTH({GND_net_1, 
        VCC_net_1, VCC_net_1}), .A_WMODE(GND_net_1), .B_EN(VCC_net_1), 
        .B_DOUT_LAT(VCC_net_1), .B_WIDTH({GND_net_1, VCC_net_1, 
        VCC_net_1}), .B_WMODE(GND_net_1), .SII_LOCK(GND_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un30_AXI_DATA_cry_1 (.A(VCC_net_1), .B(
        \nbytes[1]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un30_AXI_DATA_cry_0_net_1), .S(un30_AXI_DATA_cry_1_S), .Y(), 
        .FCO(un30_AXI_DATA_cry_1_net_1));
    CFG4 #( .INIT(16'h3021) )  \CMD_count_RNO[0]  (.A(N_335), .B(
        CMD_count_0_sqmuxa_1), .C(\CMD_count[0]_net_1 ), .D(
        \CMD_count[2]_net_1 ), .Y(N_52_i_0));
    ARI1 #( .INIT(20'h4AA00) )  un12_AXI_DATA_cry_3 (.A(VCC_net_1), .B(
        \nbytes[4]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un12_AXI_DATA_cry_2_net_1), .S(un12_AXI_DATA_cry_3_S), .Y(), 
        .FCO(un12_AXI_DATA_cry_3_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un18_AXI_DATA_cry_9 (.A(VCC_net_1), .B(
        \nbytes[9]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un18_AXI_DATA_cry_8_net_1), .S(un18_AXI_DATA_cry_9_S), .Y(), 
        .FCO(un18_AXI_DATA_cry_9_net_1));
    CFG4 #( .INIT(16'hFBBB) )  ADDR_17_0_347 (.A(N_328), .B(
        SPI_current_state_1_sqmuxa_1), .C(\reg_count[1]_net_1 ), .D(
        N_327), .Y(N_853));
    CFG2 #( .INIT(4'h1) )  \DATAOUT_1_RNO[10]  (.A(N_313_1), .B(
        \reg_count[1]_net_1 ), .Y(N_313_i_0));
    SLE \AXI_DATA_ret_6[5]  (.D(SPI_to_MDDR_0_AXI_DATA[21]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[21] ));
    ARI1 #( .INIT(20'h4AA00) )  un5_AXI_DATA_cry_7 (.A(VCC_net_1), .B(
        \nbytes[7]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un5_AXI_DATA_cry_6_net_1), .S(un5_AXI_DATA_cry_7_S), .Y(), 
        .FCO(un5_AXI_DATA_cry_7_net_1));
    CFG4 #( .INIT(16'hD800) )  read_byte_1_read_byte_0_0_RNI72431 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[43] ), .C(
        \AXI_DATA_reto[43] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[43]));
    ARI1 #( .INIT(20'h4AA00) )  un36_AXI_DATA_cry_8 (.A(VCC_net_1), .B(
        \nbytes[9]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un36_AXI_DATA_cry_7_net_1), .S(un36_AXI_DATA_cry_8_S), .Y(), 
        .FCO(un36_AXI_DATA_cry_8_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un5_AXI_DATA_cry_1 (.A(VCC_net_1), .B(
        \nbytes[1]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un5_AXI_DATA_s_1_309_FCO), .S(un5_AXI_DATA_cry_1_S), .Y(), 
        .FCO(un5_AXI_DATA_cry_1_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un30_AXI_DATA_cry_8 (.A(VCC_net_1), .B(
        \nbytes[8]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un30_AXI_DATA_cry_7_net_1), .S(un30_AXI_DATA_cry_8_S), .Y(), 
        .FCO(un30_AXI_DATA_cry_8_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un18_AXI_DATA_cry_5 (.A(VCC_net_1), .B(
        \nbytes[5]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un18_AXI_DATA_cry_4_net_1), .S(un18_AXI_DATA_cry_5_S), .Y(), 
        .FCO(un18_AXI_DATA_cry_5_net_1));
    CFG1 #( .INIT(2'h1) )  read_byte_5_read_byte_0_0_RNO (.A(
        \nbytes[0]_net_1 ), .Y(\nbytes_i_0[0] ));
    CFG4 #( .INIT(16'hEFFF) )  un1_READ_0_sqmuxa_2 (.A(
        un1_READ_0_sqmuxa_2_1_net_1), .B(un1_READ_0_sqmuxa_2_0_net_1), 
        .C(N_309), .D(N_36), .Y(un1_READ_0_sqmuxa_2_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un2_block_address_1_cry_2 (.A(
        VCC_net_1), .B(\block_address[12]_net_1 ), .C(GND_net_1), .D(
        GND_net_1), .FCI(un2_block_address_1_cry_1_net_1), .S(
        un2_block_address_1_cry_2_S), .Y(), .FCO(
        un2_block_address_1_cry_2_net_1));
    CFG4 #( .INIT(16'hD800) )  \AXI_DATA_ret_5_RNIC1RH1[1]  (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[1] ), .C(
        \AXI_DATA_reto[1] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[1]));
    SLE \AXI_DATA_ret_3[2]  (.D(SPI_to_MDDR_0_AXI_DATA[50]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[50] ));
    ARI1 #( .INIT(20'h4AA00) )  un2_block_address_1_cry_1 (.A(
        VCC_net_1), .B(\block_address[11]_net_1 ), .C(GND_net_1), .D(
        GND_net_1), .FCI(un2_block_address_1_s_1_308_FCO), .S(
        un2_block_address_1_cry_1_S), .Y(), .FCO(
        un2_block_address_1_cry_1_net_1));
    CFG3 #( .INIT(8'hD0) )  un41_i_a2 (.A(
        \SPI_current_state[10]_net_1 ), .B(nbytes_1_sqmuxa_1_net_1), 
        .C(un41_i_a2_7_net_1), .Y(N_765));
    SLE \SPI_current_state[11]  (.D(\SPI_current_state_ns[11] ), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\SPI_current_state[11]_net_1 ));
    CFG4 #( .INIT(16'hD800) )  read_byte_1_read_byte_0_0_RNI61431 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[42] ), .C(
        \AXI_DATA_reto[42] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[42]));
    ARI1 #( .INIT(20'h4AA00) )  un1_nbytes_2_cry_1 (.A(VCC_net_1), .B(
        \nbytes[1]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_nbytes_2_cry_0), .S(un1_nbytes_2_cry_1_S), .Y(), .FCO(
        un1_nbytes_2_cry_1_net_1));
    CFG4 #( .INIT(16'hFFEC) )  DATAOUT_14_iv_365_1 (.A(
        \SPI_current_state[2]_net_1 ), .B(N_887), .C(\CMD[0]_net_1 ), 
        .D(\SPI_current_state[11]_net_1 ), .Y(
        DATAOUT_14_iv_365_1_net_1));
    SLE \CMD[4]  (.D(\CMD_6[4] ), .CLK(CCC_0_GL0), .EN(VCC_net_1), 
        .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\CMD[4]_net_1 ));
    SLE \AXI_DATA_ret_6[2]  (.D(SPI_to_MDDR_0_AXI_DATA[18]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[18] ));
    SLE \AXI_DATA_ret_5[2]  (.D(SPI_to_MDDR_0_AXI_DATA[2]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[2] ));
    CFG2 #( .INIT(4'h6) )  block_address_238 (.A(CMD_count_0_sqmuxa_1), 
        .B(\block_address[10]_net_1 ), .Y(block_address_238_net_1));
    ARI1 #( .INIT(20'h595AA) )  un1_nbytes_2_cry_3 (.A(N_765), .B(
        \nbytes[3]_net_1 ), .C(N_36), .D(N_63), .FCI(
        un1_nbytes_2_cry_2_net_1), .S(un1_nbytes_2_cry_3_S), .Y(), 
        .FCO(un1_nbytes_2_cry_3_net_1));
    CFG2 #( .INIT(4'h8) )  \DATAOUT_1_RNO[4]  (.A(
        \SPI_current_state[2]_net_1 ), .B(\CMD[4]_net_1 ), .Y(
        \DATAOUT_14[4] ));
    CFG4 #( .INIT(16'hD800) )  \AXI_DATA_ret_5_RNIB0RH1[0]  (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[0] ), .C(
        \AXI_DATA_reto[0] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[0]));
    CFG4 #( .INIT(16'hFFBF) )  un1_M3_RESETn_0_sqmuxa_2 (.A(
        un1_M3_RESETn_0_sqmuxa_2_0_net_1), .B(N_36), .C(
        SPI_current_state_1_sqmuxa_1), .D(reg_count_1_sqmuxa), .Y(
        un1_M3_RESETn_0_sqmuxa_2_net_1));
    CFG2 #( .INIT(4'hE) )  un1_nbyteslto11_0_o2 (.A(\nbytes[10]_net_1 )
        , .B(\nbytes[11]_net_1 ), .Y(N_59));
    SLE \AXI_DATA_ret_2[3]  (.D(SPI_to_MDDR_0_AXI_DATA[43]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[43] ));
    CFG4 #( .INIT(16'h2000) )  un41_i_a2_7 (.A(un41_i_a2_1_net_1), .B(
        CMD_count_1_sqmuxa), .C(un41_i_a2_7_1_net_1), .D(
        un41_i_a2_4_net_1), .Y(un41_i_a2_7_net_1));
    SLE \block_address[16]  (.D(un2_block_address_1_cry_6_S), .CLK(
        CCC_0_GL0), .EN(CMD_count_0_sqmuxa_1), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\block_address[16]_net_1 ));
    CFG3 #( .INIT(8'h10) )  \CMD_6_0_iv_0_a2_2[7]  (.A(
        \CMD_count[0]_net_1 ), .B(\CMD_count[2]_net_1 ), .C(
        \CMD_count[1]_net_1 ), .Y(N_379));
    CFG4 #( .INIT(16'hEAC0) )  \CMD_6_0_iv_0[3]  (.A(
        \block_address[19]_net_1 ), .B(\block_address[11]_net_1 ), .C(
        N_379), .D(N_378), .Y(\CMD_6[3] ));
    SLE \AXI_DATA_ret_3[1]  (.D(SPI_to_MDDR_0_AXI_DATA[49]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[49] ));
    CFG3 #( .INIT(8'h02) )  \SPI_current_state_ns_a5_0_0_a2[0]  (.A(
        \SPI_current_state[11]_net_1 ), .B(\nblocks[7]_net_1 ), .C(
        AXI_IF_0_AXI_BUSY), .Y(CMD_count_0_sqmuxa_1));
    SLE \nblocks[7]  (.D(\nblocks_s[7]_net_1 ), .CLK(CCC_0_GL0), .EN(
        CMD_count_0_sqmuxa_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \nblocks[7]_net_1 ));
    CFG4 #( .INIT(16'h1F0F) )  un1_READ_0_sqmuxa_2_0 (.A(
        AHB_IF_0_AHB_BUSY), .B(AHB_IF_0_DATAOUT[8]), .C(
        SPI_current_state_1_sqmuxa_1), .D(\SPI_current_state[2]_net_1 )
        , .Y(un1_READ_0_sqmuxa_2_0_net_1));
    CFG3 #( .INIT(8'hEA) )  un1_nbytes_1_sqmuxa_1_0 (.A(
        \SPI_current_state[10]_net_1 ), .B(N_63), .C(N_36), .Y(
        un1_nbytes_1_sqmuxa_1_0_net_1));
    CFG4 #( .INIT(16'hD800) )  read_byte_4_read_byte_0_0_RNIFP241 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[20] ), .C(
        \AXI_DATA_reto[20] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[20]));
    ARI1 #( .INIT(20'h4AA00) )  un42_AXI_DATA_cry_9 (.A(VCC_net_1), .B(
        \nbytes[9]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un42_AXI_DATA_cry_8_net_1), .S(un42_AXI_DATA_cry_9_S), .Y(), 
        .FCO(un42_AXI_DATA_cry_9_net_1));
    SLE \CMD[5]  (.D(\CMD_6[5] ), .CLK(CCC_0_GL0), .EN(VCC_net_1), 
        .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\CMD[5]_net_1 ));
    SLE \AXI_DATA_ret_4[5]  (.D(SPI_to_MDDR_0_AXI_DATA[61]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[61] ));
    CFG4 #( .INIT(16'hD800) )  \AXI_DATA_ret_4_RNIT00H1[7]  (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[63] ), .C(
        \AXI_DATA_reto[63] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[63]));
    CFG4 #( .INIT(16'hF777) )  SPI_current_state_0_sqmuxa_2_i (.A(N_59)
        , .B(N_63), .C(un1_nbyteslto11_0_a2_5_net_1), .D(
        un1_nbyteslto11_0_a2_6_net_1), .Y(N_36));
    CFG3 #( .INIT(8'h20) )  read_byte_2_read_byte_0_0_RNO_0 (.A(
        MSS_HPMS_READY), .B(AHB_IF_0_AHB_BUSY), .C(
        \SPI_current_state[9]_net_1 ), .Y(read_byte_2_read_byte_0_0_we)
        );
    CFG3 #( .INIT(8'h40) )  DATAOUT_14_iv_365_a5_1 (.A(N_360), .B(
        DP_SW1_c), .C(\SPI_current_state[0]_net_1 ), .Y(N_887));
    CFG2 #( .INIT(4'h1) )  un1_AXI_WRITE6_i_a2 (.A(
        \SPI_current_state[11]_net_1 ), .B(
        \SPI_current_state[10]_net_1 ), .Y(N_401));
    ARI1 #( .INIT(20'h4AA00) )  un18_AXI_DATA_cry_2 (.A(VCC_net_1), .B(
        \nbytes[2]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un18_AXI_DATA_cry_1_net_1), .S(un18_AXI_DATA_cry_2_S), .Y(), 
        .FCO(un18_AXI_DATA_cry_2_net_1));
    CFG4 #( .INIT(16'hFF20) )  DATAOUT_14_iv_365 (.A(
        \SPI_current_state[1]_net_1 ), .B(N_360), .C(N_884), .D(
        DATAOUT_14_iv_365_1_net_1), .Y(N_869));
    CFG4 #( .INIT(16'hF222) )  \DATAOUT_14_0_iv[3]  (.A(N_360), .B(
        N_309), .C(\CMD[3]_net_1 ), .D(\SPI_current_state[2]_net_1 ), 
        .Y(\DATAOUT_14[3] ));
    SLE \reg_count[1]  (.D(N_322_i_0), .CLK(CCC_0_GL0), .EN(VCC_net_1), 
        .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\reg_count[1]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \nblocks_cry[6]  (.A(VCC_net_1), .B(
        \nblocks[6]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \nblocks_cry[5]_net_1 ), .S(\nblocks_s[6] ), .Y(), .FCO(
        \nblocks_cry[6]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \nblocks_cry[2]  (.A(VCC_net_1), .B(
        \nblocks[2]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \nblocks_cry[1]_net_1 ), .S(\nblocks_s[2] ), .Y(), .FCO(
        \nblocks_cry[2]_net_1 ));
    SLE \AXI_DATA_ret_5[1]  (.D(SPI_to_MDDR_0_AXI_DATA[1]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[1] ));
    CFG4 #( .INIT(16'hD800) )  read_byte_3_read_byte_0_0_RNIMHGV (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[25] ), .C(
        \AXI_DATA_reto[25] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[25]));
    CFG4 #( .INIT(16'hD800) )  read_byte_0_read_byte_0_0_RNI5LB51 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[49] ), .C(
        \AXI_DATA_reto[49] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[49]));
    CFG4 #( .INIT(16'h0405) )  \CMD_RNO[1]  (.A(\CMD_count[1]_net_1 ), 
        .B(\block_address[17]_net_1 ), .C(\CMD_count[2]_net_1 ), .D(
        \CMD_count[0]_net_1 ), .Y(N_44_i_0));
    SLE \AXI_DATA_ret_0[1]  (.D(SPI_to_MDDR_0_AXI_DATA[9]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[9] ));
    SLE \nblocks[2]  (.D(\nblocks_s[2] ), .CLK(CCC_0_GL0), .EN(
        CMD_count_0_sqmuxa_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \nblocks[2]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un5_AXI_DATA_cry_4 (.A(VCC_net_1), .B(
        \nbytes[4]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un5_AXI_DATA_cry_3_net_1), .S(un5_AXI_DATA_cry_4_S), .Y(), 
        .FCO(un5_AXI_DATA_cry_4_net_1));
    SLE \AXI_DATA_ret_0[7]  (.D(SPI_to_MDDR_0_AXI_DATA[15]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[15] ));
    ARI1 #( .INIT(20'h65500) )  un42_AXI_DATA_cry_0 (.A(VCC_net_1), .B(
        \nbytes[0]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        GND_net_1), .S(), .Y(un42_AXI_DATA_cry_0_Y), .FCO(
        un42_AXI_DATA_cry_0_net_1));
    CFG4 #( .INIT(16'h0A0E) )  \SPI_current_state_RNO[10]  (.A(
        \SPI_current_state[10]_net_1 ), .B(
        \SPI_current_state[13]_net_1 ), .C(N_284_1), .D(
        AHB_IF_0_AHB_BUSY), .Y(N_284_i_0));
    SLE \AXI_DATA_ret_5[0]  (.D(SPI_to_MDDR_0_AXI_DATA[0]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[0] ));
    SLE \AXI_DATA_ret_3[3]  (.D(SPI_to_MDDR_0_AXI_DATA[51]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[51] ));
    ARI1 #( .INIT(20'h4AA00) )  un2_block_address_1_cry_9 (.A(
        VCC_net_1), .B(\block_address[19]_net_1 ), .C(GND_net_1), .D(
        GND_net_1), .FCI(un2_block_address_1_cry_8_net_1), .S(
        un2_block_address_1_cry_9_S), .Y(), .FCO(
        un2_block_address_1_cry_9_net_1));
    CFG4 #( .INIT(16'h0111) )  un41_i_a2_2 (.A(
        \SPI_current_state[12]_net_1 ), .B(
        \SPI_current_state[7]_net_1 ), .C(\SPI_current_state[9]_net_1 )
        , .D(AHB_IF_0_AHB_BUSY), .Y(un41_i_a2_2_net_1));
    SLE \AXI_DATA_ret_6[4]  (.D(SPI_to_MDDR_0_AXI_DATA[20]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[20] ));
    SLE \AXI_DATA_ret_4[6]  (.D(SPI_to_MDDR_0_AXI_DATA[62]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[62] ));
    SLE WRITE (.D(N_820_i_0), .CLK(CCC_0_GL0), .EN(
        un1_WRITE_0_sqmuxa_net_1), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(SPI_to_MDDR_0_WRITE));
    ARI1 #( .INIT(20'h4AA00) )  un5_AXI_DATA_cry_5 (.A(VCC_net_1), .B(
        \nbytes[5]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un5_AXI_DATA_cry_4_net_1), .S(un5_AXI_DATA_cry_5_S), .Y(), 
        .FCO(un5_AXI_DATA_cry_5_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un1_nbytes_2_cry_8 (.A(VCC_net_1), .B(
        \nbytes[8]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_nbytes_2_cry_7_net_1), .S(un1_nbytes_2_cry_8_S), .Y(), 
        .FCO(un1_nbytes_2_cry_8_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un1_nbytes_2_cry_4 (.A(VCC_net_1), .B(
        \nbytes[4]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un1_nbytes_2_cry_3_net_1), .S(un1_nbytes_2_cry_4_S), .Y(), 
        .FCO(un1_nbytes_2_cry_4_net_1));
    CFG3 #( .INIT(8'hEF) )  \ADDR_17_i_0_1[2]  (.A(
        \SPI_current_state[7]_net_1 ), .B(\SPI_current_state[9]_net_1 )
        , .C(SPI_current_state_1_sqmuxa_1), .Y(
        \ADDR_17_i_0_1[2]_net_1 ));
    CFG1 #( .INIT(2'h1) )  read_byte_2_read_byte_0_0_RNO (.A(
        \nbytes[2]_net_1 ), .Y(\nbytes_i_0[2] ));
    SLE \reg_count[0]  (.D(N_320_i_0), .CLK(CCC_0_GL0), .EN(VCC_net_1), 
        .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\reg_count[0]_net_1 ));
    CFG4 #( .INIT(16'hD800) )  read_byte_2_read_byte_0_0_RNIBHS01 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[39] ), .C(
        \AXI_DATA_reto[39] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[39]));
    ARI1 #( .INIT(20'h65500) )  un18_AXI_DATA_cry_1 (.A(VCC_net_1), .B(
        \nbytes[1]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un18_AXI_DATA_cry_0_net_1), .S(un18_AXI_DATA_cry_1_S), .Y(), 
        .FCO(un18_AXI_DATA_cry_1_net_1));
    CFG3 #( .INIT(8'hEA) )  \SPI_current_state_ns_0[11]  (.A(N_284_1), 
        .B(AXI_IF_0_AXI_BUSY), .C(\SPI_current_state[11]_net_1 ), .Y(
        \SPI_current_state_ns[11] ));
    SLE \AXI_DATA_ret_5[7]  (.D(SPI_to_MDDR_0_AXI_DATA[7]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[7] ));
    ARI1 #( .INIT(20'h65500) )  un36_AXI_DATA_cry_0 (.A(VCC_net_1), .B(
        \nbytes[1]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        GND_net_1), .S(), .Y(un36_AXI_DATA_cry_0_Y), .FCO(
        un36_AXI_DATA_cry_0_net_1));
    SLE \DATAOUT_1[10]  (.D(N_313_i_0), .CLK(CCC_0_GL0), .EN(
        un1_M3_RESETn_0_sqmuxa_2_net_1), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(SPI_to_MDDR_0_DATAOUT_18));
    SLE \AXI_DATA_ret_0[5]  (.D(SPI_to_MDDR_0_AXI_DATA[13]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[13] ));
    ARI1 #( .INIT(20'h4AA00) )  un36_AXI_DATA_cry_4 (.A(VCC_net_1), .B(
        \nbytes[5]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un36_AXI_DATA_cry_3_net_1), .S(un36_AXI_DATA_cry_4_S), .Y(), 
        .FCO(un36_AXI_DATA_cry_4_net_1));
    CFG2 #( .INIT(4'h4) )  SPI_current_state_0_sqmuxa_0_a2_i_o2 (.A(
        AHB_IF_0_AHB_BUSY), .B(\SPI_current_state[9]_net_1 ), .Y(N_63));
    ARI1 #( .INIT(20'h65500) )  un30_AXI_DATA_cry_0 (.A(VCC_net_1), .B(
        \nbytes[0]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        GND_net_1), .S(), .Y(un30_AXI_DATA_cry_0_Y), .FCO(
        un30_AXI_DATA_cry_0_net_1));
    SLE \CMD[2]  (.D(\CMD_6[2] ), .CLK(CCC_0_GL0), .EN(VCC_net_1), 
        .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\CMD[2]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un30_AXI_DATA_cry_4 (.A(VCC_net_1), .B(
        \nbytes[4]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un30_AXI_DATA_cry_3_net_1), .S(un30_AXI_DATA_cry_4_S), .Y(), 
        .FCO(un30_AXI_DATA_cry_4_net_1));
    CFG4 #( .INIT(16'h2333) )  \reg_count_RNO[2]  (.A(N_336_0), .B(
        \reg_count_9_i_1[2]_net_1 ), .C(\reg_count[2]_net_1 ), .D(
        \reg_count[1]_net_1 ), .Y(N_324_i_0));
    ARI1 #( .INIT(20'h4AA00) )  un42_AXI_DATA_cry_8 (.A(VCC_net_1), .B(
        \nbytes[8]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un42_AXI_DATA_cry_7_net_1), .S(un42_AXI_DATA_cry_8_S), .Y(), 
        .FCO(un42_AXI_DATA_cry_8_net_1));
    SLE \nblocks[5]  (.D(\nblocks_s[5] ), .CLK(CCC_0_GL0), .EN(
        CMD_count_0_sqmuxa_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \nblocks[5]_net_1 ));
    SLE \block_address[19]  (.D(un2_block_address_1_cry_9_S), .CLK(
        CCC_0_GL0), .EN(CMD_count_0_sqmuxa_1), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\block_address[19]_net_1 ));
    CFG4 #( .INIT(16'hD800) )  \AXI_DATA_ret_5_RNIF4RH1[4]  (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[4] ), .C(
        \AXI_DATA_reto[4] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[4]));
    ARI1 #( .INIT(20'h65500) )  un18_AXI_DATA_cry_0 (.A(VCC_net_1), .B(
        \nbytes[0]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        GND_net_1), .S(), .Y(un18_AXI_DATA_cry_0_Y), .FCO(
        un18_AXI_DATA_cry_0_net_1));
    CFG2 #( .INIT(4'hB) )  \reg_count_9_i_o2[2]  (.A(N_332), .B(
        \reg_count[1]_net_1 ), .Y(N_353));
    SLE \AXI_DATA_ret[2]  (.D(SPI_to_MDDR_0_AXI_DATA[26]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[26] ));
    ARI1 #( .INIT(20'h4AA00) )  un42_AXI_DATA_cry_6 (.A(VCC_net_1), .B(
        \nbytes[6]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un42_AXI_DATA_cry_5_net_1), .S(un42_AXI_DATA_cry_6_S), .Y(), 
        .FCO(un42_AXI_DATA_cry_6_net_1));
    CFG4 #( .INIT(16'hD800) )  read_byte_1_read_byte_0_0_RNI94431 (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[45] ), .C(
        \AXI_DATA_reto[45] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[45]));
    SLE \AXI_DATA_ret_5[3]  (.D(SPI_to_MDDR_0_AXI_DATA[3]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[3] ));
    CFG3 #( .INIT(8'h23) )  READ_RNO (.A(N_385_1), .B(
        AHB_IF_0_AHB_BUSY), .C(un1_READ_0_sqmuxa_3_i_a5_1_net_1), .Y(
        N_311_i_0));
    SLE \nblocks[3]  (.D(\nblocks_s[3] ), .CLK(CCC_0_GL0), .EN(
        CMD_count_0_sqmuxa_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \nblocks[3]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un2_block_address_1_cry_10 (.A(
        VCC_net_1), .B(\block_address[20]_net_1 ), .C(GND_net_1), .D(
        GND_net_1), .FCI(un2_block_address_1_cry_9_net_1), .S(
        un2_block_address_1_cry_10_S), .Y(), .FCO(
        un2_block_address_1_cry_10_net_1));
    CFG1 #( .INIT(2'h1) )  read_byte_4_read_byte_0_0_RNO (.A(
        \nbytes[1]_net_1 ), .Y(\nbytes_i_0[1] ));
    CFG4 #( .INIT(16'h1011) )  un41_i_a2_7_1 (.A(
        \SPI_current_state[14]_net_1 ), .B(
        \SPI_current_state[13]_net_1 ), .C(
        \SPI_current_state[9]_net_1 ), .D(N_401), .Y(
        un41_i_a2_7_1_net_1));
    SLE \SPI_current_state[4]  (.D(\SPI_current_state[3]_net_1 ), .CLK(
        CCC_0_GL0), .EN(AHB_IF_0_AHB_BUSY_i_0), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\SPI_current_state[4]_net_1 ));
    SLE \SPI_current_state[13]  (.D(N_288_i_0), .CLK(CCC_0_GL0), .EN(
        VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SPI_current_state[13]_net_1 ));
    CFG3 #( .INIT(8'hCE) )  un1_SPI_current_state_7_0 (.A(
        \SPI_current_state[14]_net_1 ), .B(
        \SPI_current_state[0]_net_1 ), .C(AHB_IF_0_AHB_BUSY), .Y(
        un1_SPI_current_state_7_0_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un24_AXI_DATA_cry_6 (.A(VCC_net_1), .B(
        \nbytes[8]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un24_AXI_DATA_cry_5_net_1), .S(un24_AXI_DATA_cry_6_S), .Y(), 
        .FCO(un24_AXI_DATA_cry_6_net_1));
    CFG3 #( .INIT(8'hD0) )  \nbytes_RNO[0]  (.A(N_765), .B(
        un1_nbytes_1_sqmuxa_1_0_net_1), .C(un1_nbytes_2_cry_0_0_Y), .Y(
        \nbytes_10[0] ));
    SLE \AXI_DATA_ret_2[4]  (.D(SPI_to_MDDR_0_AXI_DATA[44]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[44] ));
    CFG4 #( .INIT(16'h070F) )  \SPI_current_state_RNO[13]  (.A(
        un1_nbyteslto11_0_a2_5_net_1), .B(\SPI_current_state[9]_net_1 )
        , .C(\SPI_current_state_ns_i_0_0[13]_net_1 ), .D(
        un1_nbyteslto11_0_a2_6_net_1), .Y(N_288_i_0));
    SLE \block_address[21]  (.D(un2_block_address_1_cry_11_S), .CLK(
        CCC_0_GL0), .EN(CMD_count_0_sqmuxa_1), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\block_address[21]_net_1 ));
    SLE \AXI_DATA_ret_4[2]  (.D(SPI_to_MDDR_0_AXI_DATA[58]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[58] ));
    ARI1 #( .INIT(20'h4AA00) )  un12_AXI_DATA_cry_5 (.A(VCC_net_1), .B(
        \nbytes[6]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un12_AXI_DATA_cry_4_net_1), .S(un12_AXI_DATA_cry_5_S), .Y(), 
        .FCO(un12_AXI_DATA_cry_5_net_1));
    CFG4 #( .INIT(16'hD800) )  \AXI_DATA_ret_5_RNII7RH1[7]  (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[7] ), .C(
        \AXI_DATA_reto[7] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[7]));
    CFG4 #( .INIT(16'hD800) )  read_byte_3_read_byte_0_0_RNIPKGV (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[28] ), .C(
        \AXI_DATA_reto[28] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[28]));
    SLE \nblocks[1]  (.D(\nblocks_s[1] ), .CLK(CCC_0_GL0), .EN(
        CMD_count_0_sqmuxa_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \nblocks[1]_net_1 ));
    SLE \nbytes[7]  (.D(\nbytes_10[7] ), .CLK(CCC_0_GL0), .EN(
        VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \nbytes[7]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un36_AXI_DATA_cry_2 (.A(VCC_net_1), .B(
        \nbytes[3]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un36_AXI_DATA_cry_1_net_1), .S(un36_AXI_DATA_cry_2_S), .Y(), 
        .FCO(un36_AXI_DATA_cry_2_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un2_block_address_1_cry_11 (.A(
        VCC_net_1), .B(\block_address[21]_net_1 ), .C(GND_net_1), .D(
        GND_net_1), .FCI(un2_block_address_1_cry_10_net_1), .S(
        un2_block_address_1_cry_11_S), .Y(), .FCO(
        un2_block_address_1_cry_11_net_1));
    CFG4 #( .INIT(16'hD800) )  \AXI_DATA_ret_5_RNIG5RH1[5]  (.A(
        AXI_DATA_0_sqmuxa_reto), .B(\read_byte_reto[5] ), .C(
        \AXI_DATA_reto[5] ), .D(AXI_DATA_rst_net_1), .Y(
        SPI_to_MDDR_0_AXI_DATA[5]));
    ARI1 #( .INIT(20'h65500) )  un30_AXI_DATA_cry_2 (.A(VCC_net_1), .B(
        \nbytes[2]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un30_AXI_DATA_cry_1_net_1), .S(un30_AXI_DATA_cry_2_S), .Y(), 
        .FCO(un30_AXI_DATA_cry_2_net_1));
    SLE \AXI_DATA_ret_3[7]  (.D(SPI_to_MDDR_0_AXI_DATA[55]), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AXI_DATA_reto[55] ));
    
endmodule


module AXI_IF_0s_1s_2s_3s_4294967292s(
       HW_Boot_Engine_0_AXI_IF_WDATA,
       SPI_to_MDDR_0_AXI_DATA,
       HW_Boot_Engine_0_AXI_IF_AWADDR,
       HW_Boot_Engine_0_AXI_IF_AWSIZE,
       MDDR_Config_0_DRAM_Ready,
       CCC_0_GL0,
       AXI_IF_0_AXI_BUSY,
       HW_Boot_Engine_0_AXI_IF_WLAST,
       HW_Boot_Engine_0_AXI_IF_BREADY,
       HW_Boot_Engine_0_AXI_IF_AWVALID,
       SPI_to_MDDR_0_AXI_WRITE,
       HW_Boot_Engine_0_AXI_IF_AWREADY,
       HW_Boot_Engine_0_AXI_IF_WREADY,
       HW_Boot_Engine_0_AXI_IF_BVALID
    );
output [63:0] HW_Boot_Engine_0_AXI_IF_WDATA;
input  [63:0] SPI_to_MDDR_0_AXI_DATA;
output [31:0] HW_Boot_Engine_0_AXI_IF_AWADDR;
output [0:0] HW_Boot_Engine_0_AXI_IF_AWSIZE;
input  MDDR_Config_0_DRAM_Ready;
input  CCC_0_GL0;
output AXI_IF_0_AXI_BUSY;
output HW_Boot_Engine_0_AXI_IF_WLAST;
output HW_Boot_Engine_0_AXI_IF_BREADY;
output HW_Boot_Engine_0_AXI_IF_AWVALID;
input  SPI_to_MDDR_0_AXI_WRITE;
input  HW_Boot_Engine_0_AXI_IF_AWREADY;
input  HW_Boot_Engine_0_AXI_IF_WREADY;
input  HW_Boot_Engine_0_AXI_IF_BVALID;

    wire VCC_net_1, \WDATA_int[61]_net_1 , WDATA_0_sqmuxa, GND_net_1, 
        \WDATA_int[62]_net_1 , \WDATA_int[63]_net_1 , 
        \WDATA_int[46]_net_1 , \WDATA_int[47]_net_1 , 
        \WDATA_int[48]_net_1 , \WDATA_int[49]_net_1 , 
        \WDATA_int[50]_net_1 , \WDATA_int[51]_net_1 , 
        \WDATA_int[52]_net_1 , \WDATA_int[53]_net_1 , 
        \WDATA_int[54]_net_1 , \WDATA_int[55]_net_1 , 
        \WDATA_int[56]_net_1 , \WDATA_int[57]_net_1 , 
        \WDATA_int[58]_net_1 , \WDATA_int[59]_net_1 , 
        \WDATA_int[60]_net_1 , \WDATA_int[31]_net_1 , 
        \WDATA_int[32]_net_1 , \WDATA_int[33]_net_1 , 
        \WDATA_int[34]_net_1 , \WDATA_int[35]_net_1 , 
        \WDATA_int[36]_net_1 , \WDATA_int[37]_net_1 , 
        \WDATA_int[38]_net_1 , \WDATA_int[39]_net_1 , 
        \WDATA_int[40]_net_1 , \WDATA_int[41]_net_1 , 
        \WDATA_int[42]_net_1 , \WDATA_int[43]_net_1 , 
        \WDATA_int[44]_net_1 , \WDATA_int[45]_net_1 , 
        \WDATA_int[16]_net_1 , \WDATA_int[17]_net_1 , 
        \WDATA_int[18]_net_1 , \WDATA_int[19]_net_1 , 
        \WDATA_int[20]_net_1 , \WDATA_int[21]_net_1 , 
        \WDATA_int[22]_net_1 , \WDATA_int[23]_net_1 , 
        \WDATA_int[24]_net_1 , \WDATA_int[25]_net_1 , 
        \WDATA_int[26]_net_1 , \WDATA_int[27]_net_1 , 
        \WDATA_int[28]_net_1 , \WDATA_int[29]_net_1 , 
        \WDATA_int[30]_net_1 , \WDATA_int[1]_net_1 , 
        \WDATA_int[2]_net_1 , \WDATA_int[3]_net_1 , 
        \WDATA_int[4]_net_1 , \WDATA_int[5]_net_1 , 
        \WDATA_int[6]_net_1 , \WDATA_int[7]_net_1 , 
        \WDATA_int[8]_net_1 , \WDATA_int[9]_net_1 , 
        \WDATA_int[10]_net_1 , \WDATA_int[11]_net_1 , 
        \WDATA_int[12]_net_1 , \WDATA_int[13]_net_1 , 
        \WDATA_int[14]_net_1 , \WDATA_int[15]_net_1 , AWADDR_0_sqmuxa, 
        \WDATA_int[0]_net_1 , \AWADDR_int[22]_net_1 , 
        \AWADDR_int[23]_net_1 , \AWADDR_int[24]_net_1 , 
        \AWADDR_int[25]_net_1 , \AWADDR_int[26]_net_1 , 
        \AWADDR_int[27]_net_1 , \AWADDR_int[28]_net_1 , 
        \AWADDR_int[29]_net_1 , \AWADDR_int[30]_net_1 , 
        \AWADDR_int[31]_net_1 , \AWADDR_int[7]_net_1 , 
        \AWADDR_int[8]_net_1 , \AWADDR_int[9]_net_1 , 
        \AWADDR_int[10]_net_1 , \AWADDR_int[11]_net_1 , 
        \AWADDR_int[12]_net_1 , \AWADDR_int[13]_net_1 , 
        \AWADDR_int[14]_net_1 , \AWADDR_int[15]_net_1 , 
        \AWADDR_int[16]_net_1 , \AWADDR_int[17]_net_1 , 
        \AWADDR_int[18]_net_1 , \AWADDR_int[19]_net_1 , 
        \AWADDR_int[20]_net_1 , \AWADDR_int[21]_net_1 , 
        \AWADDR_int[0]_net_1 , \AWADDR_int[1]_net_1 , 
        \AWADDR_int[2]_net_1 , \AWADDR_int[3]_net_1 , 
        \AWADDR_int[4]_net_1 , \AWADDR_int[5]_net_1 , 
        \AWADDR_int[6]_net_1 , un2_AWADDR_int_1_cry_20_S, 
        axi_fsm_current_state_0_sqmuxa, un2_AWADDR_int_1_cry_21_S, 
        un2_AWADDR_int_1_cry_22_S, un2_AWADDR_int_1_cry_23_S, 
        un2_AWADDR_int_1_cry_24_S, un2_AWADDR_int_1_cry_25_S, 
        un2_AWADDR_int_1_cry_26_S, un2_AWADDR_int_1_cry_27_S, 
        un2_AWADDR_int_1_s_28_S, un2_AWADDR_int_1_cry_5_S, 
        un2_AWADDR_int_1_cry_6_S, un2_AWADDR_int_1_cry_7_S, 
        un2_AWADDR_int_1_cry_8_S, un2_AWADDR_int_1_cry_9_S, 
        un2_AWADDR_int_1_cry_10_S, un2_AWADDR_int_1_cry_11_S, 
        un2_AWADDR_int_1_cry_12_S, un2_AWADDR_int_1_cry_13_S, 
        un2_AWADDR_int_1_cry_14_S, un2_AWADDR_int_1_cry_15_S, 
        un2_AWADDR_int_1_cry_16_S, un2_AWADDR_int_1_cry_17_S, 
        un2_AWADDR_int_1_cry_18_S, un2_AWADDR_int_1_cry_19_S, 
        un1_AWADDR_0_sqmuxa_4_0_net_1, un1_WDATA_0_sqmuxa_0_net_1, 
        un1_AWADDR_0_sqmuxa_1_0_o3_net_1, 
        un1_AWADDR_0_sqmuxa_2_0_net_1, \AWADDR_int_4[3]_net_1 , 
        un2_AWADDR_int_1_cry_1_S, un2_AWADDR_int_1_cry_2_S, 
        un2_AWADDR_int_1_cry_3_S, un2_AWADDR_int_1_cry_4_S, 
        \axi_fsm_current_state[0]_net_1 , 
        \axi_fsm_current_state[1]_net_1 , N_123_i_0, 
        \axi_fsm_current_state[2]_net_1 , 
        \axi_fsm_current_state_ns[2]_net_1 , 
        \axi_fsm_current_state[3]_net_1 , 
        \axi_fsm_current_state_ns[3]_net_1 , 
        \axi_fsm_current_state[4]_net_1 , 
        \axi_fsm_current_state_ns[4]_net_1 , 
        un2_AWADDR_int_1_s_1_310_FCO, un2_AWADDR_int_1_cry_1_net_1, 
        un2_AWADDR_int_1_cry_2_net_1, un2_AWADDR_int_1_cry_3_net_1, 
        un2_AWADDR_int_1_cry_4_net_1, un2_AWADDR_int_1_cry_5_net_1, 
        un2_AWADDR_int_1_cry_6_net_1, un2_AWADDR_int_1_cry_7_net_1, 
        un2_AWADDR_int_1_cry_8_net_1, un2_AWADDR_int_1_cry_9_net_1, 
        un2_AWADDR_int_1_cry_10_net_1, un2_AWADDR_int_1_cry_11_net_1, 
        un2_AWADDR_int_1_cry_12_net_1, un2_AWADDR_int_1_cry_13_net_1, 
        un2_AWADDR_int_1_cry_14_net_1, un2_AWADDR_int_1_cry_15_net_1, 
        un2_AWADDR_int_1_cry_16_net_1, un2_AWADDR_int_1_cry_17_net_1, 
        un2_AWADDR_int_1_cry_18_net_1, un2_AWADDR_int_1_cry_19_net_1, 
        un2_AWADDR_int_1_cry_20_net_1, un2_AWADDR_int_1_cry_21_net_1, 
        un2_AWADDR_int_1_cry_22_net_1, un2_AWADDR_int_1_cry_23_net_1, 
        un2_AWADDR_int_1_cry_24_net_1, un2_AWADDR_int_1_cry_25_net_1, 
        un2_AWADDR_int_1_cry_26_net_1, un2_AWADDR_int_1_cry_27_net_1, 
        N_135;
    
    CFG4 #( .INIT(16'hFFEA) )  un1_AWADDR_0_sqmuxa_4_0 (.A(
        \axi_fsm_current_state[0]_net_1 ), .B(SPI_to_MDDR_0_AXI_WRITE), 
        .C(\axi_fsm_current_state[1]_net_1 ), .D(
        axi_fsm_current_state_0_sqmuxa), .Y(
        un1_AWADDR_0_sqmuxa_4_0_net_1));
    SLE \WDATA[13]  (.D(\WDATA_int[13]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[13]));
    SLE \AWADDR_int[31]  (.D(un2_AWADDR_int_1_s_28_S), .CLK(CCC_0_GL0), 
        .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(GND_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[31]_net_1 ));
    SLE \AWADDR[11]  (.D(\AWADDR_int[11]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[11]));
    SLE \WDATA[58]  (.D(\WDATA_int[58]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[58]));
    SLE \AWADDR[29]  (.D(\AWADDR_int[29]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[29]));
    SLE \WDATA_int[61]  (.D(SPI_to_MDDR_0_AXI_DATA[61]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[61]_net_1 ));
    SLE \WDATA[59]  (.D(\WDATA_int[59]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[59]));
    SLE \AWADDR_int[28]  (.D(un2_AWADDR_int_1_cry_25_S), .CLK(
        CCC_0_GL0), .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[28]_net_1 ));
    SLE \AWADDR_int[13]  (.D(un2_AWADDR_int_1_cry_10_S), .CLK(
        CCC_0_GL0), .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[13]_net_1 ));
    SLE \WDATA_int[3]  (.D(SPI_to_MDDR_0_AXI_DATA[3]), .CLK(CCC_0_GL0), 
        .EN(AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\WDATA_int[3]_net_1 ));
    SLE \WDATA[31]  (.D(\WDATA_int[31]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[31]));
    SLE \WDATA[15]  (.D(\WDATA_int[15]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[15]));
    SLE \WDATA_int[36]  (.D(SPI_to_MDDR_0_AXI_DATA[36]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[36]_net_1 ));
    CFG4 #( .INIT(16'hECA0) )  un1_WDATA_0_sqmuxa_0 (.A(
        \axi_fsm_current_state[3]_net_1 ), .B(
        \axi_fsm_current_state[2]_net_1 ), .C(
        HW_Boot_Engine_0_AXI_IF_WREADY), .D(
        HW_Boot_Engine_0_AXI_IF_AWREADY), .Y(
        un1_WDATA_0_sqmuxa_0_net_1));
    SLE AXI_BUSY (.D(AWADDR_0_sqmuxa), .CLK(CCC_0_GL0), .EN(
        un1_AWADDR_0_sqmuxa_4_0_net_1), .ALn(MDDR_Config_0_DRAM_Ready), 
        .ADn(GND_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(AXI_IF_0_AXI_BUSY));
    SLE \WDATA[46]  (.D(\WDATA_int[46]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[46]));
    CFG3 #( .INIT(8'hF8) )  un1_AWADDR_0_sqmuxa_2_0 (.A(
        HW_Boot_Engine_0_AXI_IF_AWREADY), .B(
        \axi_fsm_current_state[2]_net_1 ), .C(AWADDR_0_sqmuxa), .Y(
        un1_AWADDR_0_sqmuxa_2_0_net_1));
    CFG2 #( .INIT(4'h8) )  AWADDR_0_sqmuxa_0_a3 (.A(
        \axi_fsm_current_state[1]_net_1 ), .B(SPI_to_MDDR_0_AXI_WRITE), 
        .Y(AWADDR_0_sqmuxa));
    SLE \WDATA_int[35]  (.D(SPI_to_MDDR_0_AXI_DATA[35]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[35]_net_1 ));
    SLE \axi_fsm_current_state[3]  (.D(
        \axi_fsm_current_state_ns[3]_net_1 ), .CLK(CCC_0_GL0), .EN(
        VCC_net_1), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \axi_fsm_current_state[3]_net_1 ));
    SLE \WDATA[44]  (.D(\WDATA_int[44]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[44]));
    SLE \AWADDR[2]  (.D(\AWADDR_int[2]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[2]));
    SLE \WDATA[26]  (.D(\WDATA_int[26]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[26]));
    SLE \WDATA[47]  (.D(\WDATA_int[47]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[47]));
    SLE \WDATA[4]  (.D(\WDATA_int[4]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[4]));
    SLE \AWADDR_int[16]  (.D(un2_AWADDR_int_1_cry_13_S), .CLK(
        CCC_0_GL0), .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[16]_net_1 ));
    SLE \WDATA[24]  (.D(\WDATA_int[24]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[24]));
    SLE \WDATA_int[49]  (.D(SPI_to_MDDR_0_AXI_DATA[49]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[49]_net_1 ));
    SLE \AWADDR_int[17]  (.D(un2_AWADDR_int_1_cry_14_S), .CLK(
        CCC_0_GL0), .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[17]_net_1 ));
    SLE \AWADDR[10]  (.D(\AWADDR_int[10]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[10]));
    SLE \WDATA_int[2]  (.D(SPI_to_MDDR_0_AXI_DATA[2]), .CLK(CCC_0_GL0), 
        .EN(AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\WDATA_int[2]_net_1 ));
    SLE \WDATA[27]  (.D(\WDATA_int[27]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[27]));
    SLE \WDATA[62]  (.D(\WDATA_int[62]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[62]));
    SLE \WDATA[9]  (.D(\WDATA_int[9]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[9]));
    SLE \WDATA[38]  (.D(\WDATA_int[38]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[38]));
    SLE \WDATA_int[43]  (.D(SPI_to_MDDR_0_AXI_DATA[43]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[43]_net_1 ));
    SLE \WDATA_int[58]  (.D(SPI_to_MDDR_0_AXI_DATA[58]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[58]_net_1 ));
    SLE \WDATA[39]  (.D(\WDATA_int[39]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[39]));
    SLE \WDATA_int[26]  (.D(SPI_to_MDDR_0_AXI_DATA[26]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[26]_net_1 ));
    SLE \WDATA_int[40]  (.D(SPI_to_MDDR_0_AXI_DATA[40]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[40]_net_1 ));
    SLE \WDATA[60]  (.D(\WDATA_int[60]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[60]));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_6 (.A(VCC_net_1), 
        .B(\AWADDR_int[9]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_5_net_1), .S(un2_AWADDR_int_1_cry_6_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_6_net_1));
    SLE \AWADDR_int[21]  (.D(un2_AWADDR_int_1_cry_18_S), .CLK(
        CCC_0_GL0), .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[21]_net_1 ));
    SLE \WDATA_int[51]  (.D(SPI_to_MDDR_0_AXI_DATA[51]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[51]_net_1 ));
    SLE \WDATA_int[19]  (.D(SPI_to_MDDR_0_AXI_DATA[19]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[19]_net_1 ));
    SLE \AWADDR_int[6]  (.D(un2_AWADDR_int_1_cry_3_S), .CLK(CCC_0_GL0), 
        .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[6]_net_1 ));
    SLE \WDATA_int[25]  (.D(SPI_to_MDDR_0_AXI_DATA[25]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[25]_net_1 ));
    GND GND (.Y(GND_net_1));
    SLE \WDATA_int[44]  (.D(SPI_to_MDDR_0_AXI_DATA[44]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[44]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_8 (.A(VCC_net_1), 
        .B(\AWADDR_int[11]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_7_net_1), .S(un2_AWADDR_int_1_cry_8_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_8_net_1));
    SLE \AWADDR[18]  (.D(\AWADDR_int[18]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[18]));
    SLE \WDATA[53]  (.D(\WDATA_int[53]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[53]));
    SLE \AWADDR_int[0]  (.D(\AWADDR_int[0]_net_1 ), .CLK(CCC_0_GL0), 
        .EN(VCC_net_1), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1)
        , .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AWADDR_int[0]_net_1 ));
    SLE \WDATA_int[47]  (.D(SPI_to_MDDR_0_AXI_DATA[47]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[47]_net_1 ));
    SLE \WDATA_int[13]  (.D(SPI_to_MDDR_0_AXI_DATA[13]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[13]_net_1 ));
    SLE \AWADDR_int[22]  (.D(un2_AWADDR_int_1_cry_19_S), .CLK(
        CCC_0_GL0), .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[22]_net_1 ));
    SLE \WDATA[1]  (.D(\WDATA_int[1]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[1]));
    SLE \WDATA_int[10]  (.D(SPI_to_MDDR_0_AXI_DATA[10]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[10]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_1 (.A(VCC_net_1), 
        .B(\AWADDR_int[4]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_s_1_310_FCO), .S(un2_AWADDR_int_1_cry_1_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_1_net_1));
    SLE \WDATA_int[4]  (.D(SPI_to_MDDR_0_AXI_DATA[4]), .CLK(CCC_0_GL0), 
        .EN(AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\WDATA_int[4]_net_1 ));
    SLE \WDATA_int[42]  (.D(SPI_to_MDDR_0_AXI_DATA[42]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[42]_net_1 ));
    SLE \AWADDR_int[10]  (.D(un2_AWADDR_int_1_cry_7_S), .CLK(CCC_0_GL0)
        , .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[10]_net_1 ));
    SLE \WDATA_int[14]  (.D(SPI_to_MDDR_0_AXI_DATA[14]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[14]_net_1 ));
    SLE \AWADDR[17]  (.D(\AWADDR_int[17]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[17]));
    SLE \AWADDR[6]  (.D(\AWADDR_int[6]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[6]));
    SLE \WDATA[55]  (.D(\WDATA_int[55]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[55]));
    SLE \AWADDR_int[5]  (.D(un2_AWADDR_int_1_cry_2_S), .CLK(CCC_0_GL0), 
        .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[5]_net_1 ));
    SLE \WDATA_int[17]  (.D(SPI_to_MDDR_0_AXI_DATA[17]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[17]_net_1 ));
    SLE \WDATA[42]  (.D(\WDATA_int[42]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[42]));
    SLE \AWADDR[3]  (.D(\AWADDR_int[3]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[3]));
    SLE \AWADDR[25]  (.D(\AWADDR_int[25]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[25]));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_s_1_310 (.A(VCC_net_1)
        , .B(\AWADDR_int[3]_net_1 ), .C(GND_net_1), .D(GND_net_1), 
        .FCI(VCC_net_1), .S(), .Y(), .FCO(un2_AWADDR_int_1_s_1_310_FCO)
        );
    SLE \WDATA[22]  (.D(\WDATA_int[22]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[22]));
    SLE \WDATA_int[0]  (.D(SPI_to_MDDR_0_AXI_DATA[0]), .CLK(CCC_0_GL0), 
        .EN(AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\WDATA_int[0]_net_1 ));
    CFG2 #( .INIT(4'h8) )  WDATA_0_sqmuxa_0_a3 (.A(
        HW_Boot_Engine_0_AXI_IF_AWREADY), .B(
        \axi_fsm_current_state[2]_net_1 ), .Y(WDATA_0_sqmuxa));
    SLE \WDATA[40]  (.D(\WDATA_int[40]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[40]));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_26 (.A(VCC_net_1), 
        .B(\AWADDR_int[29]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_25_net_1), .S(un2_AWADDR_int_1_cry_26_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_26_net_1));
    SLE \WDATA_int[12]  (.D(SPI_to_MDDR_0_AXI_DATA[12]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[12]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_4 (.A(VCC_net_1), 
        .B(\AWADDR_int[7]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_3_net_1), .S(un2_AWADDR_int_1_cry_4_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_4_net_1));
    SLE \AWADDR[13]  (.D(\AWADDR_int[13]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[13]));
    SLE \WDATA[20]  (.D(\WDATA_int[20]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[20]));
    SLE \WDATA[16]  (.D(\WDATA_int[16]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[16]));
    SLE \WDATA[33]  (.D(\WDATA_int[33]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[33]));
    SLE \WDATA[14]  (.D(\WDATA_int[14]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[14]));
    SLE \axi_fsm_current_state[0]  (.D(GND_net_1), .CLK(CCC_0_GL0), 
        .EN(VCC_net_1), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(GND_net_1)
        , .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \axi_fsm_current_state[0]_net_1 ));
    SLE \AWADDR[0]  (.D(\AWADDR_int[0]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[0]));
    SLE \WDATA_int[9]  (.D(SPI_to_MDDR_0_AXI_DATA[9]), .CLK(CCC_0_GL0), 
        .EN(AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\WDATA_int[9]_net_1 ));
    SLE \WDATA_int[39]  (.D(SPI_to_MDDR_0_AXI_DATA[39]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[39]_net_1 ));
    SLE \WDATA[17]  (.D(\WDATA_int[17]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[17]));
    SLE \AWADDR[24]  (.D(\AWADDR_int[24]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[24]));
    SLE \WDATA_int[33]  (.D(SPI_to_MDDR_0_AXI_DATA[33]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[33]_net_1 ));
    VCC VCC (.Y(VCC_net_1));
    SLE \axi_fsm_current_state[4]  (.D(
        \axi_fsm_current_state_ns[4]_net_1 ), .CLK(CCC_0_GL0), .EN(
        VCC_net_1), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \axi_fsm_current_state[4]_net_1 ));
    SLE \AWADDR[26]  (.D(\AWADDR_int[26]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[26]));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_9 (.A(VCC_net_1), 
        .B(\AWADDR_int[12]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_8_net_1), .S(un2_AWADDR_int_1_cry_9_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_9_net_1));
    SLE \AWADDR[1]  (.D(\AWADDR_int[1]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[1]));
    SLE \WDATA_int[7]  (.D(SPI_to_MDDR_0_AXI_DATA[7]), .CLK(CCC_0_GL0), 
        .EN(AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\WDATA_int[7]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_23 (.A(VCC_net_1), 
        .B(\AWADDR_int[26]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_22_net_1), .S(un2_AWADDR_int_1_cry_23_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_23_net_1));
    SLE \WDATA_int[30]  (.D(SPI_to_MDDR_0_AXI_DATA[30]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[30]_net_1 ));
    SLE \WDATA[35]  (.D(\WDATA_int[35]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[35]));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_s_28 (.A(VCC_net_1), 
        .B(\AWADDR_int[31]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_27_net_1), .S(un2_AWADDR_int_1_s_28_S), 
        .Y(), .FCO());
    SLE \WDATA_int[34]  (.D(SPI_to_MDDR_0_AXI_DATA[34]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[34]_net_1 ));
    SLE \AWADDR_int[18]  (.D(un2_AWADDR_int_1_cry_15_S), .CLK(
        CCC_0_GL0), .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[18]_net_1 ));
    SLE \WDATA_int[1]  (.D(SPI_to_MDDR_0_AXI_DATA[1]), .CLK(CCC_0_GL0), 
        .EN(AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\WDATA_int[1]_net_1 ));
    SLE \WDATA_int[6]  (.D(SPI_to_MDDR_0_AXI_DATA[6]), .CLK(CCC_0_GL0), 
        .EN(AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\WDATA_int[6]_net_1 ));
    SLE \WDATA_int[37]  (.D(SPI_to_MDDR_0_AXI_DATA[37]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[37]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_7 (.A(VCC_net_1), 
        .B(\AWADDR_int[10]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_6_net_1), .S(un2_AWADDR_int_1_cry_7_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_7_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_21 (.A(VCC_net_1), 
        .B(\AWADDR_int[24]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_20_net_1), .S(un2_AWADDR_int_1_cry_21_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_21_net_1));
    SLE \WDATA_int[29]  (.D(SPI_to_MDDR_0_AXI_DATA[29]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[29]_net_1 ));
    SLE \AWADDR_int[25]  (.D(un2_AWADDR_int_1_cry_22_S), .CLK(
        CCC_0_GL0), .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[25]_net_1 ));
    SLE \AWADDR[22]  (.D(\AWADDR_int[22]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[22]));
    SLE \WDATA_int[23]  (.D(SPI_to_MDDR_0_AXI_DATA[23]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[23]_net_1 ));
    SLE \AWADDR_int[24]  (.D(un2_AWADDR_int_1_cry_21_S), .CLK(
        CCC_0_GL0), .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[24]_net_1 ));
    SLE \WDATA_int[32]  (.D(SPI_to_MDDR_0_AXI_DATA[32]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[32]_net_1 ));
    SLE \AWADDR_int[1]  (.D(\AWADDR_int[1]_net_1 ), .CLK(CCC_0_GL0), 
        .EN(VCC_net_1), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1)
        , .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AWADDR_int[1]_net_1 ));
    SLE \WDATA_int[20]  (.D(SPI_to_MDDR_0_AXI_DATA[20]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[20]_net_1 ));
    SLE \WDATA[61]  (.D(\WDATA_int[61]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[61]));
    SLE \AWADDR_int[3]  (.D(\AWADDR_int_4[3]_net_1 ), .CLK(CCC_0_GL0), 
        .EN(VCC_net_1), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1)
        , .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AWADDR_int[3]_net_1 ));
    SLE \WDATA[12]  (.D(\WDATA_int[12]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[12]));
    SLE \WDATA_int[24]  (.D(SPI_to_MDDR_0_AXI_DATA[24]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[24]_net_1 ));
    SLE \AWADDR[21]  (.D(\AWADDR_int[21]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[21]));
    SLE \AWADDR_int[4]  (.D(un2_AWADDR_int_1_cry_1_S), .CLK(CCC_0_GL0), 
        .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[4]_net_1 ));
    SLE \AWADDR_int[2]  (.D(\AWADDR_int[2]_net_1 ), .CLK(CCC_0_GL0), 
        .EN(VCC_net_1), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1)
        , .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \AWADDR_int[2]_net_1 ));
    SLE \WDATA_int[27]  (.D(SPI_to_MDDR_0_AXI_DATA[27]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[27]_net_1 ));
    SLE \AWADDR[8]  (.D(\AWADDR_int[8]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[8]));
    CFG3 #( .INIT(8'hBA) )  \axi_fsm_current_state_ns[2]  (.A(
        AWADDR_0_sqmuxa), .B(HW_Boot_Engine_0_AXI_IF_AWREADY), .C(
        \axi_fsm_current_state[2]_net_1 ), .Y(
        \axi_fsm_current_state_ns[2]_net_1 ));
    SLE \WDATA[56]  (.D(\WDATA_int[56]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[56]));
    SLE \WDATA[10]  (.D(\WDATA_int[10]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[10]));
    SLE \WDATA[54]  (.D(\WDATA_int[54]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[54]));
    SLE \WDATA_int[56]  (.D(SPI_to_MDDR_0_AXI_DATA[56]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[56]_net_1 ));
    SLE \WDATA[57]  (.D(\WDATA_int[57]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[57]));
    SLE \WDATA_int[22]  (.D(SPI_to_MDDR_0_AXI_DATA[22]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[22]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_24 (.A(VCC_net_1), 
        .B(\AWADDR_int[27]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_23_net_1), .S(un2_AWADDR_int_1_cry_24_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_24_net_1));
    SLE \AWADDR_int[11]  (.D(un2_AWADDR_int_1_cry_8_S), .CLK(CCC_0_GL0)
        , .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[11]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_25 (.A(VCC_net_1), 
        .B(\AWADDR_int[28]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_24_net_1), .S(un2_AWADDR_int_1_cry_25_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_25_net_1));
    SLE \AWADDR[5]  (.D(\AWADDR_int[5]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[5]));
    SLE \WDATA_int[55]  (.D(SPI_to_MDDR_0_AXI_DATA[55]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[55]_net_1 ));
    SLE \WDATA[2]  (.D(\WDATA_int[2]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[2]));
    CFG3 #( .INIT(8'hEC) )  \axi_fsm_current_state_ns[4]  (.A(
        HW_Boot_Engine_0_AXI_IF_WREADY), .B(N_135), .C(
        \axi_fsm_current_state[3]_net_1 ), .Y(
        \axi_fsm_current_state_ns[4]_net_1 ));
    SLE \AWADDR[9]  (.D(\AWADDR_int[9]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[9]));
    CFG2 #( .INIT(4'h4) )  \axi_fsm_current_state_ns_i_a3[1]  (.A(
        HW_Boot_Engine_0_AXI_IF_BVALID), .B(
        \axi_fsm_current_state[4]_net_1 ), .Y(N_135));
    SLE \WDATA_int[48]  (.D(SPI_to_MDDR_0_AXI_DATA[48]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[48]_net_1 ));
    SLE \WDATA[5]  (.D(\WDATA_int[5]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[5]));
    SLE \AWADDR_int[12]  (.D(un2_AWADDR_int_1_cry_9_S), .CLK(CCC_0_GL0)
        , .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[12]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_16 (.A(VCC_net_1), 
        .B(\AWADDR_int[19]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_15_net_1), .S(un2_AWADDR_int_1_cry_16_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_16_net_1));
    SLE \AWADDR_int[7]  (.D(un2_AWADDR_int_1_cry_4_S), .CLK(CCC_0_GL0), 
        .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[7]_net_1 ));
    SLE \WDATA[41]  (.D(\WDATA_int[41]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[41]));
    SLE \WDATA_int[41]  (.D(SPI_to_MDDR_0_AXI_DATA[41]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[41]_net_1 ));
    SLE \AWADDR[20]  (.D(\AWADDR_int[20]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[20]));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_19 (.A(VCC_net_1), 
        .B(\AWADDR_int[22]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_18_net_1), .S(un2_AWADDR_int_1_cry_19_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_19_net_1));
    SLE \WDATA[21]  (.D(\WDATA_int[21]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[21]));
    SLE \AWADDR[19]  (.D(\AWADDR_int[19]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[19]));
    SLE \WDATA[6]  (.D(\WDATA_int[6]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[6]));
    SLE \WDATA_int[18]  (.D(SPI_to_MDDR_0_AXI_DATA[18]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[18]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_27 (.A(VCC_net_1), 
        .B(\AWADDR_int[30]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_26_net_1), .S(un2_AWADDR_int_1_cry_27_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_27_net_1));
    SLE \WDATA[36]  (.D(\WDATA_int[36]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[36]));
    SLE \AWADDR_int[29]  (.D(un2_AWADDR_int_1_cry_26_S), .CLK(
        CCC_0_GL0), .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(GND_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[29]_net_1 ));
    SLE \WDATA_int[63]  (.D(SPI_to_MDDR_0_AXI_DATA[63]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[63]_net_1 ));
    SLE \WDATA[34]  (.D(\WDATA_int[34]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[34]));
    SLE AWVALID (.D(AWADDR_0_sqmuxa), .CLK(CCC_0_GL0), .EN(
        un1_AWADDR_0_sqmuxa_2_0_net_1), .ALn(MDDR_Config_0_DRAM_Ready), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(HW_Boot_Engine_0_AXI_IF_AWVALID));
    SLE \AWADDR[4]  (.D(\AWADDR_int[4]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[4]));
    SLE \WDATA[8]  (.D(\WDATA_int[8]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[8]));
    SLE \WDATA[37]  (.D(\WDATA_int[37]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[37]));
    SLE \WDATA_int[11]  (.D(SPI_to_MDDR_0_AXI_DATA[11]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[11]_net_1 ));
    SLE WLAST (.D(WDATA_0_sqmuxa), .CLK(CCC_0_GL0), .EN(
        un1_WDATA_0_sqmuxa_0_net_1), .ALn(MDDR_Config_0_DRAM_Ready), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(HW_Boot_Engine_0_AXI_IF_WLAST));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_13 (.A(VCC_net_1), 
        .B(\AWADDR_int[16]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_12_net_1), .S(un2_AWADDR_int_1_cry_13_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_13_net_1));
    SLE \WDATA_int[60]  (.D(SPI_to_MDDR_0_AXI_DATA[60]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[60]_net_1 ));
    SLE \AWADDR[28]  (.D(\AWADDR_int[28]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[28]));
    CFG4 #( .INIT(16'h0001) )  \axi_fsm_current_state_RNO[1]  (.A(
        \axi_fsm_current_state[2]_net_1 ), .B(
        \axi_fsm_current_state[3]_net_1 ), .C(N_135), .D(
        AWADDR_0_sqmuxa), .Y(N_123_i_0));
    SLE \WDATA[52]  (.D(\WDATA_int[52]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[52]));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_18 (.A(VCC_net_1), 
        .B(\AWADDR_int[21]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_17_net_1), .S(un2_AWADDR_int_1_cry_18_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_18_net_1));
    SLE \WDATA[48]  (.D(\WDATA_int[48]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[48]));
    CFG3 #( .INIT(8'hF8) )  un1_AWADDR_0_sqmuxa_1_0_o3 (.A(
        \axi_fsm_current_state[1]_net_1 ), .B(SPI_to_MDDR_0_AXI_WRITE), 
        .C(axi_fsm_current_state_0_sqmuxa), .Y(
        un1_AWADDR_0_sqmuxa_1_0_o3_net_1));
    SLE \WDATA_int[8]  (.D(SPI_to_MDDR_0_AXI_DATA[8]), .CLK(CCC_0_GL0), 
        .EN(AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\WDATA_int[8]_net_1 ));
    SLE \WDATA[49]  (.D(\WDATA_int[49]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[49]));
    SLE \WDATA[28]  (.D(\WDATA_int[28]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[28]));
    SLE \WDATA_int[5]  (.D(SPI_to_MDDR_0_AXI_DATA[5]), .CLK(CCC_0_GL0), 
        .EN(AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\WDATA_int[5]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_11 (.A(VCC_net_1), 
        .B(\AWADDR_int[14]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_10_net_1), .S(un2_AWADDR_int_1_cry_11_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_11_net_1));
    SLE \WDATA[50]  (.D(\WDATA_int[50]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[50]));
    SLE \WDATA[29]  (.D(\WDATA_int[29]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[29]));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_20 (.A(VCC_net_1), 
        .B(\AWADDR_int[23]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_19_net_1), .S(un2_AWADDR_int_1_cry_20_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_20_net_1));
    SLE \AWADDR[27]  (.D(\AWADDR_int[27]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[27]));
    CFG3 #( .INIT(8'hDC) )  \axi_fsm_current_state_ns[3]  (.A(
        HW_Boot_Engine_0_AXI_IF_WREADY), .B(WDATA_0_sqmuxa), .C(
        \axi_fsm_current_state[3]_net_1 ), .Y(
        \axi_fsm_current_state_ns[3]_net_1 ));
    SLE \WDATA_int[62]  (.D(SPI_to_MDDR_0_AXI_DATA[62]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[62]_net_1 ));
    SLE \WDATA[63]  (.D(\WDATA_int[63]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[63]));
    CFG2 #( .INIT(4'h6) )  \AWADDR_int_4[3]  (.A(
        axi_fsm_current_state_0_sqmuxa), .B(\AWADDR_int[3]_net_1 ), .Y(
        \AWADDR_int_4[3]_net_1 ));
    SLE \AWADDR_int[23]  (.D(un2_AWADDR_int_1_cry_20_S), .CLK(
        CCC_0_GL0), .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[23]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_22 (.A(VCC_net_1), 
        .B(\AWADDR_int[25]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_21_net_1), .S(un2_AWADDR_int_1_cry_22_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_22_net_1));
    SLE \AWADDR[23]  (.D(\AWADDR_int[23]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[23]));
    SLE \WDATA_int[59]  (.D(SPI_to_MDDR_0_AXI_DATA[59]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[59]_net_1 ));
    SLE \WDATA_int[38]  (.D(SPI_to_MDDR_0_AXI_DATA[38]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[38]_net_1 ));
    SLE \AWADDR_int[15]  (.D(un2_AWADDR_int_1_cry_12_S), .CLK(
        CCC_0_GL0), .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[15]_net_1 ));
    SLE \AWADDR_int[30]  (.D(un2_AWADDR_int_1_cry_27_S), .CLK(
        CCC_0_GL0), .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[30]_net_1 ));
    SLE \WDATA[32]  (.D(\WDATA_int[32]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[32]));
    SLE \WDATA_int[53]  (.D(SPI_to_MDDR_0_AXI_DATA[53]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[53]_net_1 ));
    SLE \WDATA_int[31]  (.D(SPI_to_MDDR_0_AXI_DATA[31]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[31]_net_1 ));
    SLE \AWADDR_int[14]  (.D(un2_AWADDR_int_1_cry_11_S), .CLK(
        CCC_0_GL0), .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[14]_net_1 ));
    SLE \WDATA[11]  (.D(\WDATA_int[11]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[11]));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_14 (.A(VCC_net_1), 
        .B(\AWADDR_int[17]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_13_net_1), .S(un2_AWADDR_int_1_cry_14_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_14_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_3 (.A(VCC_net_1), 
        .B(\AWADDR_int[6]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_2_net_1), .S(un2_AWADDR_int_1_cry_3_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_3_net_1));
    SLE \WDATA_int[50]  (.D(SPI_to_MDDR_0_AXI_DATA[50]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[50]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_15 (.A(VCC_net_1), 
        .B(\AWADDR_int[18]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_14_net_1), .S(un2_AWADDR_int_1_cry_15_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_15_net_1));
    SLE \AWADDR_int[9]  (.D(un2_AWADDR_int_1_cry_6_S), .CLK(CCC_0_GL0), 
        .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[9]_net_1 ));
    SLE \AWADDR_int[26]  (.D(un2_AWADDR_int_1_cry_23_S), .CLK(
        CCC_0_GL0), .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[26]_net_1 ));
    SLE \WDATA[30]  (.D(\WDATA_int[30]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[30]));
    SLE \AWADDR_int[27]  (.D(un2_AWADDR_int_1_cry_24_S), .CLK(
        CCC_0_GL0), .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[27]_net_1 ));
    SLE \WDATA_int[54]  (.D(SPI_to_MDDR_0_AXI_DATA[54]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[54]_net_1 ));
    SLE \WDATA_int[57]  (.D(SPI_to_MDDR_0_AXI_DATA[57]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[57]_net_1 ));
    SLE \WDATA[43]  (.D(\WDATA_int[43]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[43]));
    SLE \AWADDR[15]  (.D(\AWADDR_int[15]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[15]));
    SLE \WDATA_int[28]  (.D(SPI_to_MDDR_0_AXI_DATA[28]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[28]_net_1 ));
    SLE \WDATA[23]  (.D(\WDATA_int[23]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[23]));
    SLE \WDATA_int[21]  (.D(SPI_to_MDDR_0_AXI_DATA[21]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[21]_net_1 ));
    SLE \WDATA[18]  (.D(\WDATA_int[18]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[18]));
    SLE \AWADDR[7]  (.D(\AWADDR_int[7]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[7]));
    SLE \WDATA_int[52]  (.D(SPI_to_MDDR_0_AXI_DATA[52]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[52]_net_1 ));
    SLE \WDATA[0]  (.D(\WDATA_int[0]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[0]));
    SLE \WDATA[19]  (.D(\WDATA_int[19]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[19]));
    SLE \axi_fsm_current_state[2]  (.D(
        \axi_fsm_current_state_ns[2]_net_1 ), .CLK(CCC_0_GL0), .EN(
        VCC_net_1), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \axi_fsm_current_state[2]_net_1 ));
    SLE \AWADDR[31]  (.D(\AWADDR_int[31]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[31]));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_17 (.A(VCC_net_1), 
        .B(\AWADDR_int[20]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_16_net_1), .S(un2_AWADDR_int_1_cry_17_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_17_net_1));
    SLE \WDATA[45]  (.D(\WDATA_int[45]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[45]));
    SLE \WDATA[25]  (.D(\WDATA_int[25]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[25]));
    SLE BREADY (.D(axi_fsm_current_state_0_sqmuxa), .CLK(CCC_0_GL0), 
        .EN(un1_AWADDR_0_sqmuxa_1_0_o3_net_1), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        HW_Boot_Engine_0_AXI_IF_BREADY));
    SLE \WDATA_int[46]  (.D(SPI_to_MDDR_0_AXI_DATA[46]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[46]_net_1 ));
    SLE \AWADDR[14]  (.D(\AWADDR_int[14]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[14]));
    SLE \AWADDR_int[20]  (.D(un2_AWADDR_int_1_cry_17_S), .CLK(
        CCC_0_GL0), .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[20]_net_1 ));
    SLE \AWADDR[16]  (.D(\AWADDR_int[16]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[16]));
    SLE \WDATA_int[45]  (.D(SPI_to_MDDR_0_AXI_DATA[45]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[45]_net_1 ));
    SLE \WDATA_int[16]  (.D(SPI_to_MDDR_0_AXI_DATA[16]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[16]_net_1 ));
    SLE \AWADDR_int[19]  (.D(un2_AWADDR_int_1_cry_16_S), .CLK(
        CCC_0_GL0), .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[19]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_10 (.A(VCC_net_1), 
        .B(\AWADDR_int[13]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_9_net_1), .S(un2_AWADDR_int_1_cry_10_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_10_net_1));
    SLE \WDATA[51]  (.D(\WDATA_int[51]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[51]));
    SLE \axi_fsm_current_state[1]  (.D(N_123_i_0), .CLK(CCC_0_GL0), 
        .EN(VCC_net_1), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1)
        , .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \axi_fsm_current_state[1]_net_1 ));
    SLE \WDATA[7]  (.D(\WDATA_int[7]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[7]));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_2 (.A(VCC_net_1), 
        .B(\AWADDR_int[5]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_1_net_1), .S(un2_AWADDR_int_1_cry_2_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_2_net_1));
    CFG2 #( .INIT(4'h8) )  axi_fsm_current_state_0_sqmuxa_0_a3 (.A(
        HW_Boot_Engine_0_AXI_IF_BVALID), .B(
        \axi_fsm_current_state[4]_net_1 ), .Y(
        axi_fsm_current_state_0_sqmuxa));
    SLE \WDATA_int[15]  (.D(SPI_to_MDDR_0_AXI_DATA[15]), .CLK(
        CCC_0_GL0), .EN(AWADDR_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[15]_net_1 ));
    SLE \AWADDR[12]  (.D(\AWADDR_int[12]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[12]));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_5 (.A(VCC_net_1), 
        .B(\AWADDR_int[8]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_4_net_1), .S(un2_AWADDR_int_1_cry_5_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_5_net_1));
    SLE \AWADDR_int[8]  (.D(un2_AWADDR_int_1_cry_5_S), .CLK(CCC_0_GL0), 
        .EN(axi_fsm_current_state_0_sqmuxa), .ALn(
        MDDR_Config_0_DRAM_Ready), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\AWADDR_int[8]_net_1 ));
    SLE \AWADDR[30]  (.D(\AWADDR_int[30]_net_1 ), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWADDR[30]));
    ARI1 #( .INIT(20'h4AA00) )  un2_AWADDR_int_1_cry_12 (.A(VCC_net_1), 
        .B(\AWADDR_int[15]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un2_AWADDR_int_1_cry_11_net_1), .S(un2_AWADDR_int_1_cry_12_S), 
        .Y(), .FCO(un2_AWADDR_int_1_cry_12_net_1));
    SLE \WDATA[3]  (.D(\WDATA_int[3]_net_1 ), .CLK(CCC_0_GL0), .EN(
        WDATA_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_WDATA[3]));
    SLE \AWSIZE_1[0]  (.D(VCC_net_1), .CLK(CCC_0_GL0), .EN(
        AWADDR_0_sqmuxa), .ALn(MDDR_Config_0_DRAM_Ready), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HW_Boot_Engine_0_AXI_IF_AWSIZE[0]));
    
endmodule


module HW_Boot_Engine(
       HW_Boot_Engine_0_AHB_IF_HTRANS,
       ahb_fsm_current_state,
       CoreAHBLite_0_AHBmslave4_HRDATA,
       HW_Boot_Engine_0_AXI_IF_WDATA,
       HW_Boot_Engine_0_AXI_IF_AWADDR,
       HW_Boot_Engine_0_AXI_IF_AWSIZE,
       HW_Boot_Engine_0_APB_IF_PWDATA,
       HW_Boot_Engine_0_AHB_IF_HWDATA_2,
       HW_Boot_Engine_0_AHB_IF_HWDATA_3,
       HW_Boot_Engine_0_AHB_IF_HWDATA_4,
       HW_Boot_Engine_0_AHB_IF_HWDATA_5,
       HW_Boot_Engine_0_AHB_IF_HWDATA_6,
       HW_Boot_Engine_0_AHB_IF_HWDATA_7,
       HW_Boot_Engine_0_AHB_IF_HWDATA_18,
       HW_Boot_Engine_0_AHB_IF_HWDATA_0,
       HW_Boot_Engine_0_AHB_IF_HWDATA_1,
       HW_Boot_Engine_0_AHB_IF_HADDR_1,
       HW_Boot_Engine_0_AHB_IF_HADDR_2,
       HW_Boot_Engine_0_AHB_IF_HADDR_10,
       HW_Boot_Engine_0_AHB_IF_HADDR_14,
       HW_Boot_Engine_0_AHB_IF_HADDR_28,
       HW_Boot_Engine_0_AHB_IF_HADDR_0,
       HW_Boot_Engine_0_APB_IF_PADDR_0,
       HW_Boot_Engine_0_APB_IF_PADDR_1,
       HW_Boot_Engine_0_APB_IF_PADDR_2,
       HW_Boot_Engine_0_APB_IF_PADDR_3,
       HW_Boot_Engine_0_APB_IF_PADDR_4,
       HW_Boot_Engine_0_APB_IF_PADDR_5,
       HW_Boot_Engine_0_APB_IF_PADDR_6,
       HW_Boot_Engine_0_APB_IF_PADDR_7,
       HW_Boot_Engine_0_APB_IF_PADDR_8,
       HW_Boot_Engine_0_APB_IF_PADDR_10,
       HW_Boot_Engine_0_APB_IF_PADDR_11,
       HW_Boot_Engine_0_APB_IF_PADDR_13,
       MSS_HPMS_READY,
       CCC_0_GL0,
       HREADY_M_iv_i_0,
       HW_Boot_Engine_0_AHB_IF_HWRITE,
       N_95,
       HREADY_M_iv_i_0_d,
       HREADY_M_iv_i_0_1_0,
       HW_Boot_Engine_0_AXI_IF_WLAST,
       HW_Boot_Engine_0_AXI_IF_BREADY,
       HW_Boot_Engine_0_AXI_IF_AWVALID,
       HW_Boot_Engine_0_AXI_IF_AWREADY,
       HW_Boot_Engine_0_AXI_IF_WREADY,
       HW_Boot_Engine_0_AXI_IF_BVALID,
       CORECONFIGP_0_APB_S_PCLK,
       HW_Boot_Engine_0_APB_IF_PWRITE,
       HW_Boot_Engine_0_APB_IF_PENABLE,
       HW_Boot_Engine_0_APB_IF_PSELx,
       HW_Boot_Engine_0_APB_IF_PREADY,
       GPIO_0_M2F_0,
       DP_SW1_c
    );
output [1:1] HW_Boot_Engine_0_AHB_IF_HTRANS;
output [5:5] ahb_fsm_current_state;
input  [8:0] CoreAHBLite_0_AHBmslave4_HRDATA;
output [63:0] HW_Boot_Engine_0_AXI_IF_WDATA;
output [31:0] HW_Boot_Engine_0_AXI_IF_AWADDR;
output [0:0] HW_Boot_Engine_0_AXI_IF_AWSIZE;
output [15:0] HW_Boot_Engine_0_APB_IF_PWDATA;
output HW_Boot_Engine_0_AHB_IF_HWDATA_2;
output HW_Boot_Engine_0_AHB_IF_HWDATA_3;
output HW_Boot_Engine_0_AHB_IF_HWDATA_4;
output HW_Boot_Engine_0_AHB_IF_HWDATA_5;
output HW_Boot_Engine_0_AHB_IF_HWDATA_6;
output HW_Boot_Engine_0_AHB_IF_HWDATA_7;
output HW_Boot_Engine_0_AHB_IF_HWDATA_18;
output HW_Boot_Engine_0_AHB_IF_HWDATA_0;
output HW_Boot_Engine_0_AHB_IF_HWDATA_1;
output HW_Boot_Engine_0_AHB_IF_HADDR_1;
output HW_Boot_Engine_0_AHB_IF_HADDR_2;
output HW_Boot_Engine_0_AHB_IF_HADDR_10;
output HW_Boot_Engine_0_AHB_IF_HADDR_14;
output HW_Boot_Engine_0_AHB_IF_HADDR_28;
output HW_Boot_Engine_0_AHB_IF_HADDR_0;
output HW_Boot_Engine_0_APB_IF_PADDR_0;
output HW_Boot_Engine_0_APB_IF_PADDR_1;
output HW_Boot_Engine_0_APB_IF_PADDR_2;
output HW_Boot_Engine_0_APB_IF_PADDR_3;
output HW_Boot_Engine_0_APB_IF_PADDR_4;
output HW_Boot_Engine_0_APB_IF_PADDR_5;
output HW_Boot_Engine_0_APB_IF_PADDR_6;
output HW_Boot_Engine_0_APB_IF_PADDR_7;
output HW_Boot_Engine_0_APB_IF_PADDR_8;
output HW_Boot_Engine_0_APB_IF_PADDR_10;
output HW_Boot_Engine_0_APB_IF_PADDR_11;
output HW_Boot_Engine_0_APB_IF_PADDR_13;
input  MSS_HPMS_READY;
input  CCC_0_GL0;
input  HREADY_M_iv_i_0;
output HW_Boot_Engine_0_AHB_IF_HWRITE;
input  N_95;
input  HREADY_M_iv_i_0_d;
input  HREADY_M_iv_i_0_1_0;
output HW_Boot_Engine_0_AXI_IF_WLAST;
output HW_Boot_Engine_0_AXI_IF_BREADY;
output HW_Boot_Engine_0_AXI_IF_AWVALID;
input  HW_Boot_Engine_0_AXI_IF_AWREADY;
input  HW_Boot_Engine_0_AXI_IF_WREADY;
input  HW_Boot_Engine_0_AXI_IF_BVALID;
input  CORECONFIGP_0_APB_S_PCLK;
output HW_Boot_Engine_0_APB_IF_PWRITE;
output HW_Boot_Engine_0_APB_IF_PENABLE;
output HW_Boot_Engine_0_APB_IF_PSELx;
input  HW_Boot_Engine_0_APB_IF_PREADY;
output GPIO_0_M2F_0;
input  DP_SW1_c;

    wire \AHB_IF_0_DATAOUT[0] , \AHB_IF_0_DATAOUT[1] , 
        \AHB_IF_0_DATAOUT[2] , \AHB_IF_0_DATAOUT[3] , 
        \AHB_IF_0_DATAOUT[4] , \AHB_IF_0_DATAOUT[5] , 
        \AHB_IF_0_DATAOUT[6] , \AHB_IF_0_DATAOUT[7] , 
        \AHB_IF_0_DATAOUT[8] , \SPI_to_MDDR_0_DATAOUT[0] , 
        \SPI_to_MDDR_0_DATAOUT[1] , \SPI_to_MDDR_0_DATAOUT[2] , 
        \SPI_to_MDDR_0_DATAOUT[3] , \SPI_to_MDDR_0_DATAOUT[4] , 
        \SPI_to_MDDR_0_DATAOUT[5] , \SPI_to_MDDR_0_DATAOUT[6] , 
        \SPI_to_MDDR_0_DATAOUT[7] , \SPI_to_MDDR_0_DATAOUT[18] , 
        \SPI_to_MDDR_0_ADDR[2] , \SPI_to_MDDR_0_ADDR[3] , 
        \SPI_to_MDDR_0_ADDR[4] , \SPI_to_MDDR_0_ADDR[12] , 
        \SPI_to_MDDR_0_ADDR[16] , \SPI_to_MDDR_0_ADDR[30] , 
        AHB_IF_0_AHB_BUSY, AHB_IF_0_AHB_BUSY_i_0, SPI_to_MDDR_0_READ, 
        SPI_to_MDDR_0_WRITE, \SPI_to_MDDR_0_AXI_DATA[0] , 
        \SPI_to_MDDR_0_AXI_DATA[1] , \SPI_to_MDDR_0_AXI_DATA[2] , 
        \SPI_to_MDDR_0_AXI_DATA[3] , \SPI_to_MDDR_0_AXI_DATA[4] , 
        \SPI_to_MDDR_0_AXI_DATA[5] , \SPI_to_MDDR_0_AXI_DATA[6] , 
        \SPI_to_MDDR_0_AXI_DATA[7] , \SPI_to_MDDR_0_AXI_DATA[8] , 
        \SPI_to_MDDR_0_AXI_DATA[9] , \SPI_to_MDDR_0_AXI_DATA[10] , 
        \SPI_to_MDDR_0_AXI_DATA[11] , \SPI_to_MDDR_0_AXI_DATA[12] , 
        \SPI_to_MDDR_0_AXI_DATA[13] , \SPI_to_MDDR_0_AXI_DATA[14] , 
        \SPI_to_MDDR_0_AXI_DATA[15] , \SPI_to_MDDR_0_AXI_DATA[16] , 
        \SPI_to_MDDR_0_AXI_DATA[17] , \SPI_to_MDDR_0_AXI_DATA[18] , 
        \SPI_to_MDDR_0_AXI_DATA[19] , \SPI_to_MDDR_0_AXI_DATA[20] , 
        \SPI_to_MDDR_0_AXI_DATA[21] , \SPI_to_MDDR_0_AXI_DATA[22] , 
        \SPI_to_MDDR_0_AXI_DATA[23] , \SPI_to_MDDR_0_AXI_DATA[24] , 
        \SPI_to_MDDR_0_AXI_DATA[25] , \SPI_to_MDDR_0_AXI_DATA[26] , 
        \SPI_to_MDDR_0_AXI_DATA[27] , \SPI_to_MDDR_0_AXI_DATA[28] , 
        \SPI_to_MDDR_0_AXI_DATA[29] , \SPI_to_MDDR_0_AXI_DATA[30] , 
        \SPI_to_MDDR_0_AXI_DATA[31] , \SPI_to_MDDR_0_AXI_DATA[32] , 
        \SPI_to_MDDR_0_AXI_DATA[33] , \SPI_to_MDDR_0_AXI_DATA[34] , 
        \SPI_to_MDDR_0_AXI_DATA[35] , \SPI_to_MDDR_0_AXI_DATA[36] , 
        \SPI_to_MDDR_0_AXI_DATA[37] , \SPI_to_MDDR_0_AXI_DATA[38] , 
        \SPI_to_MDDR_0_AXI_DATA[39] , \SPI_to_MDDR_0_AXI_DATA[40] , 
        \SPI_to_MDDR_0_AXI_DATA[41] , \SPI_to_MDDR_0_AXI_DATA[42] , 
        \SPI_to_MDDR_0_AXI_DATA[43] , \SPI_to_MDDR_0_AXI_DATA[44] , 
        \SPI_to_MDDR_0_AXI_DATA[45] , \SPI_to_MDDR_0_AXI_DATA[46] , 
        \SPI_to_MDDR_0_AXI_DATA[47] , \SPI_to_MDDR_0_AXI_DATA[48] , 
        \SPI_to_MDDR_0_AXI_DATA[49] , \SPI_to_MDDR_0_AXI_DATA[50] , 
        \SPI_to_MDDR_0_AXI_DATA[51] , \SPI_to_MDDR_0_AXI_DATA[52] , 
        \SPI_to_MDDR_0_AXI_DATA[53] , \SPI_to_MDDR_0_AXI_DATA[54] , 
        \SPI_to_MDDR_0_AXI_DATA[55] , \SPI_to_MDDR_0_AXI_DATA[56] , 
        \SPI_to_MDDR_0_AXI_DATA[57] , \SPI_to_MDDR_0_AXI_DATA[58] , 
        \SPI_to_MDDR_0_AXI_DATA[59] , \SPI_to_MDDR_0_AXI_DATA[60] , 
        \SPI_to_MDDR_0_AXI_DATA[61] , \SPI_to_MDDR_0_AXI_DATA[62] , 
        \SPI_to_MDDR_0_AXI_DATA[63] , MDDR_Config_0_DRAM_Ready, 
        AXI_IF_0_AXI_BUSY, SPI_to_MDDR_0_AXI_WRITE, GND_net_1, 
        VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    MDDR_Config_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_Z8 
        MDDR_Config_0 (.HW_Boot_Engine_0_APB_IF_PWDATA({
        HW_Boot_Engine_0_APB_IF_PWDATA[15], 
        HW_Boot_Engine_0_APB_IF_PWDATA[14], 
        HW_Boot_Engine_0_APB_IF_PWDATA[13], 
        HW_Boot_Engine_0_APB_IF_PWDATA[12], 
        HW_Boot_Engine_0_APB_IF_PWDATA[11], 
        HW_Boot_Engine_0_APB_IF_PWDATA[10], 
        HW_Boot_Engine_0_APB_IF_PWDATA[9], 
        HW_Boot_Engine_0_APB_IF_PWDATA[8], 
        HW_Boot_Engine_0_APB_IF_PWDATA[7], 
        HW_Boot_Engine_0_APB_IF_PWDATA[6], 
        HW_Boot_Engine_0_APB_IF_PWDATA[5], 
        HW_Boot_Engine_0_APB_IF_PWDATA[4], 
        HW_Boot_Engine_0_APB_IF_PWDATA[3], 
        HW_Boot_Engine_0_APB_IF_PWDATA[2], 
        HW_Boot_Engine_0_APB_IF_PWDATA[1], 
        HW_Boot_Engine_0_APB_IF_PWDATA[0]}), 
        .HW_Boot_Engine_0_APB_IF_PADDR_0(
        HW_Boot_Engine_0_APB_IF_PADDR_0), 
        .HW_Boot_Engine_0_APB_IF_PADDR_1(
        HW_Boot_Engine_0_APB_IF_PADDR_1), 
        .HW_Boot_Engine_0_APB_IF_PADDR_2(
        HW_Boot_Engine_0_APB_IF_PADDR_2), 
        .HW_Boot_Engine_0_APB_IF_PADDR_3(
        HW_Boot_Engine_0_APB_IF_PADDR_3), 
        .HW_Boot_Engine_0_APB_IF_PADDR_4(
        HW_Boot_Engine_0_APB_IF_PADDR_4), 
        .HW_Boot_Engine_0_APB_IF_PADDR_5(
        HW_Boot_Engine_0_APB_IF_PADDR_5), 
        .HW_Boot_Engine_0_APB_IF_PADDR_6(
        HW_Boot_Engine_0_APB_IF_PADDR_6), 
        .HW_Boot_Engine_0_APB_IF_PADDR_7(
        HW_Boot_Engine_0_APB_IF_PADDR_7), 
        .HW_Boot_Engine_0_APB_IF_PADDR_8(
        HW_Boot_Engine_0_APB_IF_PADDR_8), 
        .HW_Boot_Engine_0_APB_IF_PADDR_10(
        HW_Boot_Engine_0_APB_IF_PADDR_10), 
        .HW_Boot_Engine_0_APB_IF_PADDR_11(
        HW_Boot_Engine_0_APB_IF_PADDR_11), 
        .HW_Boot_Engine_0_APB_IF_PADDR_13(
        HW_Boot_Engine_0_APB_IF_PADDR_13), .MDDR_Config_0_DRAM_Ready(
        MDDR_Config_0_DRAM_Ready), .MSS_HPMS_READY(MSS_HPMS_READY), 
        .CORECONFIGP_0_APB_S_PCLK(CORECONFIGP_0_APB_S_PCLK), 
        .HW_Boot_Engine_0_APB_IF_PWRITE(HW_Boot_Engine_0_APB_IF_PWRITE)
        , .HW_Boot_Engine_0_APB_IF_PENABLE(
        HW_Boot_Engine_0_APB_IF_PENABLE), 
        .HW_Boot_Engine_0_APB_IF_PSELx(HW_Boot_Engine_0_APB_IF_PSELx), 
        .HW_Boot_Engine_0_APB_IF_PREADY(HW_Boot_Engine_0_APB_IF_PREADY)
        );
    AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z7 
        AHB_IF_0 (.AHB_IF_0_DATAOUT({\AHB_IF_0_DATAOUT[8] , 
        \AHB_IF_0_DATAOUT[7] , \AHB_IF_0_DATAOUT[6] , 
        \AHB_IF_0_DATAOUT[5] , \AHB_IF_0_DATAOUT[4] , 
        \AHB_IF_0_DATAOUT[3] , \AHB_IF_0_DATAOUT[2] , 
        \AHB_IF_0_DATAOUT[1] , \AHB_IF_0_DATAOUT[0] }), 
        .HW_Boot_Engine_0_AHB_IF_HTRANS({
        HW_Boot_Engine_0_AHB_IF_HTRANS[1]}), 
        .CoreAHBLite_0_AHBmslave4_HRDATA({
        CoreAHBLite_0_AHBmslave4_HRDATA[8], 
        CoreAHBLite_0_AHBmslave4_HRDATA[7], 
        CoreAHBLite_0_AHBmslave4_HRDATA[6], 
        CoreAHBLite_0_AHBmslave4_HRDATA[5], 
        CoreAHBLite_0_AHBmslave4_HRDATA[4], 
        CoreAHBLite_0_AHBmslave4_HRDATA[3], 
        CoreAHBLite_0_AHBmslave4_HRDATA[2], 
        CoreAHBLite_0_AHBmslave4_HRDATA[1], 
        CoreAHBLite_0_AHBmslave4_HRDATA[0]}), .SPI_to_MDDR_0_DATAOUT_0(
        \SPI_to_MDDR_0_DATAOUT[0] ), .SPI_to_MDDR_0_DATAOUT_1(
        \SPI_to_MDDR_0_DATAOUT[1] ), .SPI_to_MDDR_0_DATAOUT_2(
        \SPI_to_MDDR_0_DATAOUT[2] ), .SPI_to_MDDR_0_DATAOUT_3(
        \SPI_to_MDDR_0_DATAOUT[3] ), .SPI_to_MDDR_0_DATAOUT_4(
        \SPI_to_MDDR_0_DATAOUT[4] ), .SPI_to_MDDR_0_DATAOUT_5(
        \SPI_to_MDDR_0_DATAOUT[5] ), .SPI_to_MDDR_0_DATAOUT_6(
        \SPI_to_MDDR_0_DATAOUT[6] ), .SPI_to_MDDR_0_DATAOUT_7(
        \SPI_to_MDDR_0_DATAOUT[7] ), .SPI_to_MDDR_0_DATAOUT_18(
        \SPI_to_MDDR_0_DATAOUT[18] ), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_2(
        HW_Boot_Engine_0_AHB_IF_HWDATA_2), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_3(
        HW_Boot_Engine_0_AHB_IF_HWDATA_3), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_4(
        HW_Boot_Engine_0_AHB_IF_HWDATA_4), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_5(
        HW_Boot_Engine_0_AHB_IF_HWDATA_5), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_6(
        HW_Boot_Engine_0_AHB_IF_HWDATA_6), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_7(
        HW_Boot_Engine_0_AHB_IF_HWDATA_7), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_18(
        HW_Boot_Engine_0_AHB_IF_HWDATA_18), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_0(
        HW_Boot_Engine_0_AHB_IF_HWDATA_0), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_1(
        HW_Boot_Engine_0_AHB_IF_HWDATA_1), .SPI_to_MDDR_0_ADDR_0(
        \SPI_to_MDDR_0_ADDR[2] ), .SPI_to_MDDR_0_ADDR_1(
        \SPI_to_MDDR_0_ADDR[3] ), .SPI_to_MDDR_0_ADDR_2(
        \SPI_to_MDDR_0_ADDR[4] ), .SPI_to_MDDR_0_ADDR_10(
        \SPI_to_MDDR_0_ADDR[12] ), .SPI_to_MDDR_0_ADDR_14(
        \SPI_to_MDDR_0_ADDR[16] ), .SPI_to_MDDR_0_ADDR_28(
        \SPI_to_MDDR_0_ADDR[30] ), .HW_Boot_Engine_0_AHB_IF_HADDR_1(
        HW_Boot_Engine_0_AHB_IF_HADDR_1), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_2(
        HW_Boot_Engine_0_AHB_IF_HADDR_2), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_10(
        HW_Boot_Engine_0_AHB_IF_HADDR_10), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_14(
        HW_Boot_Engine_0_AHB_IF_HADDR_14), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_28(
        HW_Boot_Engine_0_AHB_IF_HADDR_28), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_0(
        HW_Boot_Engine_0_AHB_IF_HADDR_0), .ahb_fsm_current_state_5(
        ahb_fsm_current_state[5]), .AHB_IF_0_AHB_BUSY(
        AHB_IF_0_AHB_BUSY), .AHB_IF_0_AHB_BUSY_i_0(
        AHB_IF_0_AHB_BUSY_i_0), .MSS_HPMS_READY(MSS_HPMS_READY), 
        .CCC_0_GL0(CCC_0_GL0), .HREADY_M_iv_i_0(HREADY_M_iv_i_0), 
        .HW_Boot_Engine_0_AHB_IF_HWRITE(HW_Boot_Engine_0_AHB_IF_HWRITE)
        , .SPI_to_MDDR_0_READ(SPI_to_MDDR_0_READ), 
        .SPI_to_MDDR_0_WRITE(SPI_to_MDDR_0_WRITE), .N_95(N_95), 
        .HREADY_M_iv_i_0_d(HREADY_M_iv_i_0_d), .HREADY_M_iv_i_0_1_0(
        HREADY_M_iv_i_0_1_0));
    SPI_to_MDDR_Z9 SPI_to_MDDR_0 (.SPI_to_MDDR_0_AXI_DATA({
        \SPI_to_MDDR_0_AXI_DATA[63] , \SPI_to_MDDR_0_AXI_DATA[62] , 
        \SPI_to_MDDR_0_AXI_DATA[61] , \SPI_to_MDDR_0_AXI_DATA[60] , 
        \SPI_to_MDDR_0_AXI_DATA[59] , \SPI_to_MDDR_0_AXI_DATA[58] , 
        \SPI_to_MDDR_0_AXI_DATA[57] , \SPI_to_MDDR_0_AXI_DATA[56] , 
        \SPI_to_MDDR_0_AXI_DATA[55] , \SPI_to_MDDR_0_AXI_DATA[54] , 
        \SPI_to_MDDR_0_AXI_DATA[53] , \SPI_to_MDDR_0_AXI_DATA[52] , 
        \SPI_to_MDDR_0_AXI_DATA[51] , \SPI_to_MDDR_0_AXI_DATA[50] , 
        \SPI_to_MDDR_0_AXI_DATA[49] , \SPI_to_MDDR_0_AXI_DATA[48] , 
        \SPI_to_MDDR_0_AXI_DATA[47] , \SPI_to_MDDR_0_AXI_DATA[46] , 
        \SPI_to_MDDR_0_AXI_DATA[45] , \SPI_to_MDDR_0_AXI_DATA[44] , 
        \SPI_to_MDDR_0_AXI_DATA[43] , \SPI_to_MDDR_0_AXI_DATA[42] , 
        \SPI_to_MDDR_0_AXI_DATA[41] , \SPI_to_MDDR_0_AXI_DATA[40] , 
        \SPI_to_MDDR_0_AXI_DATA[39] , \SPI_to_MDDR_0_AXI_DATA[38] , 
        \SPI_to_MDDR_0_AXI_DATA[37] , \SPI_to_MDDR_0_AXI_DATA[36] , 
        \SPI_to_MDDR_0_AXI_DATA[35] , \SPI_to_MDDR_0_AXI_DATA[34] , 
        \SPI_to_MDDR_0_AXI_DATA[33] , \SPI_to_MDDR_0_AXI_DATA[32] , 
        \SPI_to_MDDR_0_AXI_DATA[31] , \SPI_to_MDDR_0_AXI_DATA[30] , 
        \SPI_to_MDDR_0_AXI_DATA[29] , \SPI_to_MDDR_0_AXI_DATA[28] , 
        \SPI_to_MDDR_0_AXI_DATA[27] , \SPI_to_MDDR_0_AXI_DATA[26] , 
        \SPI_to_MDDR_0_AXI_DATA[25] , \SPI_to_MDDR_0_AXI_DATA[24] , 
        \SPI_to_MDDR_0_AXI_DATA[23] , \SPI_to_MDDR_0_AXI_DATA[22] , 
        \SPI_to_MDDR_0_AXI_DATA[21] , \SPI_to_MDDR_0_AXI_DATA[20] , 
        \SPI_to_MDDR_0_AXI_DATA[19] , \SPI_to_MDDR_0_AXI_DATA[18] , 
        \SPI_to_MDDR_0_AXI_DATA[17] , \SPI_to_MDDR_0_AXI_DATA[16] , 
        \SPI_to_MDDR_0_AXI_DATA[15] , \SPI_to_MDDR_0_AXI_DATA[14] , 
        \SPI_to_MDDR_0_AXI_DATA[13] , \SPI_to_MDDR_0_AXI_DATA[12] , 
        \SPI_to_MDDR_0_AXI_DATA[11] , \SPI_to_MDDR_0_AXI_DATA[10] , 
        \SPI_to_MDDR_0_AXI_DATA[9] , \SPI_to_MDDR_0_AXI_DATA[8] , 
        \SPI_to_MDDR_0_AXI_DATA[7] , \SPI_to_MDDR_0_AXI_DATA[6] , 
        \SPI_to_MDDR_0_AXI_DATA[5] , \SPI_to_MDDR_0_AXI_DATA[4] , 
        \SPI_to_MDDR_0_AXI_DATA[3] , \SPI_to_MDDR_0_AXI_DATA[2] , 
        \SPI_to_MDDR_0_AXI_DATA[1] , \SPI_to_MDDR_0_AXI_DATA[0] }), 
        .AHB_IF_0_DATAOUT({\AHB_IF_0_DATAOUT[8] , 
        \AHB_IF_0_DATAOUT[7] , \AHB_IF_0_DATAOUT[6] , 
        \AHB_IF_0_DATAOUT[5] , \AHB_IF_0_DATAOUT[4] , 
        \AHB_IF_0_DATAOUT[3] , \AHB_IF_0_DATAOUT[2] , 
        \AHB_IF_0_DATAOUT[1] , \AHB_IF_0_DATAOUT[0] }), 
        .SPI_to_MDDR_0_ADDR_0(\SPI_to_MDDR_0_ADDR[2] ), 
        .SPI_to_MDDR_0_ADDR_1(\SPI_to_MDDR_0_ADDR[3] ), 
        .SPI_to_MDDR_0_ADDR_2(\SPI_to_MDDR_0_ADDR[4] ), 
        .SPI_to_MDDR_0_ADDR_28(\SPI_to_MDDR_0_ADDR[30] ), 
        .SPI_to_MDDR_0_ADDR_14(\SPI_to_MDDR_0_ADDR[16] ), 
        .SPI_to_MDDR_0_ADDR_10(\SPI_to_MDDR_0_ADDR[12] ), 
        .SPI_to_MDDR_0_DATAOUT_0(\SPI_to_MDDR_0_DATAOUT[0] ), 
        .SPI_to_MDDR_0_DATAOUT_1(\SPI_to_MDDR_0_DATAOUT[1] ), 
        .SPI_to_MDDR_0_DATAOUT_2(\SPI_to_MDDR_0_DATAOUT[2] ), 
        .SPI_to_MDDR_0_DATAOUT_3(\SPI_to_MDDR_0_DATAOUT[3] ), 
        .SPI_to_MDDR_0_DATAOUT_4(\SPI_to_MDDR_0_DATAOUT[4] ), 
        .SPI_to_MDDR_0_DATAOUT_5(\SPI_to_MDDR_0_DATAOUT[5] ), 
        .SPI_to_MDDR_0_DATAOUT_6(\SPI_to_MDDR_0_DATAOUT[6] ), 
        .SPI_to_MDDR_0_DATAOUT_7(\SPI_to_MDDR_0_DATAOUT[7] ), 
        .SPI_to_MDDR_0_DATAOUT_18(\SPI_to_MDDR_0_DATAOUT[18] ), 
        .CCC_0_GL0(CCC_0_GL0), .MSS_HPMS_READY(MSS_HPMS_READY), 
        .SPI_to_MDDR_0_READ(SPI_to_MDDR_0_READ), .SPI_to_MDDR_0_WRITE(
        SPI_to_MDDR_0_WRITE), .GPIO_0_M2F_0(GPIO_0_M2F_0), 
        .SPI_to_MDDR_0_AXI_WRITE(SPI_to_MDDR_0_AXI_WRITE), 
        .AHB_IF_0_AHB_BUSY_i_0(AHB_IF_0_AHB_BUSY_i_0), 
        .AHB_IF_0_AHB_BUSY(AHB_IF_0_AHB_BUSY), .AXI_IF_0_AXI_BUSY(
        AXI_IF_0_AXI_BUSY), .DP_SW1_c(DP_SW1_c));
    GND GND (.Y(GND_net_1));
    AXI_IF_0s_1s_2s_3s_4294967292s AXI_IF_0 (
        .HW_Boot_Engine_0_AXI_IF_WDATA({
        HW_Boot_Engine_0_AXI_IF_WDATA[63], 
        HW_Boot_Engine_0_AXI_IF_WDATA[62], 
        HW_Boot_Engine_0_AXI_IF_WDATA[61], 
        HW_Boot_Engine_0_AXI_IF_WDATA[60], 
        HW_Boot_Engine_0_AXI_IF_WDATA[59], 
        HW_Boot_Engine_0_AXI_IF_WDATA[58], 
        HW_Boot_Engine_0_AXI_IF_WDATA[57], 
        HW_Boot_Engine_0_AXI_IF_WDATA[56], 
        HW_Boot_Engine_0_AXI_IF_WDATA[55], 
        HW_Boot_Engine_0_AXI_IF_WDATA[54], 
        HW_Boot_Engine_0_AXI_IF_WDATA[53], 
        HW_Boot_Engine_0_AXI_IF_WDATA[52], 
        HW_Boot_Engine_0_AXI_IF_WDATA[51], 
        HW_Boot_Engine_0_AXI_IF_WDATA[50], 
        HW_Boot_Engine_0_AXI_IF_WDATA[49], 
        HW_Boot_Engine_0_AXI_IF_WDATA[48], 
        HW_Boot_Engine_0_AXI_IF_WDATA[47], 
        HW_Boot_Engine_0_AXI_IF_WDATA[46], 
        HW_Boot_Engine_0_AXI_IF_WDATA[45], 
        HW_Boot_Engine_0_AXI_IF_WDATA[44], 
        HW_Boot_Engine_0_AXI_IF_WDATA[43], 
        HW_Boot_Engine_0_AXI_IF_WDATA[42], 
        HW_Boot_Engine_0_AXI_IF_WDATA[41], 
        HW_Boot_Engine_0_AXI_IF_WDATA[40], 
        HW_Boot_Engine_0_AXI_IF_WDATA[39], 
        HW_Boot_Engine_0_AXI_IF_WDATA[38], 
        HW_Boot_Engine_0_AXI_IF_WDATA[37], 
        HW_Boot_Engine_0_AXI_IF_WDATA[36], 
        HW_Boot_Engine_0_AXI_IF_WDATA[35], 
        HW_Boot_Engine_0_AXI_IF_WDATA[34], 
        HW_Boot_Engine_0_AXI_IF_WDATA[33], 
        HW_Boot_Engine_0_AXI_IF_WDATA[32], 
        HW_Boot_Engine_0_AXI_IF_WDATA[31], 
        HW_Boot_Engine_0_AXI_IF_WDATA[30], 
        HW_Boot_Engine_0_AXI_IF_WDATA[29], 
        HW_Boot_Engine_0_AXI_IF_WDATA[28], 
        HW_Boot_Engine_0_AXI_IF_WDATA[27], 
        HW_Boot_Engine_0_AXI_IF_WDATA[26], 
        HW_Boot_Engine_0_AXI_IF_WDATA[25], 
        HW_Boot_Engine_0_AXI_IF_WDATA[24], 
        HW_Boot_Engine_0_AXI_IF_WDATA[23], 
        HW_Boot_Engine_0_AXI_IF_WDATA[22], 
        HW_Boot_Engine_0_AXI_IF_WDATA[21], 
        HW_Boot_Engine_0_AXI_IF_WDATA[20], 
        HW_Boot_Engine_0_AXI_IF_WDATA[19], 
        HW_Boot_Engine_0_AXI_IF_WDATA[18], 
        HW_Boot_Engine_0_AXI_IF_WDATA[17], 
        HW_Boot_Engine_0_AXI_IF_WDATA[16], 
        HW_Boot_Engine_0_AXI_IF_WDATA[15], 
        HW_Boot_Engine_0_AXI_IF_WDATA[14], 
        HW_Boot_Engine_0_AXI_IF_WDATA[13], 
        HW_Boot_Engine_0_AXI_IF_WDATA[12], 
        HW_Boot_Engine_0_AXI_IF_WDATA[11], 
        HW_Boot_Engine_0_AXI_IF_WDATA[10], 
        HW_Boot_Engine_0_AXI_IF_WDATA[9], 
        HW_Boot_Engine_0_AXI_IF_WDATA[8], 
        HW_Boot_Engine_0_AXI_IF_WDATA[7], 
        HW_Boot_Engine_0_AXI_IF_WDATA[6], 
        HW_Boot_Engine_0_AXI_IF_WDATA[5], 
        HW_Boot_Engine_0_AXI_IF_WDATA[4], 
        HW_Boot_Engine_0_AXI_IF_WDATA[3], 
        HW_Boot_Engine_0_AXI_IF_WDATA[2], 
        HW_Boot_Engine_0_AXI_IF_WDATA[1], 
        HW_Boot_Engine_0_AXI_IF_WDATA[0]}), .SPI_to_MDDR_0_AXI_DATA({
        \SPI_to_MDDR_0_AXI_DATA[63] , \SPI_to_MDDR_0_AXI_DATA[62] , 
        \SPI_to_MDDR_0_AXI_DATA[61] , \SPI_to_MDDR_0_AXI_DATA[60] , 
        \SPI_to_MDDR_0_AXI_DATA[59] , \SPI_to_MDDR_0_AXI_DATA[58] , 
        \SPI_to_MDDR_0_AXI_DATA[57] , \SPI_to_MDDR_0_AXI_DATA[56] , 
        \SPI_to_MDDR_0_AXI_DATA[55] , \SPI_to_MDDR_0_AXI_DATA[54] , 
        \SPI_to_MDDR_0_AXI_DATA[53] , \SPI_to_MDDR_0_AXI_DATA[52] , 
        \SPI_to_MDDR_0_AXI_DATA[51] , \SPI_to_MDDR_0_AXI_DATA[50] , 
        \SPI_to_MDDR_0_AXI_DATA[49] , \SPI_to_MDDR_0_AXI_DATA[48] , 
        \SPI_to_MDDR_0_AXI_DATA[47] , \SPI_to_MDDR_0_AXI_DATA[46] , 
        \SPI_to_MDDR_0_AXI_DATA[45] , \SPI_to_MDDR_0_AXI_DATA[44] , 
        \SPI_to_MDDR_0_AXI_DATA[43] , \SPI_to_MDDR_0_AXI_DATA[42] , 
        \SPI_to_MDDR_0_AXI_DATA[41] , \SPI_to_MDDR_0_AXI_DATA[40] , 
        \SPI_to_MDDR_0_AXI_DATA[39] , \SPI_to_MDDR_0_AXI_DATA[38] , 
        \SPI_to_MDDR_0_AXI_DATA[37] , \SPI_to_MDDR_0_AXI_DATA[36] , 
        \SPI_to_MDDR_0_AXI_DATA[35] , \SPI_to_MDDR_0_AXI_DATA[34] , 
        \SPI_to_MDDR_0_AXI_DATA[33] , \SPI_to_MDDR_0_AXI_DATA[32] , 
        \SPI_to_MDDR_0_AXI_DATA[31] , \SPI_to_MDDR_0_AXI_DATA[30] , 
        \SPI_to_MDDR_0_AXI_DATA[29] , \SPI_to_MDDR_0_AXI_DATA[28] , 
        \SPI_to_MDDR_0_AXI_DATA[27] , \SPI_to_MDDR_0_AXI_DATA[26] , 
        \SPI_to_MDDR_0_AXI_DATA[25] , \SPI_to_MDDR_0_AXI_DATA[24] , 
        \SPI_to_MDDR_0_AXI_DATA[23] , \SPI_to_MDDR_0_AXI_DATA[22] , 
        \SPI_to_MDDR_0_AXI_DATA[21] , \SPI_to_MDDR_0_AXI_DATA[20] , 
        \SPI_to_MDDR_0_AXI_DATA[19] , \SPI_to_MDDR_0_AXI_DATA[18] , 
        \SPI_to_MDDR_0_AXI_DATA[17] , \SPI_to_MDDR_0_AXI_DATA[16] , 
        \SPI_to_MDDR_0_AXI_DATA[15] , \SPI_to_MDDR_0_AXI_DATA[14] , 
        \SPI_to_MDDR_0_AXI_DATA[13] , \SPI_to_MDDR_0_AXI_DATA[12] , 
        \SPI_to_MDDR_0_AXI_DATA[11] , \SPI_to_MDDR_0_AXI_DATA[10] , 
        \SPI_to_MDDR_0_AXI_DATA[9] , \SPI_to_MDDR_0_AXI_DATA[8] , 
        \SPI_to_MDDR_0_AXI_DATA[7] , \SPI_to_MDDR_0_AXI_DATA[6] , 
        \SPI_to_MDDR_0_AXI_DATA[5] , \SPI_to_MDDR_0_AXI_DATA[4] , 
        \SPI_to_MDDR_0_AXI_DATA[3] , \SPI_to_MDDR_0_AXI_DATA[2] , 
        \SPI_to_MDDR_0_AXI_DATA[1] , \SPI_to_MDDR_0_AXI_DATA[0] }), 
        .HW_Boot_Engine_0_AXI_IF_AWADDR({
        HW_Boot_Engine_0_AXI_IF_AWADDR[31], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[30], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[29], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[28], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[27], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[26], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[25], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[24], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[23], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[22], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[21], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[20], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[19], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[18], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[17], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[16], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[15], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[14], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[13], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[12], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[11], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[10], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[9], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[8], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[7], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[6], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[5], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[4], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[3], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[2], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[1], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[0]}), 
        .HW_Boot_Engine_0_AXI_IF_AWSIZE({
        HW_Boot_Engine_0_AXI_IF_AWSIZE[0]}), .MDDR_Config_0_DRAM_Ready(
        MDDR_Config_0_DRAM_Ready), .CCC_0_GL0(CCC_0_GL0), 
        .AXI_IF_0_AXI_BUSY(AXI_IF_0_AXI_BUSY), 
        .HW_Boot_Engine_0_AXI_IF_WLAST(HW_Boot_Engine_0_AXI_IF_WLAST), 
        .HW_Boot_Engine_0_AXI_IF_BREADY(HW_Boot_Engine_0_AXI_IF_BREADY)
        , .HW_Boot_Engine_0_AXI_IF_AWVALID(
        HW_Boot_Engine_0_AXI_IF_AWVALID), .SPI_to_MDDR_0_AXI_WRITE(
        SPI_to_MDDR_0_AXI_WRITE), .HW_Boot_Engine_0_AXI_IF_AWREADY(
        HW_Boot_Engine_0_AXI_IF_AWREADY), 
        .HW_Boot_Engine_0_AXI_IF_WREADY(HW_Boot_Engine_0_AXI_IF_WREADY)
        , .HW_Boot_Engine_0_AXI_IF_BVALID(
        HW_Boot_Engine_0_AXI_IF_BVALID));
    
endmodule


module CoreResetP_Z6(
       MSS_HPMS_READY,
       CCC_0_GL0,
       POWER_ON_RESET_N,
       MSS_RESET_N_M2F,
       FIC_2_APB_M_PRESET_N
    );
output MSS_HPMS_READY;
input  CCC_0_GL0;
input  POWER_ON_RESET_N;
input  MSS_RESET_N_M2F;
input  FIC_2_APB_M_PRESET_N;

    wire MSS_HPMS_READY_int_net_1, mss_ready_select_net_1, VCC_net_1, 
        POWER_ON_RESET_N_clk_base_net_1, mss_ready_select4_net_1, 
        GND_net_1, mss_ready_state_net_1, RESET_N_M2F_clk_base_net_1, 
        POWER_ON_RESET_N_q1_net_1, RESET_N_M2F_q1_net_1, 
        FIC_2_APB_M_PRESET_N_q1_net_1, 
        FIC_2_APB_M_PRESET_N_clk_base_net_1, 
        MSS_HPMS_READY_int_4_net_1;
    
    SLE RESET_N_M2F_clk_base (.D(RESET_N_M2F_q1_net_1), .CLK(CCC_0_GL0)
        , .EN(VCC_net_1), .ALn(MSS_RESET_N_M2F), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        RESET_N_M2F_clk_base_net_1));
    SLE POWER_ON_RESET_N_clk_base (.D(POWER_ON_RESET_N_q1_net_1), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(POWER_ON_RESET_N_clk_base_net_1));
    SLE mss_ready_select (.D(VCC_net_1), .CLK(CCC_0_GL0), .EN(
        mss_ready_select4_net_1), .ALn(POWER_ON_RESET_N_clk_base_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(mss_ready_select_net_1));
    CLKINT MSS_HPMS_READY_int_RNI1SB7 (.A(MSS_HPMS_READY_int_net_1), 
        .Y(MSS_HPMS_READY));
    GND GND (.Y(GND_net_1));
    SLE mss_ready_state (.D(VCC_net_1), .CLK(CCC_0_GL0), .EN(
        RESET_N_M2F_clk_base_net_1), .ALn(
        POWER_ON_RESET_N_clk_base_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        mss_ready_state_net_1));
    VCC VCC (.Y(VCC_net_1));
    SLE RESET_N_M2F_q1 (.D(VCC_net_1), .CLK(CCC_0_GL0), .EN(VCC_net_1), 
        .ALn(MSS_RESET_N_M2F), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(RESET_N_M2F_q1_net_1));
    SLE FIC_2_APB_M_PRESET_N_clk_base (.D(
        FIC_2_APB_M_PRESET_N_q1_net_1), .CLK(CCC_0_GL0), .EN(VCC_net_1)
        , .ALn(FIC_2_APB_M_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        FIC_2_APB_M_PRESET_N_clk_base_net_1));
    SLE POWER_ON_RESET_N_q1 (.D(VCC_net_1), .CLK(CCC_0_GL0), .EN(
        VCC_net_1), .ALn(POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        POWER_ON_RESET_N_q1_net_1));
    CFG2 #( .INIT(4'h8) )  mss_ready_select4 (.A(
        FIC_2_APB_M_PRESET_N_clk_base_net_1), .B(mss_ready_state_net_1)
        , .Y(mss_ready_select4_net_1));
    CFG3 #( .INIT(8'hE0) )  MSS_HPMS_READY_int_4 (.A(
        RESET_N_M2F_clk_base_net_1), .B(mss_ready_select_net_1), .C(
        FIC_2_APB_M_PRESET_N_clk_base_net_1), .Y(
        MSS_HPMS_READY_int_4_net_1));
    SLE FIC_2_APB_M_PRESET_N_q1 (.D(VCC_net_1), .CLK(CCC_0_GL0), .EN(
        VCC_net_1), .ALn(FIC_2_APB_M_PRESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        FIC_2_APB_M_PRESET_N_q1_net_1));
    SLE MSS_HPMS_READY_int (.D(MSS_HPMS_READY_int_4_net_1), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(
        POWER_ON_RESET_N_clk_base_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MSS_HPMS_READY_int_net_1));
    
endmodule


module COREAHBLITE_SLAVEARBITER_Z3_1(
       arbRegSMCurrentState_0,
       arbRegSMCurrentState_1,
       arbRegSMCurrentState_13,
       MSS_HPMS_READY,
       CCC_0_GL0,
       N_43_mux,
       N_761,
       CoreAHBLite_0_AHBmslave4_HREADY,
       N_94_i_0
    );
output arbRegSMCurrentState_0;
output arbRegSMCurrentState_1;
output arbRegSMCurrentState_13;
input  MSS_HPMS_READY;
input  CCC_0_GL0;
input  N_43_mux;
input  N_761;
input  CoreAHBLite_0_AHBmslave4_HREADY;
input  N_94_i_0;

    wire VCC_net_1, N_137, GND_net_1;
    
    SLE \arbRegSMCurrentState[13]  (.D(GND_net_1), .CLK(CCC_0_GL0), 
        .EN(N_761), .ALn(MSS_HPMS_READY), .ADn(GND_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        arbRegSMCurrentState_13));
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    CFG2 #( .INIT(4'h4) )  \arbRegSMCurrentState_ns_i_i_a2[0]  (.A(
        CoreAHBLite_0_AHBmslave4_HREADY), .B(N_94_i_0), .Y(N_137));
    SLE \arbRegSMCurrentState[1]  (.D(N_43_mux), .CLK(CCC_0_GL0), .EN(
        VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        arbRegSMCurrentState_1));
    SLE \arbRegSMCurrentState[0]  (.D(N_137), .CLK(CCC_0_GL0), .EN(
        VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        arbRegSMCurrentState_0));
    
endmodule


module COREAHBLITE_SLAVESTAGE_0s_0_0_0(
       masterDataInProg,
       CoreAHBLite_0_AHBmslave4_HTRANS,
       HW_Boot_Engine_0_AHB_IF_HWDATA_18,
       HW_Boot_Engine_0_AHB_IF_HWDATA_7,
       HW_Boot_Engine_0_AHB_IF_HWDATA_6,
       HW_Boot_Engine_0_AHB_IF_HWDATA_5,
       HW_Boot_Engine_0_AHB_IF_HWDATA_4,
       HW_Boot_Engine_0_AHB_IF_HWDATA_3,
       HW_Boot_Engine_0_AHB_IF_HWDATA_2,
       HW_Boot_Engine_0_AHB_IF_HWDATA_1,
       HW_Boot_Engine_0_AHB_IF_HWDATA_0,
       CoreAHBLite_0_AHBmslave4_HWDATA_29,
       CoreAHBLite_0_AHBmslave4_HWDATA_7,
       CoreAHBLite_0_AHBmslave4_HWDATA_6,
       CoreAHBLite_0_AHBmslave4_HWDATA_5,
       CoreAHBLite_0_AHBmslave4_HWDATA_4,
       CoreAHBLite_0_AHBmslave4_HWDATA_3,
       CoreAHBLite_0_AHBmslave4_HWDATA_2,
       CoreAHBLite_0_AHBmslave4_HWDATA_1,
       CoreAHBLite_0_AHBmslave4_HWDATA_0,
       regHADDR_15,
       regHADDR_10,
       regHADDR_2,
       regHADDR_1,
       regHADDR_0,
       HW_Boot_Engine_0_AHB_IF_HADDR_28,
       HW_Boot_Engine_0_AHB_IF_HADDR_14,
       HW_Boot_Engine_0_AHB_IF_HADDR_10,
       HW_Boot_Engine_0_AHB_IF_HADDR_2,
       HW_Boot_Engine_0_AHB_IF_HADDR_1,
       HW_Boot_Engine_0_AHB_IF_HADDR_0,
       arbRegSMCurrentState_0,
       arbRegSMCurrentState_1,
       arbRegSMCurrentState_13,
       MSS_HPMS_READY,
       CCC_0_GL0,
       N_94_i_0,
       CoreAHBLite_0_AHBmslave4_HREADY,
       m0s4DataSel,
       N_91,
       defSlaveSMCurrentState,
       N_144,
       N_171,
       masterRegAddrSel,
       regHWRITE,
       HW_Boot_Engine_0_AHB_IF_HWRITE,
       N_52_i_0,
       regHTRANS,
       N_50_i_0,
       N_48_i_0,
       N_46_i_0,
       N_767_i_0,
       N_766_i_0,
       N_765_i_0,
       N_764_i_0,
       N_43_mux,
       N_761
    );
output [0:0] masterDataInProg;
output [1:1] CoreAHBLite_0_AHBmslave4_HTRANS;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_18;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_7;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_6;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_5;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_4;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_3;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_2;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_1;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_0;
output CoreAHBLite_0_AHBmslave4_HWDATA_29;
output CoreAHBLite_0_AHBmslave4_HWDATA_7;
output CoreAHBLite_0_AHBmslave4_HWDATA_6;
output CoreAHBLite_0_AHBmslave4_HWDATA_5;
output CoreAHBLite_0_AHBmslave4_HWDATA_4;
output CoreAHBLite_0_AHBmslave4_HWDATA_3;
output CoreAHBLite_0_AHBmslave4_HWDATA_2;
output CoreAHBLite_0_AHBmslave4_HWDATA_1;
output CoreAHBLite_0_AHBmslave4_HWDATA_0;
input  regHADDR_15;
input  regHADDR_10;
input  regHADDR_2;
input  regHADDR_1;
input  regHADDR_0;
input  HW_Boot_Engine_0_AHB_IF_HADDR_28;
input  HW_Boot_Engine_0_AHB_IF_HADDR_14;
input  HW_Boot_Engine_0_AHB_IF_HADDR_10;
input  HW_Boot_Engine_0_AHB_IF_HADDR_2;
input  HW_Boot_Engine_0_AHB_IF_HADDR_1;
input  HW_Boot_Engine_0_AHB_IF_HADDR_0;
output arbRegSMCurrentState_0;
output arbRegSMCurrentState_1;
output arbRegSMCurrentState_13;
input  MSS_HPMS_READY;
input  CCC_0_GL0;
input  N_94_i_0;
input  CoreAHBLite_0_AHBmslave4_HREADY;
input  m0s4DataSel;
input  N_91;
input  defSlaveSMCurrentState;
input  N_144;
input  N_171;
input  masterRegAddrSel;
input  regHWRITE;
input  HW_Boot_Engine_0_AHB_IF_HWRITE;
output N_52_i_0;
input  regHTRANS;
output N_50_i_0;
output N_48_i_0;
output N_46_i_0;
output N_767_i_0;
output N_766_i_0;
output N_765_i_0;
output N_764_i_0;
input  N_43_mux;
input  N_761;

    wire VCC_net_1, GND_net_1, \CoreAHBLite_0_AHBmslave4_HTRANS_tz[1] ;
    
    CFG4 #( .INIT(16'hC480) )  N_765_i (.A(masterRegAddrSel), .B(
        N_94_i_0), .C(regHADDR_1), .D(HW_Boot_Engine_0_AHB_IF_HADDR_1), 
        .Y(N_765_i_0));
    CFG2 #( .INIT(4'h8) )  \HWDATA[2]  (.A(masterDataInProg[0]), .B(
        HW_Boot_Engine_0_AHB_IF_HWDATA_2), .Y(
        CoreAHBLite_0_AHBmslave4_HWDATA_2));
    CFG4 #( .INIT(16'hC480) )  N_48_i (.A(masterRegAddrSel), .B(
        N_94_i_0), .C(regHTRANS), .D(HW_Boot_Engine_0_AHB_IF_HADDR_28), 
        .Y(N_48_i_0));
    CFG4 #( .INIT(16'hC480) )  N_766_i (.A(masterRegAddrSel), .B(
        N_94_i_0), .C(regHADDR_2), .D(HW_Boot_Engine_0_AHB_IF_HADDR_2), 
        .Y(N_766_i_0));
    CFG2 #( .INIT(4'h8) )  \HWDATA[7]  (.A(masterDataInProg[0]), .B(
        HW_Boot_Engine_0_AHB_IF_HWDATA_7), .Y(
        CoreAHBLite_0_AHBmslave4_HWDATA_7));
    GND GND (.Y(GND_net_1));
    CFG4 #( .INIT(16'hC480) )  N_764_i (.A(masterRegAddrSel), .B(
        N_94_i_0), .C(regHADDR_0), .D(HW_Boot_Engine_0_AHB_IF_HADDR_0), 
        .Y(N_764_i_0));
    CFG2 #( .INIT(4'h8) )  \HWDATA[3]  (.A(masterDataInProg[0]), .B(
        HW_Boot_Engine_0_AHB_IF_HWDATA_3), .Y(
        CoreAHBLite_0_AHBmslave4_HWDATA_3));
    CFG2 #( .INIT(4'h8) )  \HWDATA[5]  (.A(masterDataInProg[0]), .B(
        HW_Boot_Engine_0_AHB_IF_HWDATA_5), .Y(
        CoreAHBLite_0_AHBmslave4_HWDATA_5));
    CFG2 #( .INIT(4'h8) )  \HWDATA[10]  (.A(masterDataInProg[0]), .B(
        HW_Boot_Engine_0_AHB_IF_HWDATA_18), .Y(
        CoreAHBLite_0_AHBmslave4_HWDATA_29));
    CFG4 #( .INIT(16'hC080) )  HTRANS_0 (.A(N_144), .B(N_94_i_0), .C(
        \CoreAHBLite_0_AHBmslave4_HTRANS_tz[1] ), .D(N_171), .Y(
        CoreAHBLite_0_AHBmslave4_HTRANS[1]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[1]  (.A(masterDataInProg[0]), .B(
        HW_Boot_Engine_0_AHB_IF_HWDATA_1), .Y(
        CoreAHBLite_0_AHBmslave4_HWDATA_1));
    CFG2 #( .INIT(4'h8) )  \HWDATA[4]  (.A(masterDataInProg[0]), .B(
        HW_Boot_Engine_0_AHB_IF_HWDATA_4), .Y(
        CoreAHBLite_0_AHBmslave4_HWDATA_4));
    CFG3 #( .INIT(8'hFB) )  HTRANS_0_tz (.A(m0s4DataSel), .B(N_91), .C(
        defSlaveSMCurrentState), .Y(
        \CoreAHBLite_0_AHBmslave4_HTRANS_tz[1] ));
    CFG3 #( .INIT(8'hC4) )  N_50_i (.A(masterRegAddrSel), .B(N_94_i_0), 
        .C(regHTRANS), .Y(N_50_i_0));
    CFG2 #( .INIT(4'h8) )  \HWDATA[6]  (.A(masterDataInProg[0]), .B(
        HW_Boot_Engine_0_AHB_IF_HWDATA_6), .Y(
        CoreAHBLite_0_AHBmslave4_HWDATA_6));
    CFG4 #( .INIT(16'hC480) )  N_52_i (.A(masterRegAddrSel), .B(
        N_94_i_0), .C(regHWRITE), .D(HW_Boot_Engine_0_AHB_IF_HWRITE), 
        .Y(N_52_i_0));
    VCC VCC (.Y(VCC_net_1));
    CFG4 #( .INIT(16'hC480) )  N_767_i (.A(masterRegAddrSel), .B(
        N_94_i_0), .C(regHADDR_10), .D(
        HW_Boot_Engine_0_AHB_IF_HADDR_10), .Y(N_767_i_0));
    SLE \masterDataInProg[0]  (.D(N_94_i_0), .CLK(CCC_0_GL0), .EN(
        CoreAHBLite_0_AHBmslave4_HREADY), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(masterDataInProg[0]));
    COREAHBLITE_SLAVEARBITER_Z3_1 slave_arbiter (
        .arbRegSMCurrentState_0(arbRegSMCurrentState_0), 
        .arbRegSMCurrentState_1(arbRegSMCurrentState_1), 
        .arbRegSMCurrentState_13(arbRegSMCurrentState_13), 
        .MSS_HPMS_READY(MSS_HPMS_READY), .CCC_0_GL0(CCC_0_GL0), 
        .N_43_mux(N_43_mux), .N_761(N_761), 
        .CoreAHBLite_0_AHBmslave4_HREADY(
        CoreAHBLite_0_AHBmslave4_HREADY), .N_94_i_0(N_94_i_0));
    CFG4 #( .INIT(16'hC480) )  N_46_i (.A(masterRegAddrSel), .B(
        N_94_i_0), .C(regHADDR_15), .D(
        HW_Boot_Engine_0_AHB_IF_HADDR_14), .Y(N_46_i_0));
    CFG2 #( .INIT(4'h8) )  \HWDATA[0]  (.A(masterDataInProg[0]), .B(
        HW_Boot_Engine_0_AHB_IF_HWDATA_0), .Y(
        CoreAHBLite_0_AHBmslave4_HWDATA_0));
    
endmodule


module COREAHBLITE_DEFAULTSLAVESM_0s_0_1_0(
       ahb_fsm_current_state,
       masterDataInProg,
       defSlaveSMCurrentState,
       MSS_HPMS_READY,
       CCC_0_GL0,
       N_91,
       m0s4DataSel,
       HREADY_M_iv_i_0_0,
       HREADY_M_iv_i_0_1_0
    );
input  [5:5] ahb_fsm_current_state;
input  [0:0] masterDataInProg;
output defSlaveSMCurrentState;
input  MSS_HPMS_READY;
input  CCC_0_GL0;
input  N_91;
input  m0s4DataSel;
output HREADY_M_iv_i_0_0;
output HREADY_M_iv_i_0_1_0;

    wire VCC_net_1, N_760_i_0, GND_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    CFG3 #( .INIT(8'hD1) )  defSlaveSMCurrentState_RNISH4P (.A(
        m0s4DataSel), .B(N_91), .C(defSlaveSMCurrentState), .Y(
        HREADY_M_iv_i_0_0));
    CFG2 #( .INIT(4'h2) )  defSlaveSMCurrentState_RNO (.A(N_91), .B(
        defSlaveSMCurrentState), .Y(N_760_i_0));
    CFG3 #( .INIT(8'hA8) )  defSlaveSMCurrentState_RNIN0411 (.A(
        ahb_fsm_current_state[5]), .B(HREADY_M_iv_i_0_0), .C(
        masterDataInProg[0]), .Y(HREADY_M_iv_i_0_1_0));
    SLE defSlaveSMCurrentState_inst_1 (.D(N_760_i_0), .CLK(CCC_0_GL0), 
        .EN(VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        defSlaveSMCurrentState));
    
endmodule


module COREAHBLITE_MASTERSTAGE_1_1_0_16_0s_0_1_0(
       HW_Boot_Engine_0_AHB_IF_HTRANS,
       masterDataInProg,
       ahb_fsm_current_state,
       regHADDR_15,
       regHADDR_0,
       regHADDR_1,
       regHADDR_2,
       regHADDR_10,
       HW_Boot_Engine_0_AHB_IF_HADDR_14,
       HW_Boot_Engine_0_AHB_IF_HADDR_0,
       HW_Boot_Engine_0_AHB_IF_HADDR_1,
       HW_Boot_Engine_0_AHB_IF_HADDR_2,
       HW_Boot_Engine_0_AHB_IF_HADDR_10,
       HW_Boot_Engine_0_AHB_IF_HADDR_28,
       arbRegSMCurrentState_1,
       arbRegSMCurrentState_13,
       arbRegSMCurrentState_0,
       N_91,
       MSS_HPMS_READY,
       CCC_0_GL0,
       HREADY_M_iv_i_0_d,
       m0s4DataSel,
       N_761,
       regHWRITE,
       HW_Boot_Engine_0_AHB_IF_HWRITE,
       regHTRANS,
       masterRegAddrSel,
       N_94_i_0,
       N_144,
       N_95,
       N_171,
       CoreAHBLite_0_AHBmslave4_HREADY,
       HREADY_M_iv_i_0,
       defSlaveSMCurrentState,
       N_43_mux,
       HREADY_M_iv_i_0_1_0
    );
input  [1:1] HW_Boot_Engine_0_AHB_IF_HTRANS;
input  [0:0] masterDataInProg;
input  [5:5] ahb_fsm_current_state;
output regHADDR_15;
output regHADDR_0;
output regHADDR_1;
output regHADDR_2;
output regHADDR_10;
input  HW_Boot_Engine_0_AHB_IF_HADDR_14;
input  HW_Boot_Engine_0_AHB_IF_HADDR_0;
input  HW_Boot_Engine_0_AHB_IF_HADDR_1;
input  HW_Boot_Engine_0_AHB_IF_HADDR_2;
input  HW_Boot_Engine_0_AHB_IF_HADDR_10;
input  HW_Boot_Engine_0_AHB_IF_HADDR_28;
input  arbRegSMCurrentState_1;
input  arbRegSMCurrentState_13;
input  arbRegSMCurrentState_0;
output N_91;
input  MSS_HPMS_READY;
input  CCC_0_GL0;
output HREADY_M_iv_i_0_d;
output m0s4DataSel;
output N_761;
output regHWRITE;
input  HW_Boot_Engine_0_AHB_IF_HWRITE;
output regHTRANS;
output masterRegAddrSel;
output N_94_i_0;
output N_144;
output N_95;
output N_171;
input  CoreAHBLite_0_AHBmslave4_HREADY;
output HREADY_M_iv_i_0;
output defSlaveSMCurrentState;
output N_43_mux;
output HREADY_M_iv_i_0_1_0;

    wire VCC_net_1, \SADDRSEL[0] , GND_net_1, masterAddrClockEnable, 
        d_masterRegAddrSel, N_39_mux, N_6_0, 
        masterAddrClockEnable_0_a2_0_1_net_1, N_141, HREADY_M_iv_i_0_0, 
        N_142, N_138;
    
    SLE \regHADDR[2]  (.D(HW_Boot_Engine_0_AHB_IF_HADDR_0), .CLK(
        CCC_0_GL0), .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_0));
    SLE \regHADDR[12]  (.D(HW_Boot_Engine_0_AHB_IF_HADDR_10), .CLK(
        CCC_0_GL0), .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_10));
    CFG2 #( .INIT(4'h4) )  \SADDRSEL_3_0_a2_0[0]  (.A(masterRegAddrSel)
        , .B(HW_Boot_Engine_0_AHB_IF_HTRANS[1]), .Y(N_144));
    SLE regHTRANS_inst_1 (.D(VCC_net_1), .CLK(CCC_0_GL0), .EN(
        masterAddrClockEnable), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHTRANS)
        );
    CFG3 #( .INIT(8'hCE) )  HREADY_M_pre25_0_o2_RNII4L21 (.A(
        CoreAHBLite_0_AHBmslave4_HREADY), .B(HREADY_M_iv_i_0_0), .C(
        N_95), .Y(HREADY_M_iv_i_0_d));
    SLE \regHADDR[4]  (.D(HW_Boot_Engine_0_AHB_IF_HADDR_2), .CLK(
        CCC_0_GL0), .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_2));
    COREAHBLITE_DEFAULTSLAVESM_0s_0_1_0 default_slave_sm (
        .ahb_fsm_current_state({ahb_fsm_current_state[5]}), 
        .masterDataInProg({masterDataInProg[0]}), 
        .defSlaveSMCurrentState(defSlaveSMCurrentState), 
        .MSS_HPMS_READY(MSS_HPMS_READY), .CCC_0_GL0(CCC_0_GL0), .N_91(
        N_91), .m0s4DataSel(m0s4DataSel), .HREADY_M_iv_i_0_0(
        HREADY_M_iv_i_0_0), .HREADY_M_iv_i_0_1_0(HREADY_M_iv_i_0_1_0));
    GND GND (.Y(GND_net_1));
    CFG4 #( .INIT(16'hFF2A) )  d_masterRegAddrSel_0 (.A(N_171), .B(
        N_94_i_0), .C(CoreAHBLite_0_AHBmslave4_HREADY), .D(
        masterAddrClockEnable), .Y(d_masterRegAddrSel));
    SLE masterRegAddrSel_inst_1 (.D(d_masterRegAddrSel), .CLK(
        CCC_0_GL0), .EN(VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(masterRegAddrSel));
    CFG2 #( .INIT(4'h2) )  \SADDRSEL_3_0_a2[0]  (.A(N_144), .B(
        HW_Boot_Engine_0_AHB_IF_HADDR_28), .Y(\SADDRSEL[0] ));
    CFG2 #( .INIT(4'h8) )  d_masterRegAddrSel_0_a2_0 (.A(
        masterRegAddrSel), .B(regHTRANS), .Y(N_171));
    SLE \SDATASELInt[4]  (.D(N_761), .CLK(CCC_0_GL0), .EN(
        HREADY_M_iv_i_0_d), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        m0s4DataSel));
    CFG4 #( .INIT(16'h7340) )  regHTRANS_RNIJ4UD2 (.A(N_39_mux), .B(
        N_761), .C(CoreAHBLite_0_AHBmslave4_HREADY), .D(N_6_0), .Y(
        N_43_mux));
    CFG4 #( .INIT(16'h0080) )  masterAddrClockEnable_0_a2_1 (.A(
        N_39_mux), .B(masterDataInProg[0]), .C(
        CoreAHBLite_0_AHBmslave4_HREADY), .D(N_95), .Y(N_141));
    CFG4 #( .INIT(16'h1000) )  masterAddrClockEnable_0_a2_0_1 (.A(
        m0s4DataSel), .B(N_91), .C(HW_Boot_Engine_0_AHB_IF_HADDR_28), 
        .D(N_144), .Y(masterAddrClockEnable_0_a2_0_1_net_1));
    CFG4 #( .INIT(16'hCECC) )  HREADY_M_pre25_0_o2_RNIKEI91 (.A(
        masterDataInProg[0]), .B(HREADY_M_iv_i_0_0), .C(N_95), .D(
        CoreAHBLite_0_AHBmslave4_HREADY), .Y(HREADY_M_iv_i_0));
    CFG4 #( .INIT(16'hE000) )  masterAddrClockEnable_0_a2 (.A(N_141), 
        .B(N_142), .C(HW_Boot_Engine_0_AHB_IF_HADDR_28), .D(N_144), .Y(
        N_138));
    CFG3 #( .INIT(8'h01) )  m8 (.A(arbRegSMCurrentState_13), .B(
        arbRegSMCurrentState_1), .C(arbRegSMCurrentState_0), .Y(
        N_39_mux));
    CFG2 #( .INIT(4'hB) )  HREADY_M_pre25_0_o2 (.A(N_91), .B(
        m0s4DataSel), .Y(N_95));
    SLE \SDATASELInt[0]  (.D(\SADDRSEL[0] ), .CLK(CCC_0_GL0), .EN(
        HREADY_M_iv_i_0_d), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(N_91));
    CFG4 #( .INIT(16'hFFE0) )  regHTRANS_RNIAO7S1 (.A(
        arbRegSMCurrentState_1), .B(arbRegSMCurrentState_13), .C(N_761)
        , .D(arbRegSMCurrentState_0), .Y(N_94_i_0));
    CFG4 #( .INIT(16'hEC20) )  regHTRANS_RNIMTCJ1 (.A(
        HW_Boot_Engine_0_AHB_IF_HADDR_28), .B(masterRegAddrSel), .C(
        HW_Boot_Engine_0_AHB_IF_HTRANS[1]), .D(regHTRANS), .Y(N_761));
    SLE regHWRITE_inst_1 (.D(HW_Boot_Engine_0_AHB_IF_HWRITE), .CLK(
        CCC_0_GL0), .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHWRITE));
    SLE \regHADDR[3]  (.D(HW_Boot_Engine_0_AHB_IF_HADDR_1), .CLK(
        CCC_0_GL0), .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_1));
    VCC VCC (.Y(VCC_net_1));
    SLE \regHADDR[15]  (.D(HW_Boot_Engine_0_AHB_IF_HADDR_14), .CLK(
        CCC_0_GL0), .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_15));
    CFG4 #( .INIT(16'hFF2A) )  masterAddrClockEnable_0 (.A(
        masterAddrClockEnable_0_a2_0_1_net_1), .B(N_94_i_0), .C(
        CoreAHBLite_0_AHBmslave4_HREADY), .D(N_138), .Y(
        masterAddrClockEnable));
    CFG4 #( .INIT(16'h8C00) )  masterAddrClockEnable_0_a2_2 (.A(
        N_39_mux), .B(defSlaveSMCurrentState), .C(
        CoreAHBLite_0_AHBmslave4_HREADY), .D(N_95), .Y(N_142));
    CFG3 #( .INIT(8'hF8) )  m5 (.A(arbRegSMCurrentState_0), .B(
        CoreAHBLite_0_AHBmslave4_HREADY), .C(arbRegSMCurrentState_1), 
        .Y(N_6_0));
    
endmodule


module COREAHBLITE_MATRIX4X16_1_1_0_16_0_0_0_0s(
       HW_Boot_Engine_0_AHB_IF_HTRANS,
       ahb_fsm_current_state,
       CoreAHBLite_0_AHBmslave4_HTRANS,
       HW_Boot_Engine_0_AHB_IF_HADDR_14,
       HW_Boot_Engine_0_AHB_IF_HADDR_0,
       HW_Boot_Engine_0_AHB_IF_HADDR_1,
       HW_Boot_Engine_0_AHB_IF_HADDR_2,
       HW_Boot_Engine_0_AHB_IF_HADDR_10,
       HW_Boot_Engine_0_AHB_IF_HADDR_28,
       HW_Boot_Engine_0_AHB_IF_HWDATA_18,
       HW_Boot_Engine_0_AHB_IF_HWDATA_7,
       HW_Boot_Engine_0_AHB_IF_HWDATA_6,
       HW_Boot_Engine_0_AHB_IF_HWDATA_5,
       HW_Boot_Engine_0_AHB_IF_HWDATA_4,
       HW_Boot_Engine_0_AHB_IF_HWDATA_3,
       HW_Boot_Engine_0_AHB_IF_HWDATA_2,
       HW_Boot_Engine_0_AHB_IF_HWDATA_1,
       HW_Boot_Engine_0_AHB_IF_HWDATA_0,
       CoreAHBLite_0_AHBmslave4_HWDATA_29,
       CoreAHBLite_0_AHBmslave4_HWDATA_7,
       CoreAHBLite_0_AHBmslave4_HWDATA_6,
       CoreAHBLite_0_AHBmslave4_HWDATA_5,
       CoreAHBLite_0_AHBmslave4_HWDATA_4,
       CoreAHBLite_0_AHBmslave4_HWDATA_3,
       CoreAHBLite_0_AHBmslave4_HWDATA_2,
       CoreAHBLite_0_AHBmslave4_HWDATA_1,
       CoreAHBLite_0_AHBmslave4_HWDATA_0,
       MSS_HPMS_READY,
       CCC_0_GL0,
       HREADY_M_iv_i_0_d,
       HW_Boot_Engine_0_AHB_IF_HWRITE,
       N_94_i_0,
       N_95,
       CoreAHBLite_0_AHBmslave4_HREADY,
       HREADY_M_iv_i_0,
       HREADY_M_iv_i_0_1_0,
       N_52_i_0,
       N_50_i_0,
       N_48_i_0,
       N_46_i_0,
       N_767_i_0,
       N_766_i_0,
       N_765_i_0,
       N_764_i_0
    );
input  [1:1] HW_Boot_Engine_0_AHB_IF_HTRANS;
input  [5:5] ahb_fsm_current_state;
output [1:1] CoreAHBLite_0_AHBmslave4_HTRANS;
input  HW_Boot_Engine_0_AHB_IF_HADDR_14;
input  HW_Boot_Engine_0_AHB_IF_HADDR_0;
input  HW_Boot_Engine_0_AHB_IF_HADDR_1;
input  HW_Boot_Engine_0_AHB_IF_HADDR_2;
input  HW_Boot_Engine_0_AHB_IF_HADDR_10;
input  HW_Boot_Engine_0_AHB_IF_HADDR_28;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_18;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_7;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_6;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_5;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_4;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_3;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_2;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_1;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_0;
output CoreAHBLite_0_AHBmslave4_HWDATA_29;
output CoreAHBLite_0_AHBmslave4_HWDATA_7;
output CoreAHBLite_0_AHBmslave4_HWDATA_6;
output CoreAHBLite_0_AHBmslave4_HWDATA_5;
output CoreAHBLite_0_AHBmslave4_HWDATA_4;
output CoreAHBLite_0_AHBmslave4_HWDATA_3;
output CoreAHBLite_0_AHBmslave4_HWDATA_2;
output CoreAHBLite_0_AHBmslave4_HWDATA_1;
output CoreAHBLite_0_AHBmslave4_HWDATA_0;
input  MSS_HPMS_READY;
input  CCC_0_GL0;
output HREADY_M_iv_i_0_d;
input  HW_Boot_Engine_0_AHB_IF_HWRITE;
output N_94_i_0;
output N_95;
input  CoreAHBLite_0_AHBmslave4_HREADY;
output HREADY_M_iv_i_0;
output HREADY_M_iv_i_0_1_0;
output N_52_i_0;
output N_50_i_0;
output N_48_i_0;
output N_46_i_0;
output N_767_i_0;
output N_766_i_0;
output N_765_i_0;
output N_764_i_0;

    wire \regHADDR[17] , \regHADDR[2] , \regHADDR[3] , \regHADDR[4] , 
        \regHADDR[12] , \arbRegSMCurrentState[1] , 
        \arbRegSMCurrentState[13] , \arbRegSMCurrentState[0] , 
        \masterDataInProg[0] , N_91, m0s4DataSel, N_761, regHWRITE, 
        regHTRANS, masterRegAddrSel, N_144, N_171, 
        defSlaveSMCurrentState, N_43_mux, GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    COREAHBLITE_SLAVESTAGE_0s_0_0_0 slavestage_4 (.masterDataInProg({
        \masterDataInProg[0] }), .CoreAHBLite_0_AHBmslave4_HTRANS({
        CoreAHBLite_0_AHBmslave4_HTRANS[1]}), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_18(
        HW_Boot_Engine_0_AHB_IF_HWDATA_18), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_7(
        HW_Boot_Engine_0_AHB_IF_HWDATA_7), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_6(
        HW_Boot_Engine_0_AHB_IF_HWDATA_6), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_5(
        HW_Boot_Engine_0_AHB_IF_HWDATA_5), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_4(
        HW_Boot_Engine_0_AHB_IF_HWDATA_4), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_3(
        HW_Boot_Engine_0_AHB_IF_HWDATA_3), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_2(
        HW_Boot_Engine_0_AHB_IF_HWDATA_2), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_1(
        HW_Boot_Engine_0_AHB_IF_HWDATA_1), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_0(
        HW_Boot_Engine_0_AHB_IF_HWDATA_0), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_29(
        CoreAHBLite_0_AHBmslave4_HWDATA_29), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_7(
        CoreAHBLite_0_AHBmslave4_HWDATA_7), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_6(
        CoreAHBLite_0_AHBmslave4_HWDATA_6), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_5(
        CoreAHBLite_0_AHBmslave4_HWDATA_5), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_4(
        CoreAHBLite_0_AHBmslave4_HWDATA_4), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_3(
        CoreAHBLite_0_AHBmslave4_HWDATA_3), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_2(
        CoreAHBLite_0_AHBmslave4_HWDATA_2), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_1(
        CoreAHBLite_0_AHBmslave4_HWDATA_1), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_0(
        CoreAHBLite_0_AHBmslave4_HWDATA_0), .regHADDR_15(
        \regHADDR[17] ), .regHADDR_10(\regHADDR[12] ), .regHADDR_2(
        \regHADDR[4] ), .regHADDR_1(\regHADDR[3] ), .regHADDR_0(
        \regHADDR[2] ), .HW_Boot_Engine_0_AHB_IF_HADDR_28(
        HW_Boot_Engine_0_AHB_IF_HADDR_28), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_14(
        HW_Boot_Engine_0_AHB_IF_HADDR_14), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_10(
        HW_Boot_Engine_0_AHB_IF_HADDR_10), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_2(
        HW_Boot_Engine_0_AHB_IF_HADDR_2), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_1(
        HW_Boot_Engine_0_AHB_IF_HADDR_1), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_0(
        HW_Boot_Engine_0_AHB_IF_HADDR_0), .arbRegSMCurrentState_0(
        \arbRegSMCurrentState[0] ), .arbRegSMCurrentState_1(
        \arbRegSMCurrentState[1] ), .arbRegSMCurrentState_13(
        \arbRegSMCurrentState[13] ), .MSS_HPMS_READY(MSS_HPMS_READY), 
        .CCC_0_GL0(CCC_0_GL0), .N_94_i_0(N_94_i_0), 
        .CoreAHBLite_0_AHBmslave4_HREADY(
        CoreAHBLite_0_AHBmslave4_HREADY), .m0s4DataSel(m0s4DataSel), 
        .N_91(N_91), .defSlaveSMCurrentState(defSlaveSMCurrentState), 
        .N_144(N_144), .N_171(N_171), .masterRegAddrSel(
        masterRegAddrSel), .regHWRITE(regHWRITE), 
        .HW_Boot_Engine_0_AHB_IF_HWRITE(HW_Boot_Engine_0_AHB_IF_HWRITE)
        , .N_52_i_0(N_52_i_0), .regHTRANS(regHTRANS), .N_50_i_0(
        N_50_i_0), .N_48_i_0(N_48_i_0), .N_46_i_0(N_46_i_0), 
        .N_767_i_0(N_767_i_0), .N_766_i_0(N_766_i_0), .N_765_i_0(
        N_765_i_0), .N_764_i_0(N_764_i_0), .N_43_mux(N_43_mux), .N_761(
        N_761));
    GND GND (.Y(GND_net_1));
    COREAHBLITE_MASTERSTAGE_1_1_0_16_0s_0_1_0 masterstage_0 (
        .HW_Boot_Engine_0_AHB_IF_HTRANS({
        HW_Boot_Engine_0_AHB_IF_HTRANS[1]}), .masterDataInProg({
        \masterDataInProg[0] }), .ahb_fsm_current_state({
        ahb_fsm_current_state[5]}), .regHADDR_15(\regHADDR[17] ), 
        .regHADDR_0(\regHADDR[2] ), .regHADDR_1(\regHADDR[3] ), 
        .regHADDR_2(\regHADDR[4] ), .regHADDR_10(\regHADDR[12] ), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_14(
        HW_Boot_Engine_0_AHB_IF_HADDR_14), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_0(
        HW_Boot_Engine_0_AHB_IF_HADDR_0), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_1(
        HW_Boot_Engine_0_AHB_IF_HADDR_1), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_2(
        HW_Boot_Engine_0_AHB_IF_HADDR_2), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_10(
        HW_Boot_Engine_0_AHB_IF_HADDR_10), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_28(
        HW_Boot_Engine_0_AHB_IF_HADDR_28), .arbRegSMCurrentState_1(
        \arbRegSMCurrentState[1] ), .arbRegSMCurrentState_13(
        \arbRegSMCurrentState[13] ), .arbRegSMCurrentState_0(
        \arbRegSMCurrentState[0] ), .N_91(N_91), .MSS_HPMS_READY(
        MSS_HPMS_READY), .CCC_0_GL0(CCC_0_GL0), .HREADY_M_iv_i_0_d(
        HREADY_M_iv_i_0_d), .m0s4DataSel(m0s4DataSel), .N_761(N_761), 
        .regHWRITE(regHWRITE), .HW_Boot_Engine_0_AHB_IF_HWRITE(
        HW_Boot_Engine_0_AHB_IF_HWRITE), .regHTRANS(regHTRANS), 
        .masterRegAddrSel(masterRegAddrSel), .N_94_i_0(N_94_i_0), 
        .N_144(N_144), .N_95(N_95), .N_171(N_171), 
        .CoreAHBLite_0_AHBmslave4_HREADY(
        CoreAHBLite_0_AHBmslave4_HREADY), .HREADY_M_iv_i_0(
        HREADY_M_iv_i_0), .defSlaveSMCurrentState(
        defSlaveSMCurrentState), .N_43_mux(N_43_mux), 
        .HREADY_M_iv_i_0_1_0(HREADY_M_iv_i_0_1_0));
    
endmodule


module CoreAHBLite_Z4(
       HW_Boot_Engine_0_AHB_IF_HTRANS,
       ahb_fsm_current_state,
       CoreAHBLite_0_AHBmslave4_HTRANS,
       HW_Boot_Engine_0_AHB_IF_HADDR_14,
       HW_Boot_Engine_0_AHB_IF_HADDR_0,
       HW_Boot_Engine_0_AHB_IF_HADDR_1,
       HW_Boot_Engine_0_AHB_IF_HADDR_2,
       HW_Boot_Engine_0_AHB_IF_HADDR_10,
       HW_Boot_Engine_0_AHB_IF_HADDR_28,
       HW_Boot_Engine_0_AHB_IF_HWDATA_18,
       HW_Boot_Engine_0_AHB_IF_HWDATA_7,
       HW_Boot_Engine_0_AHB_IF_HWDATA_6,
       HW_Boot_Engine_0_AHB_IF_HWDATA_5,
       HW_Boot_Engine_0_AHB_IF_HWDATA_4,
       HW_Boot_Engine_0_AHB_IF_HWDATA_3,
       HW_Boot_Engine_0_AHB_IF_HWDATA_2,
       HW_Boot_Engine_0_AHB_IF_HWDATA_1,
       HW_Boot_Engine_0_AHB_IF_HWDATA_0,
       CoreAHBLite_0_AHBmslave4_HWDATA_29,
       CoreAHBLite_0_AHBmslave4_HWDATA_7,
       CoreAHBLite_0_AHBmslave4_HWDATA_6,
       CoreAHBLite_0_AHBmslave4_HWDATA_5,
       CoreAHBLite_0_AHBmslave4_HWDATA_4,
       CoreAHBLite_0_AHBmslave4_HWDATA_3,
       CoreAHBLite_0_AHBmslave4_HWDATA_2,
       CoreAHBLite_0_AHBmslave4_HWDATA_1,
       CoreAHBLite_0_AHBmslave4_HWDATA_0,
       MSS_HPMS_READY,
       CCC_0_GL0,
       HREADY_M_iv_i_0_d,
       HW_Boot_Engine_0_AHB_IF_HWRITE,
       N_94_i_0,
       N_95,
       CoreAHBLite_0_AHBmslave4_HREADY,
       HREADY_M_iv_i_0,
       HREADY_M_iv_i_0_1_0,
       N_52_i_0,
       N_50_i_0,
       N_48_i_0,
       N_46_i_0,
       N_767_i_0,
       N_766_i_0,
       N_765_i_0,
       N_764_i_0
    );
input  [1:1] HW_Boot_Engine_0_AHB_IF_HTRANS;
input  [5:5] ahb_fsm_current_state;
output [1:1] CoreAHBLite_0_AHBmslave4_HTRANS;
input  HW_Boot_Engine_0_AHB_IF_HADDR_14;
input  HW_Boot_Engine_0_AHB_IF_HADDR_0;
input  HW_Boot_Engine_0_AHB_IF_HADDR_1;
input  HW_Boot_Engine_0_AHB_IF_HADDR_2;
input  HW_Boot_Engine_0_AHB_IF_HADDR_10;
input  HW_Boot_Engine_0_AHB_IF_HADDR_28;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_18;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_7;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_6;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_5;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_4;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_3;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_2;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_1;
input  HW_Boot_Engine_0_AHB_IF_HWDATA_0;
output CoreAHBLite_0_AHBmslave4_HWDATA_29;
output CoreAHBLite_0_AHBmslave4_HWDATA_7;
output CoreAHBLite_0_AHBmslave4_HWDATA_6;
output CoreAHBLite_0_AHBmslave4_HWDATA_5;
output CoreAHBLite_0_AHBmslave4_HWDATA_4;
output CoreAHBLite_0_AHBmslave4_HWDATA_3;
output CoreAHBLite_0_AHBmslave4_HWDATA_2;
output CoreAHBLite_0_AHBmslave4_HWDATA_1;
output CoreAHBLite_0_AHBmslave4_HWDATA_0;
input  MSS_HPMS_READY;
input  CCC_0_GL0;
output HREADY_M_iv_i_0_d;
input  HW_Boot_Engine_0_AHB_IF_HWRITE;
output N_94_i_0;
output N_95;
input  CoreAHBLite_0_AHBmslave4_HREADY;
output HREADY_M_iv_i_0;
output HREADY_M_iv_i_0_1_0;
output N_52_i_0;
output N_50_i_0;
output N_48_i_0;
output N_46_i_0;
output N_767_i_0;
output N_766_i_0;
output N_765_i_0;
output N_764_i_0;

    wire GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    COREAHBLITE_MATRIX4X16_1_1_0_16_0_0_0_0s matrix4x16 (
        .HW_Boot_Engine_0_AHB_IF_HTRANS({
        HW_Boot_Engine_0_AHB_IF_HTRANS[1]}), .ahb_fsm_current_state({
        ahb_fsm_current_state[5]}), .CoreAHBLite_0_AHBmslave4_HTRANS({
        CoreAHBLite_0_AHBmslave4_HTRANS[1]}), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_14(
        HW_Boot_Engine_0_AHB_IF_HADDR_14), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_0(
        HW_Boot_Engine_0_AHB_IF_HADDR_0), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_1(
        HW_Boot_Engine_0_AHB_IF_HADDR_1), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_2(
        HW_Boot_Engine_0_AHB_IF_HADDR_2), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_10(
        HW_Boot_Engine_0_AHB_IF_HADDR_10), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_28(
        HW_Boot_Engine_0_AHB_IF_HADDR_28), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_18(
        HW_Boot_Engine_0_AHB_IF_HWDATA_18), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_7(
        HW_Boot_Engine_0_AHB_IF_HWDATA_7), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_6(
        HW_Boot_Engine_0_AHB_IF_HWDATA_6), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_5(
        HW_Boot_Engine_0_AHB_IF_HWDATA_5), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_4(
        HW_Boot_Engine_0_AHB_IF_HWDATA_4), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_3(
        HW_Boot_Engine_0_AHB_IF_HWDATA_3), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_2(
        HW_Boot_Engine_0_AHB_IF_HWDATA_2), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_1(
        HW_Boot_Engine_0_AHB_IF_HWDATA_1), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_0(
        HW_Boot_Engine_0_AHB_IF_HWDATA_0), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_29(
        CoreAHBLite_0_AHBmslave4_HWDATA_29), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_7(
        CoreAHBLite_0_AHBmslave4_HWDATA_7), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_6(
        CoreAHBLite_0_AHBmslave4_HWDATA_6), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_5(
        CoreAHBLite_0_AHBmslave4_HWDATA_5), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_4(
        CoreAHBLite_0_AHBmslave4_HWDATA_4), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_3(
        CoreAHBLite_0_AHBmslave4_HWDATA_3), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_2(
        CoreAHBLite_0_AHBmslave4_HWDATA_2), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_1(
        CoreAHBLite_0_AHBmslave4_HWDATA_1), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_0(
        CoreAHBLite_0_AHBmslave4_HWDATA_0), .MSS_HPMS_READY(
        MSS_HPMS_READY), .CCC_0_GL0(CCC_0_GL0), .HREADY_M_iv_i_0_d(
        HREADY_M_iv_i_0_d), .HW_Boot_Engine_0_AHB_IF_HWRITE(
        HW_Boot_Engine_0_AHB_IF_HWRITE), .N_94_i_0(N_94_i_0), .N_95(
        N_95), .CoreAHBLite_0_AHBmslave4_HREADY(
        CoreAHBLite_0_AHBmslave4_HREADY), .HREADY_M_iv_i_0(
        HREADY_M_iv_i_0), .HREADY_M_iv_i_0_1_0(HREADY_M_iv_i_0_1_0), 
        .N_52_i_0(N_52_i_0), .N_50_i_0(N_50_i_0), .N_48_i_0(N_48_i_0), 
        .N_46_i_0(N_46_i_0), .N_767_i_0(N_767_i_0), .N_766_i_0(
        N_766_i_0), .N_765_i_0(N_765_i_0), .N_764_i_0(N_764_i_0));
    GND GND (.Y(GND_net_1));
    
endmodule


module CoreConfigP_Z5(
       CORECONFIGP_0_MDDR_APBmslave_PADDR,
       CORECONFIGP_0_MDDR_APBmslave_PWDATA,
       HW_Boot_Engine_0_APB_IF_PWDATA,
       HW_Boot_Engine_0_APB_IF_PADDR_0,
       HW_Boot_Engine_0_APB_IF_PADDR_1,
       HW_Boot_Engine_0_APB_IF_PADDR_2,
       HW_Boot_Engine_0_APB_IF_PADDR_3,
       HW_Boot_Engine_0_APB_IF_PADDR_4,
       HW_Boot_Engine_0_APB_IF_PADDR_5,
       HW_Boot_Engine_0_APB_IF_PADDR_6,
       HW_Boot_Engine_0_APB_IF_PADDR_7,
       HW_Boot_Engine_0_APB_IF_PADDR_8,
       HW_Boot_Engine_0_APB_IF_PADDR_10,
       HW_Boot_Engine_0_APB_IF_PADDR_11,
       HW_Boot_Engine_0_APB_IF_PADDR_13,
       MSS_HPMS_READY,
       CORECONFIGP_0_APB_S_PCLK,
       HW_Boot_Engine_0_APB_IF_PREADY,
       CORECONFIGP_0_MDDR_APBmslave_PWRITE,
       HW_Boot_Engine_0_APB_IF_PWRITE,
       CORECONFIGP_0_APB_S_PCLK_i_0,
       CORECONFIGP_0_MDDR_APBmslave_PENABLE,
       HW_Boot_Engine_0_APB_IF_PSELx,
       HW_Boot_Engine_0_APB_IF_PENABLE,
       N_4,
       CORECONFIGP_0_MDDR_APBmslave_PREADY
    );
output [10:2] CORECONFIGP_0_MDDR_APBmslave_PADDR;
output [15:0] CORECONFIGP_0_MDDR_APBmslave_PWDATA;
input  [15:0] HW_Boot_Engine_0_APB_IF_PWDATA;
input  HW_Boot_Engine_0_APB_IF_PADDR_0;
input  HW_Boot_Engine_0_APB_IF_PADDR_1;
input  HW_Boot_Engine_0_APB_IF_PADDR_2;
input  HW_Boot_Engine_0_APB_IF_PADDR_3;
input  HW_Boot_Engine_0_APB_IF_PADDR_4;
input  HW_Boot_Engine_0_APB_IF_PADDR_5;
input  HW_Boot_Engine_0_APB_IF_PADDR_6;
input  HW_Boot_Engine_0_APB_IF_PADDR_7;
input  HW_Boot_Engine_0_APB_IF_PADDR_8;
input  HW_Boot_Engine_0_APB_IF_PADDR_10;
input  HW_Boot_Engine_0_APB_IF_PADDR_11;
input  HW_Boot_Engine_0_APB_IF_PADDR_13;
input  MSS_HPMS_READY;
input  CORECONFIGP_0_APB_S_PCLK;
output HW_Boot_Engine_0_APB_IF_PREADY;
output CORECONFIGP_0_MDDR_APBmslave_PWRITE;
input  HW_Boot_Engine_0_APB_IF_PWRITE;
input  CORECONFIGP_0_APB_S_PCLK_i_0;
output CORECONFIGP_0_MDDR_APBmslave_PENABLE;
input  HW_Boot_Engine_0_APB_IF_PSELx;
input  HW_Boot_Engine_0_APB_IF_PENABLE;
output N_4;
input  CORECONFIGP_0_MDDR_APBmslave_PREADY;

    wire VCC_net_1, state_187_d, GND_net_1, \paddr[12]_net_1 , 
        \paddr[13]_net_1 , \paddr[15]_net_1 , 
        FIC_2_APB_M_PREADY_ldmx_net_1, N_771_i_0, \state[0]_net_1 , 
        \state_ns[0] , \state[1]_net_1 , \state_ns[1] , psel_net_1, 
        state_187_d_i_0, N_769_i_0, N_770;
    
    SLE \pwdata[15]  (.D(HW_Boot_Engine_0_APB_IF_PWDATA[15]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[15]));
    SLE \pwdata[8]  (.D(HW_Boot_Engine_0_APB_IF_PWDATA[8]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[8]));
    SLE \pwdata[3]  (.D(HW_Boot_Engine_0_APB_IF_PWDATA[3]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[3]));
    CFG4 #( .INIT(16'h0004) )  MDDR_PENABLE_RNO (.A(\paddr[12]_net_1 ), 
        .B(\state[1]_net_1 ), .C(\paddr[15]_net_1 ), .D(
        \paddr[13]_net_1 ), .Y(N_769_i_0));
    SLE \paddr[8]  (.D(HW_Boot_Engine_0_APB_IF_PADDR_6), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[8]));
    CFG4 #( .INIT(16'h0004) )  MDDR_PSEL_i (.A(\paddr[12]_net_1 ), .B(
        psel_net_1), .C(\paddr[15]_net_1 ), .D(\paddr[13]_net_1 ), .Y(
        N_4));
    SLE \pwdata[5]  (.D(HW_Boot_Engine_0_APB_IF_PWDATA[5]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[5]));
    CFG4 #( .INIT(16'hCECC) )  \state_ns_0_0[1]  (.A(\state[1]_net_1 ), 
        .B(\state[0]_net_1 ), .C(CORECONFIGP_0_MDDR_APBmslave_PREADY), 
        .D(N_4), .Y(\state_ns[1] ));
    SLE \paddr[5]  (.D(HW_Boot_Engine_0_APB_IF_PADDR_3), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[5]));
    CFG2 #( .INIT(4'h1) )  state_s0_0_a2_0_a3 (.A(\state[1]_net_1 ), 
        .B(\state[0]_net_1 ), .Y(state_187_d));
    SLE \paddr[3]  (.D(HW_Boot_Engine_0_APB_IF_PADDR_1), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[3]));
    SLE \pwdata[9]  (.D(HW_Boot_Engine_0_APB_IF_PWDATA[9]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[9]));
    SLE FIC_2_APB_M_PREADY (.D(FIC_2_APB_M_PREADY_ldmx_net_1), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_771_i_0), .ALn(MSS_HPMS_READY)
        , .ADn(GND_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(HW_Boot_Engine_0_APB_IF_PREADY));
    SLE \pwdata[7]  (.D(HW_Boot_Engine_0_APB_IF_PWDATA[7]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[7]));
    VCC VCC (.Y(VCC_net_1));
    SLE \pwdata[1]  (.D(HW_Boot_Engine_0_APB_IF_PWDATA[1]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[1]));
    SLE \pwdata[13]  (.D(HW_Boot_Engine_0_APB_IF_PWDATA[13]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[13]));
    SLE psel (.D(state_187_d_i_0), .CLK(CORECONFIGP_0_APB_S_PCLK_i_0), 
        .EN(VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(psel_net_1));
    SLE pwrite (.D(HW_Boot_Engine_0_APB_IF_PWRITE), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWRITE));
    SLE \pwdata[6]  (.D(HW_Boot_Engine_0_APB_IF_PWDATA[6]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[6]));
    SLE \paddr[12]  (.D(HW_Boot_Engine_0_APB_IF_PADDR_10), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\paddr[12]_net_1 ));
    CFG3 #( .INIT(8'hBF) )  FIC_2_APB_M_PREADY_RNO (.A(
        CORECONFIGP_0_MDDR_APBmslave_PREADY), .B(\state[1]_net_1 ), .C(
        N_4), .Y(N_771_i_0));
    SLE \paddr[13]  (.D(HW_Boot_Engine_0_APB_IF_PADDR_11), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\paddr[13]_net_1 ));
    SLE \pwdata[2]  (.D(HW_Boot_Engine_0_APB_IF_PWDATA[2]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[2]));
    CFG3 #( .INIT(8'hFD) )  
        un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_o3 (.A(
        HW_Boot_Engine_0_APB_IF_PSELx), .B(
        HW_Boot_Engine_0_APB_IF_PENABLE), .C(\state[0]_net_1 ), .Y(
        N_770));
    SLE \paddr[7]  (.D(HW_Boot_Engine_0_APB_IF_PADDR_5), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[7]));
    SLE \paddr[6]  (.D(HW_Boot_Engine_0_APB_IF_PADDR_4), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[6]));
    SLE \pwdata[11]  (.D(HW_Boot_Engine_0_APB_IF_PWDATA[11]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[11]));
    GND GND (.Y(GND_net_1));
    SLE \state[0]  (.D(\state_ns[0] ), .CLK(CORECONFIGP_0_APB_S_PCLK), 
        .EN(VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \state[0]_net_1 ));
    SLE \pwdata[14]  (.D(HW_Boot_Engine_0_APB_IF_PWDATA[14]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[14]));
    SLE MDDR_PENABLE (.D(N_769_i_0), .CLK(CORECONFIGP_0_APB_S_PCLK_i_0)
        , .EN(VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PENABLE));
    SLE \pwdata[10]  (.D(HW_Boot_Engine_0_APB_IF_PWDATA[10]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[10]));
    SLE \state[1]  (.D(\state_ns[1] ), .CLK(CORECONFIGP_0_APB_S_PCLK), 
        .EN(VCC_net_1), .ALn(MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \state[1]_net_1 ));
    CFG2 #( .INIT(4'hE) )  state_s0_0_a2_0_a3_i (.A(\state[1]_net_1 ), 
        .B(\state[0]_net_1 ), .Y(state_187_d_i_0));
    SLE \paddr[4]  (.D(HW_Boot_Engine_0_APB_IF_PADDR_2), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[4]));
    SLE \pwdata[12]  (.D(HW_Boot_Engine_0_APB_IF_PWDATA[12]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[12]));
    SLE \paddr[9]  (.D(HW_Boot_Engine_0_APB_IF_PADDR_7), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[9]));
    SLE \pwdata[0]  (.D(HW_Boot_Engine_0_APB_IF_PWDATA[0]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[0]));
    SLE \pwdata[4]  (.D(HW_Boot_Engine_0_APB_IF_PWDATA[4]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[4]));
    CFG3 #( .INIT(8'hEA) )  FIC_2_APB_M_PREADY_ldmx (.A(
        \state[1]_net_1 ), .B(N_770), .C(
        HW_Boot_Engine_0_APB_IF_PREADY), .Y(
        FIC_2_APB_M_PREADY_ldmx_net_1));
    SLE \paddr[2]  (.D(HW_Boot_Engine_0_APB_IF_PADDR_0), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[2]));
    SLE \paddr[10]  (.D(HW_Boot_Engine_0_APB_IF_PADDR_8), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[10]));
    CFG2 #( .INIT(4'h1) )  
        un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_a3_0_a3 (.A(N_770), .B(
        \state[1]_net_1 ), .Y(\state_ns[0] ));
    SLE \paddr[15]  (.D(HW_Boot_Engine_0_APB_IF_PADDR_13), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_187_d), .ALn(
        MSS_HPMS_READY), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\paddr[15]_net_1 ));
    
endmodule


module CodeShadowing_Fabric_CCC_0_FCCC(
       CCC_0_GL0,
       MSS_DDR_FIC_SUBSYSTEM_LOCK,
       FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
    );
output CCC_0_GL0;
output MSS_DDR_FIC_SUBSYSTEM_LOCK;
input  FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC;

    wire GL0_net, VCC_net_1, GND_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    CLKINT GL0_INST (.A(GL0_net), .Y(CCC_0_GL0));
    CCC #( .INIT(210'h0000007FA8000044964000318C6318C1F18C61EC0404040400F04)
        , .VCOFREQUENCY(640.0) )  CCC_INST (.Y0(), .Y1(), .Y2(), .Y3(), 
        .PRDATA({nc0, nc1, nc2, nc3, nc4, nc5, nc6, nc7}), .LOCK(
        MSS_DDR_FIC_SUBSYSTEM_LOCK), .BUSY(), .CLK0(VCC_net_1), .CLK1(
        VCC_net_1), .CLK2(VCC_net_1), .CLK3(VCC_net_1), .NGMUX0_SEL(
        GND_net_1), .NGMUX1_SEL(GND_net_1), .NGMUX2_SEL(GND_net_1), 
        .NGMUX3_SEL(GND_net_1), .NGMUX0_HOLD_N(VCC_net_1), 
        .NGMUX1_HOLD_N(VCC_net_1), .NGMUX2_HOLD_N(VCC_net_1), 
        .NGMUX3_HOLD_N(VCC_net_1), .NGMUX0_ARST_N(VCC_net_1), 
        .NGMUX1_ARST_N(VCC_net_1), .NGMUX2_ARST_N(VCC_net_1), 
        .NGMUX3_ARST_N(VCC_net_1), .PLL_BYPASS_N(VCC_net_1), 
        .PLL_ARST_N(VCC_net_1), .PLL_POWERDOWN_N(VCC_net_1), 
        .GPD0_ARST_N(VCC_net_1), .GPD1_ARST_N(VCC_net_1), .GPD2_ARST_N(
        VCC_net_1), .GPD3_ARST_N(VCC_net_1), .PRESET_N(GND_net_1), 
        .PCLK(VCC_net_1), .PSEL(VCC_net_1), .PENABLE(VCC_net_1), 
        .PWRITE(VCC_net_1), .PADDR({VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1}), .PWDATA({VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1}), .CLK0_PAD(GND_net_1), .CLK1_PAD(
        GND_net_1), .CLK2_PAD(GND_net_1), .CLK3_PAD(GND_net_1), .GL0(
        GL0_net), .GL1(), .GL2(), .GL3(), .RCOSC_25_50MHZ(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC), 
        .RCOSC_1MHZ(GND_net_1), .XTLOSC(GND_net_1));
    
endmodule


module CodeShadowing_Fabric_MSS(
       MDDR_DQS,
       MDDR_DQ,
       MDDR_DM_RDQS,
       MDDR_BA,
       MDDR_ADDR,
       CoreAHBLite_0_AHBmslave4_HTRANS,
       HW_Boot_Engine_0_AXI_IF_AWADDR,
       HW_Boot_Engine_0_AXI_IF_AWSIZE,
       HW_Boot_Engine_0_AXI_IF_WDATA,
       CORECONFIGP_0_MDDR_APBmslave_PADDR,
       CORECONFIGP_0_MDDR_APBmslave_PWDATA,
       CoreAHBLite_0_AHBmslave4_HRDATA_0,
       CoreAHBLite_0_AHBmslave4_HRDATA_1,
       CoreAHBLite_0_AHBmslave4_HRDATA_2,
       CoreAHBLite_0_AHBmslave4_HRDATA_3,
       CoreAHBLite_0_AHBmslave4_HRDATA_4,
       CoreAHBLite_0_AHBmslave4_HRDATA_5,
       CoreAHBLite_0_AHBmslave4_HRDATA_6,
       CoreAHBLite_0_AHBmslave4_HRDATA_7,
       CoreAHBLite_0_AHBmslave4_HRDATA_8,
       CoreAHBLite_0_AHBmslave4_HWDATA_0,
       CoreAHBLite_0_AHBmslave4_HWDATA_1,
       CoreAHBLite_0_AHBmslave4_HWDATA_2,
       CoreAHBLite_0_AHBmslave4_HWDATA_3,
       CoreAHBLite_0_AHBmslave4_HWDATA_4,
       CoreAHBLite_0_AHBmslave4_HWDATA_5,
       CoreAHBLite_0_AHBmslave4_HWDATA_6,
       CoreAHBLite_0_AHBmslave4_HWDATA_7,
       CoreAHBLite_0_AHBmslave4_HWDATA_29,
       CORECONFIGP_0_APB_S_PCLK,
       CORECONFIGP_0_APB_S_PCLK_i_0,
       SPI_0_SS0,
       SPI_0_DO,
       SPI_0_DI,
       SPI_0_CLK,
       MMUART_1_TXD,
       MMUART_1_RXD,
       MDDR_WE_N,
       MDDR_RESET_N,
       MDDR_RAS_N,
       MDDR_ODT,
       MDDR_DQS_TMATCH_0_OUT,
       MDDR_DQS_TMATCH_0_IN,
       MDDR_CS_N,
       MDDR_CKE,
       MDDR_CAS_N,
       GPIO_3_M2F_c,
       GPIO_4_M2F_c,
       GPIO_2_M2F_c,
       FIC_2_APB_M_PRESET_N,
       CoreAHBLite_0_AHBmslave4_HREADY,
       MSS_RESET_N_M2F,
       GPIO_1_M2F_c,
       GPIO_0_M2F_c,
       GPIO_8_M2F_c,
       GPIO_9_M2F_c,
       GPIO_10_M2F_c,
       HW_Boot_Engine_0_AXI_IF_AWREADY,
       HW_Boot_Engine_0_AXI_IF_BVALID,
       HW_Boot_Engine_0_AXI_IF_WREADY,
       CORECONFIGP_0_MDDR_APBmslave_PREADY,
       N_764_i_0,
       N_765_i_0,
       N_766_i_0,
       N_767_i_0,
       N_46_i_0,
       N_48_i_0,
       N_94_i_0,
       N_50_i_0,
       N_52_i_0,
       GPIO_0_M2F_0,
       MSS_DDR_FIC_SUBSYSTEM_LOCK,
       GPIO_11_F2M_c,
       GPIO_12_F2M_c,
       CCC_0_GL0,
       HW_Boot_Engine_0_AXI_IF_AWVALID,
       HW_Boot_Engine_0_AXI_IF_BREADY,
       HW_Boot_Engine_0_AXI_IF_WLAST,
       CORECONFIGP_0_MDDR_APBmslave_PENABLE,
       N_4,
       CORECONFIGP_0_MDDR_APBmslave_PWRITE,
       MSS_HPMS_READY,
       MDDR_CLK_N,
       MDDR_CLK
    );
inout  [1:0] MDDR_DQS;
inout  [15:0] MDDR_DQ;
inout  [1:0] MDDR_DM_RDQS;
output [2:0] MDDR_BA;
output [15:0] MDDR_ADDR;
input  [1:1] CoreAHBLite_0_AHBmslave4_HTRANS;
input  [31:0] HW_Boot_Engine_0_AXI_IF_AWADDR;
input  [0:0] HW_Boot_Engine_0_AXI_IF_AWSIZE;
input  [63:0] HW_Boot_Engine_0_AXI_IF_WDATA;
input  [10:2] CORECONFIGP_0_MDDR_APBmslave_PADDR;
input  [15:0] CORECONFIGP_0_MDDR_APBmslave_PWDATA;
output CoreAHBLite_0_AHBmslave4_HRDATA_0;
output CoreAHBLite_0_AHBmslave4_HRDATA_1;
output CoreAHBLite_0_AHBmslave4_HRDATA_2;
output CoreAHBLite_0_AHBmslave4_HRDATA_3;
output CoreAHBLite_0_AHBmslave4_HRDATA_4;
output CoreAHBLite_0_AHBmslave4_HRDATA_5;
output CoreAHBLite_0_AHBmslave4_HRDATA_6;
output CoreAHBLite_0_AHBmslave4_HRDATA_7;
output CoreAHBLite_0_AHBmslave4_HRDATA_8;
input  CoreAHBLite_0_AHBmslave4_HWDATA_0;
input  CoreAHBLite_0_AHBmslave4_HWDATA_1;
input  CoreAHBLite_0_AHBmslave4_HWDATA_2;
input  CoreAHBLite_0_AHBmslave4_HWDATA_3;
input  CoreAHBLite_0_AHBmslave4_HWDATA_4;
input  CoreAHBLite_0_AHBmslave4_HWDATA_5;
input  CoreAHBLite_0_AHBmslave4_HWDATA_6;
input  CoreAHBLite_0_AHBmslave4_HWDATA_7;
input  CoreAHBLite_0_AHBmslave4_HWDATA_29;
output CORECONFIGP_0_APB_S_PCLK;
output CORECONFIGP_0_APB_S_PCLK_i_0;
inout  SPI_0_SS0;
output SPI_0_DO;
input  SPI_0_DI;
inout  SPI_0_CLK;
output MMUART_1_TXD;
input  MMUART_1_RXD;
output MDDR_WE_N;
output MDDR_RESET_N;
output MDDR_RAS_N;
output MDDR_ODT;
output MDDR_DQS_TMATCH_0_OUT;
input  MDDR_DQS_TMATCH_0_IN;
output MDDR_CS_N;
output MDDR_CKE;
output MDDR_CAS_N;
output GPIO_3_M2F_c;
output GPIO_4_M2F_c;
output GPIO_2_M2F_c;
output FIC_2_APB_M_PRESET_N;
inout  CoreAHBLite_0_AHBmslave4_HREADY;
output MSS_RESET_N_M2F;
output GPIO_1_M2F_c;
output GPIO_0_M2F_c;
output GPIO_8_M2F_c;
output GPIO_9_M2F_c;
output GPIO_10_M2F_c;
output HW_Boot_Engine_0_AXI_IF_AWREADY;
output HW_Boot_Engine_0_AXI_IF_BVALID;
output HW_Boot_Engine_0_AXI_IF_WREADY;
output CORECONFIGP_0_MDDR_APBmslave_PREADY;
input  N_764_i_0;
input  N_765_i_0;
input  N_766_i_0;
input  N_767_i_0;
input  N_46_i_0;
input  N_48_i_0;
input  N_94_i_0;
input  N_50_i_0;
input  N_52_i_0;
input  GPIO_0_M2F_0;
input  MSS_DDR_FIC_SUBSYSTEM_LOCK;
input  GPIO_11_F2M_c;
input  GPIO_12_F2M_c;
input  CCC_0_GL0;
input  HW_Boot_Engine_0_AXI_IF_AWVALID;
input  HW_Boot_Engine_0_AXI_IF_BREADY;
input  HW_Boot_Engine_0_AXI_IF_WLAST;
input  CORECONFIGP_0_MDDR_APBmslave_PENABLE;
input  N_4;
input  CORECONFIGP_0_MDDR_APBmslave_PWRITE;
input  MSS_HPMS_READY;
output MDDR_CLK_N;
output MDDR_CLK;

    wire FIC_2_APB_M_PCLK, SPI_0_SS0_PAD_Y, 
        MSS_ADLIB_INST_SPI0_SS0_USBA_NXT_MGPIO7A_OUT, 
        MSS_ADLIB_INST_SPI0_SS0_USBA_NXT_MGPIO7A_OE, 
        MSS_ADLIB_INST_SPI0_SDO_USBA_STP_MGPIO6A_OUT, 
        MSS_ADLIB_INST_SPI0_SDO_USBA_STP_MGPIO6A_OE, SPI_0_DI_PAD_Y, 
        SPI_0_CLK_PAD_Y, MSS_ADLIB_INST_SPI0_SCK_USBA_XCLK_OUT, 
        MSS_ADLIB_INST_SPI0_SCK_USBA_XCLK_OE, 
        MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT, 
        MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OE, 
        MMUART_1_RXD_PAD_Y, MSS_ADLIB_INST_DRAM_WEN, 
        MSS_ADLIB_INST_DRAM_RSTN, MSS_ADLIB_INST_DRAM_RASN, 
        MSS_ADLIB_INST_DRAM_ODT, \DRAM_FIFO_WE_OUT_net_0[0] , 
        MDDR_DQS_TMATCH_0_IN_PAD_Y, MDDR_DQS_1_PAD_Y, 
        \DRAM_DQS_OUT_net_0[1] , \DRAM_DQS_OE_net_0[1] , 
        MDDR_DQS_0_PAD_Y, \DRAM_DQS_OUT_net_0[0] , 
        \DRAM_DQS_OE_net_0[0] , MDDR_DQ_15_PAD_Y, 
        \DRAM_DQ_OUT_net_0[15] , \DRAM_DQ_OE_net_0[15] , 
        MDDR_DQ_14_PAD_Y, \DRAM_DQ_OUT_net_0[14] , 
        \DRAM_DQ_OE_net_0[14] , MDDR_DQ_13_PAD_Y, 
        \DRAM_DQ_OUT_net_0[13] , \DRAM_DQ_OE_net_0[13] , 
        MDDR_DQ_12_PAD_Y, \DRAM_DQ_OUT_net_0[12] , 
        \DRAM_DQ_OE_net_0[12] , MDDR_DQ_11_PAD_Y, 
        \DRAM_DQ_OUT_net_0[11] , \DRAM_DQ_OE_net_0[11] , 
        MDDR_DQ_10_PAD_Y, \DRAM_DQ_OUT_net_0[10] , 
        \DRAM_DQ_OE_net_0[10] , MDDR_DQ_9_PAD_Y, 
        \DRAM_DQ_OUT_net_0[9] , \DRAM_DQ_OE_net_0[9] , MDDR_DQ_8_PAD_Y, 
        \DRAM_DQ_OUT_net_0[8] , \DRAM_DQ_OE_net_0[8] , MDDR_DQ_7_PAD_Y, 
        \DRAM_DQ_OUT_net_0[7] , \DRAM_DQ_OE_net_0[7] , MDDR_DQ_6_PAD_Y, 
        \DRAM_DQ_OUT_net_0[6] , \DRAM_DQ_OE_net_0[6] , MDDR_DQ_5_PAD_Y, 
        \DRAM_DQ_OUT_net_0[5] , \DRAM_DQ_OE_net_0[5] , MDDR_DQ_4_PAD_Y, 
        \DRAM_DQ_OUT_net_0[4] , \DRAM_DQ_OE_net_0[4] , MDDR_DQ_3_PAD_Y, 
        \DRAM_DQ_OUT_net_0[3] , \DRAM_DQ_OE_net_0[3] , MDDR_DQ_2_PAD_Y, 
        \DRAM_DQ_OUT_net_0[2] , \DRAM_DQ_OE_net_0[2] , MDDR_DQ_1_PAD_Y, 
        \DRAM_DQ_OUT_net_0[1] , \DRAM_DQ_OE_net_0[1] , MDDR_DQ_0_PAD_Y, 
        \DRAM_DQ_OUT_net_0[0] , \DRAM_DQ_OE_net_0[0] , 
        MDDR_DM_RDQS_1_PAD_Y, \DRAM_DM_RDQS_OUT_net_0[1] , 
        \DM_OE_net_0[1] , MDDR_DM_RDQS_0_PAD_Y, 
        \DRAM_DM_RDQS_OUT_net_0[0] , \DM_OE_net_0[0] , 
        MSS_ADLIB_INST_DRAM_CSN, MSS_ADLIB_INST_DRAM_CKE, 
        MSS_ADLIB_INST_DRAM_CASN, \DRAM_BA_net_0[2] , 
        \DRAM_BA_net_0[1] , \DRAM_BA_net_0[0] , \DRAM_ADDR_net_0[15] , 
        \DRAM_ADDR_net_0[14] , \DRAM_ADDR_net_0[13] , 
        \DRAM_ADDR_net_0[12] , \DRAM_ADDR_net_0[11] , 
        \DRAM_ADDR_net_0[10] , \DRAM_ADDR_net_0[9] , 
        \DRAM_ADDR_net_0[8] , \DRAM_ADDR_net_0[7] , 
        \DRAM_ADDR_net_0[6] , \DRAM_ADDR_net_0[5] , 
        \DRAM_ADDR_net_0[4] , \DRAM_ADDR_net_0[3] , 
        \DRAM_ADDR_net_0[2] , \DRAM_ADDR_net_0[1] , 
        \DRAM_ADDR_net_0[0] , VCC_net_1, GND_net_1, 
        MSS_ADLIB_INST_DRAM_CLK;
    
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_6_PAD (.D(
        \DRAM_ADDR_net_0[6] ), .PAD(MDDR_ADDR[6]));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_CAS_N_PAD (.D(
        MSS_ADLIB_INST_DRAM_CASN), .PAD(MDDR_CAS_N));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_RESET_N_PAD (.D(
        MSS_ADLIB_INST_DRAM_RSTN), .PAD(MDDR_RESET_N));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ODT_PAD (.D(
        MSS_ADLIB_INST_DRAM_ODT), .PAD(MDDR_ODT));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_11_PAD (.D(
        \DRAM_ADDR_net_0[11] ), .PAD(MDDR_ADDR[11]));
    TRIBUFF MMUART_1_TXD_PAD (.D(
        MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT), .E(
        MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OE), .PAD(
        MMUART_1_TXD));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_10_PAD (.PAD(MDDR_DQ[10]), .D(
        \DRAM_DQ_OUT_net_0[10] ), .E(\DRAM_DQ_OE_net_0[10] ), .Y(
        MDDR_DQ_10_PAD_Y));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_1_PAD (.PAD(MDDR_DQ[1]), .D(
        \DRAM_DQ_OUT_net_0[1] ), .E(\DRAM_DQ_OE_net_0[1] ), .Y(
        MDDR_DQ_1_PAD_Y));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_7_PAD (.D(
        \DRAM_ADDR_net_0[7] ), .PAD(MDDR_ADDR[7]));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_11_PAD (.PAD(MDDR_DQ[11]), .D(
        \DRAM_DQ_OUT_net_0[11] ), .E(\DRAM_DQ_OE_net_0[11] ), .Y(
        MDDR_DQ_11_PAD_Y));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_9_PAD (.PAD(MDDR_DQ[9]), .D(
        \DRAM_DQ_OUT_net_0[9] ), .E(\DRAM_DQ_OE_net_0[9] ), .Y(
        MDDR_DQ_9_PAD_Y));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_3_PAD (.PAD(MDDR_DQ[3]), .D(
        \DRAM_DQ_OUT_net_0[3] ), .E(\DRAM_DQ_OE_net_0[3] ), .Y(
        MDDR_DQ_3_PAD_Y));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_0_PAD (.PAD(MDDR_DQ[0]), .D(
        \DRAM_DQ_OUT_net_0[0] ), .E(\DRAM_DQ_OE_net_0[0] ), .Y(
        MDDR_DQ_0_PAD_Y));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_12_PAD (.D(
        \DRAM_ADDR_net_0[12] ), .PAD(MDDR_ADDR[12]));
    VCC VCC (.Y(VCC_net_1));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_2_PAD (.PAD(MDDR_DQ[2]), .D(
        \DRAM_DQ_OUT_net_0[2] ), .E(\DRAM_DQ_OE_net_0[2] ), .Y(
        MDDR_DQ_2_PAD_Y));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_12_PAD (.PAD(MDDR_DQ[12]), .D(
        \DRAM_DQ_OUT_net_0[12] ), .E(\DRAM_DQ_OE_net_0[12] ), .Y(
        MDDR_DQ_12_PAD_Y));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_CKE_PAD (.D(
        MSS_ADLIB_INST_DRAM_CKE), .PAD(MDDR_CKE));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_2_PAD (.D(
        \DRAM_ADDR_net_0[2] ), .PAD(MDDR_ADDR[2]));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_13_PAD (.D(
        \DRAM_ADDR_net_0[13] ), .PAD(MDDR_ADDR[13]));
    CFG1 #( .INIT(2'h1) )  FIC_2_APB_M_PCLK_inferred_clock_RNIN4LA_0 (
        .A(CORECONFIGP_0_APB_S_PCLK), .Y(CORECONFIGP_0_APB_S_PCLK_i_0));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_5_PAD (.D(
        \DRAM_ADDR_net_0[5] ), .PAD(MDDR_ADDR[5]));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DM_RDQS_1_PAD (.PAD(
        MDDR_DM_RDQS[1]), .D(\DRAM_DM_RDQS_OUT_net_0[1] ), .E(
        \DM_OE_net_0[1] ), .Y(MDDR_DM_RDQS_1_PAD_Y));
    TRIBUFF SPI_0_DO_PAD (.D(
        MSS_ADLIB_INST_SPI0_SDO_USBA_STP_MGPIO6A_OUT), .E(
        MSS_ADLIB_INST_SPI0_SDO_USBA_STP_MGPIO6A_OE), .PAD(SPI_0_DO));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQS_0_PAD (.PAD(MDDR_DQS[0]), .D(
        \DRAM_DQS_OUT_net_0[0] ), .E(\DRAM_DQS_OE_net_0[0] ), .Y(
        MDDR_DQS_0_PAD_Y));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQS_1_PAD (.PAD(MDDR_DQS[1]), .D(
        \DRAM_DQS_OUT_net_0[1] ), .E(\DRAM_DQS_OE_net_0[1] ), .Y(
        MDDR_DQS_1_PAD_Y));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_15_PAD (.PAD(MDDR_DQ[15]), .D(
        \DRAM_DQ_OUT_net_0[15] ), .E(\DRAM_DQ_OE_net_0[15] ), .Y(
        MDDR_DQ_15_PAD_Y));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DM_RDQS_0_PAD (.PAD(
        MDDR_DM_RDQS[0]), .D(\DRAM_DM_RDQS_OUT_net_0[0] ), .E(
        \DM_OE_net_0[0] ), .Y(MDDR_DM_RDQS_0_PAD_Y));
    GND GND (.Y(GND_net_1));
    INBUF #( .IOSTD("") )  SPI_0_DI_PAD (.PAD(SPI_0_DI), .Y(
        SPI_0_DI_PAD_Y));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_8_PAD (.PAD(MDDR_DQ[8]), .D(
        \DRAM_DQ_OUT_net_0[8] ), .E(\DRAM_DQ_OE_net_0[8] ), .Y(
        MDDR_DQ_8_PAD_Y));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_9_PAD (.D(
        \DRAM_ADDR_net_0[9] ), .PAD(MDDR_ADDR[9]));
    CLKINT FIC_2_APB_M_PCLK_inferred_clock_RNIN4LA (.A(
        FIC_2_APB_M_PCLK), .Y(CORECONFIGP_0_APB_S_PCLK));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_BA_2_PAD (.D(\DRAM_BA_net_0[2] )
        , .PAD(MDDR_BA[2]));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_14_PAD (.D(
        \DRAM_ADDR_net_0[14] ), .PAD(MDDR_ADDR[14]));
    MSS_075 #( .INIT(1438'h00000000000000000000000000000036100080000000000000000000000000000000000000000000000000000000000001203610000000000000000000000000000000000000000F00000000F000000000000000000000000000000007FFFFFFFB000001007C33C0002480060908030C003FFFFE4000000000000400000000F0F11C00000002DF3C010842108421000001FE34001FF8000000400000000000EF1007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
        , .ACT_UBITS(56'hFFFFFFFFFFFFFF), .MEMORYFILE("ENVM_init.mem")
        , .RTC_MAIN_XTL_FREQ(0.0), .RTC_MAIN_XTL_MODE(""), .DDR_CLK_FREQ(160.0)
         )  MSS_ADLIB_INST (.CAN_RXBUS_MGPIO3A_H2F_A(), 
        .CAN_RXBUS_MGPIO3A_H2F_B(GPIO_3_M2F_c), 
        .CAN_TX_EBL_MGPIO4A_H2F_A(), .CAN_TX_EBL_MGPIO4A_H2F_B(
        GPIO_4_M2F_c), .CAN_TXBUS_MGPIO2A_H2F_A(), 
        .CAN_TXBUS_MGPIO2A_H2F_B(GPIO_2_M2F_c), .CLK_CONFIG_APB(
        FIC_2_APB_M_PCLK), .COMMS_INT(), .CONFIG_PRESET_N(
        FIC_2_APB_M_PRESET_N), .EDAC_ERROR({nc0, nc1, nc2, nc3, nc4, 
        nc5, nc6, nc7}), .F_FM0_RDATA({nc8, nc9, nc10, nc11, nc12, 
        nc13, nc14, nc15, nc16, nc17, nc18, nc19, nc20, nc21, nc22, 
        nc23, nc24, nc25, nc26, nc27, nc28, nc29, nc30, 
        CoreAHBLite_0_AHBmslave4_HRDATA_8, 
        CoreAHBLite_0_AHBmslave4_HRDATA_7, 
        CoreAHBLite_0_AHBmslave4_HRDATA_6, 
        CoreAHBLite_0_AHBmslave4_HRDATA_5, 
        CoreAHBLite_0_AHBmslave4_HRDATA_4, 
        CoreAHBLite_0_AHBmslave4_HRDATA_3, 
        CoreAHBLite_0_AHBmslave4_HRDATA_2, 
        CoreAHBLite_0_AHBmslave4_HRDATA_1, 
        CoreAHBLite_0_AHBmslave4_HRDATA_0}), .F_FM0_READYOUT(
        CoreAHBLite_0_AHBmslave4_HREADY), .F_FM0_RESP(), .F_HM0_ADDR({
        nc31, nc32, nc33, nc34, nc35, nc36, nc37, nc38, nc39, nc40, 
        nc41, nc42, nc43, nc44, nc45, nc46, nc47, nc48, nc49, nc50, 
        nc51, nc52, nc53, nc54, nc55, nc56, nc57, nc58, nc59, nc60, 
        nc61, nc62}), .F_HM0_ENABLE(), .F_HM0_SEL(), .F_HM0_SIZE({nc63, 
        nc64}), .F_HM0_TRANS1(), .F_HM0_WDATA({nc65, nc66, nc67, nc68, 
        nc69, nc70, nc71, nc72, nc73, nc74, nc75, nc76, nc77, nc78, 
        nc79, nc80, nc81, nc82, nc83, nc84, nc85, nc86, nc87, nc88, 
        nc89, nc90, nc91, nc92, nc93, nc94, nc95, nc96}), .F_HM0_WRITE(
        ), .FAB_CHRGVBUS(), .FAB_DISCHRGVBUS(), .FAB_DMPULLDOWN(), 
        .FAB_DPPULLDOWN(), .FAB_DRVVBUS(), .FAB_IDPULLUP(), 
        .FAB_OPMODE({nc97, nc98}), .FAB_SUSPENDM(), .FAB_TERMSEL(), 
        .FAB_TXVALID(), .FAB_VCONTROL({nc99, nc100, nc101, nc102}), 
        .FAB_VCONTROLLOADM(), .FAB_XCVRSEL({nc103, nc104}), 
        .FAB_XDATAOUT({nc105, nc106, nc107, nc108, nc109, nc110, nc111, 
        nc112}), .FACC_GLMUX_SEL(), .FIC32_0_MASTER({nc113, nc114}), 
        .FIC32_1_MASTER({nc115, nc116}), .FPGA_RESET_N(MSS_RESET_N_M2F)
        , .GTX_CLK(), .H2F_INTERRUPT({nc117, nc118, nc119, nc120, 
        nc121, nc122, nc123, nc124, nc125, nc126, nc127, nc128, nc129, 
        nc130, nc131, nc132}), .H2F_NMI(), .H2FCALIB(), 
        .I2C0_SCL_MGPIO31B_H2F_A(), .I2C0_SCL_MGPIO31B_H2F_B(), 
        .I2C0_SDA_MGPIO30B_H2F_A(), .I2C0_SDA_MGPIO30B_H2F_B(), 
        .I2C1_SCL_MGPIO1A_H2F_A(), .I2C1_SCL_MGPIO1A_H2F_B(
        GPIO_1_M2F_c), .I2C1_SDA_MGPIO0A_H2F_A(), 
        .I2C1_SDA_MGPIO0A_H2F_B(GPIO_0_M2F_c), .MDCF(), .MDOENF(), 
        .MDOF(), .MMUART0_CTS_MGPIO19B_H2F_A(), 
        .MMUART0_CTS_MGPIO19B_H2F_B(), .MMUART0_DCD_MGPIO22B_H2F_A(), 
        .MMUART0_DCD_MGPIO22B_H2F_B(), .MMUART0_DSR_MGPIO20B_H2F_A(), 
        .MMUART0_DSR_MGPIO20B_H2F_B(), .MMUART0_DTR_MGPIO18B_H2F_A(), 
        .MMUART0_DTR_MGPIO18B_H2F_B(), .MMUART0_RI_MGPIO21B_H2F_A(), 
        .MMUART0_RI_MGPIO21B_H2F_B(), .MMUART0_RTS_MGPIO17B_H2F_A(), 
        .MMUART0_RTS_MGPIO17B_H2F_B(), .MMUART0_RXD_MGPIO28B_H2F_A(), 
        .MMUART0_RXD_MGPIO28B_H2F_B(), .MMUART0_SCK_MGPIO29B_H2F_A(), 
        .MMUART0_SCK_MGPIO29B_H2F_B(), .MMUART0_TXD_MGPIO27B_H2F_A(), 
        .MMUART0_TXD_MGPIO27B_H2F_B(), .MMUART1_DTR_MGPIO12B_H2F_A(), 
        .MMUART1_RTS_MGPIO11B_H2F_A(), .MMUART1_RTS_MGPIO11B_H2F_B(), 
        .MMUART1_RXD_MGPIO26B_H2F_A(), .MMUART1_RXD_MGPIO26B_H2F_B(), 
        .MMUART1_SCK_MGPIO25B_H2F_A(), .MMUART1_SCK_MGPIO25B_H2F_B(), 
        .MMUART1_TXD_MGPIO24B_H2F_A(), .MMUART1_TXD_MGPIO24B_H2F_B(), 
        .MPLL_LOCK(), .PER2_FABRIC_PADDR({nc133, nc134, nc135, nc136, 
        nc137, nc138, nc139, nc140, nc141, nc142, nc143, nc144, nc145, 
        nc146}), .PER2_FABRIC_PENABLE(), .PER2_FABRIC_PSEL(), 
        .PER2_FABRIC_PWDATA({nc147, nc148, nc149, nc150, nc151, nc152, 
        nc153, nc154, nc155, nc156, nc157, nc158, nc159, nc160, nc161, 
        nc162, nc163, nc164, nc165, nc166, nc167, nc168, nc169, nc170, 
        nc171, nc172, nc173, nc174, nc175, nc176, nc177, nc178}), 
        .PER2_FABRIC_PWRITE(), .RTC_MATCH(), .SLEEPDEEP(), 
        .SLEEPHOLDACK(), .SLEEPING(), .SMBALERT_NO0(), .SMBALERT_NO1(), 
        .SMBSUS_NO0(), .SMBSUS_NO1(), .SPI0_CLK_OUT(), 
        .SPI0_SDI_MGPIO5A_H2F_A(), .SPI0_SDI_MGPIO5A_H2F_B(), 
        .SPI0_SDO_MGPIO6A_H2F_A(), .SPI0_SDO_MGPIO6A_H2F_B(), 
        .SPI0_SS0_MGPIO7A_H2F_A(), .SPI0_SS0_MGPIO7A_H2F_B(), 
        .SPI0_SS1_MGPIO8A_H2F_A(), .SPI0_SS1_MGPIO8A_H2F_B(
        GPIO_8_M2F_c), .SPI0_SS2_MGPIO9A_H2F_A(), 
        .SPI0_SS2_MGPIO9A_H2F_B(GPIO_9_M2F_c), 
        .SPI0_SS3_MGPIO10A_H2F_A(), .SPI0_SS3_MGPIO10A_H2F_B(
        GPIO_10_M2F_c), .SPI0_SS4_MGPIO19A_H2F_A(), 
        .SPI0_SS5_MGPIO20A_H2F_A(), .SPI0_SS6_MGPIO21A_H2F_A(), 
        .SPI0_SS7_MGPIO22A_H2F_A(), .SPI1_CLK_OUT(), 
        .SPI1_SDI_MGPIO11A_H2F_A(), .SPI1_SDI_MGPIO11A_H2F_B(), 
        .SPI1_SDO_MGPIO12A_H2F_A(), .SPI1_SDO_MGPIO12A_H2F_B(), 
        .SPI1_SS0_MGPIO13A_H2F_A(), .SPI1_SS0_MGPIO13A_H2F_B(), 
        .SPI1_SS1_MGPIO14A_H2F_A(), .SPI1_SS1_MGPIO14A_H2F_B(), 
        .SPI1_SS2_MGPIO15A_H2F_A(), .SPI1_SS2_MGPIO15A_H2F_B(), 
        .SPI1_SS3_MGPIO16A_H2F_A(), .SPI1_SS3_MGPIO16A_H2F_B(), 
        .SPI1_SS4_MGPIO17A_H2F_A(), .SPI1_SS5_MGPIO18A_H2F_A(), 
        .SPI1_SS6_MGPIO23A_H2F_A(), .SPI1_SS7_MGPIO24A_H2F_A(), .TCGF({
        nc179, nc180, nc181, nc182, nc183, nc184, nc185, nc186, nc187, 
        nc188}), .TRACECLK(), .TRACEDATA({nc189, nc190, nc191, nc192}), 
        .TX_CLK(), .TX_ENF(), .TX_ERRF(), .TXCTL_EN_RIF(), .TXD_RIF({
        nc193, nc194, nc195, nc196}), .TXDF({nc197, nc198, nc199, 
        nc200, nc201, nc202, nc203, nc204}), .TXEV(), .WDOGTIMEOUT(), 
        .F_ARREADY_HREADYOUT1(), .F_AWREADY_HREADYOUT0(
        HW_Boot_Engine_0_AXI_IF_AWREADY), .F_BID({nc205, nc206, nc207, 
        nc208}), .F_BRESP_HRESP0({nc209, nc210}), .F_BVALID(
        HW_Boot_Engine_0_AXI_IF_BVALID), .F_RDATA_HRDATA01({nc211, 
        nc212, nc213, nc214, nc215, nc216, nc217, nc218, nc219, nc220, 
        nc221, nc222, nc223, nc224, nc225, nc226, nc227, nc228, nc229, 
        nc230, nc231, nc232, nc233, nc234, nc235, nc236, nc237, nc238, 
        nc239, nc240, nc241, nc242, nc243, nc244, nc245, nc246, nc247, 
        nc248, nc249, nc250, nc251, nc252, nc253, nc254, nc255, nc256, 
        nc257, nc258, nc259, nc260, nc261, nc262, nc263, nc264, nc265, 
        nc266, nc267, nc268, nc269, nc270, nc271, nc272, nc273, nc274})
        , .F_RID({nc275, nc276, nc277, nc278}), .F_RLAST(), 
        .F_RRESP_HRESP1({nc279, nc280}), .F_RVALID(), .F_WREADY(
        HW_Boot_Engine_0_AXI_IF_WREADY), .MDDR_FABRIC_PRDATA({nc281, 
        nc282, nc283, nc284, nc285, nc286, nc287, nc288, nc289, nc290, 
        nc291, nc292, nc293, nc294, nc295, nc296}), 
        .MDDR_FABRIC_PREADY(CORECONFIGP_0_MDDR_APBmslave_PREADY), 
        .MDDR_FABRIC_PSLVERR(), .CAN_RXBUS_F2H_SCP(VCC_net_1), 
        .CAN_TX_EBL_F2H_SCP(VCC_net_1), .CAN_TXBUS_F2H_SCP(VCC_net_1), 
        .COLF(VCC_net_1), .CRSF(VCC_net_1), .F2_DMAREADY({VCC_net_1, 
        VCC_net_1}), .F2H_INTERRUPT({GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1}), .F2HCALIB(VCC_net_1), 
        .F_DMAREADY({VCC_net_1, VCC_net_1}), .F_FM0_ADDR({GND_net_1, 
        N_48_i_0, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, N_46_i_0, N_46_i_0, N_46_i_0, 
        GND_net_1, GND_net_1, N_767_i_0, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        N_766_i_0, N_765_i_0, N_764_i_0, GND_net_1, GND_net_1}), 
        .F_FM0_ENABLE(GND_net_1), .F_FM0_MASTLOCK(GND_net_1), 
        .F_FM0_READY(CoreAHBLite_0_AHBmslave4_HREADY), .F_FM0_SEL(
        N_94_i_0), .F_FM0_SIZE({N_50_i_0, GND_net_1}), .F_FM0_TRANS1(
        CoreAHBLite_0_AHBmslave4_HTRANS[1]), .F_FM0_WDATA({GND_net_1, 
        GND_net_1, CoreAHBLite_0_AHBmslave4_HWDATA_29, GND_net_1, 
        GND_net_1, GND_net_1, CoreAHBLite_0_AHBmslave4_HWDATA_29, 
        CoreAHBLite_0_AHBmslave4_HWDATA_29, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, 
        CoreAHBLite_0_AHBmslave4_HWDATA_29, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        CoreAHBLite_0_AHBmslave4_HWDATA_29, GND_net_1, GND_net_1, 
        CoreAHBLite_0_AHBmslave4_HWDATA_7, 
        CoreAHBLite_0_AHBmslave4_HWDATA_6, 
        CoreAHBLite_0_AHBmslave4_HWDATA_5, 
        CoreAHBLite_0_AHBmslave4_HWDATA_4, 
        CoreAHBLite_0_AHBmslave4_HWDATA_3, 
        CoreAHBLite_0_AHBmslave4_HWDATA_2, 
        CoreAHBLite_0_AHBmslave4_HWDATA_1, 
        CoreAHBLite_0_AHBmslave4_HWDATA_0}), .F_FM0_WRITE(N_52_i_0), 
        .F_HM0_RDATA({GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1}), .F_HM0_READY(VCC_net_1), 
        .F_HM0_RESP(GND_net_1), .FAB_AVALID(VCC_net_1), 
        .FAB_HOSTDISCON(VCC_net_1), .FAB_IDDIG(VCC_net_1), 
        .FAB_LINESTATE({VCC_net_1, VCC_net_1}), .FAB_M3_RESET_N(
        GPIO_0_M2F_0), .FAB_PLL_LOCK(MSS_DDR_FIC_SUBSYSTEM_LOCK), 
        .FAB_RXACTIVE(VCC_net_1), .FAB_RXERROR(VCC_net_1), 
        .FAB_RXVALID(VCC_net_1), .FAB_RXVALIDH(GND_net_1), 
        .FAB_SESSEND(VCC_net_1), .FAB_TXREADY(VCC_net_1), 
        .FAB_VBUSVALID(VCC_net_1), .FAB_VSTATUS({VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1}), .FAB_XDATAIN({VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .GTX_CLKPF(VCC_net_1), .I2C0_BCLK(VCC_net_1), 
        .I2C0_SCL_F2H_SCP(VCC_net_1), .I2C0_SDA_F2H_SCP(VCC_net_1), 
        .I2C1_BCLK(VCC_net_1), .I2C1_SCL_F2H_SCP(VCC_net_1), 
        .I2C1_SDA_F2H_SCP(VCC_net_1), .MDIF(VCC_net_1), 
        .MGPIO0A_F2H_GPIN(VCC_net_1), .MGPIO10A_F2H_GPIN(VCC_net_1), 
        .MGPIO11A_F2H_GPIN(GPIO_11_F2M_c), .MGPIO11B_F2H_GPIN(
        VCC_net_1), .MGPIO12A_F2H_GPIN(GPIO_12_F2M_c), 
        .MGPIO13A_F2H_GPIN(VCC_net_1), .MGPIO14A_F2H_GPIN(VCC_net_1), 
        .MGPIO15A_F2H_GPIN(VCC_net_1), .MGPIO16A_F2H_GPIN(VCC_net_1), 
        .MGPIO17B_F2H_GPIN(VCC_net_1), .MGPIO18B_F2H_GPIN(VCC_net_1), 
        .MGPIO19B_F2H_GPIN(VCC_net_1), .MGPIO1A_F2H_GPIN(VCC_net_1), 
        .MGPIO20B_F2H_GPIN(VCC_net_1), .MGPIO21B_F2H_GPIN(VCC_net_1), 
        .MGPIO22B_F2H_GPIN(VCC_net_1), .MGPIO24B_F2H_GPIN(VCC_net_1), 
        .MGPIO25B_F2H_GPIN(VCC_net_1), .MGPIO26B_F2H_GPIN(VCC_net_1), 
        .MGPIO27B_F2H_GPIN(VCC_net_1), .MGPIO28B_F2H_GPIN(VCC_net_1), 
        .MGPIO29B_F2H_GPIN(VCC_net_1), .MGPIO2A_F2H_GPIN(VCC_net_1), 
        .MGPIO30B_F2H_GPIN(VCC_net_1), .MGPIO31B_F2H_GPIN(VCC_net_1), 
        .MGPIO3A_F2H_GPIN(VCC_net_1), .MGPIO4A_F2H_GPIN(VCC_net_1), 
        .MGPIO5A_F2H_GPIN(VCC_net_1), .MGPIO6A_F2H_GPIN(VCC_net_1), 
        .MGPIO7A_F2H_GPIN(VCC_net_1), .MGPIO8A_F2H_GPIN(VCC_net_1), 
        .MGPIO9A_F2H_GPIN(VCC_net_1), .MMUART0_CTS_F2H_SCP(VCC_net_1), 
        .MMUART0_DCD_F2H_SCP(VCC_net_1), .MMUART0_DSR_F2H_SCP(
        VCC_net_1), .MMUART0_DTR_F2H_SCP(VCC_net_1), 
        .MMUART0_RI_F2H_SCP(VCC_net_1), .MMUART0_RTS_F2H_SCP(VCC_net_1)
        , .MMUART0_RXD_F2H_SCP(VCC_net_1), .MMUART0_SCK_F2H_SCP(
        VCC_net_1), .MMUART0_TXD_F2H_SCP(VCC_net_1), 
        .MMUART1_CTS_F2H_SCP(VCC_net_1), .MMUART1_DCD_F2H_SCP(
        VCC_net_1), .MMUART1_DSR_F2H_SCP(VCC_net_1), 
        .MMUART1_RI_F2H_SCP(VCC_net_1), .MMUART1_RTS_F2H_SCP(VCC_net_1)
        , .MMUART1_RXD_F2H_SCP(VCC_net_1), .MMUART1_SCK_F2H_SCP(
        VCC_net_1), .MMUART1_TXD_F2H_SCP(VCC_net_1), 
        .PER2_FABRIC_PRDATA({GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .PER2_FABRIC_PREADY(VCC_net_1), .PER2_FABRIC_PSLVERR(GND_net_1)
        , .RCGF({VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .RX_CLKPF(VCC_net_1), .RX_DVF(VCC_net_1), .RX_ERRF(VCC_net_1), 
        .RX_EV(VCC_net_1), .RXDF({VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .SLEEPHOLDREQ(GND_net_1), .SMBALERT_NI0(VCC_net_1), 
        .SMBALERT_NI1(VCC_net_1), .SMBSUS_NI0(VCC_net_1), .SMBSUS_NI1(
        VCC_net_1), .SPI0_CLK_IN(VCC_net_1), .SPI0_SDI_F2H_SCP(
        VCC_net_1), .SPI0_SDO_F2H_SCP(VCC_net_1), .SPI0_SS0_F2H_SCP(
        VCC_net_1), .SPI0_SS1_F2H_SCP(VCC_net_1), .SPI0_SS2_F2H_SCP(
        VCC_net_1), .SPI0_SS3_F2H_SCP(VCC_net_1), .SPI1_CLK_IN(
        VCC_net_1), .SPI1_SDI_F2H_SCP(VCC_net_1), .SPI1_SDO_F2H_SCP(
        VCC_net_1), .SPI1_SS0_F2H_SCP(VCC_net_1), .SPI1_SS1_F2H_SCP(
        VCC_net_1), .SPI1_SS2_F2H_SCP(VCC_net_1), .SPI1_SS3_F2H_SCP(
        VCC_net_1), .TX_CLKPF(VCC_net_1), .USER_MSS_GPIO_RESET_N(
        VCC_net_1), .USER_MSS_RESET_N(VCC_net_1), .XCLK_FAB(VCC_net_1), 
        .CLK_BASE(CCC_0_GL0), .CLK_MDDR_APB(CORECONFIGP_0_APB_S_PCLK), 
        .F_ARADDR_HADDR1({GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1}), .F_ARBURST_HTRANS1({
        GND_net_1, GND_net_1}), .F_ARID_HSEL1({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1}), .F_ARLEN_HBURST1({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1}), .F_ARLOCK_HMASTLOCK1({GND_net_1, 
        GND_net_1}), .F_ARSIZE_HSIZE1({GND_net_1, GND_net_1}), 
        .F_ARVALID_HWRITE1(GND_net_1), .F_AWADDR_HADDR0({
        HW_Boot_Engine_0_AXI_IF_AWADDR[31], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[30], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[29], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[28], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[27], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[26], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[25], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[24], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[23], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[22], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[21], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[20], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[19], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[18], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[17], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[16], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[15], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[14], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[13], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[12], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[11], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[10], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[9], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[8], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[7], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[6], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[5], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[4], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[3], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[2], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[1], 
        HW_Boot_Engine_0_AXI_IF_AWADDR[0]}), .F_AWBURST_HTRANS0({
        GND_net_1, HW_Boot_Engine_0_AXI_IF_AWSIZE[0]}), .F_AWID_HSEL0({
        GND_net_1, GND_net_1, GND_net_1, GND_net_1}), .F_AWLEN_HBURST0({
        GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .F_AWLOCK_HMASTLOCK0({GND_net_1, GND_net_1}), .F_AWSIZE_HSIZE0({
        HW_Boot_Engine_0_AXI_IF_AWSIZE[0], 
        HW_Boot_Engine_0_AXI_IF_AWSIZE[0]}), .F_AWVALID_HWRITE0(
        HW_Boot_Engine_0_AXI_IF_AWVALID), .F_BREADY(
        HW_Boot_Engine_0_AXI_IF_BREADY), .F_RMW_AXI(GND_net_1), 
        .F_RREADY(GND_net_1), .F_WDATA_HWDATA01({
        HW_Boot_Engine_0_AXI_IF_WDATA[63], 
        HW_Boot_Engine_0_AXI_IF_WDATA[62], 
        HW_Boot_Engine_0_AXI_IF_WDATA[61], 
        HW_Boot_Engine_0_AXI_IF_WDATA[60], 
        HW_Boot_Engine_0_AXI_IF_WDATA[59], 
        HW_Boot_Engine_0_AXI_IF_WDATA[58], 
        HW_Boot_Engine_0_AXI_IF_WDATA[57], 
        HW_Boot_Engine_0_AXI_IF_WDATA[56], 
        HW_Boot_Engine_0_AXI_IF_WDATA[55], 
        HW_Boot_Engine_0_AXI_IF_WDATA[54], 
        HW_Boot_Engine_0_AXI_IF_WDATA[53], 
        HW_Boot_Engine_0_AXI_IF_WDATA[52], 
        HW_Boot_Engine_0_AXI_IF_WDATA[51], 
        HW_Boot_Engine_0_AXI_IF_WDATA[50], 
        HW_Boot_Engine_0_AXI_IF_WDATA[49], 
        HW_Boot_Engine_0_AXI_IF_WDATA[48], 
        HW_Boot_Engine_0_AXI_IF_WDATA[47], 
        HW_Boot_Engine_0_AXI_IF_WDATA[46], 
        HW_Boot_Engine_0_AXI_IF_WDATA[45], 
        HW_Boot_Engine_0_AXI_IF_WDATA[44], 
        HW_Boot_Engine_0_AXI_IF_WDATA[43], 
        HW_Boot_Engine_0_AXI_IF_WDATA[42], 
        HW_Boot_Engine_0_AXI_IF_WDATA[41], 
        HW_Boot_Engine_0_AXI_IF_WDATA[40], 
        HW_Boot_Engine_0_AXI_IF_WDATA[39], 
        HW_Boot_Engine_0_AXI_IF_WDATA[38], 
        HW_Boot_Engine_0_AXI_IF_WDATA[37], 
        HW_Boot_Engine_0_AXI_IF_WDATA[36], 
        HW_Boot_Engine_0_AXI_IF_WDATA[35], 
        HW_Boot_Engine_0_AXI_IF_WDATA[34], 
        HW_Boot_Engine_0_AXI_IF_WDATA[33], 
        HW_Boot_Engine_0_AXI_IF_WDATA[32], 
        HW_Boot_Engine_0_AXI_IF_WDATA[31], 
        HW_Boot_Engine_0_AXI_IF_WDATA[30], 
        HW_Boot_Engine_0_AXI_IF_WDATA[29], 
        HW_Boot_Engine_0_AXI_IF_WDATA[28], 
        HW_Boot_Engine_0_AXI_IF_WDATA[27], 
        HW_Boot_Engine_0_AXI_IF_WDATA[26], 
        HW_Boot_Engine_0_AXI_IF_WDATA[25], 
        HW_Boot_Engine_0_AXI_IF_WDATA[24], 
        HW_Boot_Engine_0_AXI_IF_WDATA[23], 
        HW_Boot_Engine_0_AXI_IF_WDATA[22], 
        HW_Boot_Engine_0_AXI_IF_WDATA[21], 
        HW_Boot_Engine_0_AXI_IF_WDATA[20], 
        HW_Boot_Engine_0_AXI_IF_WDATA[19], 
        HW_Boot_Engine_0_AXI_IF_WDATA[18], 
        HW_Boot_Engine_0_AXI_IF_WDATA[17], 
        HW_Boot_Engine_0_AXI_IF_WDATA[16], 
        HW_Boot_Engine_0_AXI_IF_WDATA[15], 
        HW_Boot_Engine_0_AXI_IF_WDATA[14], 
        HW_Boot_Engine_0_AXI_IF_WDATA[13], 
        HW_Boot_Engine_0_AXI_IF_WDATA[12], 
        HW_Boot_Engine_0_AXI_IF_WDATA[11], 
        HW_Boot_Engine_0_AXI_IF_WDATA[10], 
        HW_Boot_Engine_0_AXI_IF_WDATA[9], 
        HW_Boot_Engine_0_AXI_IF_WDATA[8], 
        HW_Boot_Engine_0_AXI_IF_WDATA[7], 
        HW_Boot_Engine_0_AXI_IF_WDATA[6], 
        HW_Boot_Engine_0_AXI_IF_WDATA[5], 
        HW_Boot_Engine_0_AXI_IF_WDATA[4], 
        HW_Boot_Engine_0_AXI_IF_WDATA[3], 
        HW_Boot_Engine_0_AXI_IF_WDATA[2], 
        HW_Boot_Engine_0_AXI_IF_WDATA[1], 
        HW_Boot_Engine_0_AXI_IF_WDATA[0]}), .F_WID_HREADY01({GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1}), .F_WLAST(
        HW_Boot_Engine_0_AXI_IF_WLAST), .F_WSTRB({VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1}), .F_WVALID(HW_Boot_Engine_0_AXI_IF_WLAST), 
        .FPGA_MDDR_ARESET_N(VCC_net_1), .MDDR_FABRIC_PADDR({
        CORECONFIGP_0_MDDR_APBmslave_PADDR[10], 
        CORECONFIGP_0_MDDR_APBmslave_PADDR[9], 
        CORECONFIGP_0_MDDR_APBmslave_PADDR[8], 
        CORECONFIGP_0_MDDR_APBmslave_PADDR[7], 
        CORECONFIGP_0_MDDR_APBmslave_PADDR[6], 
        CORECONFIGP_0_MDDR_APBmslave_PADDR[5], 
        CORECONFIGP_0_MDDR_APBmslave_PADDR[4], 
        CORECONFIGP_0_MDDR_APBmslave_PADDR[3], 
        CORECONFIGP_0_MDDR_APBmslave_PADDR[2]}), .MDDR_FABRIC_PENABLE(
        CORECONFIGP_0_MDDR_APBmslave_PENABLE), .MDDR_FABRIC_PSEL(N_4), 
        .MDDR_FABRIC_PWDATA({CORECONFIGP_0_MDDR_APBmslave_PWDATA[15], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[14], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[13], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[12], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[11], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[10], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[9], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[8], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[7], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[6], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[5], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[4], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[3], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[2], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[1], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[0]}), .MDDR_FABRIC_PWRITE(
        CORECONFIGP_0_MDDR_APBmslave_PWRITE), .PRESET_N(MSS_HPMS_READY)
        , .CAN_RXBUS_USBA_DATA1_MGPIO3A_IN(GND_net_1), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN(GND_net_1), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_IN(GND_net_1), .DM_IN({GND_net_1, 
        MDDR_DM_RDQS_1_PAD_Y, MDDR_DM_RDQS_0_PAD_Y}), .DRAM_DQ_IN({
        GND_net_1, GND_net_1, MDDR_DQ_15_PAD_Y, MDDR_DQ_14_PAD_Y, 
        MDDR_DQ_13_PAD_Y, MDDR_DQ_12_PAD_Y, MDDR_DQ_11_PAD_Y, 
        MDDR_DQ_10_PAD_Y, MDDR_DQ_9_PAD_Y, MDDR_DQ_8_PAD_Y, 
        MDDR_DQ_7_PAD_Y, MDDR_DQ_6_PAD_Y, MDDR_DQ_5_PAD_Y, 
        MDDR_DQ_4_PAD_Y, MDDR_DQ_3_PAD_Y, MDDR_DQ_2_PAD_Y, 
        MDDR_DQ_1_PAD_Y, MDDR_DQ_0_PAD_Y}), .DRAM_DQS_IN({GND_net_1, 
        MDDR_DQS_1_PAD_Y, MDDR_DQS_0_PAD_Y}), .DRAM_FIFO_WE_IN({
        GND_net_1, MDDR_DQS_TMATCH_0_IN_PAD_Y}), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_IN(GND_net_1), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_IN(GND_net_1), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_IN(GND_net_1), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_IN(GND_net_1), .MGPIO0B_IN(
        GND_net_1), .MGPIO10B_IN(GND_net_1), .MGPIO1B_IN(GND_net_1), 
        .MGPIO25A_IN(GND_net_1), .MGPIO26A_IN(GND_net_1), .MGPIO27A_IN(
        GND_net_1), .MGPIO28A_IN(GND_net_1), .MGPIO29A_IN(GND_net_1), 
        .MGPIO2B_IN(GND_net_1), .MGPIO30A_IN(GND_net_1), .MGPIO31A_IN(
        GND_net_1), .MGPIO3B_IN(GND_net_1), .MGPIO4B_IN(GND_net_1), 
        .MGPIO5B_IN(GND_net_1), .MGPIO6B_IN(GND_net_1), .MGPIO7B_IN(
        GND_net_1), .MGPIO8B_IN(GND_net_1), .MGPIO9B_IN(GND_net_1), 
        .MMUART0_CTS_USBC_DATA7_MGPIO19B_IN(GND_net_1), 
        .MMUART0_DCD_MGPIO22B_IN(GND_net_1), .MMUART0_DSR_MGPIO20B_IN(
        GND_net_1), .MMUART0_DTR_USBC_DATA6_MGPIO18B_IN(GND_net_1), 
        .MMUART0_RI_MGPIO21B_IN(GND_net_1), 
        .MMUART0_RTS_USBC_DATA5_MGPIO17B_IN(GND_net_1), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_IN(GND_net_1), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_IN(GND_net_1), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_IN(GND_net_1), 
        .MMUART1_CTS_MGPIO13B_IN(GND_net_1), .MMUART1_DCD_MGPIO16B_IN(
        GND_net_1), .MMUART1_DSR_MGPIO14B_IN(GND_net_1), 
        .MMUART1_DTR_MGPIO12B_IN(GND_net_1), .MMUART1_RI_MGPIO15B_IN(
        GND_net_1), .MMUART1_RTS_MGPIO11B_IN(GND_net_1), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_IN(MMUART_1_RXD_PAD_Y), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_IN(GND_net_1), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_IN(GND_net_1), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN(GND_net_1), 
        .RGMII_MDC_RMII_MDC_IN(GND_net_1), 
        .RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN(GND_net_1), 
        .RGMII_RX_CLK_IN(GND_net_1), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN(GND_net_1), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN(GND_net_1), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN(GND_net_1), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN(GND_net_1), 
        .RGMII_RXD3_USBB_DATA4_IN(GND_net_1), .RGMII_TX_CLK_IN(
        GND_net_1), .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN(GND_net_1), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_IN(GND_net_1), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_IN(GND_net_1), 
        .RGMII_TXD2_USBB_DATA5_IN(GND_net_1), 
        .RGMII_TXD3_USBB_DATA6_IN(GND_net_1), .SPI0_SCK_USBA_XCLK_IN(
        SPI_0_CLK_PAD_Y), .SPI0_SDI_USBA_DIR_MGPIO5A_IN(SPI_0_DI_PAD_Y)
        , .SPI0_SDO_USBA_STP_MGPIO6A_IN(GND_net_1), 
        .SPI0_SS0_USBA_NXT_MGPIO7A_IN(SPI_0_SS0_PAD_Y), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_IN(GND_net_1), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_IN(GND_net_1), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_IN(GND_net_1), 
        .SPI0_SS4_MGPIO19A_IN(GND_net_1), .SPI0_SS5_MGPIO20A_IN(
        GND_net_1), .SPI0_SS6_MGPIO21A_IN(GND_net_1), 
        .SPI0_SS7_MGPIO22A_IN(GND_net_1), .SPI1_SCK_IN(GND_net_1), 
        .SPI1_SDI_MGPIO11A_IN(GND_net_1), .SPI1_SDO_MGPIO12A_IN(
        GND_net_1), .SPI1_SS0_MGPIO13A_IN(GND_net_1), 
        .SPI1_SS1_MGPIO14A_IN(GND_net_1), .SPI1_SS2_MGPIO15A_IN(
        GND_net_1), .SPI1_SS3_MGPIO16A_IN(GND_net_1), 
        .SPI1_SS4_MGPIO17A_IN(GND_net_1), .SPI1_SS5_MGPIO18A_IN(
        GND_net_1), .SPI1_SS6_MGPIO23A_IN(GND_net_1), 
        .SPI1_SS7_MGPIO24A_IN(GND_net_1), .USBC_XCLK_IN(GND_net_1), 
        .USBD_DATA0_IN(GND_net_1), .USBD_DATA1_IN(GND_net_1), 
        .USBD_DATA2_IN(GND_net_1), .USBD_DATA3_IN(GND_net_1), 
        .USBD_DATA4_IN(GND_net_1), .USBD_DATA5_IN(GND_net_1), 
        .USBD_DATA6_IN(GND_net_1), .USBD_DATA7_MGPIO23B_IN(GND_net_1), 
        .USBD_DIR_IN(GND_net_1), .USBD_NXT_IN(GND_net_1), .USBD_STP_IN(
        GND_net_1), .USBD_XCLK_IN(GND_net_1), 
        .CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT(), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT(), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT(), .DRAM_ADDR({
        \DRAM_ADDR_net_0[15] , \DRAM_ADDR_net_0[14] , 
        \DRAM_ADDR_net_0[13] , \DRAM_ADDR_net_0[12] , 
        \DRAM_ADDR_net_0[11] , \DRAM_ADDR_net_0[10] , 
        \DRAM_ADDR_net_0[9] , \DRAM_ADDR_net_0[8] , 
        \DRAM_ADDR_net_0[7] , \DRAM_ADDR_net_0[6] , 
        \DRAM_ADDR_net_0[5] , \DRAM_ADDR_net_0[4] , 
        \DRAM_ADDR_net_0[3] , \DRAM_ADDR_net_0[2] , 
        \DRAM_ADDR_net_0[1] , \DRAM_ADDR_net_0[0] }), .DRAM_BA({
        \DRAM_BA_net_0[2] , \DRAM_BA_net_0[1] , \DRAM_BA_net_0[0] }), 
        .DRAM_CASN(MSS_ADLIB_INST_DRAM_CASN), .DRAM_CKE(
        MSS_ADLIB_INST_DRAM_CKE), .DRAM_CLK(MSS_ADLIB_INST_DRAM_CLK), 
        .DRAM_CSN(MSS_ADLIB_INST_DRAM_CSN), .DRAM_DM_RDQS_OUT({nc297, 
        \DRAM_DM_RDQS_OUT_net_0[1] , \DRAM_DM_RDQS_OUT_net_0[0] }), 
        .DRAM_DQ_OUT({nc298, nc299, \DRAM_DQ_OUT_net_0[15] , 
        \DRAM_DQ_OUT_net_0[14] , \DRAM_DQ_OUT_net_0[13] , 
        \DRAM_DQ_OUT_net_0[12] , \DRAM_DQ_OUT_net_0[11] , 
        \DRAM_DQ_OUT_net_0[10] , \DRAM_DQ_OUT_net_0[9] , 
        \DRAM_DQ_OUT_net_0[8] , \DRAM_DQ_OUT_net_0[7] , 
        \DRAM_DQ_OUT_net_0[6] , \DRAM_DQ_OUT_net_0[5] , 
        \DRAM_DQ_OUT_net_0[4] , \DRAM_DQ_OUT_net_0[3] , 
        \DRAM_DQ_OUT_net_0[2] , \DRAM_DQ_OUT_net_0[1] , 
        \DRAM_DQ_OUT_net_0[0] }), .DRAM_DQS_OUT({nc300, 
        \DRAM_DQS_OUT_net_0[1] , \DRAM_DQS_OUT_net_0[0] }), 
        .DRAM_FIFO_WE_OUT({nc301, \DRAM_FIFO_WE_OUT_net_0[0] }), 
        .DRAM_ODT(MSS_ADLIB_INST_DRAM_ODT), .DRAM_RASN(
        MSS_ADLIB_INST_DRAM_RASN), .DRAM_RSTN(MSS_ADLIB_INST_DRAM_RSTN)
        , .DRAM_WEN(MSS_ADLIB_INST_DRAM_WEN), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_OUT(), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_OUT(), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_OUT(), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_OUT(), .MGPIO0B_OUT(), 
        .MGPIO10B_OUT(), .MGPIO1B_OUT(), .MGPIO25A_OUT(), 
        .MGPIO26A_OUT(), .MGPIO27A_OUT(), .MGPIO28A_OUT(), 
        .MGPIO29A_OUT(), .MGPIO2B_OUT(), .MGPIO30A_OUT(), 
        .MGPIO31A_OUT(), .MGPIO3B_OUT(), .MGPIO4B_OUT(), .MGPIO5B_OUT()
        , .MGPIO6B_OUT(), .MGPIO7B_OUT(), .MGPIO8B_OUT(), .MGPIO9B_OUT(
        ), .MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT(), 
        .MMUART0_DCD_MGPIO22B_OUT(), .MMUART0_DSR_MGPIO20B_OUT(), 
        .MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT(), 
        .MMUART0_RI_MGPIO21B_OUT(), 
        .MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT(), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_OUT(), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_OUT(), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_OUT(), 
        .MMUART1_CTS_MGPIO13B_OUT(), .MMUART1_DCD_MGPIO16B_OUT(), 
        .MMUART1_DSR_MGPIO14B_OUT(), .MMUART1_DTR_MGPIO12B_OUT(), 
        .MMUART1_RI_MGPIO15B_OUT(), .MMUART1_RTS_MGPIO11B_OUT(), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT(), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT(), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT(
        MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT(), 
        .RGMII_MDC_RMII_MDC_OUT(), 
        .RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT(), .RGMII_RX_CLK_OUT(), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT(), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT(), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT(), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT(), 
        .RGMII_RXD3_USBB_DATA4_OUT(), .RGMII_TX_CLK_OUT(), 
        .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT(), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT(), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_OUT(), 
        .RGMII_TXD2_USBB_DATA5_OUT(), .RGMII_TXD3_USBB_DATA6_OUT(), 
        .SPI0_SCK_USBA_XCLK_OUT(MSS_ADLIB_INST_SPI0_SCK_USBA_XCLK_OUT), 
        .SPI0_SDI_USBA_DIR_MGPIO5A_OUT(), 
        .SPI0_SDO_USBA_STP_MGPIO6A_OUT(
        MSS_ADLIB_INST_SPI0_SDO_USBA_STP_MGPIO6A_OUT), 
        .SPI0_SS0_USBA_NXT_MGPIO7A_OUT(
        MSS_ADLIB_INST_SPI0_SS0_USBA_NXT_MGPIO7A_OUT), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_OUT(), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_OUT(), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_OUT(), .SPI0_SS4_MGPIO19A_OUT(), 
        .SPI0_SS5_MGPIO20A_OUT(), .SPI0_SS6_MGPIO21A_OUT(), 
        .SPI0_SS7_MGPIO22A_OUT(), .SPI1_SCK_OUT(), 
        .SPI1_SDI_MGPIO11A_OUT(), .SPI1_SDO_MGPIO12A_OUT(), 
        .SPI1_SS0_MGPIO13A_OUT(), .SPI1_SS1_MGPIO14A_OUT(), 
        .SPI1_SS2_MGPIO15A_OUT(), .SPI1_SS3_MGPIO16A_OUT(), 
        .SPI1_SS4_MGPIO17A_OUT(), .SPI1_SS5_MGPIO18A_OUT(), 
        .SPI1_SS6_MGPIO23A_OUT(), .SPI1_SS7_MGPIO24A_OUT(), 
        .USBC_XCLK_OUT(), .USBD_DATA0_OUT(), .USBD_DATA1_OUT(), 
        .USBD_DATA2_OUT(), .USBD_DATA3_OUT(), .USBD_DATA4_OUT(), 
        .USBD_DATA5_OUT(), .USBD_DATA6_OUT(), .USBD_DATA7_MGPIO23B_OUT(
        ), .USBD_DIR_OUT(), .USBD_NXT_OUT(), .USBD_STP_OUT(), 
        .USBD_XCLK_OUT(), .CAN_RXBUS_USBA_DATA1_MGPIO3A_OE(), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE(), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_OE(), .DM_OE({nc302, 
        \DM_OE_net_0[1] , \DM_OE_net_0[0] }), .DRAM_DQ_OE({nc303, 
        nc304, \DRAM_DQ_OE_net_0[15] , \DRAM_DQ_OE_net_0[14] , 
        \DRAM_DQ_OE_net_0[13] , \DRAM_DQ_OE_net_0[12] , 
        \DRAM_DQ_OE_net_0[11] , \DRAM_DQ_OE_net_0[10] , 
        \DRAM_DQ_OE_net_0[9] , \DRAM_DQ_OE_net_0[8] , 
        \DRAM_DQ_OE_net_0[7] , \DRAM_DQ_OE_net_0[6] , 
        \DRAM_DQ_OE_net_0[5] , \DRAM_DQ_OE_net_0[4] , 
        \DRAM_DQ_OE_net_0[3] , \DRAM_DQ_OE_net_0[2] , 
        \DRAM_DQ_OE_net_0[1] , \DRAM_DQ_OE_net_0[0] }), .DRAM_DQS_OE({
        nc305, \DRAM_DQS_OE_net_0[1] , \DRAM_DQS_OE_net_0[0] }), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_OE(), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_OE(), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_OE(), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_OE(), .MGPIO0B_OE(), .MGPIO10B_OE(
        ), .MGPIO1B_OE(), .MGPIO25A_OE(), .MGPIO26A_OE(), .MGPIO27A_OE(
        ), .MGPIO28A_OE(), .MGPIO29A_OE(), .MGPIO2B_OE(), .MGPIO30A_OE(
        ), .MGPIO31A_OE(), .MGPIO3B_OE(), .MGPIO4B_OE(), .MGPIO5B_OE(), 
        .MGPIO6B_OE(), .MGPIO7B_OE(), .MGPIO8B_OE(), .MGPIO9B_OE(), 
        .MMUART0_CTS_USBC_DATA7_MGPIO19B_OE(), 
        .MMUART0_DCD_MGPIO22B_OE(), .MMUART0_DSR_MGPIO20B_OE(), 
        .MMUART0_DTR_USBC_DATA6_MGPIO18B_OE(), .MMUART0_RI_MGPIO21B_OE(
        ), .MMUART0_RTS_USBC_DATA5_MGPIO17B_OE(), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_OE(), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_OE(), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_OE(), .MMUART1_CTS_MGPIO13B_OE()
        , .MMUART1_DCD_MGPIO16B_OE(), .MMUART1_DSR_MGPIO14B_OE(), 
        .MMUART1_DTR_MGPIO12B_OE(), .MMUART1_RI_MGPIO15B_OE(), 
        .MMUART1_RTS_MGPIO11B_OE(), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_OE(), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_OE(), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_OE(
        MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OE), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE(), .RGMII_MDC_RMII_MDC_OE(
        ), .RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE(), .RGMII_RX_CLK_OE(), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE(), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE(), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE(), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE(), 
        .RGMII_RXD3_USBB_DATA4_OE(), .RGMII_TX_CLK_OE(), 
        .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE(), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_OE(), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_OE(), .RGMII_TXD2_USBB_DATA5_OE(
        ), .RGMII_TXD3_USBB_DATA6_OE(), .SPI0_SCK_USBA_XCLK_OE(
        MSS_ADLIB_INST_SPI0_SCK_USBA_XCLK_OE), 
        .SPI0_SDI_USBA_DIR_MGPIO5A_OE(), .SPI0_SDO_USBA_STP_MGPIO6A_OE(
        MSS_ADLIB_INST_SPI0_SDO_USBA_STP_MGPIO6A_OE), 
        .SPI0_SS0_USBA_NXT_MGPIO7A_OE(
        MSS_ADLIB_INST_SPI0_SS0_USBA_NXT_MGPIO7A_OE), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_OE(), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_OE(), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_OE(), .SPI0_SS4_MGPIO19A_OE(), 
        .SPI0_SS5_MGPIO20A_OE(), .SPI0_SS6_MGPIO21A_OE(), 
        .SPI0_SS7_MGPIO22A_OE(), .SPI1_SCK_OE(), .SPI1_SDI_MGPIO11A_OE(
        ), .SPI1_SDO_MGPIO12A_OE(), .SPI1_SS0_MGPIO13A_OE(), 
        .SPI1_SS1_MGPIO14A_OE(), .SPI1_SS2_MGPIO15A_OE(), 
        .SPI1_SS3_MGPIO16A_OE(), .SPI1_SS4_MGPIO17A_OE(), 
        .SPI1_SS5_MGPIO18A_OE(), .SPI1_SS6_MGPIO23A_OE(), 
        .SPI1_SS7_MGPIO24A_OE(), .USBC_XCLK_OE(), .USBD_DATA0_OE(), 
        .USBD_DATA1_OE(), .USBD_DATA2_OE(), .USBD_DATA3_OE(), 
        .USBD_DATA4_OE(), .USBD_DATA5_OE(), .USBD_DATA6_OE(), 
        .USBD_DATA7_MGPIO23B_OE(), .USBD_DIR_OE(), .USBD_NXT_OE(), 
        .USBD_STP_OE(), .USBD_XCLK_OE());
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_RAS_N_PAD (.D(
        MSS_ADLIB_INST_DRAM_RASN), .PAD(MDDR_RAS_N));
    BIBUF #( .IOSTD("") )  SPI_0_CLK_PAD (.PAD(SPI_0_CLK), .D(
        MSS_ADLIB_INST_SPI0_SCK_USBA_XCLK_OUT), .E(
        MSS_ADLIB_INST_SPI0_SCK_USBA_XCLK_OE), .Y(SPI_0_CLK_PAD_Y));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_4_PAD (.PAD(MDDR_DQ[4]), .D(
        \DRAM_DQ_OUT_net_0[4] ), .E(\DRAM_DQ_OE_net_0[4] ), .Y(
        MDDR_DQ_4_PAD_Y));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_10_PAD (.D(
        \DRAM_ADDR_net_0[10] ), .PAD(MDDR_ADDR[10]));
    INBUF #( .IOSTD("LPDDRI") )  MDDR_DQS_TMATCH_0_IN_PAD (.PAD(
        MDDR_DQS_TMATCH_0_IN), .Y(MDDR_DQS_TMATCH_0_IN_PAD_Y));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_CS_N_PAD (.D(
        MSS_ADLIB_INST_DRAM_CSN), .PAD(MDDR_CS_N));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_4_PAD (.D(
        \DRAM_ADDR_net_0[4] ), .PAD(MDDR_ADDR[4]));
    BIBUF #( .IOSTD("") )  SPI_0_SS0_PAD (.PAD(SPI_0_SS0), .D(
        MSS_ADLIB_INST_SPI0_SS0_USBA_NXT_MGPIO7A_OUT), .E(
        MSS_ADLIB_INST_SPI0_SS0_USBA_NXT_MGPIO7A_OE), .Y(
        SPI_0_SS0_PAD_Y));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_7_PAD (.PAD(MDDR_DQ[7]), .D(
        \DRAM_DQ_OUT_net_0[7] ), .E(\DRAM_DQ_OE_net_0[7] ), .Y(
        MDDR_DQ_7_PAD_Y));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_WE_N_PAD (.D(
        MSS_ADLIB_INST_DRAM_WEN), .PAD(MDDR_WE_N));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_8_PAD (.D(
        \DRAM_ADDR_net_0[8] ), .PAD(MDDR_ADDR[8]));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_15_PAD (.D(
        \DRAM_ADDR_net_0[15] ), .PAD(MDDR_ADDR[15]));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_0_PAD (.D(
        \DRAM_ADDR_net_0[0] ), .PAD(MDDR_ADDR[0]));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_1_PAD (.D(
        \DRAM_ADDR_net_0[1] ), .PAD(MDDR_ADDR[1]));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_13_PAD (.PAD(MDDR_DQ[13]), .D(
        \DRAM_DQ_OUT_net_0[13] ), .E(\DRAM_DQ_OE_net_0[13] ), .Y(
        MDDR_DQ_13_PAD_Y));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_3_PAD (.D(
        \DRAM_ADDR_net_0[3] ), .PAD(MDDR_ADDR[3]));
    INBUF #( .IOSTD("") )  MMUART_1_RXD_PAD (.PAD(MMUART_1_RXD), .Y(
        MMUART_1_RXD_PAD_Y));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_BA_0_PAD (.D(\DRAM_BA_net_0[0] )
        , .PAD(MDDR_BA[0]));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_6_PAD (.PAD(MDDR_DQ[6]), .D(
        \DRAM_DQ_OUT_net_0[6] ), .E(\DRAM_DQ_OE_net_0[6] ), .Y(
        MDDR_DQ_6_PAD_Y));
    OUTBUF_DIFF #( .IOSTD("LPDDRI") )  MDDR_CLK_PAD (.D(
        MSS_ADLIB_INST_DRAM_CLK), .PADP(MDDR_CLK), .PADN(MDDR_CLK_N));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_14_PAD (.PAD(MDDR_DQ[14]), .D(
        \DRAM_DQ_OUT_net_0[14] ), .E(\DRAM_DQ_OE_net_0[14] ), .Y(
        MDDR_DQ_14_PAD_Y));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_DQS_TMATCH_0_OUT_PAD (.D(
        \DRAM_FIFO_WE_OUT_net_0[0] ), .PAD(MDDR_DQS_TMATCH_0_OUT));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_BA_1_PAD (.D(\DRAM_BA_net_0[1] )
        , .PAD(MDDR_BA[1]));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_5_PAD (.PAD(MDDR_DQ[5]), .D(
        \DRAM_DQ_OUT_net_0[5] ), .E(\DRAM_DQ_OE_net_0[5] ), .Y(
        MDDR_DQ_5_PAD_Y));
    
endmodule


module CodeShadowing_Fabric_FABOSC_0_OSC(
       FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
    );
output FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC;

    wire GND_net_1, VCC_net_1;
    
    RCOSC_25_50MHZ #( .FREQUENCY(50.0) )  I_RCOSC_25_50MHZ (.CLKOUT(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC));
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    
endmodule


module CodeShadowing_Fabric(
       MDDR_ADDR,
       MDDR_BA,
       MDDR_DM_RDQS,
       MDDR_DQ,
       MDDR_DQS,
       DEVRST_N,
       DP_SW1,
       GPIO_11_F2M,
       GPIO_12_F2M,
       MDDR_DQS_TMATCH_0_IN,
       MMUART_1_RXD,
       SPI_0_DI,
       GPIO_0_M2F,
       GPIO_10_M2F,
       GPIO_1_M2F,
       GPIO_2_M2F,
       GPIO_3_M2F,
       GPIO_4_M2F,
       GPIO_8_M2F,
       GPIO_9_M2F,
       MDDR_CAS_N,
       MDDR_CKE,
       MDDR_CLK,
       MDDR_CLK_N,
       MDDR_CS_N,
       MDDR_DQS_TMATCH_0_OUT,
       MDDR_ODT,
       MDDR_RAS_N,
       MDDR_RESET_N,
       MDDR_WE_N,
       MMUART_1_TXD,
       SPI_0_DO,
       SPI_0_CLK,
       SPI_0_SS0
    );
output [15:0] MDDR_ADDR;
output [2:0] MDDR_BA;
inout  [1:0] MDDR_DM_RDQS;
inout  [15:0] MDDR_DQ;
inout  [1:0] MDDR_DQS;
input  DEVRST_N;
input  DP_SW1;
input  GPIO_11_F2M;
input  GPIO_12_F2M;
input  MDDR_DQS_TMATCH_0_IN;
input  MMUART_1_RXD;
input  SPI_0_DI;
output GPIO_0_M2F;
output GPIO_10_M2F;
output GPIO_1_M2F;
output GPIO_2_M2F;
output GPIO_3_M2F;
output GPIO_4_M2F;
output GPIO_8_M2F;
output GPIO_9_M2F;
output MDDR_CAS_N;
output MDDR_CKE;
output MDDR_CLK;
output MDDR_CLK_N;
output MDDR_CS_N;
output MDDR_DQS_TMATCH_0_OUT;
output MDDR_ODT;
output MDDR_RAS_N;
output MDDR_RESET_N;
output MDDR_WE_N;
output MMUART_1_TXD;
output SPI_0_DO;
inout  SPI_0_CLK;
inout  SPI_0_SS0;

    wire FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC, 
        MSS_DDR_FIC_SUBSYSTEM_LOCK, CCC_0_GL0, 
        \CoreAHBLite_0_AHBmslave4_HTRANS[1] , 
        \CoreAHBLite_0_AHBmslave4_HWDATA[0] , 
        \CoreAHBLite_0_AHBmslave4_HWDATA[1] , 
        \CoreAHBLite_0_AHBmslave4_HWDATA[2] , 
        \CoreAHBLite_0_AHBmslave4_HWDATA[3] , 
        \CoreAHBLite_0_AHBmslave4_HWDATA[4] , 
        \CoreAHBLite_0_AHBmslave4_HWDATA[5] , 
        \CoreAHBLite_0_AHBmslave4_HWDATA[6] , 
        \CoreAHBLite_0_AHBmslave4_HWDATA[7] , 
        \CoreAHBLite_0_AHBmslave4_HWDATA[29] , GND_net_1, GPIO_0_M2F_0, 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[2] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[3] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[4] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[5] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[6] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[7] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[8] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[9] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[10] , 
        CORECONFIGP_0_MDDR_APBmslave_PENABLE, 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[0] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[1] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[2] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[3] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[4] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[5] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[6] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[7] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[8] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[9] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[10] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[11] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[12] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[13] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[14] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[15] , 
        CORECONFIGP_0_MDDR_APBmslave_PWRITE, 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[0] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[1] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[2] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[3] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[4] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[5] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[6] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[7] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[8] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[9] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[10] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[11] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[12] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[13] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[14] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[15] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[16] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[17] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[18] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[19] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[20] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[21] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[22] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[23] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[24] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[25] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[26] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[27] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[28] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[29] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[30] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[31] , 
        \HW_Boot_Engine_0_AXI_IF_AWSIZE[0] , 
        HW_Boot_Engine_0_AXI_IF_AWVALID, 
        HW_Boot_Engine_0_AXI_IF_BREADY, 
        \HW_Boot_Engine_0_AXI_IF_WDATA[0] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[1] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[2] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[3] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[4] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[5] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[6] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[7] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[8] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[9] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[10] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[11] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[12] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[13] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[14] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[15] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[16] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[17] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[18] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[19] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[20] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[21] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[22] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[23] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[24] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[25] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[26] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[27] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[28] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[29] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[30] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[31] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[32] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[33] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[34] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[35] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[36] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[37] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[38] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[39] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[40] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[41] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[42] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[43] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[44] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[45] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[46] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[47] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[48] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[49] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[50] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[51] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[52] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[53] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[54] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[55] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[56] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[57] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[58] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[59] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[60] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[61] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[62] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[63] , 
        HW_Boot_Engine_0_AXI_IF_WLAST, 
        \CoreAHBLite_0_AHBmslave4_HRDATA[0] , 
        \CoreAHBLite_0_AHBmslave4_HRDATA[1] , 
        \CoreAHBLite_0_AHBmslave4_HRDATA[2] , 
        \CoreAHBLite_0_AHBmslave4_HRDATA[3] , 
        \CoreAHBLite_0_AHBmslave4_HRDATA[4] , 
        \CoreAHBLite_0_AHBmslave4_HRDATA[5] , 
        \CoreAHBLite_0_AHBmslave4_HRDATA[6] , 
        \CoreAHBLite_0_AHBmslave4_HRDATA[7] , 
        \CoreAHBLite_0_AHBmslave4_HRDATA[8] , 
        CoreAHBLite_0_AHBmslave4_HREADY, CORECONFIGP_0_APB_S_PCLK, 
        FIC_2_APB_M_PRESET_N, CORECONFIGP_0_MDDR_APBmslave_PREADY, 
        HW_Boot_Engine_0_AXI_IF_AWREADY, 
        HW_Boot_Engine_0_AXI_IF_BVALID, HW_Boot_Engine_0_AXI_IF_WREADY, 
        MSS_RESET_N_M2F, MSS_HPMS_READY, 
        \HW_Boot_Engine_0_AHB_IF_HADDR[2] , 
        \HW_Boot_Engine_0_AHB_IF_HADDR[3] , 
        \HW_Boot_Engine_0_AHB_IF_HADDR[4] , 
        \HW_Boot_Engine_0_AHB_IF_HADDR[12] , 
        \HW_Boot_Engine_0_AHB_IF_HADDR[16] , 
        \HW_Boot_Engine_0_AHB_IF_HADDR[30] , 
        \HW_Boot_Engine_0_AHB_IF_HTRANS[1] , 
        HW_Boot_Engine_0_AHB_IF_HWRITE, 
        \HW_Boot_Engine_0_AHB_IF_HWDATA[0] , 
        \HW_Boot_Engine_0_AHB_IF_HWDATA[1] , 
        \HW_Boot_Engine_0_AHB_IF_HWDATA[2] , 
        \HW_Boot_Engine_0_AHB_IF_HWDATA[3] , 
        \HW_Boot_Engine_0_AHB_IF_HWDATA[4] , 
        \HW_Boot_Engine_0_AHB_IF_HWDATA[5] , 
        \HW_Boot_Engine_0_AHB_IF_HWDATA[6] , 
        \HW_Boot_Engine_0_AHB_IF_HWDATA[7] , 
        \HW_Boot_Engine_0_AHB_IF_HWDATA[18] , 
        HW_Boot_Engine_0_APB_IF_PSELx, HW_Boot_Engine_0_APB_IF_PENABLE, 
        HW_Boot_Engine_0_APB_IF_PWRITE, 
        \HW_Boot_Engine_0_APB_IF_PADDR[2] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[0] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[1] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[2] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[3] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[4] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[5] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[6] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[7] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[8] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[9] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[10] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[11] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[12] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[13] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[14] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[15] , 
        HW_Boot_Engine_0_APB_IF_PREADY, POWER_ON_RESET_N, VCC_net_1, 
        N_94_i_0, 
        \CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv_i_0 , N_4, 
        \HW_Boot_Engine_0.AHB_IF_0.ahb_fsm_current_state[5] , DP_SW1_c, 
        GPIO_11_F2M_c, GPIO_12_F2M_c, GPIO_0_M2F_c, GPIO_10_M2F_c, 
        GPIO_1_M2F_c, GPIO_2_M2F_c, GPIO_3_M2F_c, GPIO_4_M2F_c, 
        GPIO_8_M2F_c, GPIO_9_M2F_c, N_95, 
        \CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv_i_0_d , 
        \HW_Boot_Engine_0_APB_IF_PADDR[3] , 
        \HW_Boot_Engine_0_APB_IF_PADDR[4] , 
        \HW_Boot_Engine_0_APB_IF_PADDR[5] , 
        \HW_Boot_Engine_0_APB_IF_PADDR[6] , 
        \HW_Boot_Engine_0_APB_IF_PADDR[7] , 
        \HW_Boot_Engine_0_APB_IF_PADDR[8] , 
        \HW_Boot_Engine_0_APB_IF_PADDR[9] , 
        \HW_Boot_Engine_0_APB_IF_PADDR[10] , 
        \HW_Boot_Engine_0_APB_IF_PADDR[12] , 
        \HW_Boot_Engine_0_APB_IF_PADDR[13] , 
        \HW_Boot_Engine_0_APB_IF_PADDR[15] , 
        \CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv_i_0_1_0 , 
        CORECONFIGP_0_APB_S_PCLK_i_0, N_764_i_0, N_765_i_0, N_766_i_0, 
        N_767_i_0, N_46_i_0, N_48_i_0, N_50_i_0, N_52_i_0;
    
    HW_Boot_Engine HW_Boot_Engine_0 (.HW_Boot_Engine_0_AHB_IF_HTRANS({
        \HW_Boot_Engine_0_AHB_IF_HTRANS[1] }), .ahb_fsm_current_state({
        \HW_Boot_Engine_0.AHB_IF_0.ahb_fsm_current_state[5] }), 
        .CoreAHBLite_0_AHBmslave4_HRDATA({
        \CoreAHBLite_0_AHBmslave4_HRDATA[8] , 
        \CoreAHBLite_0_AHBmslave4_HRDATA[7] , 
        \CoreAHBLite_0_AHBmslave4_HRDATA[6] , 
        \CoreAHBLite_0_AHBmslave4_HRDATA[5] , 
        \CoreAHBLite_0_AHBmslave4_HRDATA[4] , 
        \CoreAHBLite_0_AHBmslave4_HRDATA[3] , 
        \CoreAHBLite_0_AHBmslave4_HRDATA[2] , 
        \CoreAHBLite_0_AHBmslave4_HRDATA[1] , 
        \CoreAHBLite_0_AHBmslave4_HRDATA[0] }), 
        .HW_Boot_Engine_0_AXI_IF_WDATA({
        \HW_Boot_Engine_0_AXI_IF_WDATA[63] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[62] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[61] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[60] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[59] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[58] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[57] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[56] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[55] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[54] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[53] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[52] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[51] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[50] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[49] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[48] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[47] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[46] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[45] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[44] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[43] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[42] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[41] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[40] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[39] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[38] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[37] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[36] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[35] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[34] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[33] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[32] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[31] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[30] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[29] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[28] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[27] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[26] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[25] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[24] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[23] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[22] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[21] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[20] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[19] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[18] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[17] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[16] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[15] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[14] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[13] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[12] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[11] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[10] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[9] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[8] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[7] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[6] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[5] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[4] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[3] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[2] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[1] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[0] }), 
        .HW_Boot_Engine_0_AXI_IF_AWADDR({
        \HW_Boot_Engine_0_AXI_IF_AWADDR[31] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[30] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[29] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[28] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[27] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[26] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[25] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[24] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[23] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[22] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[21] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[20] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[19] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[18] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[17] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[16] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[15] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[14] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[13] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[12] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[11] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[10] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[9] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[8] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[7] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[6] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[5] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[4] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[3] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[2] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[1] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[0] }), 
        .HW_Boot_Engine_0_AXI_IF_AWSIZE({
        \HW_Boot_Engine_0_AXI_IF_AWSIZE[0] }), 
        .HW_Boot_Engine_0_APB_IF_PWDATA({
        \HW_Boot_Engine_0_APB_IF_PWDATA[15] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[14] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[13] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[12] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[11] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[10] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[9] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[8] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[7] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[6] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[5] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[4] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[3] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[2] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[1] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[0] }), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_2(
        \HW_Boot_Engine_0_AHB_IF_HWDATA[2] ), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_3(
        \HW_Boot_Engine_0_AHB_IF_HWDATA[3] ), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_4(
        \HW_Boot_Engine_0_AHB_IF_HWDATA[4] ), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_5(
        \HW_Boot_Engine_0_AHB_IF_HWDATA[5] ), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_6(
        \HW_Boot_Engine_0_AHB_IF_HWDATA[6] ), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_7(
        \HW_Boot_Engine_0_AHB_IF_HWDATA[7] ), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_18(
        \HW_Boot_Engine_0_AHB_IF_HWDATA[18] ), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_0(
        \HW_Boot_Engine_0_AHB_IF_HWDATA[0] ), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_1(
        \HW_Boot_Engine_0_AHB_IF_HWDATA[1] ), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_1(
        \HW_Boot_Engine_0_AHB_IF_HADDR[3] ), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_2(
        \HW_Boot_Engine_0_AHB_IF_HADDR[4] ), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_10(
        \HW_Boot_Engine_0_AHB_IF_HADDR[12] ), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_14(
        \HW_Boot_Engine_0_AHB_IF_HADDR[16] ), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_28(
        \HW_Boot_Engine_0_AHB_IF_HADDR[30] ), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_0(
        \HW_Boot_Engine_0_AHB_IF_HADDR[2] ), 
        .HW_Boot_Engine_0_APB_IF_PADDR_0(
        \HW_Boot_Engine_0_APB_IF_PADDR[2] ), 
        .HW_Boot_Engine_0_APB_IF_PADDR_1(
        \HW_Boot_Engine_0_APB_IF_PADDR[3] ), 
        .HW_Boot_Engine_0_APB_IF_PADDR_2(
        \HW_Boot_Engine_0_APB_IF_PADDR[4] ), 
        .HW_Boot_Engine_0_APB_IF_PADDR_3(
        \HW_Boot_Engine_0_APB_IF_PADDR[5] ), 
        .HW_Boot_Engine_0_APB_IF_PADDR_4(
        \HW_Boot_Engine_0_APB_IF_PADDR[6] ), 
        .HW_Boot_Engine_0_APB_IF_PADDR_5(
        \HW_Boot_Engine_0_APB_IF_PADDR[7] ), 
        .HW_Boot_Engine_0_APB_IF_PADDR_6(
        \HW_Boot_Engine_0_APB_IF_PADDR[8] ), 
        .HW_Boot_Engine_0_APB_IF_PADDR_7(
        \HW_Boot_Engine_0_APB_IF_PADDR[9] ), 
        .HW_Boot_Engine_0_APB_IF_PADDR_8(
        \HW_Boot_Engine_0_APB_IF_PADDR[10] ), 
        .HW_Boot_Engine_0_APB_IF_PADDR_10(
        \HW_Boot_Engine_0_APB_IF_PADDR[12] ), 
        .HW_Boot_Engine_0_APB_IF_PADDR_11(
        \HW_Boot_Engine_0_APB_IF_PADDR[13] ), 
        .HW_Boot_Engine_0_APB_IF_PADDR_13(
        \HW_Boot_Engine_0_APB_IF_PADDR[15] ), .MSS_HPMS_READY(
        MSS_HPMS_READY), .CCC_0_GL0(CCC_0_GL0), .HREADY_M_iv_i_0(
        \CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv_i_0 ), 
        .HW_Boot_Engine_0_AHB_IF_HWRITE(HW_Boot_Engine_0_AHB_IF_HWRITE)
        , .N_95(N_95), .HREADY_M_iv_i_0_d(
        \CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv_i_0_d ), 
        .HREADY_M_iv_i_0_1_0(
        \CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv_i_0_1_0 ), 
        .HW_Boot_Engine_0_AXI_IF_WLAST(HW_Boot_Engine_0_AXI_IF_WLAST), 
        .HW_Boot_Engine_0_AXI_IF_BREADY(HW_Boot_Engine_0_AXI_IF_BREADY)
        , .HW_Boot_Engine_0_AXI_IF_AWVALID(
        HW_Boot_Engine_0_AXI_IF_AWVALID), 
        .HW_Boot_Engine_0_AXI_IF_AWREADY(
        HW_Boot_Engine_0_AXI_IF_AWREADY), 
        .HW_Boot_Engine_0_AXI_IF_WREADY(HW_Boot_Engine_0_AXI_IF_WREADY)
        , .HW_Boot_Engine_0_AXI_IF_BVALID(
        HW_Boot_Engine_0_AXI_IF_BVALID), .CORECONFIGP_0_APB_S_PCLK(
        CORECONFIGP_0_APB_S_PCLK), .HW_Boot_Engine_0_APB_IF_PWRITE(
        HW_Boot_Engine_0_APB_IF_PWRITE), 
        .HW_Boot_Engine_0_APB_IF_PENABLE(
        HW_Boot_Engine_0_APB_IF_PENABLE), 
        .HW_Boot_Engine_0_APB_IF_PSELx(HW_Boot_Engine_0_APB_IF_PSELx), 
        .HW_Boot_Engine_0_APB_IF_PREADY(HW_Boot_Engine_0_APB_IF_PREADY)
        , .GPIO_0_M2F_0(GPIO_0_M2F_0), .DP_SW1_c(DP_SW1_c));
    OUTBUF GPIO_1_M2F_obuf (.D(GPIO_1_M2F_c), .PAD(GPIO_1_M2F));
    INBUF DP_SW1_ibuf (.PAD(DP_SW1), .Y(DP_SW1_c));
    OUTBUF GPIO_2_M2F_obuf (.D(GPIO_2_M2F_c), .PAD(GPIO_2_M2F));
    INBUF GPIO_11_F2M_ibuf (.PAD(GPIO_11_F2M), .Y(GPIO_11_F2M_c));
    GND GND (.Y(GND_net_1));
    CoreResetP_Z6 CORERESETP_0 (.MSS_HPMS_READY(MSS_HPMS_READY), 
        .CCC_0_GL0(CCC_0_GL0), .POWER_ON_RESET_N(POWER_ON_RESET_N), 
        .MSS_RESET_N_M2F(MSS_RESET_N_M2F), .FIC_2_APB_M_PRESET_N(
        FIC_2_APB_M_PRESET_N));
    SYSRESET SYSRESET_POR (.POWER_ON_RESET_N(POWER_ON_RESET_N), 
        .DEVRST_N(DEVRST_N));
    CoreAHBLite_Z4 CoreAHBLite_0 (.HW_Boot_Engine_0_AHB_IF_HTRANS({
        \HW_Boot_Engine_0_AHB_IF_HTRANS[1] }), .ahb_fsm_current_state({
        \HW_Boot_Engine_0.AHB_IF_0.ahb_fsm_current_state[5] }), 
        .CoreAHBLite_0_AHBmslave4_HTRANS({
        \CoreAHBLite_0_AHBmslave4_HTRANS[1] }), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_14(
        \HW_Boot_Engine_0_AHB_IF_HADDR[16] ), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_0(
        \HW_Boot_Engine_0_AHB_IF_HADDR[2] ), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_1(
        \HW_Boot_Engine_0_AHB_IF_HADDR[3] ), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_2(
        \HW_Boot_Engine_0_AHB_IF_HADDR[4] ), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_10(
        \HW_Boot_Engine_0_AHB_IF_HADDR[12] ), 
        .HW_Boot_Engine_0_AHB_IF_HADDR_28(
        \HW_Boot_Engine_0_AHB_IF_HADDR[30] ), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_18(
        \HW_Boot_Engine_0_AHB_IF_HWDATA[18] ), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_7(
        \HW_Boot_Engine_0_AHB_IF_HWDATA[7] ), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_6(
        \HW_Boot_Engine_0_AHB_IF_HWDATA[6] ), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_5(
        \HW_Boot_Engine_0_AHB_IF_HWDATA[5] ), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_4(
        \HW_Boot_Engine_0_AHB_IF_HWDATA[4] ), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_3(
        \HW_Boot_Engine_0_AHB_IF_HWDATA[3] ), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_2(
        \HW_Boot_Engine_0_AHB_IF_HWDATA[2] ), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_1(
        \HW_Boot_Engine_0_AHB_IF_HWDATA[1] ), 
        .HW_Boot_Engine_0_AHB_IF_HWDATA_0(
        \HW_Boot_Engine_0_AHB_IF_HWDATA[0] ), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_29(
        \CoreAHBLite_0_AHBmslave4_HWDATA[29] ), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_7(
        \CoreAHBLite_0_AHBmslave4_HWDATA[7] ), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_6(
        \CoreAHBLite_0_AHBmslave4_HWDATA[6] ), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_5(
        \CoreAHBLite_0_AHBmslave4_HWDATA[5] ), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_4(
        \CoreAHBLite_0_AHBmslave4_HWDATA[4] ), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_3(
        \CoreAHBLite_0_AHBmslave4_HWDATA[3] ), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_2(
        \CoreAHBLite_0_AHBmslave4_HWDATA[2] ), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_1(
        \CoreAHBLite_0_AHBmslave4_HWDATA[1] ), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_0(
        \CoreAHBLite_0_AHBmslave4_HWDATA[0] ), .MSS_HPMS_READY(
        MSS_HPMS_READY), .CCC_0_GL0(CCC_0_GL0), .HREADY_M_iv_i_0_d(
        \CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv_i_0_d ), 
        .HW_Boot_Engine_0_AHB_IF_HWRITE(HW_Boot_Engine_0_AHB_IF_HWRITE)
        , .N_94_i_0(N_94_i_0), .N_95(N_95), 
        .CoreAHBLite_0_AHBmslave4_HREADY(
        CoreAHBLite_0_AHBmslave4_HREADY), .HREADY_M_iv_i_0(
        \CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv_i_0 ), 
        .HREADY_M_iv_i_0_1_0(
        \CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv_i_0_1_0 ), 
        .N_52_i_0(N_52_i_0), .N_50_i_0(N_50_i_0), .N_48_i_0(N_48_i_0), 
        .N_46_i_0(N_46_i_0), .N_767_i_0(N_767_i_0), .N_766_i_0(
        N_766_i_0), .N_765_i_0(N_765_i_0), .N_764_i_0(N_764_i_0));
    INBUF GPIO_12_F2M_ibuf (.PAD(GPIO_12_F2M), .Y(GPIO_12_F2M_c));
    CoreConfigP_Z5 CORECONFIGP_0 (.CORECONFIGP_0_MDDR_APBmslave_PADDR({
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[10] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[9] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[8] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[7] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[6] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[5] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[4] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[3] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[2] }), 
        .CORECONFIGP_0_MDDR_APBmslave_PWDATA({
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[15] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[14] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[13] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[12] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[11] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[10] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[9] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[8] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[7] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[6] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[5] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[4] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[3] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[2] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[1] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[0] }), 
        .HW_Boot_Engine_0_APB_IF_PWDATA({
        \HW_Boot_Engine_0_APB_IF_PWDATA[15] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[14] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[13] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[12] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[11] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[10] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[9] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[8] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[7] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[6] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[5] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[4] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[3] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[2] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[1] , 
        \HW_Boot_Engine_0_APB_IF_PWDATA[0] }), 
        .HW_Boot_Engine_0_APB_IF_PADDR_0(
        \HW_Boot_Engine_0_APB_IF_PADDR[2] ), 
        .HW_Boot_Engine_0_APB_IF_PADDR_1(
        \HW_Boot_Engine_0_APB_IF_PADDR[3] ), 
        .HW_Boot_Engine_0_APB_IF_PADDR_2(
        \HW_Boot_Engine_0_APB_IF_PADDR[4] ), 
        .HW_Boot_Engine_0_APB_IF_PADDR_3(
        \HW_Boot_Engine_0_APB_IF_PADDR[5] ), 
        .HW_Boot_Engine_0_APB_IF_PADDR_4(
        \HW_Boot_Engine_0_APB_IF_PADDR[6] ), 
        .HW_Boot_Engine_0_APB_IF_PADDR_5(
        \HW_Boot_Engine_0_APB_IF_PADDR[7] ), 
        .HW_Boot_Engine_0_APB_IF_PADDR_6(
        \HW_Boot_Engine_0_APB_IF_PADDR[8] ), 
        .HW_Boot_Engine_0_APB_IF_PADDR_7(
        \HW_Boot_Engine_0_APB_IF_PADDR[9] ), 
        .HW_Boot_Engine_0_APB_IF_PADDR_8(
        \HW_Boot_Engine_0_APB_IF_PADDR[10] ), 
        .HW_Boot_Engine_0_APB_IF_PADDR_10(
        \HW_Boot_Engine_0_APB_IF_PADDR[12] ), 
        .HW_Boot_Engine_0_APB_IF_PADDR_11(
        \HW_Boot_Engine_0_APB_IF_PADDR[13] ), 
        .HW_Boot_Engine_0_APB_IF_PADDR_13(
        \HW_Boot_Engine_0_APB_IF_PADDR[15] ), .MSS_HPMS_READY(
        MSS_HPMS_READY), .CORECONFIGP_0_APB_S_PCLK(
        CORECONFIGP_0_APB_S_PCLK), .HW_Boot_Engine_0_APB_IF_PREADY(
        HW_Boot_Engine_0_APB_IF_PREADY), 
        .CORECONFIGP_0_MDDR_APBmslave_PWRITE(
        CORECONFIGP_0_MDDR_APBmslave_PWRITE), 
        .HW_Boot_Engine_0_APB_IF_PWRITE(HW_Boot_Engine_0_APB_IF_PWRITE)
        , .CORECONFIGP_0_APB_S_PCLK_i_0(CORECONFIGP_0_APB_S_PCLK_i_0), 
        .CORECONFIGP_0_MDDR_APBmslave_PENABLE(
        CORECONFIGP_0_MDDR_APBmslave_PENABLE), 
        .HW_Boot_Engine_0_APB_IF_PSELx(HW_Boot_Engine_0_APB_IF_PSELx), 
        .HW_Boot_Engine_0_APB_IF_PENABLE(
        HW_Boot_Engine_0_APB_IF_PENABLE), .N_4(N_4), 
        .CORECONFIGP_0_MDDR_APBmslave_PREADY(
        CORECONFIGP_0_MDDR_APBmslave_PREADY));
    OUTBUF GPIO_0_M2F_obuf (.D(GPIO_0_M2F_c), .PAD(GPIO_0_M2F));
    VCC VCC (.Y(VCC_net_1));
    OUTBUF GPIO_4_M2F_obuf (.D(GPIO_4_M2F_c), .PAD(GPIO_4_M2F));
    OUTBUF GPIO_3_M2F_obuf (.D(GPIO_3_M2F_c), .PAD(GPIO_3_M2F));
    CodeShadowing_Fabric_CCC_0_FCCC CCC_0 (.CCC_0_GL0(CCC_0_GL0), 
        .MSS_DDR_FIC_SUBSYSTEM_LOCK(MSS_DDR_FIC_SUBSYSTEM_LOCK), 
        .FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC));
    OUTBUF GPIO_9_M2F_obuf (.D(GPIO_9_M2F_c), .PAD(GPIO_9_M2F));
    OUTBUF GPIO_8_M2F_obuf (.D(GPIO_8_M2F_c), .PAD(GPIO_8_M2F));
    CodeShadowing_Fabric_MSS CodeShadowing_Fabric_MSS_0 (.MDDR_DQS({
        MDDR_DQS[1], MDDR_DQS[0]}), .MDDR_DQ({MDDR_DQ[15], MDDR_DQ[14], 
        MDDR_DQ[13], MDDR_DQ[12], MDDR_DQ[11], MDDR_DQ[10], MDDR_DQ[9], 
        MDDR_DQ[8], MDDR_DQ[7], MDDR_DQ[6], MDDR_DQ[5], MDDR_DQ[4], 
        MDDR_DQ[3], MDDR_DQ[2], MDDR_DQ[1], MDDR_DQ[0]}), 
        .MDDR_DM_RDQS({MDDR_DM_RDQS[1], MDDR_DM_RDQS[0]}), .MDDR_BA({
        MDDR_BA[2], MDDR_BA[1], MDDR_BA[0]}), .MDDR_ADDR({
        MDDR_ADDR[15], MDDR_ADDR[14], MDDR_ADDR[13], MDDR_ADDR[12], 
        MDDR_ADDR[11], MDDR_ADDR[10], MDDR_ADDR[9], MDDR_ADDR[8], 
        MDDR_ADDR[7], MDDR_ADDR[6], MDDR_ADDR[5], MDDR_ADDR[4], 
        MDDR_ADDR[3], MDDR_ADDR[2], MDDR_ADDR[1], MDDR_ADDR[0]}), 
        .CoreAHBLite_0_AHBmslave4_HTRANS({
        \CoreAHBLite_0_AHBmslave4_HTRANS[1] }), 
        .HW_Boot_Engine_0_AXI_IF_AWADDR({
        \HW_Boot_Engine_0_AXI_IF_AWADDR[31] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[30] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[29] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[28] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[27] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[26] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[25] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[24] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[23] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[22] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[21] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[20] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[19] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[18] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[17] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[16] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[15] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[14] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[13] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[12] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[11] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[10] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[9] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[8] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[7] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[6] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[5] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[4] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[3] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[2] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[1] , 
        \HW_Boot_Engine_0_AXI_IF_AWADDR[0] }), 
        .HW_Boot_Engine_0_AXI_IF_AWSIZE({
        \HW_Boot_Engine_0_AXI_IF_AWSIZE[0] }), 
        .HW_Boot_Engine_0_AXI_IF_WDATA({
        \HW_Boot_Engine_0_AXI_IF_WDATA[63] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[62] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[61] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[60] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[59] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[58] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[57] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[56] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[55] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[54] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[53] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[52] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[51] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[50] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[49] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[48] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[47] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[46] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[45] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[44] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[43] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[42] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[41] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[40] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[39] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[38] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[37] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[36] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[35] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[34] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[33] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[32] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[31] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[30] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[29] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[28] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[27] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[26] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[25] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[24] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[23] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[22] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[21] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[20] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[19] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[18] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[17] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[16] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[15] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[14] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[13] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[12] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[11] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[10] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[9] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[8] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[7] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[6] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[5] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[4] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[3] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[2] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[1] , 
        \HW_Boot_Engine_0_AXI_IF_WDATA[0] }), 
        .CORECONFIGP_0_MDDR_APBmslave_PADDR({
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[10] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[9] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[8] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[7] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[6] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[5] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[4] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[3] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[2] }), 
        .CORECONFIGP_0_MDDR_APBmslave_PWDATA({
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[15] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[14] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[13] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[12] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[11] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[10] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[9] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[8] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[7] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[6] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[5] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[4] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[3] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[2] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[1] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[0] }), 
        .CoreAHBLite_0_AHBmslave4_HRDATA_0(
        \CoreAHBLite_0_AHBmslave4_HRDATA[0] ), 
        .CoreAHBLite_0_AHBmslave4_HRDATA_1(
        \CoreAHBLite_0_AHBmslave4_HRDATA[1] ), 
        .CoreAHBLite_0_AHBmslave4_HRDATA_2(
        \CoreAHBLite_0_AHBmslave4_HRDATA[2] ), 
        .CoreAHBLite_0_AHBmslave4_HRDATA_3(
        \CoreAHBLite_0_AHBmslave4_HRDATA[3] ), 
        .CoreAHBLite_0_AHBmslave4_HRDATA_4(
        \CoreAHBLite_0_AHBmslave4_HRDATA[4] ), 
        .CoreAHBLite_0_AHBmslave4_HRDATA_5(
        \CoreAHBLite_0_AHBmslave4_HRDATA[5] ), 
        .CoreAHBLite_0_AHBmslave4_HRDATA_6(
        \CoreAHBLite_0_AHBmslave4_HRDATA[6] ), 
        .CoreAHBLite_0_AHBmslave4_HRDATA_7(
        \CoreAHBLite_0_AHBmslave4_HRDATA[7] ), 
        .CoreAHBLite_0_AHBmslave4_HRDATA_8(
        \CoreAHBLite_0_AHBmslave4_HRDATA[8] ), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_0(
        \CoreAHBLite_0_AHBmslave4_HWDATA[0] ), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_1(
        \CoreAHBLite_0_AHBmslave4_HWDATA[1] ), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_2(
        \CoreAHBLite_0_AHBmslave4_HWDATA[2] ), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_3(
        \CoreAHBLite_0_AHBmslave4_HWDATA[3] ), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_4(
        \CoreAHBLite_0_AHBmslave4_HWDATA[4] ), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_5(
        \CoreAHBLite_0_AHBmslave4_HWDATA[5] ), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_6(
        \CoreAHBLite_0_AHBmslave4_HWDATA[6] ), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_7(
        \CoreAHBLite_0_AHBmslave4_HWDATA[7] ), 
        .CoreAHBLite_0_AHBmslave4_HWDATA_29(
        \CoreAHBLite_0_AHBmslave4_HWDATA[29] ), 
        .CORECONFIGP_0_APB_S_PCLK(CORECONFIGP_0_APB_S_PCLK), 
        .CORECONFIGP_0_APB_S_PCLK_i_0(CORECONFIGP_0_APB_S_PCLK_i_0), 
        .SPI_0_SS0(SPI_0_SS0), .SPI_0_DO(SPI_0_DO), .SPI_0_DI(SPI_0_DI)
        , .SPI_0_CLK(SPI_0_CLK), .MMUART_1_TXD(MMUART_1_TXD), 
        .MMUART_1_RXD(MMUART_1_RXD), .MDDR_WE_N(MDDR_WE_N), 
        .MDDR_RESET_N(MDDR_RESET_N), .MDDR_RAS_N(MDDR_RAS_N), 
        .MDDR_ODT(MDDR_ODT), .MDDR_DQS_TMATCH_0_OUT(
        MDDR_DQS_TMATCH_0_OUT), .MDDR_DQS_TMATCH_0_IN(
        MDDR_DQS_TMATCH_0_IN), .MDDR_CS_N(MDDR_CS_N), .MDDR_CKE(
        MDDR_CKE), .MDDR_CAS_N(MDDR_CAS_N), .GPIO_3_M2F_c(GPIO_3_M2F_c)
        , .GPIO_4_M2F_c(GPIO_4_M2F_c), .GPIO_2_M2F_c(GPIO_2_M2F_c), 
        .FIC_2_APB_M_PRESET_N(FIC_2_APB_M_PRESET_N), 
        .CoreAHBLite_0_AHBmslave4_HREADY(
        CoreAHBLite_0_AHBmslave4_HREADY), .MSS_RESET_N_M2F(
        MSS_RESET_N_M2F), .GPIO_1_M2F_c(GPIO_1_M2F_c), .GPIO_0_M2F_c(
        GPIO_0_M2F_c), .GPIO_8_M2F_c(GPIO_8_M2F_c), .GPIO_9_M2F_c(
        GPIO_9_M2F_c), .GPIO_10_M2F_c(GPIO_10_M2F_c), 
        .HW_Boot_Engine_0_AXI_IF_AWREADY(
        HW_Boot_Engine_0_AXI_IF_AWREADY), 
        .HW_Boot_Engine_0_AXI_IF_BVALID(HW_Boot_Engine_0_AXI_IF_BVALID)
        , .HW_Boot_Engine_0_AXI_IF_WREADY(
        HW_Boot_Engine_0_AXI_IF_WREADY), 
        .CORECONFIGP_0_MDDR_APBmslave_PREADY(
        CORECONFIGP_0_MDDR_APBmslave_PREADY), .N_764_i_0(N_764_i_0), 
        .N_765_i_0(N_765_i_0), .N_766_i_0(N_766_i_0), .N_767_i_0(
        N_767_i_0), .N_46_i_0(N_46_i_0), .N_48_i_0(N_48_i_0), 
        .N_94_i_0(N_94_i_0), .N_50_i_0(N_50_i_0), .N_52_i_0(N_52_i_0), 
        .GPIO_0_M2F_0(GPIO_0_M2F_0), .MSS_DDR_FIC_SUBSYSTEM_LOCK(
        MSS_DDR_FIC_SUBSYSTEM_LOCK), .GPIO_11_F2M_c(GPIO_11_F2M_c), 
        .GPIO_12_F2M_c(GPIO_12_F2M_c), .CCC_0_GL0(CCC_0_GL0), 
        .HW_Boot_Engine_0_AXI_IF_AWVALID(
        HW_Boot_Engine_0_AXI_IF_AWVALID), 
        .HW_Boot_Engine_0_AXI_IF_BREADY(HW_Boot_Engine_0_AXI_IF_BREADY)
        , .HW_Boot_Engine_0_AXI_IF_WLAST(HW_Boot_Engine_0_AXI_IF_WLAST)
        , .CORECONFIGP_0_MDDR_APBmslave_PENABLE(
        CORECONFIGP_0_MDDR_APBmslave_PENABLE), .N_4(N_4), 
        .CORECONFIGP_0_MDDR_APBmslave_PWRITE(
        CORECONFIGP_0_MDDR_APBmslave_PWRITE), .MSS_HPMS_READY(
        MSS_HPMS_READY), .MDDR_CLK_N(MDDR_CLK_N), .MDDR_CLK(MDDR_CLK));
    OUTBUF GPIO_10_M2F_obuf (.D(GPIO_10_M2F_c), .PAD(GPIO_10_M2F));
    CodeShadowing_Fabric_FABOSC_0_OSC FABOSC_0 (
        .FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC));
    
endmodule
