Project Settings
Project Name | CodeShadowing_Fabric_syn | Implementation Name | synthesis
Top Module | [auto] | Retiming | 0
Resource Sharing | 1 | Fanout Guide | 10000
Disable I/O Insertion | 0 | FSM Compiler | 1

Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
(compiler) | Complete | 68 | 332 | 0 | - | 0m:02s | - | 23-03-2016 11:55:15
(premap) | Complete | 109 | 59 | 0 | 0m:00s | 0m:00s | 150MB | 23-03-2016 11:55:17
(fpga_mapper) | Complete | 129 | 257 | 0 | 0m:03s | 0m:03s | 166MB | 23-03-2016 11:55:21
Multi-srs Generator | Complete |  |  |  | 0m:00s |  |  | 23-03-2016 11:55:16

Area Summary
Carry Cells | 170 | Sequential Cells | 516
DSP Blocks (MACC) (dsp_used) | 0 | I/O Cells | 66
Global Clock Buffers | 4 | Block Rams (RAM1K18) (v_ram) | 7
LUTs (total_luts) | 615 |  |

Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
CodeShadowing_Fabric_CCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | 134.5 MHz | 2.563
CodeShadowing_Fabric_MSS|FIC_2_APB_M_PCLK_inferred_clock | 100.0 MHz | 165.1 MHz | 2.545
System | 100.0 MHz | 1029.4 MHz | 9.029

Optimizations Summary
Combined Clock Conversion | 1 / 1 |  |