//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Wed Mar 23 11:44:43 2016
// Version: v11.7 11.7.0.119
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

// HW_Boot_Engine
module HW_Boot_Engine(
    // Inputs
    APB_CLK,
    ARREADY,
    AWREADY,
    BID,
    BRESP,
    BVALID,
    CLK,
    HRDATA,
    HREADY,
    HRESP,
    PRDATA,
    PREADY,
    PSLVERR,
    RDATA,
    RESETn,
    RID,
    RLAST,
    RRESP,
    RVALID,
    START_CODE_SHADOW,
    WREADY,
    // Outputs
    ARADDR,
    ARBURST,
    ARID,
    ARLEN,
    ARLOCK,
    ARSIZE,
    ARVALID,
    AWADDR,
    AWBURST,
    AWID,
    AWLEN,
    AWLOCK,
    AWSIZE,
    AWVALID,
    BREADY,
    HADDR,
    HBURST,
    HPROT,
    HSIZE,
    HTRANS,
    HWDATA,
    HWRITE,
    M3_RESETn,
    PADDR,
    PENABLE,
    PSEL,
    PWDATA,
    PWRITE,
    RREADY,
    WDATA,
    WID,
    WLAST,
    WSTRB,
    WVALID
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input         APB_CLK;
input         ARREADY;
input         AWREADY;
input  [3:0]  BID;
input  [1:0]  BRESP;
input         BVALID;
input         CLK;
input  [31:0] HRDATA;
input         HREADY;
input  [1:0]  HRESP;
input  [15:0] PRDATA;
input         PREADY;
input         PSLVERR;
input  [63:0] RDATA;
input         RESETn;
input  [3:0]  RID;
input         RLAST;
input  [1:0]  RRESP;
input         RVALID;
input         START_CODE_SHADOW;
input         WREADY;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output [31:0] ARADDR;
output [1:0]  ARBURST;
output [3:0]  ARID;
output [3:0]  ARLEN;
output [1:0]  ARLOCK;
output [1:0]  ARSIZE;
output        ARVALID;
output [31:0] AWADDR;
output [1:0]  AWBURST;
output [3:0]  AWID;
output [3:0]  AWLEN;
output [1:0]  AWLOCK;
output [2:0]  AWSIZE;
output        AWVALID;
output        BREADY;
output [31:0] HADDR;
output [2:0]  HBURST;
output [3:0]  HPROT;
output [2:0]  HSIZE;
output [1:0]  HTRANS;
output [31:0] HWDATA;
output        HWRITE;
output        M3_RESETn;
output [15:2] PADDR;
output        PENABLE;
output        PSEL;
output [15:0] PWDATA;
output        PWRITE;
output        RREADY;
output [63:0] WDATA;
output [3:0]  WID;
output        WLAST;
output [7:0]  WSTRB;
output        WVALID;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire   [31:0] AHB_IF_HADDR;
wire   [2:0]  AHB_IF_HBURST;
wire   [3:0]  AHB_IF_HPROT;
wire   [31:0] HRDATA;
wire          HREADY;
wire   [1:0]  HRESP;
wire   [2:0]  AHB_IF_HSIZE;
wire   [1:0]  AHB_IF_HTRANS;
wire   [31:0] AHB_IF_HWDATA;
wire          AHB_IF_HWRITE;
wire          AHB_IF_0_AHB_BUSY;
wire   [31:0] AHB_IF_0_DATAOUT;
wire          APB_CLK;
wire   [15:2] APB_IF_PADDR;
wire          APB_IF_PENABLE;
wire   [15:0] PRDATA;
wire          PREADY;
wire          APB_IF_PSELx;
wire          PSLVERR;
wire   [15:0] APB_IF_PWDATA;
wire          APB_IF_PWRITE;
wire   [31:0] AXI_IF_ARADDR;
wire   [1:0]  AXI_IF_ARBURST;
wire   [3:0]  AXI_IF_ARID;
wire   [3:0]  AXI_IF_ARLEN;
wire   [1:0]  AXI_IF_ARLOCK;
wire          ARREADY;
wire   [1:0]  AXI_IF_ARSIZE;
wire          AXI_IF_ARVALID;
wire   [31:0] AXI_IF_AWADDR;
wire   [1:0]  AXI_IF_AWBURST;
wire   [3:0]  AXI_IF_AWID;
wire   [3:0]  AXI_IF_AWLEN;
wire   [1:0]  AXI_IF_AWLOCK;
wire          AWREADY;
wire   [2:0]  AXI_IF_AWSIZE;
wire          AXI_IF_AWVALID;
wire   [3:0]  BID;
wire          AXI_IF_BREADY;
wire   [1:0]  BRESP;
wire          BVALID;
wire   [63:0] RDATA;
wire   [3:0]  RID;
wire          RLAST;
wire          AXI_IF_RREADY;
wire   [1:0]  RRESP;
wire          RVALID;
wire   [63:0] AXI_IF_WDATA;
wire   [3:0]  AXI_IF_WID;
wire          AXI_IF_WLAST;
wire          WREADY;
wire   [7:0]  AXI_IF_WSTRB;
wire          AXI_IF_WVALID;
wire          AXI_IF_0_AXI_BUSY;
wire          CLK;
wire          M3_RESETn_net_0;
wire          MDDR_Config_0_DRAM_Ready;
wire          RESETn;
wire   [31:0] SPI_to_MDDR_0_ADDR;
wire   [63:0] SPI_to_MDDR_0_AXI_DATA;
wire          SPI_to_MDDR_0_AXI_WRITE;
wire   [31:0] SPI_to_MDDR_0_DATAOUT;
wire          SPI_to_MDDR_0_READ;
wire          SPI_to_MDDR_0_WRITE;
wire          START_CODE_SHADOW;
wire          AXI_IF_AWVALID_net_0;
wire          AXI_IF_WLAST_net_0;
wire          AXI_IF_WVALID_net_0;
wire          AXI_IF_BREADY_net_0;
wire          AXI_IF_ARVALID_net_0;
wire          AXI_IF_RREADY_net_0;
wire          APB_IF_PENABLE_net_0;
wire          APB_IF_PWRITE_net_0;
wire          APB_IF_PSELx_net_0;
wire          M3_RESETn_net_1;
wire          AHB_IF_HWRITE_net_0;
wire   [3:0]  AXI_IF_AWID_net_0;
wire   [31:0] AXI_IF_AWADDR_net_0;
wire   [3:0]  AXI_IF_AWLEN_net_0;
wire   [2:0]  AXI_IF_AWSIZE_net_0;
wire   [1:0]  AXI_IF_AWBURST_net_0;
wire   [1:0]  AXI_IF_AWLOCK_net_0;
wire   [3:0]  AXI_IF_WID_net_0;
wire   [63:0] AXI_IF_WDATA_net_0;
wire   [7:0]  AXI_IF_WSTRB_net_0;
wire   [3:0]  AXI_IF_ARID_net_0;
wire   [31:0] AXI_IF_ARADDR_net_0;
wire   [3:0]  AXI_IF_ARLEN_net_0;
wire   [1:0]  AXI_IF_ARSIZE_net_0;
wire   [1:0]  AXI_IF_ARBURST_net_0;
wire   [1:0]  AXI_IF_ARLOCK_net_0;
wire   [15:2] APB_IF_PADDR_net_0;
wire   [15:0] APB_IF_PWDATA_net_0;
wire   [31:0] AHB_IF_HADDR_net_0;
wire   [1:0]  AHB_IF_HTRANS_net_0;
wire   [2:0]  AHB_IF_HSIZE_net_0;
wire   [2:0]  AHB_IF_HBURST_net_0;
wire   [3:0]  AHB_IF_HPROT_net_0;
wire   [31:0] AHB_IF_HWDATA_net_0;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign AXI_IF_AWVALID_net_0 = AXI_IF_AWVALID;
assign AWVALID              = AXI_IF_AWVALID_net_0;
assign AXI_IF_WLAST_net_0   = AXI_IF_WLAST;
assign WLAST                = AXI_IF_WLAST_net_0;
assign AXI_IF_WVALID_net_0  = AXI_IF_WVALID;
assign WVALID               = AXI_IF_WVALID_net_0;
assign AXI_IF_BREADY_net_0  = AXI_IF_BREADY;
assign BREADY               = AXI_IF_BREADY_net_0;
assign AXI_IF_ARVALID_net_0 = AXI_IF_ARVALID;
assign ARVALID              = AXI_IF_ARVALID_net_0;
assign AXI_IF_RREADY_net_0  = AXI_IF_RREADY;
assign RREADY               = AXI_IF_RREADY_net_0;
assign APB_IF_PENABLE_net_0 = APB_IF_PENABLE;
assign PENABLE              = APB_IF_PENABLE_net_0;
assign APB_IF_PWRITE_net_0  = APB_IF_PWRITE;
assign PWRITE               = APB_IF_PWRITE_net_0;
assign APB_IF_PSELx_net_0   = APB_IF_PSELx;
assign PSEL                 = APB_IF_PSELx_net_0;
assign M3_RESETn_net_1      = M3_RESETn_net_0;
assign M3_RESETn            = M3_RESETn_net_1;
assign AHB_IF_HWRITE_net_0  = AHB_IF_HWRITE;
assign HWRITE               = AHB_IF_HWRITE_net_0;
assign AXI_IF_AWID_net_0    = AXI_IF_AWID;
assign AWID[3:0]            = AXI_IF_AWID_net_0;
assign AXI_IF_AWADDR_net_0  = AXI_IF_AWADDR;
assign AWADDR[31:0]         = AXI_IF_AWADDR_net_0;
assign AXI_IF_AWLEN_net_0   = AXI_IF_AWLEN;
assign AWLEN[3:0]           = AXI_IF_AWLEN_net_0;
assign AXI_IF_AWSIZE_net_0  = AXI_IF_AWSIZE;
assign AWSIZE[2:0]          = AXI_IF_AWSIZE_net_0;
assign AXI_IF_AWBURST_net_0 = AXI_IF_AWBURST;
assign AWBURST[1:0]         = AXI_IF_AWBURST_net_0;
assign AXI_IF_AWLOCK_net_0  = AXI_IF_AWLOCK;
assign AWLOCK[1:0]          = AXI_IF_AWLOCK_net_0;
assign AXI_IF_WID_net_0     = AXI_IF_WID;
assign WID[3:0]             = AXI_IF_WID_net_0;
assign AXI_IF_WDATA_net_0   = AXI_IF_WDATA;
assign WDATA[63:0]          = AXI_IF_WDATA_net_0;
assign AXI_IF_WSTRB_net_0   = AXI_IF_WSTRB;
assign WSTRB[7:0]           = AXI_IF_WSTRB_net_0;
assign AXI_IF_ARID_net_0    = AXI_IF_ARID;
assign ARID[3:0]            = AXI_IF_ARID_net_0;
assign AXI_IF_ARADDR_net_0  = AXI_IF_ARADDR;
assign ARADDR[31:0]         = AXI_IF_ARADDR_net_0;
assign AXI_IF_ARLEN_net_0   = AXI_IF_ARLEN;
assign ARLEN[3:0]           = AXI_IF_ARLEN_net_0;
assign AXI_IF_ARSIZE_net_0  = AXI_IF_ARSIZE;
assign ARSIZE[1:0]          = AXI_IF_ARSIZE_net_0;
assign AXI_IF_ARBURST_net_0 = AXI_IF_ARBURST;
assign ARBURST[1:0]         = AXI_IF_ARBURST_net_0;
assign AXI_IF_ARLOCK_net_0  = AXI_IF_ARLOCK;
assign ARLOCK[1:0]          = AXI_IF_ARLOCK_net_0;
assign APB_IF_PADDR_net_0   = APB_IF_PADDR;
assign PADDR[15:2]          = APB_IF_PADDR_net_0;
assign APB_IF_PWDATA_net_0  = APB_IF_PWDATA;
assign PWDATA[15:0]         = APB_IF_PWDATA_net_0;
assign AHB_IF_HADDR_net_0   = AHB_IF_HADDR;
assign HADDR[31:0]          = AHB_IF_HADDR_net_0;
assign AHB_IF_HTRANS_net_0  = AHB_IF_HTRANS;
assign HTRANS[1:0]          = AHB_IF_HTRANS_net_0;
assign AHB_IF_HSIZE_net_0   = AHB_IF_HSIZE;
assign HSIZE[2:0]           = AHB_IF_HSIZE_net_0;
assign AHB_IF_HBURST_net_0  = AHB_IF_HBURST;
assign HBURST[2:0]          = AHB_IF_HBURST_net_0;
assign AHB_IF_HPROT_net_0   = AHB_IF_HPROT;
assign HPROT[3:0]           = AHB_IF_HPROT_net_0;
assign AHB_IF_HWDATA_net_0  = AHB_IF_HWDATA;
assign HWDATA[31:0]         = AHB_IF_HWDATA_net_0;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------AHB_IF
AHB_IF #( 
        .Data_size   ( 32 ),
        .Idle_1      ( 0 ),
        .Read_FIC_0  ( 4 ),
        .Read_FIC_1  ( 5 ),
        .Read_FIC_2  ( 6 ),
        .Write_FIC_0 ( 1 ),
        .Write_FIC_1 ( 2 ),
        .Write_FIC_2 ( 3 ) )
AHB_IF_0(
        // Inputs
        .HCLK     ( CLK ),
        .HRESETn  ( RESETn ),
        .READ     ( SPI_to_MDDR_0_READ ),
        .WRITE    ( SPI_to_MDDR_0_WRITE ),
        .HREADY   ( HREADY ),
        .ADDR     ( SPI_to_MDDR_0_ADDR ),
        .DATAIN   ( SPI_to_MDDR_0_DATAOUT ),
        .HRDATA   ( HRDATA ),
        .HRESP    ( HRESP ),
        // Outputs
        .HWRITE   ( AHB_IF_HWRITE ),
        .AHB_BUSY ( AHB_IF_0_AHB_BUSY ),
        .DATAOUT  ( AHB_IF_0_DATAOUT ),
        .HADDR    ( AHB_IF_HADDR ),
        .HTRANS   ( AHB_IF_HTRANS ),
        .HSIZE    ( AHB_IF_HSIZE ),
        .HBURST   ( AHB_IF_HBURST ),
        .HPROT    ( AHB_IF_HPROT ),
        .HWDATA   ( AHB_IF_HWDATA ),
        .RESP_err (  ) 
        );

//--------AXI_IF
AXI_IF #( 
        .Bresp_0 ( 4 ),
        .Idle_0  ( 0 ),
        .Idle_1  ( 1 ),
        .Write_0 ( 2 ),
        .Write_1 ( 3 ) )
AXI_IF_0(
        // Inputs
        .CLK      ( CLK ),
        .RESETn   ( MDDR_Config_0_DRAM_Ready ),
        .WRITE    ( SPI_to_MDDR_0_AXI_WRITE ),
        .AWREADY  ( AWREADY ),
        .WREADY   ( WREADY ),
        .BVALID   ( BVALID ),
        .ARREADY  ( ARREADY ),
        .RLAST    ( RLAST ),
        .RVALID   ( RVALID ),
        .DATA_IN  ( SPI_to_MDDR_0_AXI_DATA ),
        .BID      ( BID ),
        .BRESP    ( BRESP ),
        .RID      ( RID ),
        .RDATA    ( RDATA ),
        .RRESP    ( RRESP ),
        // Outputs
        .AXI_BUSY ( AXI_IF_0_AXI_BUSY ),
        .AWVALID  ( AXI_IF_AWVALID ),
        .WLAST    ( AXI_IF_WLAST ),
        .WVALID   ( AXI_IF_WVALID ),
        .BREADY   ( AXI_IF_BREADY ),
        .ARVALID  ( AXI_IF_ARVALID ),
        .RREADY   ( AXI_IF_RREADY ),
        .AWID     ( AXI_IF_AWID ),
        .AWADDR   ( AXI_IF_AWADDR ),
        .AWLEN    ( AXI_IF_AWLEN ),
        .AWSIZE   ( AXI_IF_AWSIZE ),
        .AWLOCK   ( AXI_IF_AWLOCK ),
        .AWBURST  ( AXI_IF_AWBURST ),
        .WID      ( AXI_IF_WID ),
        .WSTRB    ( AXI_IF_WSTRB ),
        .WDATA    ( AXI_IF_WDATA ),
        .ARID     ( AXI_IF_ARID ),
        .ARADDR   ( AXI_IF_ARADDR ),
        .ARLEN    ( AXI_IF_ARLEN ),
        .ARSIZE   ( AXI_IF_ARSIZE ),
        .ARLOCK   ( AXI_IF_ARLOCK ),
        .ARBURST  ( AXI_IF_ARBURST ) 
        );

//--------MDDR_Config
MDDR_Config #( 
        .Idle    ( 0 ),
        .Read_0  ( 4 ),
        .Read_1  ( 5 ),
        .Write_0 ( 1 ),
        .Write_1 ( 2 ),
        .Write_2 ( 3 ),
        .Write_3 ( 6 ) )
MDDR_Config_0(
        // Inputs
        .CLK        ( APB_CLK ),
        .RESETn     ( RESETn ),
        .PREADY     ( PREADY ),
        .PSLVERR    ( PSLVERR ),
        .PRDATA     ( PRDATA ),
        // Outputs
        .PSEL       ( APB_IF_PSELx ),
        .PENABLE    ( APB_IF_PENABLE ),
        .PWRITE     ( APB_IF_PWRITE ),
        .DRAM_Ready ( MDDR_Config_0_DRAM_Ready ),
        .PWDATA     ( APB_IF_PWDATA ),
        .PADDR      ( APB_IF_PADDR ) 
        );

//--------SPI_to_MDDR
SPI_to_MDDR #( 
        .block_length   ( 1028 ),
        .File_size      ( 128 ),
        .final_st       ( 15 ),
        .Idle           ( 0 ),
        .next_block     ( 11 ),
        .Read           ( 7 ),
        .Read2          ( 8 ),
        .Read3          ( 9 ),
        .Read_status    ( 5 ),
        .Read_status2   ( 6 ),
        .Read_statusTx  ( 3 ),
        .Read_statusTx2 ( 4 ),
        .Reg_init       ( 1 ),
        .SPI_disable    ( 13 ),
        .stop_st        ( 12 ),
        .Write_cmd      ( 2 ),
        .write_ddr      ( 10 ) )
SPI_to_MDDR_0(
        // Inputs
        .CLK               ( CLK ),
        .RESETn            ( RESETn ),
        .BUSY              ( AHB_IF_0_AHB_BUSY ),
        .AXI_BUSY          ( AXI_IF_0_AXI_BUSY ),
        .START_CODE_SHADOW ( START_CODE_SHADOW ),
        .DATAIN            ( AHB_IF_0_DATAOUT ),
        // Outputs
        .READ              ( SPI_to_MDDR_0_READ ),
        .WRITE             ( SPI_to_MDDR_0_WRITE ),
        .AXI_WRITE         ( SPI_to_MDDR_0_AXI_WRITE ),
        .M3_RESETn         ( M3_RESETn_net_0 ),
        .ADDR              ( SPI_to_MDDR_0_ADDR ),
        .DATAOUT           ( SPI_to_MDDR_0_DATAOUT ),
        .AXI_DATA          ( SPI_to_MDDR_0_AXI_DATA ) 
        );


endmodule
