`

    #Build: Synplify Pro I-2013.09M-SP1-1 , Build 034R, Jan 17 2014
    #install: E:\Microsemi\Libero_v11.4\Synopsys\synplify_I201309MSP1-1
    #OS: Windows 7 6.1
    #Hostname: W764-KUMARJ

    #Implementation: synthesis

    $ Start of Compile
    #Wed Sep 03 12:04:45 2014

    Synopsys Verilog Compiler, version comp201309rcp1, Build 078R, built Jan 14 2014
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

    @I::"E:\Microsemi\Libero_v11.4\Synopsys\synplify_I201309MSP1-1\lib\generic\smartfusion2.v"
    @I::"E:\Microsemi\Libero_v11.4\Synopsys\synplify_I201309MSP1-1\lib\vlog\umr_capim.v"
    @I::"E:\Microsemi\Libero_v11.4\Synopsys\synplify_I201309MSP1-1\lib\vlog\scemi_objects.v"
    @I::"E:\Microsemi\Libero_v11.4\Synopsys\synplify_I201309MSP1-1\lib\vlog\scemi_pipes.svh"
    @I::"E:\Microsemi\Libero_v11.4\Synopsys\synplify_I201309MSP1-1\lib\vlog\hypermods.v"
    @I::"E:\Libero_11.4_updates\SF2\HWBootEngine_method\system_builder_approch\CodeShadowing_Fabric\component\work\CodeShadowing_Fabric_MSS\CodeShadowing_Fabric_MSS_syn.v"
    @I::"E:\Libero_11.4_updates\SF2\HWBootEngine_method\system_builder_approch\CodeShadowing_Fabric\component\work\CodeShadowing_Fabric_MSS\CodeShadowing_Fabric_MSS.v"
    Verilog syntax check successful!
    Selecting top level module CodeShadowing_Fabric_MSS
    @N:CG364 : smartfusion2.v(274) | Synthesizing module OUTBUF

    @N:CG364 : smartfusion2.v(326) | Synthesizing module OUTBUF_DIFF

    @N:CG364 : smartfusion2.v(286) | Synthesizing module BIBUF

    @N:CG364 : smartfusion2.v(338) | Synthesizing module BIBUF_DIFF

    @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF

    @N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF

    @N:CG364 : CodeShadowing_Fabric_MSS_syn.v(5) | Synthesizing module MSS_120

    @N:CG364 : CodeShadowing_Fabric_MSS.v(9) | Synthesizing module CodeShadowing_Fabric_MSS

    @W:CL247 : CodeShadowing_Fabric_MSS.v(125) | Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused

    @END

    At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 72MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed Sep 03 12:04:45 2014

    ###########################################################]
    Pre-mapping Report

    Synopsys Generic Technology Pre-mapping, Version mapact, Build 004R, Built May 28 2014 16:50:32
    Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
    Product Version I-2013.09M-SP1-1

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Linked File: CodeShadowing_Fabric_MSS_scck.rpt
    Printing clock  summary report in "E:\Libero_11.4_updates\SF2\HWBootEngine_method\system_builder_approch\CodeShadowing_Fabric\synthesis\CodeShadowing_Fabric_MSS_scck.rpt" file
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 104MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 106MB)

    syn_allowed_resources : blockrams=236  set on top level netlist CodeShadowing_Fabric_MSS

    Clock Summary
    **************

    Start                                        Requested     Requested     Clock        Clock
    Clock                                        Frequency     Period        Type         Group
    ---------------------------------------------------------------------------------------------------------
    CodeShadowing_Fabric_MSS|MCCC_CLK_BASE       100.0 MHz     10.000        inferred     Inferred_clkgroup_1
    CodeShadowing_Fabric_MSS|MDDR_APB_S_PCLK     100.0 MHz     10.000        inferred     Inferred_clkgroup_0
    =========================================================================================================

    @W:MT530 : codeshadowing_fabric_mss.v(1451) | Found inferred clock CodeShadowing_Fabric_MSS|MDDR_APB_S_PCLK which controls 0 sequential elements including MSS_ADLIB_INST. This clock has no specified timing constraint which may adversely impact design performance.
    @W:MT530 : codeshadowing_fabric_mss.v(1451) | Found inferred clock CodeShadowing_Fabric_MSS|MCCC_CLK_BASE which controls 0 sequential elements including MSS_ADLIB_INST. This clock has no specified timing constraint which may adversely impact design performance.

    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file E:\Libero_11.4_updates\SF2\HWBootEngine_method\system_builder_approch\CodeShadowing_Fabric\synthesis\CodeShadowing_Fabric_MSS.sap.
    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 135MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed Sep 03 12:04:47 2014

    ###########################################################]
    Map & Optimize Report

    Synopsys Generic Technology Mapper, Version mapact, Build 004R, Built May 28 2014 16:50:32
    Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
    Product Version I-2013.09M-SP1-1

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

    Available hyper_sources - for debug and ip models
    	None Found

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

    Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

    Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

    Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB)

    Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    ------------------------------------------------------------

    Added 0 Buffers
    Added 0 Cells via replication
    	Added 0 Sequential Cells via replication
    	Added 0 Combinational Cells via replication

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

    Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

    #### START OF CLOCK OPTIMIZATION REPORT #####[

    Clock optimization not enabled
    2 non-gated/non-generated clock tree(s) driving 2 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    ClockId0001        MDDR_APB_S_PCLK     port                   1          MSS_ADLIB_INST
    ClockId0002        MCCC_CLK_BASE       port                   1          MSS_ADLIB_INST
    =======================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######]

    Writing Analyst data base E:\Libero_11.4_updates\SF2\HWBootEngine_method\system_builder_approch\CodeShadowing_Fabric\synthesis\CodeShadowing_Fabric_MSS.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 135MB)

    Writing EDIF Netlist and constraint files
    @N:BW103 :  | Synopsys Constraint File time units using default value of 1ns
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF
    I-2013.09M-SP1-1

    Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 134MB peak: 136MB)

    @W:MT420 :  | Found inferred clock CodeShadowing_Fabric_MSS|MCCC_CLK_BASE with period 10.00ns. Please declare a user-defined clock on object "p:MCCC_CLK_BASE"

    @W:MT420 :  | Found inferred clock CodeShadowing_Fabric_MSS|MDDR_APB_S_PCLK with period 10.00ns. Please declare a user-defined clock on object "p:MDDR_APB_S_PCLK"

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Wed Sep 03 12:04:49 2014
    #

    Top view:               CodeShadowing_Fabric_MSS
    Requested Frequency:    100.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing.

    @N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock.

    Performance Summary
    *******************

    Worst slack in design: NA

                                                 Requested     Estimated     Requested     Estimated               Clock        Clock
    Starting Clock                               Frequency     Frequency     Period        Period        Slack     Type         Group
    -----------------------------------------------------------------------------------------------------------------------------------------------
    CodeShadowing_Fabric_MSS|MCCC_CLK_BASE       100.0 MHz     NA            10.000        NA            NA        inferred     Inferred_clkgroup_1
    CodeShadowing_Fabric_MSS|MDDR_APB_S_PCLK     100.0 MHz     NA            10.000        NA            NA        inferred     Inferred_clkgroup_0
    ===============================================================================================================================================

    Clock Relationships
    *******************

    Clocks            |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    --------------------------------------------------------------------------------------------------------
    Starting  Ending  |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
    --------------------------------------------------------------------------------------------------------
    ========================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ##### END OF TIMING REPORT #####]

    ---------------------------------------
    Resource Usage Report for CodeShadowing_Fabric_MSS

    Mapping to part: m2s150tfc1152-1
    Cell usage:
    MSS_120         1 use

    Sequential Cells:
    SLE            0 uses

    DSP Blocks:    0

    I/O ports: 570
    I/O primitives: 566
    BIBUF          20 uses
    BIBUF_DIFF     2 uses
    INBUF          319 uses
    OUTBUF         222 uses
    OUTBUF_DIFF    1 use
    TRIBUFF        2 uses

    Total LUTs:    0

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 48MB peak: 136MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed Sep 03 12:04:49 2014

    ###########################################################]

`