Project Settings Project Name CoreTSE_M2S090_syn Implementation Name synthesis Top Module CoreTSE_M2S090 Retiming 0 Resource Sharing 1 Fanout Guide 10000 Disable I/O Insertion 0 Disable Sequential Optimizations 0 Run Status Job Name Status CPU Time Real Time Memory Date/Time (compiler) Complete 382 449 0 - 00m:09s - 3/14/2017 3:02:38 PM (premap) Complete 93 41 0 0m:03s 0m:03s 208MB 3/14/2017 3:02:44 PM (fpga_mapper) Complete 202 103 0 01m:02s 01m:03s 326MB 3/14/2017 3:03:47 PM Multi-srs Generator Complete 00m:01s 3/14/2017 3:02:40 PM Area Summary Carry Cells 1514 Sequential Cells 5293 DSP Blocks (MACC) (dsp_used) 0 I/O Cells 26 Global Clock Buffers 27 RAM1K18 (v_ram) 16 LUTs (total_luts) 10108 Timing Summary Clock Name Req Freq Est Freq Slack CLK1_PAD 50.0 MHz NA NA CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock 100.0 MHz 149.0 MHz 3.290 CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB 12.5 MHz 108.5 MHz 35.393 CoreTSE_M2S090_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock 100.0 MHz NA NA FCCC_0/GL0 50.0 MHz 34.8 MHz -1.470 FCCC_1/GL0 125.0 MHz 95.4 MHz -0.794 FCCC_2/GL0 125.0 MHz 148.8 MHz 2.347 FCCC_3/GL0 125.0 MHz NA NA FCCC_3/GL1 125.0 MHz 87.1 MHz -1.739 OSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 431.2 MHz 17.681 SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] 125.0 MHz NA NA SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1] 125.0 MHz NA NA System 100.0 MHz 477.6 MHz 7.906 Optimizations Summary Combined Clock Conversion 3 / 5