#Build: Synplify Pro L-2016.09M-2, Build 065R, Nov 16 2016 #install: D:\Microsemi\Libero_SoC_v11.8\SynplifyPro #OS: Windows 7 6.1 #Hostname: W764-AITHAS # Tue Mar 14 15:02:29 2017 #Implementation: synthesis Synopsys HDL Compiler, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Synopsys Verilog Compiler, version comp2016q3p1, Build 127R, built Nov 24 2016 @N: : | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. @I::"D:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.v" (library work) @I::"D:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\msgmii_clkrst.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\msgmii_cnvrxi.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\msgmii_cnvrxo.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\msgmii_cnvtxi.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\msgmii_cnvtxo.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\peanx_sync.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\msgmii_peanx_top.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\r10b8b.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perex_pcs.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perex_pma.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petbm.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petcr.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\t8b10b.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petex_top.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\msgmii_tbi.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\msgmii_core.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\rx4096x36.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxfif_clkrst.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxfif_hst.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxrfif_fab.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxrfif_sys.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxtfif_fab.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxtfif_sys.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxtfif_wtm.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxfif.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\arfque.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\decoder.v" (library work) @I:"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\decoder.v":"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\include.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\dmarx.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\dmatx.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\dma_dual.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\slave.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\tsm_sysreg.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\mahbe_dual.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\mmcxwol.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_cntrl.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_eim.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_ladd.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_linc.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_sadd.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_sinc.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_sinchd.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_sincnf.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_store.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pecar.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pehst.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemgt.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pecrc.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perfn_top.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\permc_top.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petfn_top.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petmc_top.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pe_mcxmac_core.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pe_mcxmac.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\sib_sync_2flp.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\sib_sync_pulse.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\si_sal.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\tsmac_ahb_top.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\tx2048x40.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\CoreTSE_AHB_top.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\CoreTSE_AHB.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\FCCC_0\CoreTSE_M2S090_FCCC_0_FCCC.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\FCCC_1\CoreTSE_M2S090_FCCC_1_FCCC.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\FCCC_2\CoreTSE_M2S090_FCCC_2_FCCC.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\FCCC_3\CoreTSE_M2S090_FCCC_3_FCCC.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090_MSS\CoreTSE_M2S090_MSS_syn.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090_MSS\CoreTSE_M2S090_MSS.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\OSC_0\CoreTSE_M2S090_OSC_0_OSC.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\SERDES_IF2_0\CoreTSE_M2S090_SERDES_IF2_0_SERDES_IF2_syn.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\SERDES_IF2_0\CoreTSE_M2S090_SERDES_IF2_0_SERDES_IF2.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\hdl\MON_ANX.v" (library work) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v" (library COREAHBLITE_LIB) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v" (library COREAHBLITE_LIB) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v" (library COREAHBLITE_LIB) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v" (library COREAHBLITE_LIB) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v" (library COREAHBLITE_LIB) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v" (library COREAHBLITE_LIB) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v" (library COREAHBLITE_LIB) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\AHBLSramIf.v" (library COREAHBLSRAM_LIB) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v" (library COREAHBLSRAM_LIB) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\usram_128to9216x8.v" (library COREAHBLSRAM_LIB) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v" (library COREAHBLSRAM_LIB) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v" (library COREAHBLSRAM_LIB) @I::"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CoreTSE_M2S090.v" (library work) Verilog syntax check successful! Selecting top level module CoreTSE_M2S090 @N:CG364 : smartfusion2.v(126) | Synthesizing module AND2 in library work. @N:CG364 : smartfusion2.v(286) | Synthesizing module BIBUF in library work. @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT in library work. @W:CG775 : coreahblite.v(23) | Found Component CoreAHBLite in library COREAHBLITE_LIB @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000101000 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z1 @N:CG364 : coreahblite_defaultslavesm.v(20) | Synthesizing module COREAHBLITE_DEFAULTSLAVESM in library COREAHBLITE_LIB. SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 HRESPEXTEND=1'b1 Generated name = COREAHBLITE_DEFAULTSLAVESM_0s_0_1 @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000101000 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_0_40_0s_0_1_0 @W:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing. @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000100100 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z2 @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000100100 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_0_36_0s_0_1_0 @W:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing. @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000000 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z3 @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_0_0_0s_0_1_0 @W:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing. @N:CG364 : coreahblite_slavearbiter.v(20) | Synthesizing module COREAHBLITE_SLAVEARBITER in library COREAHBLITE_LIB. SYNC_RESET=32'b00000000000000000000000000000000 M0EXTEND=4'b0000 M0DONE=4'b0001 M0LOCK=4'b0010 M0LOCKEXTEND=4'b0011 M1EXTEND=4'b0100 M1DONE=4'b0101 M1LOCK=4'b0110 M1LOCKEXTEND=4'b0111 M2EXTEND=4'b1000 M2DONE=4'b1001 M2LOCK=4'b1010 M2LOCKEXTEND=4'b1011 M3EXTEND=4'b1100 M3DONE=4'b1101 M3LOCK=4'b1110 M3LOCKEXTEND=4'b1111 MASTER_0=4'b0001 MASTER_1=4'b0010 MASTER_2=4'b0100 MASTER_3=4'b1000 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVEARBITER_Z4 @N:CG364 : coreahblite_slavestage.v(22) | Synthesizing module COREAHBLITE_SLAVESTAGE in library COREAHBLITE_LIB. SYNC_RESET=32'b00000000000000000000000000000000 TRN_IDLE=1'b0 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVESTAGE_0s_0_0 @N:CG364 : coreahblite_matrix4x16.v(23) | Synthesizing module COREAHBLITE_MATRIX4X16 in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M0_AHBSLOTENABLE=17'b00000000000101000 M1_AHBSLOTENABLE=17'b00000000000100100 M2_AHBSLOTENABLE=17'b00000000000100100 M3_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = COREAHBLITE_MATRIX4X16_1_1_0_40_36_36_0_0s @N:CG364 : coreahblite.v(23) | Synthesizing module CoreAHBLite in library COREAHBLITE_LIB. FAMILY=6'b010011 MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 M0_AHBSLOT0ENABLE=1'b0 M0_AHBSLOT1ENABLE=1'b0 M0_AHBSLOT2ENABLE=1'b0 M0_AHBSLOT3ENABLE=1'b1 M0_AHBSLOT4ENABLE=1'b0 M0_AHBSLOT5ENABLE=1'b1 M0_AHBSLOT6ENABLE=1'b0 M0_AHBSLOT7ENABLE=1'b0 M0_AHBSLOT8ENABLE=1'b0 M0_AHBSLOT9ENABLE=1'b0 M0_AHBSLOT10ENABLE=1'b0 M0_AHBSLOT11ENABLE=1'b0 M0_AHBSLOT12ENABLE=1'b0 M0_AHBSLOT13ENABLE=1'b0 M0_AHBSLOT14ENABLE=1'b0 M0_AHBSLOT15ENABLE=1'b0 M0_AHBSLOT16ENABLE=1'b0 M1_AHBSLOT0ENABLE=1'b0 M1_AHBSLOT1ENABLE=1'b0 M1_AHBSLOT2ENABLE=1'b1 M1_AHBSLOT3ENABLE=1'b0 M1_AHBSLOT4ENABLE=1'b0 M1_AHBSLOT5ENABLE=1'b1 M1_AHBSLOT6ENABLE=1'b0 M1_AHBSLOT7ENABLE=1'b0 M1_AHBSLOT8ENABLE=1'b0 M1_AHBSLOT9ENABLE=1'b0 M1_AHBSLOT10ENABLE=1'b0 M1_AHBSLOT11ENABLE=1'b0 M1_AHBSLOT12ENABLE=1'b0 M1_AHBSLOT13ENABLE=1'b0 M1_AHBSLOT14ENABLE=1'b0 M1_AHBSLOT15ENABLE=1'b0 M1_AHBSLOT16ENABLE=1'b0 M2_AHBSLOT0ENABLE=1'b0 M2_AHBSLOT1ENABLE=1'b0 M2_AHBSLOT2ENABLE=1'b1 M2_AHBSLOT3ENABLE=1'b0 M2_AHBSLOT4ENABLE=1'b0 M2_AHBSLOT5ENABLE=1'b1 M2_AHBSLOT6ENABLE=1'b0 M2_AHBSLOT7ENABLE=1'b0 M2_AHBSLOT8ENABLE=1'b0 M2_AHBSLOT9ENABLE=1'b0 M2_AHBSLOT10ENABLE=1'b0 M2_AHBSLOT11ENABLE=1'b0 M2_AHBSLOT12ENABLE=1'b0 M2_AHBSLOT13ENABLE=1'b0 M2_AHBSLOT14ENABLE=1'b0 M2_AHBSLOT15ENABLE=1'b0 M2_AHBSLOT16ENABLE=1'b0 M3_AHBSLOT0ENABLE=1'b0 M3_AHBSLOT1ENABLE=1'b0 M3_AHBSLOT2ENABLE=1'b0 M3_AHBSLOT3ENABLE=1'b0 M3_AHBSLOT4ENABLE=1'b0 M3_AHBSLOT5ENABLE=1'b0 M3_AHBSLOT6ENABLE=1'b0 M3_AHBSLOT7ENABLE=1'b0 M3_AHBSLOT8ENABLE=1'b0 M3_AHBSLOT9ENABLE=1'b0 M3_AHBSLOT10ENABLE=1'b0 M3_AHBSLOT11ENABLE=1'b0 M3_AHBSLOT12ENABLE=1'b0 M3_AHBSLOT13ENABLE=1'b0 M3_AHBSLOT14ENABLE=1'b0 M3_AHBSLOT15ENABLE=1'b0 M3_AHBSLOT16ENABLE=1'b0 SYNC_RESET=32'b00000000000000000000000000000000 M0_AHBSLOTENABLE=17'b00000000000101000 M1_AHBSLOTENABLE=17'b00000000000100100 M2_AHBSLOTENABLE=17'b00000000000100100 M3_AHBSLOTENABLE=17'b00000000000000000 SC=16'b0000000000000000 Generated name = CoreAHBLite_Z5 @W:CG775 : CoreAHBLSRAM.v(29) | Found Component CoreTSE_M2S090_COREAHBLSRAM_0_COREAHBLSRAM in library COREAHBLSRAM_LIB @N:CG364 : AHBLSramIf.v(29) | Synthesizing module CoreTSE_M2S090_COREAHBLSRAM_0_AHBLSramIf in library COREAHBLSRAM_LIB. SYNC_RESET=32'b00000000000000000000000000000000 IDLE=2'b00 AHB_WR=2'b01 AHB_RD=2'b10 AHB_DWIDTH=32'b00000000000000000000000000100000 AHB_AWIDTH=32'b00000000000000000000000000100000 RESP_OKAY=2'b00 RESP_ERROR=2'b01 TRN_IDLE=2'b00 TRN_BUSY=2'b01 TRN_SEQ=2'b11 TRN_NONSEQ=2'b10 SINGLE=3'b000 INCR=3'b001 WRAP4=3'b010 INCR4=3'b011 WRAP8=3'b100 INCR8=3'b101 WRAP16=3'b110 INCR16=3'b111 Generated name = CoreTSE_M2S090_COREAHBLSRAM_0_AHBLSramIf_Z6 @N:CG179 : AHBLSramIf.v(328) | Removing redundant assignment. @W:CG133 : AHBLSramIf.v(148) | Object sramahb_ack_cnt is declared but not assigned. Either assign a value or remove the declaration. @W:CL169 : AHBLSramIf.v(184) | Pruning unused register HWDATA_d[31:0]. Make sure that there are no unused intermediate registers. @W:CL169 : AHBLSramIf.v(184) | Pruning unused register HTRANS_d[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : AHBLSramIf.v(184) | Pruning unused register HBURST_d[2:0]. Make sure that there are no unused intermediate registers. @W:CL169 : AHBLSramIf.v(184) | Pruning unused register HSEL_d. Make sure that there are no unused intermediate registers. @W:CL169 : AHBLSramIf.v(184) | Pruning unused register HREADYIN_d. Make sure that there are no unused intermediate registers. @N:CG364 : SramCtrlIf.v(29) | Synthesizing module CoreTSE_M2S090_COREAHBLSRAM_0_SramCtrlIf in library COREAHBLSRAM_LIB. SEL_SRAM_TYPE=32'b00000000000000000000000000000000 LSRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000000001000000000000 LSRAM_NUM_LOCATIONS_4=32'b00000000000000000001000000000000 USRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000000000001000000000 USRAM_NUM_LOCATIONS_4=32'b00000000000000000000000010000000 AHB_DWIDTH=32'b00000000000000000000000000100000 SYNC_RESET=32'b00000000000000000000000000000000 S_IDLE=2'b00 S_WR=2'b01 S_RD=2'b10 Generated name = CoreTSE_M2S090_COREAHBLSRAM_0_SramCtrlIf_0s_4096s_4096s_512s_128s_32s_0s_0_1_2 @N:CG364 : smartfusion2.v(382) | Synthesizing module RAM1K18 in library work. @N:CG364 : lsram_2048to139264x8.v(28) | Synthesizing module CoreTSE_M2S090_COREAHBLSRAM_0_lsram_2048to139264x8 in library COREAHBLSRAM_LIB. DEPTH=32'b00000000000000000001000000000000 SYNC_RESET=32'b00000000000000000000000000000000 AHB_DWIDTH=32'b00000000000000000000000000100000 Generated name = CoreTSE_M2S090_COREAHBLSRAM_0_lsram_2048to139264x8_4096s_0s_32s @W:CG133 : lsram_2048to139264x8.v(364) | Object writeAddr0 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(365) | Object writeAddr1 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(366) | Object writeAddr2 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(367) | Object writeAddr3 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(368) | Object writeAddr4 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(369) | Object writeAddr5 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(370) | Object writeAddr6 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(371) | Object writeAddr7 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(372) | Object writeAddr8 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(373) | Object writeAddr9 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(374) | Object writeAddr10 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(375) | Object writeAddr11 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(376) | Object writeAddr12 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(377) | Object writeAddr13 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(378) | Object writeAddr14 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(379) | Object writeAddr15 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(380) | Object writeAddr16 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(381) | Object writeAddr17 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(382) | Object writeAddr18 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(383) | Object writeAddr19 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(384) | Object writeAddr20 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(385) | Object writeAddr21 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(386) | Object writeAddr22 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(387) | Object writeAddr23 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(388) | Object writeAddr24 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(389) | Object writeAddr25 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(390) | Object writeAddr26 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(391) | Object writeAddr27 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(392) | Object writeAddr28 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(393) | Object writeAddr29 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(394) | Object writeAddr30 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(395) | Object writeAddr31 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(396) | Object writeAddr32 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(397) | Object writeAddr33 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(398) | Object writeAddr34 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(399) | Object writeAddr35 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(400) | Object writeAddr36 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(401) | Object writeAddr37 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(402) | Object writeAddr38 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(403) | Object writeAddr39 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(404) | Object writeAddr40 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(405) | Object writeAddr41 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(406) | Object writeAddr42 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(407) | Object writeAddr43 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(408) | Object writeAddr44 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(409) | Object writeAddr45 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(410) | Object writeAddr46 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(411) | Object writeAddr47 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(412) | Object writeAddr48 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(413) | Object writeAddr49 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(414) | Object writeAddr50 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(415) | Object writeAddr51 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(416) | Object writeAddr52 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(417) | Object writeAddr53 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(418) | Object writeAddr54 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(419) | Object writeAddr55 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(420) | Object writeAddr56 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(421) | Object writeAddr57 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(422) | Object writeAddr58 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(423) | Object writeAddr59 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(424) | Object writeAddr60 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(425) | Object writeAddr61 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(426) | Object writeAddr62 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(427) | Object writeAddr63 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(428) | Object writeAddr64 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(429) | Object writeAddr65 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(430) | Object writeAddr66 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(431) | Object writeAddr67 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(432) | Object writeAddr68 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(434) | Object readAddr0 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(435) | Object readAddr1 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(436) | Object readAddr2 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(437) | Object readAddr3 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(438) | Object readAddr4 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(439) | Object readAddr5 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(440) | Object readAddr6 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(441) | Object readAddr7 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(442) | Object readAddr8 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(443) | Object readAddr9 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(444) | Object readAddr10 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(445) | Object readAddr11 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(446) | Object readAddr12 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(447) | Object readAddr13 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(448) | Object readAddr14 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(449) | Object readAddr15 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(450) | Object readAddr16 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(451) | Object readAddr17 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(452) | Object readAddr18 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(453) | Object readAddr19 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(454) | Object readAddr20 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(455) | Object readAddr21 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(456) | Object readAddr22 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(457) | Object readAddr23 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(458) | Object readAddr24 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(459) | Object readAddr25 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(460) | Object readAddr26 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(461) | Object readAddr27 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(462) | Object readAddr28 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(463) | Object readAddr29 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(464) | Object readAddr30 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(465) | Object readAddr31 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(466) | Object readAddr32 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(467) | Object readAddr33 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(468) | Object readAddr34 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(469) | Object readAddr35 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(470) | Object readAddr36 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(471) | Object readAddr37 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(472) | Object readAddr38 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(473) | Object readAddr39 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(474) | Object readAddr40 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(475) | Object readAddr41 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(476) | Object readAddr42 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(477) | Object readAddr43 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(478) | Object readAddr44 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(479) | Object readAddr45 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(480) | Object readAddr46 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(481) | Object readAddr47 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(482) | Object readAddr48 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(483) | Object readAddr49 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(484) | Object readAddr50 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(485) | Object readAddr51 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(486) | Object readAddr52 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(487) | Object readAddr53 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(488) | Object readAddr54 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(489) | Object readAddr55 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(490) | Object readAddr56 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(491) | Object readAddr57 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(492) | Object readAddr58 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(493) | Object readAddr59 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(494) | Object readAddr60 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(495) | Object readAddr61 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(496) | Object readAddr62 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(497) | Object readAddr63 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(498) | Object readAddr64 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(499) | Object readAddr65 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(500) | Object readAddr66 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(501) | Object readAddr67 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : lsram_2048to139264x8.v(502) | Object readAddr68 is declared but not assigned. Either assign a value or remove the declaration. @W:CL168 : lsram_2048to139264x8.v(9909) | Removing instance block17 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9889) | Removing instance block18 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9868) | Removing instance block19 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9848) | Removing instance block20 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9827) | Removing instance block21 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9807) | Removing instance block22 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9786) | Removing instance block23 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9765) | Removing instance block24 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9744) | Removing instance block25 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9724) | Removing instance block26 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9704) | Removing instance block27 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9683) | Removing instance block28 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9662) | Removing instance block29 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9640) | Removing instance block30 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9619) | Removing instance block31 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9599) | Removing instance block32 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9578) | Removing instance block33 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9558) | Removing instance block34 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9538) | Removing instance block35 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9517) | Removing instance block36 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9497) | Removing instance block37 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9477) | Removing instance block38 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9456) | Removing instance block39 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9435) | Removing instance block40 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9415) | Removing instance block41 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9394) | Removing instance block42 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9373) | Removing instance block43 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9352) | Removing instance block44 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9331) | Removing instance block45 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9310) | Removing instance block46 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9289) | Removing instance block47 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9268) | Removing instance block48 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9247) | Removing instance block49 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9226) | Removing instance block50 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9205) | Removing instance block51 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9184) | Removing instance block52 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9163) | Removing instance block53 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9142) | Removing instance block54 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9121) | Removing instance block55 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9100) | Removing instance block56 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9079) | Removing instance block57 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9058) | Removing instance block58 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9037) | Removing instance block59 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(9016) | Removing instance block60 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(8995) | Removing instance block61 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(8974) | Removing instance block62 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(8953) | Removing instance block63 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(8933) | Removing instance block64 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(8913) | Removing instance block65 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(8893) | Removing instance block66 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(8872) | Removing instance block67 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : lsram_2048to139264x8.v(8851) | Removing instance block68 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL169 : lsram_2048to139264x8.v(586) | Pruning unused register ckRdAddr[15:9]. Make sure that there are no unused intermediate registers. @N:CG179 : SramCtrlIf.v(356) | Removing redundant assignment. @W:CG133 : SramCtrlIf.v(103) | Object ahbsram_wdata_upd_r is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : SramCtrlIf.v(104) | Object u_ahbsram_wdata_upd_r is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : SramCtrlIf.v(111) | Removing wire u_BUSY_all_0, as there is no assignment to it. @W:CG360 : SramCtrlIf.v(112) | Removing wire u_BUSY_all_1, as there is no assignment to it. @W:CG360 : SramCtrlIf.v(113) | Removing wire u_BUSY_all_2, as there is no assignment to it. @W:CG360 : SramCtrlIf.v(114) | Removing wire u_BUSY_all_3, as there is no assignment to it. @W:CG360 : SramCtrlIf.v(116) | Removing wire l_BUSY_all_1, as there is no assignment to it. @W:CG360 : SramCtrlIf.v(117) | Removing wire l_BUSY_all_2, as there is no assignment to it. @W:CG360 : SramCtrlIf.v(118) | Removing wire l_BUSY_all_3, as there is no assignment to it. @N:CG364 : CoreAHBLSRAM.v(29) | Synthesizing module CoreTSE_M2S090_COREAHBLSRAM_0_COREAHBLSRAM in library COREAHBLSRAM_LIB. FAMILY=32'b00000000000000000000000000010011 AHB_DWIDTH=32'b00000000000000000000000000100000 AHB_AWIDTH=32'b00000000000000000000000000100000 LSRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000000001000000000000 USRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000000000001000000000 SEL_SRAM_TYPE=32'b00000000000000000000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CoreTSE_M2S090_COREAHBLSRAM_0_COREAHBLSRAM_19s_32s_32s_4096s_512s_0s_0s @N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP in library work. FAMILY=32'b00000000000000000000000000010011 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000 DEVICE_090=32'b00000000000000000000000000000000 VERSION_MAJOR=32'b00000000000000000000000000000111 VERSION_MINOR=32'b00000000000000000000000000000000 VERSION_MAJOR_VECTOR=16'b0000000000000111 VERSION_MINOR_VECTOR=16'b0000000000000000 S0=2'b00 S1=2'b01 S2=2'b10 Generated name = CoreConfigP_Z7 @W:CL113 : coreconfigp.v(626) | Feedback mux created for signal soft_reset_reg[16:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL250 : coreconfigp.v(626) | All reachable assignments to soft_reset_reg[16:0] assign 0, register removed by optimization @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP in library work. FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000 DEVICE_090=32'b00000000000000000000000000000000 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z8 @W:CL169 : coreresetp.v(1613) | Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1581) | Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1549) | Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1517) | Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1365) | Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1300) | Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1235) | Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1089) | Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers. @W:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : coreresetp.v(1089) | Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers. @N:CG364 : dmatx.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_DMATX in library work. FAMILY=32'b00000000000000000000000000010011 CORETSEO=32'b00000000000000000000000000000000 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_DMATX_19s_0s @N:CG179 : dmatx.v(1221) | Removing redundant assignment. @N:CG179 : dmatx.v(1229) | Removing redundant assignment. @N:CG179 : dmatx.v(1237) | Removing redundant assignment. @N:CG364 : dmarx.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_DMARX in library work. FAMILY=32'b00000000000000000000000000010011 CORETSEO=32'b00000000000000000000000000000000 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_DMARX_19s_0s @N:CG179 : dmarx.v(1150) | Removing redundant assignment. @N:CG179 : dmarx.v(1158) | Removing redundant assignment. @N:CG179 : dmarx.v(1166) | Removing redundant assignment. @W:CG133 : dmarx.v(302) | Object CORETSEI100I is declared but not assigned. Either assign a value or remove the declaration. @N:CG364 : dma_dual.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_DMA_DUAL in library work. FAMILY=32'b00000000000000000000000000010011 CORETSEO=32'b00000000000000000000000000000000 CORETSEoO00=32'b00000000000000000000000000000000 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_DMA_DUAL_19s_0s_0s @N:CG179 : dma_dual.v(974) | Removing redundant assignment. @N:CG179 : dma_dual.v(1034) | Removing redundant assignment. @W:CG360 : dma_dual.v(397) | Removing wire CORETSEoOl0I, as there is no assignment to it. @W:CG360 : dma_dual.v(400) | Removing wire CORETSEiOl0I, as there is no assignment to it. @W:CG360 : dma_dual.v(424) | Removing wire CORETSEiIl0I, as there is no assignment to it. @W:CG360 : dma_dual.v(426) | Removing wire CORETSEOll0I, as there is no assignment to it. @W:CG360 : dma_dual.v(565) | Removing wire CORETSEOO10, as there is no assignment to it. @W:CG133 : dma_dual.v(573) | Object CORETSEIO10 is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : dma_dual.v(581) | Removing wire CORETSElO10, as there is no assignment to it. @W:CG133 : dma_dual.v(589) | Object CORETSEoO10 is declared but not assigned. Either assign a value or remove the declaration. @W:CL265 : dma_dual.v(1572) | Removing unused bit 5 of CORETSEI0l0I[9:0]. Either assign all bits or reduce the width of the signal. @W:CL265 : dma_dual.v(1572) | Removing unused bit 2 of CORETSEI0l0I[9:0]. Either assign all bits or reduce the width of the signal. @N:CG364 : slave.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_SLAVE in library work. FAMILY=32'b00000000000000000000000000010011 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_SLAVE_19s @N:CG364 : decoder.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_DECODER in library work. @N:CG364 : tsm_sysreg.v(4) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_TSM_SYSREG in library work. FAMILY=32'b00000000000000000000000000010011 CORETSEoO00=32'b00000000000000000000000000000000 CORETSEO=32'b00000000000000000000000000000000 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_TSM_SYSREG_19s_0s_0s @W:CG360 : tsm_sysreg.v(216) | Removing wire CORETSEoi00, as there is no assignment to it. @W:CG360 : tsm_sysreg.v(219) | Removing wire CORETSEii00, as there is no assignment to it. @W:CG360 : tsm_sysreg.v(227) | Removing wire CORETSEOO10, as there is no assignment to it. @W:CG133 : tsm_sysreg.v(235) | Object CORETSEIO10 is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : tsm_sysreg.v(243) | Removing wire CORETSElO10, as there is no assignment to it. @W:CG133 : tsm_sysreg.v(251) | Object CORETSEoO10 is declared but not assigned. Either assign a value or remove the declaration. @N:CG364 : mahbe_dual.v(5) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_MAHBE_DUAL in library work. FAMILY=32'b00000000000000000000000000010011 CORETSEO=32'b00000000000000000000000000000000 CORETSEoO00=32'b00000000000000000000000000000000 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_MAHBE_DUAL_19s_0s_0s @N:CG364 : arfque.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_ARFQUE in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000010011 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_ARFQUE_1s_19s @N:CG364 : amcxtfif_fab.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_AMCXTFIF_FAB in library work. FAMILY=32'b00000000000000000000000000010011 TABITS=32'b00000000000000000000000000001011 CORETSEi00i=32'b00000000000000000000000000100000 CORETSEO10i=32'b00000000000000000000000000000010 CORETSEol0OI=11'b00000000000 CORETSEOlIOI=12'b000000000000 CORETSEOII=32'b00000000000000000000000000000001 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_AMCXTFIF_FAB_19s_11s_32s_2s_0_0_1s @N:CG364 : amcxtfif_sys.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_AMCXTFIF_SYS in library work. FAMILY=32'b00000000000000000000000000010011 TABITS=32'b00000000000000000000000000001011 CORETSEi00i=32'b00000000000000000000000000100000 CORETSEO10i=32'b00000000000000000000000000000010 CORETSEO=32'b00000000000000000000000000000000 CORETSEOlIOI=12'b000000000000 CORETSEiO1OI=14'b00000000000000 CORETSEOII=32'b00000000000000000000000000000001 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_AMCXTFIF_SYS_19s_11s_32s_2s_0s_0_0_1s @W:CG133 : amcxtfif_sys.v(546) | Object CORETSEiOoOI is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : amcxtfif_sys.v(549) | Object CORETSEOIoOI is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : amcxtfif_sys.v(552) | Object CORETSEIIoOI is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : amcxtfif_sys.v(562) | Object CORETSElIoOI is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : amcxtfif_sys.v(572) | Object CORETSEoIoOI is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : amcxtfif_sys.v(588) | Object CORETSEiIoOI is declared but not assigned. Either assign a value or remove the declaration. @W:CL271 : amcxtfif_sys.v(2068) | Pruning unused bits 1 to 0 of genblk2.CORETSEl01OI[13:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL271 : amcxtfif_sys.v(1583) | Pruning unused bits 13 to 2 of CORETSEo01OI[13:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL271 : amcxtfif_sys.v(1553) | Pruning unused bits 1 to 0 of CORETSEI01OI[13:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL271 : amcxtfif_sys.v(1484) | Pruning unused bits 1 to 0 of CORETSEO01OI[13:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL265 : amcxtfif_sys.v(2019) | Removing unused bit 38 of genblk2.CORETSEI11OI[39:0]. Either assign all bits or reduce the width of the signal. @N:CG364 : amcxrfif_fab.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_AMCXRFIF_FAB in library work. FAMILY=32'b00000000000000000000000000010011 RABITS=32'b00000000000000000000000000001100 CORETSEi00i=32'b00000000000000000000000000100000 CORETSEO10i=32'b00000000000000000000000000000010 CORETSEOlIOI=13'b0000000000000 CORETSEOII=32'b00000000000000000000000000000001 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_AMCXRFIF_FAB_19s_12s_32s_2s_0_1s @N:CG179 : amcxrfif_fab.v(1479) | Removing redundant assignment. @N:CG179 : amcxrfif_fab.v(1485) | Removing redundant assignment. @N:CG179 : amcxrfif_fab.v(1491) | Removing redundant assignment. @N:CG179 : amcxrfif_fab.v(1497) | Removing redundant assignment. @N:CG179 : amcxrfif_fab.v(1503) | Removing redundant assignment. @W:CL169 : amcxrfif_fab.v(636) | Pruning unused register CORETSEiiIOI. Make sure that there are no unused intermediate registers. @W:CL190 : amcxrfif_fab.v(2168) | Optimizing register bit CORETSEoloi[36] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : amcxrfif_fab.v(2168) | Optimizing register bit CORETSEoloi[37] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : amcxrfif_fab.v(2168) | Optimizing register bit CORETSEoloi[38] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : amcxrfif_fab.v(2168) | Optimizing register bit CORETSEoloi[39] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL279 : amcxrfif_fab.v(2168) | Pruning register bits 39 to 36 of CORETSEoloi[39:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL169 : amcxrfif_fab.v(1532) | Pruning unused register CORETSEl0IOI. Make sure that there are no unused intermediate registers. @N:CG364 : amcxrfif_sys.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_AMCXRFIF_SYS in library work. FAMILY=32'b00000000000000000000000000010011 CORETSEO=32'b00000000000000000000000000000000 RABITS=32'b00000000000000000000000000001100 CORETSEi00i=32'b00000000000000000000000000100000 CORETSEO10i=32'b00000000000000000000000000000010 CORETSEOOlOI=14'b00000000000000 CORETSEIOlOI=13'b0000000000000 CORETSEOlIOI=15'b000000000000000 CORETSEOII=32'b00000000000000000000000000000001 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_AMCXRFIF_SYS_19s_0s_12s_32s_2s_0_0_0_1s @W:CL169 : amcxrfif_sys.v(2075) | Pruning unused register CORETSEoI0OI. Make sure that there are no unused intermediate registers. @W:CL169 : amcxrfif_sys.v(1783) | Pruning unused register CORETSElI0OI[14:0]. Make sure that there are no unused intermediate registers. @N:CG364 : amcxtfif_wtm.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_AMCXTFIF_WTM in library work. FAMILY=32'b00000000000000000000000000010011 RABITS=32'b00000000000000000000000000001100 CORETSEOII=32'b00000000000000000000000000000001 CORETSEol0OI=12'b000000000000 CORETSEOlIOI=13'b0000000000000 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_AMCXTFIF_WTM_19s_12s_1s_0_0 @N:CG364 : amcxfif_hst.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_AMCXFIF_HST in library work. FAMILY=32'b00000000000000000000000000010011 TABITS=32'b00000000000000000000000000001011 RABITS=32'b00000000000000000000000000001100 CORETSEi00i=32'b00000000000000000000000000100000 CORETSEO10i=32'b00000000000000000000000000000010 CORETSEOII=32'b00000000000000000000000000000001 CORETSEiiii=13'b0000000000000 CORETSEOOOOI=4'b0000 CORETSEIOOOI=19'b0000000000000000000 CORETSElOOOI=12'b111111111111 CORETSEoOOOI=12'b111111111111 CORETSEiOOOI=14'b00000000000000 CORETSEOIOOI=4'b0000 CORETSEIIOOI=3'b000 CORETSElIOOI=18'b000000000000000000 CORETSEoIOOI=13'b1111111111111 CORETSEiIOOI=13'b1111111111111 CORETSEOlOOI=12'b111111111111 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_AMCXFIF_HST_Z9 @W:CG360 : amcxfif_hst.v(909) | Removing wire CORETSEo1OOI, as there is no assignment to it. @N:CG364 : amcxfif_clkrst.v(7) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_AMCXFIF_CLKRST in library work. @N:CG364 : amcxfif.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_AMCXFIF in library work. FAMILY=32'b00000000000000000000000000010011 TABITS=32'b00000000000000000000000000001011 RABITS=32'b00000000000000000000000000001100 CORETSEi00i=32'b00000000000000000000000000100000 CORETSEO10i=32'b00000000000000000000000000000010 CORETSEO=32'b00000000000000000000000000000000 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_AMCXFIF_19s_11s_12s_32s_2s_0s @N:CG364 : petmc_top.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PETMC_TOP in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000010011 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_PETMC_TOP_1s_19s @N:CG364 : pecrc.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PECRC in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000010011 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_PECRC_1s_19s @N:CG364 : petfn_top.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PETFN_TOP in library work. FAMILY=32'b00000000000000000000000000010011 CORETSEIi0I=32'b00000000000000000000000000000000 CORETSEI=1'b0 CORETSEOII=32'b00000000000000000000000000000001 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_PETFN_TOP_19s_0s_0_1s @N:CG179 : petfn_top.v(10504) | Removing redundant assignment. @N:CG179 : petfn_top.v(10566) | Removing redundant assignment. @W:CG133 : petfn_top.v(423) | Object CORETSEl0oI is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : petfn_top.v(426) | Removing wire CORETSEo0oI, as there is no assignment to it. @W:CG360 : petfn_top.v(450) | Removing wire CORETSEiOlI, as there is no assignment to it. @W:CG133 : petfn_top.v(510) | Object CORETSEiOiI is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : petfn_top.v(513) | Object CORETSEOIiI is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : petfn_top.v(532) | Object CORETSEOliI is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : petfn_top.v(534) | Object CORETSEIliI is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : petfn_top.v(537) | Object CORETSElliI is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : petfn_top.v(539) | Object CORETSEoliI is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : petfn_top.v(977) | Removing wire CORETSEOOll, as there is no assignment to it. @W:CL169 : petfn_top.v(4448) | Pruning unused register CORETSEioiI[15:0]. Make sure that there are no unused intermediate registers. @W:CL190 : petfn_top.v(4128) | Optimizing register bit CORETSEooOl[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : petfn_top.v(4128) | Optimizing register bit CORETSEooOl[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL279 : petfn_top.v(4128) | Pruning register bits 6 to 5 of CORETSEooOl[6:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @N:CG364 : perfn_top.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PERFN_TOP in library work. FAMILY=32'b00000000000000000000000000010011 CORETSEO=32'b00000000000000000000000000000000 CORETSEI=1'b0 CORETSEOII=32'b00000000000000000000000000000001 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_PERFN_TOP_19s_0s_0_1s @W:CG360 : perfn_top.v(348) | Removing wire CORETSEI0I, as there is no assignment to it. @W:CG360 : perfn_top.v(655) | Removing wire CORETSEOI1, as there is no assignment to it. @W:CG133 : perfn_top.v(658) | Object CORETSEII1 is declared but not assigned. Either assign a value or remove the declaration. @N:CG364 : permc_top.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PERMC_TOP in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000010011 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_PERMC_TOP_1s_19s @N:CG364 : pe_mcxmac_core.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PE_MCXMAC_CORE in library work. FAMILY=32'b00000000000000000000000000010011 CORETSEI=1'b0 CORETSEO=32'b00000000000000000000000000000000 CORETSEIi0I=32'b00000000000000000000000000000000 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_PE_MCXMAC_CORE_19s_0_0s_0s @N:CG364 : pemgt.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PEMGT in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000010011 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s @N:CG364 : pehst.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PEHST in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000010011 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_PEHST_1s_19s @W:CG133 : pehst.v(613) | Object CORETSEOlI1 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : pehst.v(709) | Object CORETSEIlI1 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : pehst.v(714) | Object CORETSEllI1 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : pehst.v(716) | Object CORETSEolI1 is declared but not assigned. Either assign a value or remove the declaration. @W:CL169 : pehst.v(2022) | Pruning unused register CORETSEllo1. Make sure that there are no unused intermediate registers. @W:CL169 : pehst.v(1990) | Pruning unused register CORETSEIlo1. Make sure that there are no unused intermediate registers. @W:CL169 : pehst.v(1958) | Pruning unused register CORETSEOlo1. Make sure that there are no unused intermediate registers. @N:CG364 : pecar.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PECAR in library work. @N:CG364 : pe_mcxmac.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PE_MCXMAC in library work. FAMILY=32'b00000000000000000000000000010011 CORETSEI=1'b0 CORETSEIi0I=32'b00000000000000000000000000000000 CORETSEO=32'b00000000000000000000000000000000 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_PE_MCXMAC_19s_0_0s_0s @W:CG360 : pe_mcxmac.v(681) | Removing wire CORETSEllO1, as there is no assignment to it. @W:CG360 : pe_mcxmac.v(684) | Removing wire CORETSEOio0, as there is no assignment to it. @W:CG360 : pe_mcxmac.v(687) | Removing wire CORETSEiIo0, as there is no assignment to it. @N:CG364 : tsmac_ahb_top.v(4) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_TSMAC_AHB_TOP in library work. FAMILY=32'b00000000000000000000000000010011 TABITS=32'b00000000000000000000000000001011 RABITS=32'b00000000000000000000000000001100 MCXMAC_SAL_ON=32'b00000000000000000000000000000001 MCXMAC_WOL_ON=32'b00000000000000000000000000000001 MCXMAC_STATS_ON=32'b00000000000000000000000000000001 CORETSEO=32'b00000000000000000000000000000000 CORETSEIi0I=32'b00000000000000000000000000000000 CORETSEI=32'b00000000000000000000000000000000 CORETSEo1llI=32'b00000000000000000000000000000001 CORETSEi1llI=32'b00000000000000000000000000000010 CORETSEOollI=32'b00000000000000000000000000000001 CORETSEIollI=32'b00000000000000000000000000000010 CORETSElollI=32'b00000000000000000000000000010010 CORETSEoollI=32'b00000000000000000000000000010010 CORETSEiollI=32'b00000000000000000000000000000101 CORETSEOillI=32'b00000000000000000000000000000101 CORETSEoO00=32'b00000000000000000000000000000000 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_TSMAC_AHB_TOP_Z10 @N:CG364 : sib_sync_pulse.v(5) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_SIB_SYNC_PULSE in library work. FAMILY=32'b00000000000000000000000000010011 CORETSEO0O0=32'b00000000000000000000000000000000 CORETSEiOl0=32'b00000000000000000000000000000000 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_SIB_SYNC_PULSE_19s_0s_0s @N:CG364 : sib_sync_2flp.v(5) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_SIB_SYNC_2FLP in library work. CORETSEO0I0=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000010011 CORETSEI0I0=32'b00000000000000000000000000000000 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_SIB_SYNC_2FLP_1s_19s_0s @W:CG133 : sib_sync_2flp.v(77) | Object CORETSEolO0 is declared but not assigned. Either assign a value or remove the declaration. @N:CG364 : pemstat_cntrl.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_CNTRL in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000010011 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_CNTRL_1s_19s @W:CG360 : pemstat_cntrl.v(113) | Removing wire CORETSElllo, as there is no assignment to it. @W:CG360 : pemstat_cntrl.v(115) | Removing wire CORETSEollo, as there is no assignment to it. @W:CG133 : pemstat_cntrl.v(118) | Object CORETSEillo is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : pemstat_cntrl.v(120) | Object CORETSEO0lo is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : pemstat_cntrl.v(129) | Object CORETSEi0lo is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : pemstat_cntrl.v(131) | Object CORETSEO1lo is declared but not assigned. Either assign a value or remove the declaration. @N:CG364 : pemstat_linc.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_LINC in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000010011 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_LINC_1s_19s @N:CG179 : pemstat_linc.v(226) | Removing redundant assignment. @N:CG179 : pemstat_linc.v(300) | Removing redundant assignment. @N:CG364 : pemstat_ladd.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_LADD in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000010011 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_LADD_1s_19s @N:CG179 : pemstat_ladd.v(383) | Removing redundant assignment. @N:CG364 : pemstat_sinc.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_SINC in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000010011 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_SINC_1s_19s @N:CG179 : pemstat_sinc.v(226) | Removing redundant assignment. @N:CG179 : pemstat_sinc.v(300) | Removing redundant assignment. @N:CG364 : pemstat_sinchd.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_SINCHD in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000010011 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_SINCHD_1s_19s @N:CG179 : pemstat_sinchd.v(226) | Removing redundant assignment. @N:CG179 : pemstat_sinchd.v(300) | Removing redundant assignment. @N:CG364 : pemstat_sadd.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_SADD in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000010011 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_SADD_1s_19s @N:CG179 : pemstat_sadd.v(244) | Removing redundant assignment. @N:CG179 : pemstat_sadd.v(323) | Removing redundant assignment. @N:CG364 : pemstat_sincnf.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_SINCNF in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000010011 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_SINCNF_1s_19s @N:CG179 : pemstat_sincnf.v(226) | Removing redundant assignment. @N:CG179 : pemstat_sincnf.v(300) | Removing redundant assignment. @N:CG364 : pemstat_store.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_STORE in library work. FAMILY=32'b00000000000000000000000000010011 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_STORE_19s @N:CG364 : pemstat_eim.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_EIM in library work. FAMILY=32'b00000000000000000000000000010011 CORETSEOII=32'b00000000000000000000000000000001 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_EIM_19s_1s @N:CG364 : pemstat.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT in library work. FAMILY=32'b00000000000000000000000000010011 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s @N:CG364 : mmcxwol.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_MMCXWOL in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000010011 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_MMCXWOL_1s_19s @N:CG364 : si_sal.v(4) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_SI_SAL in library work. FAMILY=32'b00000000000000000000000000010011 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_SI_SAL_19s @N:CG179 : si_sal.v(931) | Removing redundant assignment. @W:CG360 : tsmac_ahb_top.v(282) | Removing wire CORETSEII1lI, as there is no assignment to it. @W:CG360 : tsmac_ahb_top.v(284) | Removing wire CORETSElI1lI, as there is no assignment to it. @W:CG360 : tsmac_ahb_top.v(286) | Removing wire CORETSEoI1lI, as there is no assignment to it. @W:CG360 : tsmac_ahb_top.v(288) | Removing wire CORETSEiI1lI, as there is no assignment to it. @W:CG360 : tsmac_ahb_top.v(290) | Removing wire CORETSEOl1lI, as there is no assignment to it. @N:CG364 : tx2048x40.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_TX2048X40 in library work. TABITS=32'b00000000000000000000000000001011 CORETSEOII=32'b00000000000000000000000000000001 CORETSEoOil=32'b00000000000000000000000000000001 CORETSEiOil=32'b00000000000000000000000000000100 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_TX2048X40_11s_1s_1s_4s @W:CG133 : tx2048x40.v(93) | Object CORETSElOil is declared but not assigned. Either assign a value or remove the declaration. @N:CL134 : tx2048x40.v(139) | Found RAM CORETSEIIil, depth=2048, width=40 @N:CG364 : rx4096x36.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_RX4096X36 in library work. RABITS=32'b00000000000000000000000000001100 CORETSEOII=32'b00000000000000000000000000000001 CORETSEoOil=32'b00000000000000000000000000000001 CORETSEiOil=32'b00000000000000000000000000000100 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_RX4096X36_12s_1s_1s_4s @W:CG133 : rx4096x36.v(93) | Object CORETSElOil is declared but not assigned. Either assign a value or remove the declaration. @N:CL134 : rx4096x36.v(139) | Found RAM CORETSEIIil, depth=4096, width=36 @N:CG364 : CoreTSE_AHB_top.v(2) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP in library work. FAMILY=32'b00000000000000000000000000010011 GMII_TBI=32'b00000000000000000000000000000001 TABITS=32'b00000000000000000000000000001011 RABITS=32'b00000000000000000000000000001100 MCXMAC_SAL_ON=32'b00000000000000000000000000000001 MCXMAC_WOL_ON=32'b00000000000000000000000000000001 MCXMAC_STATS_ON=32'b00000000000000000000000000000001 MDIO_PHYID=32'b00000000000000000000000000010010 SLIP_ENABLE=32'b00000000000000000000000000000000 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP_19s_1s_11s_12s_1s_1s_1s_18s_0s @N:CG364 : msgmii_clkrst.v(7) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_CLKRST in library work. @N:CG364 : msgmii_cnvtxi.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_CNVTXI in library work. FAMILY=32'b00000000000000000000000000010011 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_CNVTXI_19s @W:CL169 : msgmii_cnvtxi.v(364) | Pruning unused register CORETSEO0oII[3:0]. Make sure that there are no unused intermediate registers. @N:CG364 : msgmii_cnvtxo.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_CNVTXO in library work. FAMILY=32'b00000000000000000000000000010011 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_CNVTXO_19s @N:CG364 : t8b10b.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_T8B10B in library work. @N:CG364 : petex_top.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PETEX_TOP in library work. FAMILY=32'b00000000000000000000000000010011 CORETSEI=32'b00000000000000000000000000000000 CORETSEOII=32'b00000000000000000000000000000001 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_PETEX_TOP_19s_0s_1s @N:CG179 : petex_top.v(2139) | Removing redundant assignment. @W:CL169 : petex_top.v(690) | Pruning unused register CORETSEO1II. Make sure that there are no unused intermediate registers. @N:CG364 : perex_pma.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PEREX_PMA in library work. FAMILY=32'b00000000000000000000000000010011 SLIP_ENABLE=32'b00000000000000000000000000000000 CORETSEOII=32'b00000000000000000000000000000001 CORETSEiili=3'b000 CORETSEOO0i=3'b001 CORETSEIO0i=3'b010 CORETSElO0i=3'b011 CORETSEoO0i=3'b100 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_PEREX_PMA_19s_0s_1s_0_1_2_3_4 @W:CG133 : perex_pma.v(219) | Object CORETSEiOo0 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : perex_pma.v(188) | Object CORETSEiO0i is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : perex_pma.v(196) | Object CORETSEOI0i is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : perex_pma.v(199) | Object CORETSEII0i is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : perex_pma.v(202) | Object CORETSElI0i is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : perex_pma.v(205) | Object CORETSEoI0i is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : perex_pma.v(213) | Object CORETSEiI0i is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : perex_pma.v(216) | Removing wire CORETSEOl0i, as there is no assignment to it. @W:CG133 : perex_pma.v(222) | Object CORETSEIl0i is declared but not assigned. Either assign a value or remove the declaration. @W:CL169 : perex_pma.v(2085) | Pruning unused register CORETSEll0i. Make sure that there are no unused intermediate registers. @W:CL169 : perex_pma.v(1890) | Pruning unused register CORETSEIili. Make sure that there are no unused intermediate registers. @W:CL169 : perex_pma.v(1854) | Pruning unused register CORETSEOili. Make sure that there are no unused intermediate registers. @W:CL169 : perex_pma.v(1818) | Pruning unused register CORETSEioli. Make sure that there are no unused intermediate registers. @N:CG364 : r10b8b.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_R10B8B in library work. @N:CG364 : perex_pcs.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PEREX_PCS in library work. CORETSEI=32'b00000000000000000000000000000000 FAMILY=32'b00000000000000000000000000010011 CORETSEOII=32'b00000000000000000000000000000001 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_PEREX_PCS_0s_19s_1s @W:CL169 : perex_pcs.v(4321) | Pruning unused register CORETSElIli. Make sure that there are no unused intermediate registers. @W:CL169 : perex_pcs.v(4260) | Pruning unused register CORETSEOIli. Make sure that there are no unused intermediate registers. @W:CL169 : perex_pcs.v(4101) | Pruning unused register CORETSEI1lI. Make sure that there are no unused intermediate registers. @W:CL265 : perex_pcs.v(1303) | Removing unused bit 3 of CORETSEoIol[3:0]. Either assign all bits or reduce the width of the signal. @W:CL265 : perex_pcs.v(1303) | Removing unused bit 1 of CORETSEoIol[3:0]. Either assign all bits or reduce the width of the signal. @N:CG364 : peanx_sync.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PEANX_SYNC in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000010011 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_PEANX_SYNC_1s_19s @N:CG364 : msgmii_peanx_top.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_PEANX_TOP in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000010011 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_PEANX_TOP_1s_19s @W:CL169 : msgmii_peanx_top.v(3121) | Pruning unused register CORETSEiIIlI. Make sure that there are no unused intermediate registers. @W:CL265 : msgmii_peanx_top.v(3041) | Removing unused bit 14 of CORETSElIIlI[15:0]. Either assign all bits or reduce the width of the signal. @W:CL265 : msgmii_peanx_top.v(2437) | Removing unused bit 14 of CORETSEl1OlI[15:0]. Either assign all bits or reduce the width of the signal. @W:CL177 : msgmii_peanx_top.v(2361) | Sharing sequential element CORETSEI0OlI. Add a syn_preserve attribute to the element to prevent sharing. @N:CG364 : petbm.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PETBM in library work. FAMILY=32'b00000000000000000000000000010011 CORETSEI=32'b00000000000000000000000000000000 CORETSEOII=32'b00000000000000000000000000000001 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_PETBM_19s_0s_1s @W:CL169 : petbm.v(2544) | Pruning unused register CORETSEIIio. Make sure that there are no unused intermediate registers. @N:CG364 : petcr.v(7) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_PETCR in library work. @W:CG133 : petcr.v(145) | Object CORETSEIiOI is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : petcr.v(147) | Object CORETSEliOI is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : petcr.v(150) | Removing wire CORETSEoiOI, as there is no assignment to it. @W:CL177 : petcr.v(319) | Sharing sequential element CORETSEooOI. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : petcr.v(422) | Sharing sequential element CORETSEoOII. Add a syn_preserve attribute to the element to prevent sharing. @N:CG364 : msgmii_tbi.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_TBI in library work. FAMILY=32'b00000000000000000000000000010011 CORETSEI=32'b00000000000000000000000000000000 SLIP_ENABLE=32'b00000000000000000000000000000000 CORETSEOII=32'b00000000000000000000000000000001 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_TBI_19s_0s_0s_1s @W:CG360 : msgmii_tbi.v(411) | Removing wire CORETSEIio0, as there is no assignment to it. @N:CG364 : msgmii_cnvrxi.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_CNVRXI in library work. FAMILY=32'b00000000000000000000000000010011 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_CNVRXI_19s @W:CL169 : msgmii_cnvrxi.v(496) | Pruning unused register CORETSEIl1II[1:0]. Make sure that there are no unused intermediate registers. @N:CG364 : msgmii_cnvrxo.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_CNVRXO in library work. FAMILY=32'b00000000000000000000000000010011 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_CNVRXO_19s @N:CG364 : msgmii_core.v(6) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_CORE in library work. FAMILY=32'b00000000000000000000000000010011 CORETSEI=32'b00000000000000000000000000000000 MDIO_PHYID=32'b00000000000000000000000000010010 SLIP_ENABLE=32'b00000000000000000000000000000000 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_CORE_19s_0s_18s_0s @W:CG781 : CoreTSE_AHB_top.v(1291) | Input CORETSEoO1lI on instance CORETSEIoilI is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : CoreTSE_AHB_top.v(1295) | Input CORETSEiO1lI on instance CORETSEIoilI is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : CoreTSE_AHB_top.v(1299) | Input CORETSEOI1lI on instance CORETSEIoilI is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : CoreTSE_AHB_top.v(1303) | Input CORETSEIO1lI on instance CORETSEIoilI is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : CoreTSE_AHB_top.v(1307) | Input CORETSElO1lI on instance CORETSEIoilI is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG360 : CoreTSE_AHB_top.v(592) | Removing wire CORETSEl0llI, as there is no assignment to it. @W:CG360 : CoreTSE_AHB_top.v(609) | Removing wire CORETSEioIlI, as there is no assignment to it. @W:CG360 : CoreTSE_AHB_top.v(717) | Removing wire CORETSEIoolI, as there is no assignment to it. @N:CG364 : CoreTSE_AHB.v(2) | Synthesizing module CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB in library work. FAMILY=32'b00000000000000000000000000010011 GMII_TBI=32'b00000000000000000000000000000001 PACKET_SIZE=32'b00000000000000000000000000001011 SAL=32'b00000000000000000000000000000001 WoL=32'b00000000000000000000000000000001 STATS=32'b00000000000000000000000000000001 MDIO_PHYID=32'b00000000000000000000000000010010 SLIP_ENABLE=32'b00000000000000000000000000000000 Generated name = CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s_0s @W:CG781 : CoreTSE_AHB.v(691) | Input AHBS_HPROT_I on instance CORETSEi0ilI is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF in library work. @N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF in library work. @N:CG364 : CoreTSE_M2S090_MSS_syn.v(5) | Synthesizing module MSS_075 in library work. @N:CG364 : CoreTSE_M2S090_MSS.v(9) | Synthesizing module CoreTSE_M2S090_MSS in library work. @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC in library work. @N:CG364 : smartfusion2.v(372) | Synthesizing module GND in library work. @N:CG364 : smartfusion2.v(727) | Synthesizing module CCC in library work. @N:CG364 : CoreTSE_M2S090_FCCC_0_FCCC.v(5) | Synthesizing module CoreTSE_M2S090_FCCC_0_FCCC in library work. @N:CG364 : CoreTSE_M2S090_FCCC_1_FCCC.v(5) | Synthesizing module CoreTSE_M2S090_FCCC_1_FCCC in library work. @N:CG364 : CoreTSE_M2S090_FCCC_2_FCCC.v(5) | Synthesizing module CoreTSE_M2S090_FCCC_2_FCCC in library work. @N:CG364 : CoreTSE_M2S090_FCCC_3_FCCC.v(5) | Synthesizing module CoreTSE_M2S090_FCCC_3_FCCC in library work. @N:CG364 : MON_ANX.v(21) | Synthesizing module MON_ANX in library work. @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB in library work. @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ in library work. @N:CG364 : CoreTSE_M2S090_OSC_0_OSC.v(5) | Synthesizing module CoreTSE_M2S090_OSC_0_OSC in library work. @N:CG364 : smartfusion2.v(320) | Synthesizing module INBUF_DIFF in library work. @N:CG364 : CoreTSE_M2S090_SERDES_IF2_0_SERDES_IF2_syn.v(5) | Synthesizing module SERDESIF_075 in library work. @N:CG364 : CoreTSE_M2S090_SERDES_IF2_0_SERDES_IF2.v(5) | Synthesizing module CoreTSE_M2S090_SERDES_IF2_0_SERDES_IF2 in library work. @N:CG364 : smartfusion2.v(718) | Synthesizing module SYSRESET in library work. @N:CG364 : CoreTSE_M2S090.v(9) | Synthesizing module CoreTSE_M2S090 in library work. @W:CL157 : CoreTSE_M2S090_OSC_0_OSC.v(15) | *Output RCOSC_25_50MHZ_CCC has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreTSE_M2S090_OSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreTSE_M2S090_OSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreTSE_M2S090_OSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreTSE_M2S090_OSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @N:CL159 : CoreTSE_M2S090_OSC_0_OSC.v(14) | Input XTL is unused. @W:CL247 : CoreTSE_M2S090_MSS.v(71) | Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused @W:CL246 : CoreTSE_AHB.v(286) | Input port bits 2 to 1 of HSIZE[2:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : CoreTSE_AHB.v(294) | Input port bits 2 to 1 of HBURST[2:0] are unused. Assign logic for all port bits or change the input port size. @N:CL135 : petcr.v(377) | Found sequential shift CORETSEo0OI with address depth of 3 words and data bit width of 1. @W:CL177 : petcr.v(333) | Sharing sequential element CORETSEioOI. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : petcr.v(436) | Sharing sequential element CORETSEiOII. Add a syn_preserve attribute to the element to prevent sharing. @W:CL190 : petbm.v(714) | Optimizing register bit CORETSEIi1o[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : petbm.v(714) | Pruning register bit 5 of CORETSEIi1o[5:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL201 : msgmii_peanx_top.v(3461) | Trying to extract state machine for register CORETSEilIlI. @W:CL247 : msgmii_peanx_top.v(113) | Input port bit 14 of CORETSEo0o0[15:0] is unused @W:CL247 : msgmii_peanx_top.v(113) | Input port bit 11 of CORETSEo0o0[15:0] is unused @N:CL201 : perex_pcs.v(4925) | Trying to extract state machine for register CORETSEIo10. Extracted state machine for register CORETSEIo10 State machine has 4 reachable states with original encodings of: 00 01 10 11 @A:CL153 : perex_pma.v(219) | *Unassigned bits of CORETSEiOo0 are referenced and tied to 0 -- simulation mismatch possible. @N:CL159 : perex_pma.v(75) | Input CORETSEoOo0 is unused. @N:CL159 : perex_pma.v(78) | Input CORETSElOo0 is unused. @W:CL246 : CoreTSE_AHB_top.v(287) | Input port bits 31 to 10 of AHBS_HADDR_I[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : CoreTSE_AHB_top.v(287) | Input port bits 1 to 0 of AHBS_HADDR_I[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL157 : CoreTSE_AHB_top.v(239) | *Output TSMAC_TXD_O has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreTSE_AHB_top.v(242) | *Output TSMAC_TXEN_O has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreTSE_AHB_top.v(245) | *Output TSMAC_TXER_O has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @N:CL159 : CoreTSE_AHB_top.v(206) | Input GTXCLK_I is unused. @N:CL159 : CoreTSE_AHB_top.v(253) | Input TSMAC_RXD_I is unused. @N:CL159 : CoreTSE_AHB_top.v(256) | Input TSMAC_RXDV_I is unused. @N:CL159 : CoreTSE_AHB_top.v(259) | Input TSMAC_RXER_I is unused. @N:CL159 : CoreTSE_AHB_top.v(262) | Input TSMAC_CRS_I is unused. @N:CL159 : CoreTSE_AHB_top.v(265) | Input TSMAC_COL_I is unused. @N:CL159 : CoreTSE_AHB_top.v(473) | Input AHBS_HBURST_I is unused. @N:CL159 : CoreTSE_AHB_top.v(476) | Input AHBS_HMASTLOCK_I is unused. @N:CL159 : CoreTSE_AHB_top.v(479) | Input AHBS_HPROT_I is unused. @N:CL159 : CoreTSE_AHB_top.v(482) | Input AHBS_HSIZE_I is unused. @W:CL246 : pemstat_eim.v(156) | Input port bits 24 to 20 of CORETSEo1Oo[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL247 : pemstat_store.v(181) | Input port bit 31 of CORETSEOllo[31:0] is unused @W:CL246 : pemstat_sincnf.v(44) | Input port bits 30 to 12 of CORETSEOllo[30:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : pemstat_sadd.v(54) | Input port bits 30 to 12 of CORETSEOllo[30:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : pemstat_sinchd.v(44) | Input port bits 30 to 12 of CORETSEOllo[30:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : pemstat_sinc.v(44) | Input port bits 30 to 12 of CORETSEOllo[30:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : pemstat_ladd.v(54) | Input port bits 30 to 24 of CORETSEOllo[30:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : pemstat_linc.v(44) | Input port bits 30 to 18 of CORETSEOllo[30:0] are unused. Assign logic for all port bits or change the input port size. @W:CL247 : pemstat_cntrl.v(51) | Input port bit 22 of CORETSEoo[30:0] is unused @W:CL246 : pemstat_cntrl.v(51) | Input port bits 17 to 16 of CORETSEoo[30:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : pemstat_cntrl.v(62) | Input port bits 31 to 30 of CORETSEoIoI[51:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : pemstat_cntrl.v(62) | Input port bits 23 to 21 of CORETSEoIoI[51:0] are unused. Assign logic for all port bits or change the input port size. @N:CL159 : sib_sync_2flp.v(29) | Input CORETSEO1I0 is unused. @N:CL159 : sib_sync_2flp.v(31) | Input CORETSEI1I0 is unused. @W:CL157 : tsmac_ahb_top.v(282) | *Output CORETSEII1lI has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : tsmac_ahb_top.v(284) | *Output CORETSElI1lI has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : tsmac_ahb_top.v(286) | *Output CORETSEoI1lI has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : tsmac_ahb_top.v(288) | *Output CORETSEiI1lI has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : tsmac_ahb_top.v(290) | *Output CORETSEOl1lI has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @N:CL159 : tsmac_ahb_top.v(272) | Input CORETSEIO1lI is unused. @N:CL159 : tsmac_ahb_top.v(274) | Input CORETSElO1lI is unused. @N:CL159 : tsmac_ahb_top.v(276) | Input CORETSEoO1lI is unused. @N:CL159 : tsmac_ahb_top.v(278) | Input CORETSEiO1lI is unused. @N:CL159 : tsmac_ahb_top.v(280) | Input CORETSEOI1lI is unused. @N:CL159 : pecar.v(120) | Input CORETSElli0 is unused. @N:CL159 : pecar.v(130) | Input CORETSEili0 is unused. @N:CL159 : pecar.v(143) | Input CORETSEo1i0 is unused. @A:CL153 : pehst.v(613) | *Unassigned bits of CORETSEOlI1 are referenced and tied to 0 -- simulation mismatch possible. @A:CL153 : pehst.v(709) | *Unassigned bits of CORETSEIlI1 are referenced and tied to 0 -- simulation mismatch possible. @A:CL153 : pehst.v(714) | *Unassigned bits of CORETSEllI1 are referenced and tied to 0 -- simulation mismatch possible. @A:CL153 : pehst.v(716) | *Unassigned bits of CORETSEolI1 are referenced and tied to 0 -- simulation mismatch possible. @N:CL159 : pehst.v(198) | Input CORETSEloi0 is unused. @N:CL201 : pemgt.v(588) | Trying to extract state machine for register CORETSEo0o1. Extracted state machine for register CORETSEo0o1 State machine has 32 reachable states with original encodings of: 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 @W:CL247 : permc_top.v(98) | Input port bit 0 of CORETSEiI[1:0] is unused @W:CL138 : perfn_top.v(3490) | Removing register 'CORETSEOo' because it is only assigned 0 or its original value. @N:CL201 : perfn_top.v(5295) | Trying to extract state machine for register CORETSEoo. @W:CL246 : perfn_top.v(147) | Input port bits 1 to 0 of CORETSEil[7:0] are unused. Assign logic for all port bits or change the input port size. @N:CL135 : petfn_top.v(6630) | Found sequential shift CORETSEoIll with address depth of 3 words and data bit width of 8. @N:CL135 : petfn_top.v(7633) | Found sequential shift CORETSEilll with address depth of 4 words and data bit width of 1. @N:CL135 : petfn_top.v(7496) | Found sequential shift CORETSEllll with address depth of 4 words and data bit width of 1. @N:CL135 : petfn_top.v(7755) | Found sequential shift CORETSEI0ll with address depth of 4 words and data bit width of 1. @N:CL135 : petfn_top.v(2998) | Found sequential shift CORETSEOoiI with address depth of 3 words and data bit width of 1. @N:CL135 : petfn_top.v(3171) | Found sequential shift CORETSEoOOl with address depth of 3 words and data bit width of 4. @N:CL135 : petfn_top.v(8862) | Found sequential shift CORETSEoIII with address depth of 4 words and data bit width of 1. @N:CL135 : petfn_top.v(8161) | Found sequential shift CORETSEIIII with address depth of 4 words and data bit width of 1. @N:CL201 : petfn_top.v(10871) | Trying to extract state machine for register CORETSEoIoI. @W:CL246 : petfn_top.v(219) | Input port bits 1 to 0 of CORETSEil1I[6:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : petfn_top.v(221) | Input port bits 1 to 0 of CORETSEO01I[6:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : petfn_top.v(223) | Input port bits 1 to 0 of CORETSEI01I[6:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : petfn_top.v(231) | Input port bits 9 to 6 of CORETSEl01I[9:0] are unused. Assign logic for all port bits or change the input port size. @N:CL159 : petfn_top.v(331) | Input CORETSEIOoI is unused. @N:CL159 : petfn_top.v(334) | Input CORETSElOoI is unused. @N:CL159 : petfn_top.v(342) | Input CORETSEoOoI is unused. @N:CL159 : petfn_top.v(345) | Input CORETSEiOoI is unused. @N:CL159 : petfn_top.v(356) | Input CORETSEOIoI is unused. @N:CL159 : petfn_top.v(348) | Input CORETSEIIoI is unused. @W:CL247 : petmc_top.v(113) | Input port bit 0 of CORETSEiI[1:0] is unused @N:CL159 : amcxfif_hst.v(237) | Input CORETSElloi is unused. @N:CL201 : amcxtfif_wtm.v(309) | Trying to extract state machine for register CORETSEOloOI. Extracted state machine for register CORETSEOloOI State machine has 6 reachable states with original encodings of: 000001 000010 000100 001000 010000 100000 @W:CL246 : amcxrfif_sys.v(239) | Input port bits 39 to 36 of CORETSEoIii[39:0] are unused. Assign logic for all port bits or change the input port size. @N:CL135 : amcxrfif_fab.v(1591) | Found sequential shift CORETSElOoi with address depth of 3 words and data bit width of 1. @N:CL201 : amcxrfif_fab.v(1094) | Trying to extract state machine for register genblk1.CORETSEooIOI. Extracted state machine for register genblk1.CORETSEooIOI State machine has 5 reachable states with original encodings of: 0000 1000 1100 1110 1111 @W:CL247 : amcxrfif_fab.v(128) | Input port bit 12 of CORETSEiIii[13:0] is unused @N:CL201 : amcxtfif_sys.v(896) | Trying to extract state machine for register CORETSEOI1OI. Extracted state machine for register CORETSEOI1OI State machine has 6 reachable states with original encodings of: 000001 000010 000100 001000 010000 100000 @W:CL247 : slave.v(74) | Input port bit 0 of HTRANS[1:0] is unused @N:CL159 : dma_dual.v(353) | Input CORETSEiII0I is unused. @N:CL159 : dma_dual.v(361) | Input CORETSEOlI0I is unused. @N:CL201 : dmarx.v(1088) | Trying to extract state machine for register CORETSEii00I. Extracted state machine for register CORETSEii00I State machine has 4 reachable states with original encodings of: 000 100 110 111 @N:CL201 : dmarx.v(546) | Trying to extract state machine for register CORETSEo000I. Extracted state machine for register CORETSEo000I State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL246 : dmarx.v(95) | Input port bits 1 to 0 of HRDATA[31:0] are unused. Assign logic for all port bits or change the input port size. @N:CL201 : dmatx.v(1159) | Trying to extract state machine for register CORETSEii00I. Extracted state machine for register CORETSEii00I State machine has 4 reachable states with original encodings of: 000 100 110 111 @N:CL201 : dmatx.v(611) | Trying to extract state machine for register CORETSEo000I. Extracted state machine for register CORETSEo000I State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state. Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state. Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state. Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state. Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state. Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @N:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused. @N:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused. @N:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused. @N:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused. @N:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused. @N:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused. @N:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused. @N:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused. @N:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused. @N:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused. @N:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused. @N:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused. @N:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused. @N:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused. @N:CL159 : coreresetp.v(107) | Input SOFT_EXT_RESET_OUT is unused. @N:CL159 : coreresetp.v(108) | Input SOFT_RESET_F2M is unused. @N:CL159 : coreresetp.v(109) | Input SOFT_M3_RESET is unused. @N:CL159 : coreresetp.v(110) | Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused. @N:CL159 : coreresetp.v(111) | Input SOFT_FDDR_CORE_RESET is unused. @N:CL159 : coreresetp.v(112) | Input SOFT_SDIF0_PHY_RESET is unused. @N:CL159 : coreresetp.v(113) | Input SOFT_SDIF0_CORE_RESET is unused. @N:CL159 : coreresetp.v(114) | Input SOFT_SDIF1_PHY_RESET is unused. @N:CL159 : coreresetp.v(115) | Input SOFT_SDIF1_CORE_RESET is unused. @N:CL159 : coreresetp.v(116) | Input SOFT_SDIF2_PHY_RESET is unused. @N:CL159 : coreresetp.v(117) | Input SOFT_SDIF2_CORE_RESET is unused. @N:CL159 : coreresetp.v(118) | Input SOFT_SDIF3_PHY_RESET is unused. @N:CL159 : coreresetp.v(119) | Input SOFT_SDIF3_CORE_RESET is unused. @N:CL159 : coreresetp.v(123) | Input SOFT_SDIF0_0_CORE_RESET is unused. @N:CL159 : coreresetp.v(124) | Input SOFT_SDIF0_1_CORE_RESET is unused. @N:CL201 : coreconfigp.v(447) | Trying to extract state machine for register state. Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL246 : CoreAHBLSRAM.v(69) | Input port bits 31 to 20 of HADDR[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : lsram_2048to139264x8.v(64) | Input port bits 15 to 13 of writeAddr[15:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : lsram_2048to139264x8.v(65) | Input port bits 15 to 13 of readAddr[15:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : lsram_2048to139264x8.v(65) | Input port bits 8 to 0 of readAddr[15:0] are unused. Assign logic for all port bits or change the input port size. @N:CL201 : SramCtrlIf.v(138) | Trying to extract state machine for register sramcurr_state. Extracted state machine for register sramcurr_state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL246 : SramCtrlIf.v(78) | Input port bits 19 to 18 of ahbsram_addr[19:0] are unused. Assign logic for all port bits or change the input port size. @W:CL156 : SramCtrlIf.v(118) | *Input l_BUSY_all_3 to expression [or] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @N:CL159 : SramCtrlIf.v(80) | Input ahbsram_wdata_usram is unused. @N:CL201 : AHBLSramIf.v(209) | Trying to extract state machine for register ahbcurr_state. Extracted state machine for register ahbcurr_state State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL159 : AHBLSramIf.v(108) | Input BUSY is unused. @W:CL247 : coreahblite.v(120) | Input port bit 0 of HTRANS_M0[1:0] is unused @W:CL247 : coreahblite.v(131) | Input port bit 0 of HTRANS_M1[1:0] is unused @W:CL247 : coreahblite.v(142) | Input port bit 0 of HTRANS_M2[1:0] is unused @W:CL247 : coreahblite.v(153) | Input port bit 0 of HTRANS_M3[1:0] is unused @W:CL247 : coreahblite.v(163) | Input port bit 1 of HRESP_S0[1:0] is unused @W:CL247 : coreahblite.v(176) | Input port bit 1 of HRESP_S1[1:0] is unused @W:CL247 : coreahblite.v(189) | Input port bit 1 of HRESP_S2[1:0] is unused @W:CL247 : coreahblite.v(202) | Input port bit 1 of HRESP_S3[1:0] is unused @W:CL247 : coreahblite.v(215) | Input port bit 1 of HRESP_S4[1:0] is unused @W:CL247 : coreahblite.v(228) | Input port bit 1 of HRESP_S5[1:0] is unused @W:CL247 : coreahblite.v(241) | Input port bit 1 of HRESP_S6[1:0] is unused @W:CL247 : coreahblite.v(254) | Input port bit 1 of HRESP_S7[1:0] is unused @W:CL247 : coreahblite.v(267) | Input port bit 1 of HRESP_S8[1:0] is unused @W:CL247 : coreahblite.v(280) | Input port bit 1 of HRESP_S9[1:0] is unused @W:CL247 : coreahblite.v(293) | Input port bit 1 of HRESP_S10[1:0] is unused @W:CL247 : coreahblite.v(306) | Input port bit 1 of HRESP_S11[1:0] is unused @W:CL247 : coreahblite.v(319) | Input port bit 1 of HRESP_S12[1:0] is unused @W:CL247 : coreahblite.v(332) | Input port bit 1 of HRESP_S13[1:0] is unused @W:CL247 : coreahblite.v(345) | Input port bit 1 of HRESP_S14[1:0] is unused @W:CL247 : coreahblite.v(358) | Input port bit 1 of HRESP_S15[1:0] is unused @W:CL247 : coreahblite.v(371) | Input port bit 1 of HRESP_S16[1:0] is unused @N:CL159 : coreahblite.v(123) | Input HBURST_M0 is unused. @N:CL159 : coreahblite.v(124) | Input HPROT_M0 is unused. @N:CL159 : coreahblite.v(134) | Input HBURST_M1 is unused. @N:CL159 : coreahblite.v(135) | Input HPROT_M1 is unused. @N:CL159 : coreahblite.v(145) | Input HBURST_M2 is unused. @N:CL159 : coreahblite.v(146) | Input HPROT_M2 is unused. @N:CL159 : coreahblite.v(156) | Input HBURST_M3 is unused. @N:CL159 : coreahblite.v(157) | Input HPROT_M3 is unused. @N:CL159 : coreahblite_matrix4x16.v(69) | Input HWDATA_M3 is unused. @N:CL159 : coreahblite_matrix4x16.v(73) | Input HRDATA_S0 is unused. @N:CL159 : coreahblite_matrix4x16.v(74) | Input HREADYOUT_S0 is unused. @N:CL159 : coreahblite_matrix4x16.v(75) | Input HRESP_S0 is unused. @N:CL159 : coreahblite_matrix4x16.v(84) | Input HRDATA_S1 is unused. @N:CL159 : coreahblite_matrix4x16.v(85) | Input HREADYOUT_S1 is unused. @N:CL159 : coreahblite_matrix4x16.v(86) | Input HRESP_S1 is unused. @N:CL159 : coreahblite_matrix4x16.v(117) | Input HRDATA_S4 is unused. @N:CL159 : coreahblite_matrix4x16.v(118) | Input HREADYOUT_S4 is unused. @N:CL159 : coreahblite_matrix4x16.v(119) | Input HRESP_S4 is unused. @N:CL159 : coreahblite_matrix4x16.v(139) | Input HRDATA_S6 is unused. @N:CL159 : coreahblite_matrix4x16.v(140) | Input HREADYOUT_S6 is unused. @N:CL159 : coreahblite_matrix4x16.v(141) | Input HRESP_S6 is unused. @N:CL159 : coreahblite_matrix4x16.v(150) | Input HRDATA_S7 is unused. @N:CL159 : coreahblite_matrix4x16.v(151) | Input HREADYOUT_S7 is unused. @N:CL159 : coreahblite_matrix4x16.v(152) | Input HRESP_S7 is unused. @N:CL159 : coreahblite_matrix4x16.v(161) | Input HRDATA_S8 is unused. @N:CL159 : coreahblite_matrix4x16.v(162) | Input HREADYOUT_S8 is unused. @N:CL159 : coreahblite_matrix4x16.v(163) | Input HRESP_S8 is unused. @N:CL159 : coreahblite_matrix4x16.v(172) | Input HRDATA_S9 is unused. @N:CL159 : coreahblite_matrix4x16.v(173) | Input HREADYOUT_S9 is unused. @N:CL159 : coreahblite_matrix4x16.v(174) | Input HRESP_S9 is unused. @N:CL159 : coreahblite_matrix4x16.v(183) | Input HRDATA_S10 is unused. @N:CL159 : coreahblite_matrix4x16.v(184) | Input HREADYOUT_S10 is unused. @N:CL159 : coreahblite_matrix4x16.v(185) | Input HRESP_S10 is unused. @N:CL159 : coreahblite_matrix4x16.v(194) | Input HRDATA_S11 is unused. @N:CL159 : coreahblite_matrix4x16.v(195) | Input HREADYOUT_S11 is unused. @N:CL159 : coreahblite_matrix4x16.v(196) | Input HRESP_S11 is unused. @N:CL159 : coreahblite_matrix4x16.v(205) | Input HRDATA_S12 is unused. @N:CL159 : coreahblite_matrix4x16.v(206) | Input HREADYOUT_S12 is unused. @N:CL159 : coreahblite_matrix4x16.v(207) | Input HRESP_S12 is unused. @N:CL159 : coreahblite_matrix4x16.v(216) | Input HRDATA_S13 is unused. @N:CL159 : coreahblite_matrix4x16.v(217) | Input HREADYOUT_S13 is unused. @N:CL159 : coreahblite_matrix4x16.v(218) | Input HRESP_S13 is unused. @N:CL159 : coreahblite_matrix4x16.v(227) | Input HRDATA_S14 is unused. @N:CL159 : coreahblite_matrix4x16.v(228) | Input HREADYOUT_S14 is unused. @N:CL159 : coreahblite_matrix4x16.v(229) | Input HRESP_S14 is unused. @N:CL159 : coreahblite_matrix4x16.v(238) | Input HRDATA_S15 is unused. @N:CL159 : coreahblite_matrix4x16.v(239) | Input HREADYOUT_S15 is unused. @N:CL159 : coreahblite_matrix4x16.v(240) | Input HRESP_S15 is unused. @N:CL159 : coreahblite_matrix4x16.v(249) | Input HRDATA_S16 is unused. @N:CL159 : coreahblite_matrix4x16.v(250) | Input HREADYOUT_S16 is unused. @N:CL159 : coreahblite_matrix4x16.v(251) | Input HRESP_S16 is unused. @N:CL201 : coreahblite_slavearbiter.v(449) | Trying to extract state machine for register arbRegSMCurrentState. Extracted state machine for register arbRegSMCurrentState State machine has 16 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 @N:CL159 : coreahblite_masterstage.v(42) | Input SDATAREADY is unused. @N:CL159 : coreahblite_masterstage.v(43) | Input SHRESP is unused. @N:CL159 : coreahblite_masterstage.v(52) | Input HRDATA_S0 is unused. @N:CL159 : coreahblite_masterstage.v(53) | Input HREADYOUT_S0 is unused. @N:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused. @N:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused. @N:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused. @N:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused. @N:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused. @N:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused. @N:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused. @N:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused. @N:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused. @N:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused. @N:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused. @N:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused. @N:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused. @N:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused. @N:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused. @N:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused. @N:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused. @N:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused. @N:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused. @N:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused. @N:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused. @N:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused. @N:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused. @N:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused. @N:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused. @N:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused. @N:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused. @N:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused. @N:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused. @N:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused. @N:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S16 is unused. @N:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S16 is unused. @W:CL246 : coreahblite_masterstage.v(42) | Input port bits 16 to 6 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : coreahblite_masterstage.v(42) | Input port bits 4 to 3 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : coreahblite_masterstage.v(42) | Input port bits 1 to 0 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : coreahblite_masterstage.v(43) | Input port bits 16 to 6 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : coreahblite_masterstage.v(43) | Input port bits 4 to 3 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : coreahblite_masterstage.v(43) | Input port bits 1 to 0 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size. @N:CL159 : coreahblite_masterstage.v(52) | Input HRDATA_S0 is unused. @N:CL159 : coreahblite_masterstage.v(53) | Input HREADYOUT_S0 is unused. @N:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused. @N:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused. @N:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused. @N:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused. @N:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused. @N:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused. @N:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused. @N:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused. @N:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused. @N:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused. @N:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused. @N:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused. @N:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused. @N:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused. @N:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused. @N:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused. @N:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused. @N:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused. @N:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused. @N:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused. @N:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused. @N:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused. @N:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused. @N:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused. @N:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused. @N:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused. @N:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S16 is unused. @N:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S16 is unused. @W:CL246 : coreahblite_masterstage.v(42) | Input port bits 16 to 6 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size. @W:CL247 : coreahblite_masterstage.v(42) | Input port bit 4 of SDATAREADY[16:0] is unused @W:CL246 : coreahblite_masterstage.v(42) | Input port bits 2 to 0 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : coreahblite_masterstage.v(43) | Input port bits 16 to 6 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size. @W:CL247 : coreahblite_masterstage.v(43) | Input port bit 4 of SHRESP[16:0] is unused @W:CL246 : coreahblite_masterstage.v(43) | Input port bits 2 to 0 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size. @N:CL159 : coreahblite_masterstage.v(52) | Input HRDATA_S0 is unused. @N:CL159 : coreahblite_masterstage.v(53) | Input HREADYOUT_S0 is unused. @N:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused. @N:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused. @N:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused. @N:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused. @N:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused. @N:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused. @N:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused. @N:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused. @N:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused. @N:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused. @N:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused. @N:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused. @N:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused. @N:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused. @N:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused. @N:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused. @N:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused. @N:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused. @N:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused. @N:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused. @N:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused. @N:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused. @N:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused. @N:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused. @N:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused. @N:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused. @N:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S16 is unused. @N:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S16 is unused. At c_ver Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 144MB peak: 166MB) Process took 0h:00m:07s realtime, 0h:00m:07s cputime Process completed successfully. # Tue Mar 14 15:02:37 2017 ###########################################################] Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 100MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Mar 14 15:02:38 2017 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:08s realtime, 0h:00m:08s cputime Process completed successfully. # Tue Mar 14 15:02:38 2017 ###########################################################] Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 114MB peak: 115MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Mar 14 15:02:40 2017 ###########################################################] Pre-mapping Report # Tue Mar 14 15:02:40 2017 Synopsys Generic Technology Pre-mapping, Version map201609actrcp1, Build 005R, Built Jan 25 2017 01:01:33 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.09M-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Reading constraint file: D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\designer\CoreTSE_M2S090\synthesis.fdc Linked File: CoreTSE_M2S090_scck.rpt Printing clock summary report in "D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\synthesis\CoreTSE_M2S090_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 178MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 178MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 151MB peak: 178MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 151MB peak: 178MB) @W:BN132 : coreahblite_matrix4x16.v(3626) | Removing user instance CoreAHBLite_1.matrix4x16.slavestage_16 because it is equivalent to instance CoreAHBLite_1.matrix4x16.slavestage_15. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3580) | Removing user instance CoreAHBLite_1.matrix4x16.slavestage_15 because it is equivalent to instance CoreAHBLite_1.matrix4x16.slavestage_14. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3534) | Removing user instance CoreAHBLite_1.matrix4x16.slavestage_14 because it is equivalent to instance CoreAHBLite_1.matrix4x16.slavestage_13. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3488) | Removing user instance CoreAHBLite_1.matrix4x16.slavestage_13 because it is equivalent to instance CoreAHBLite_1.matrix4x16.slavestage_12. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3442) | Removing user instance CoreAHBLite_1.matrix4x16.slavestage_12 because it is equivalent to instance CoreAHBLite_1.matrix4x16.slavestage_11. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3396) | Removing user instance CoreAHBLite_1.matrix4x16.slavestage_11 because it is equivalent to instance CoreAHBLite_1.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3304) | Removing user instance CoreAHBLite_1.matrix4x16.slavestage_9 because it is equivalent to instance CoreAHBLite_1.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3258) | Removing user instance CoreAHBLite_1.matrix4x16.slavestage_8 because it is equivalent to instance CoreAHBLite_1.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3212) | Removing user instance CoreAHBLite_1.matrix4x16.slavestage_7 because it is equivalent to instance CoreAHBLite_1.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3166) | Removing user instance CoreAHBLite_1.matrix4x16.slavestage_6 because it is equivalent to instance CoreAHBLite_1.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MO111 : tsmac_ahb_top.v(282) | Tristate driver CORETSEII1lI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_TSMAC_AHB_TOP_Z10(verilog)) on net CORETSEII1lI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_TSMAC_AHB_TOP_Z10(verilog)) has its enable tied to GND. @N:MO111 : tsmac_ahb_top.v(290) | Tristate driver CORETSEOl1lI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_TSMAC_AHB_TOP_Z10(verilog)) on net CORETSEOl1lI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_TSMAC_AHB_TOP_Z10(verilog)) has its enable tied to GND. @N:MO111 : tsmac_ahb_top.v(288) | Tristate driver CORETSEiI1lI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_TSMAC_AHB_TOP_Z10(verilog)) on net CORETSEiI1lI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_TSMAC_AHB_TOP_Z10(verilog)) has its enable tied to GND. @N:MO111 : tsmac_ahb_top.v(284) | Tristate driver CORETSElI1lI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_TSMAC_AHB_TOP_Z10(verilog)) on net CORETSElI1lI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_TSMAC_AHB_TOP_Z10(verilog)) has its enable tied to GND. @N:MO111 : tsmac_ahb_top.v(286) | Tristate driver CORETSEoI1lI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_TSMAC_AHB_TOP_Z10(verilog)) on net CORETSEoI1lI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_TSMAC_AHB_TOP_Z10(verilog)) has its enable tied to GND. @N:MO111 : coretse_ahb_top.v(239) | Tristate driver TSMAC_TXD_O_1 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP_19s_1s_11s_12s_1s_1s_1s_18s_0s(verilog)) on net TSMAC_TXD_O_1 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP_19s_1s_11s_12s_1s_1s_1s_18s_0s(verilog)) has its enable tied to GND. @N:MO111 : coretse_ahb_top.v(239) | Tristate driver TSMAC_TXD_O_2 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP_19s_1s_11s_12s_1s_1s_1s_18s_0s(verilog)) on net TSMAC_TXD_O_2 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP_19s_1s_11s_12s_1s_1s_1s_18s_0s(verilog)) has its enable tied to GND. @N:MO111 : coretse_ahb_top.v(239) | Tristate driver TSMAC_TXD_O_3 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP_19s_1s_11s_12s_1s_1s_1s_18s_0s(verilog)) on net TSMAC_TXD_O_3 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP_19s_1s_11s_12s_1s_1s_1s_18s_0s(verilog)) has its enable tied to GND. @N:MO111 : coretse_ahb_top.v(239) | Tristate driver TSMAC_TXD_O_4 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP_19s_1s_11s_12s_1s_1s_1s_18s_0s(verilog)) on net TSMAC_TXD_O_4 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP_19s_1s_11s_12s_1s_1s_1s_18s_0s(verilog)) has its enable tied to GND. @N:MO111 : coretse_ahb_top.v(239) | Tristate driver TSMAC_TXD_O_5 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP_19s_1s_11s_12s_1s_1s_1s_18s_0s(verilog)) on net TSMAC_TXD_O_5 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP_19s_1s_11s_12s_1s_1s_1s_18s_0s(verilog)) has its enable tied to GND. @W:MO129 : pecar.v(886) | Sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEilI1.CORETSEi001 is reduced to a combinational gate by constant propagation. @W:MO129 : pecar.v(872) | Sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEilI1.CORETSEo001 is reduced to a combinational gate by constant propagation. @W:MO129 : pecar.v(1055) | Sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEilI1.CORETSEIo01 is reduced to a combinational gate by constant propagation. @W:MO129 : pecar.v(1041) | Sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEilI1.CORETSEOo01 is reduced to a combinational gate by constant propagation. @W:MO129 : msgmii_clkrst.v(337) | Sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI.CORETSEo1O0I.CORETSEOIiII.CORETSEl10II is reduced to a combinational gate by constant propagation. @W:MO129 : msgmii_clkrst.v(350) | Sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI.CORETSEo1O0I.CORETSEOIiII.CORETSEo10II is reduced to a combinational gate by constant propagation. @W:MO129 : msgmii_clkrst.v(389) | Sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI.CORETSEo1O0I.CORETSEOIiII.CORETSEOo0II is reduced to a combinational gate by constant propagation. @W:MO129 : msgmii_clkrst.v(376) | Sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI.CORETSEo1O0I.CORETSEOIiII.CORETSEi10II is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance CoreResetP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : msgmii_clkrst.v(415) | Sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI.CORETSEo1O0I.CORETSEOIiII.CORETSEIo0II is reduced to a combinational gate by constant propagation. @W:MO129 : msgmii_clkrst.v(454) | Sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI.CORETSEo1O0I.CORETSEOIiII.CORETSEO00II is reduced to a combinational gate by constant propagation. @W:MO129 : msgmii_clkrst.v(428) | Sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI.CORETSEo1O0I.CORETSEOIiII.CORETSElo0II is reduced to a combinational gate by constant propagation. @W:MO129 : petcr.v(185) | Sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI.CORETSEo1O0I.CORETSEoIiII.CORETSElIi0.CORETSEO1OI is reduced to a combinational gate by constant propagation. @W:MO129 : petcr.v(171) | Sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI.CORETSEo1O0I.CORETSEoIiII.CORETSElIi0.CORETSEi0OI is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance CoreResetP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance CoreResetP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance CoreResetP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance CoreResetP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance CoreResetP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance CoreResetP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance CoreResetP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance CoreResetP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance CoreResetP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(1388) | Sequential instance CoreResetP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance CoreResetP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance CoreResetP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance CoreResetP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance CoreResetP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation. @N:BN115 : coreahblite_masterstage.v(209) | Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0s_0_1_0(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z3(verilog) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHTRANS (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0s_0_1_0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(639) | Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0s_0_1_0(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_2_1(verilog) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(2831) | Removing instance masterstage_3 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_1_1_0_40_36_36_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0s_0_1_0(verilog) because it does not drive other instances. @N:BN362 : pemgt.v(2294) | Removing sequential instance CORETSEoII1 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance MDDR_PENABLE (in view: work.CoreConfigP_Z7(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE (in view: work.CoreConfigP_Z7(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF1_PENABLE (in view: work.CoreConfigP_Z7(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE (in view: work.CoreConfigP_Z7(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF3_PENABLE (in view: work.CoreConfigP_Z7(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : pecar.v(630) | Removing sequential instance CORETSEOoOI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(683) | Removing sequential instance CORETSEioOI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(1196) | Removing sequential instance CORETSEIO11 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(1240) | Removing sequential instance CORETSEiO11 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : sib_sync_pulse.v(262) | Removing sequential instance CORETSEo1l0\.CORETSEI0l0 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_SIB_SYNC_PULSE_19s_0s_0s_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : sib_sync_pulse.v(262) | Removing sequential instance CORETSEo1l0\.CORETSEI0l0 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_SIB_SYNC_PULSE_19s_0s_0s_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(2890) | Removing instance slavestage_0 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_1_1_0_40_36_36_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_3(verilog) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[3:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_3(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : pecar.v(616) | Removing sequential instance CORETSEi1OI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(669) | Removing sequential instance CORETSEooOI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(1182) | Removing sequential instance CORETSEOO11 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(1226) | Removing sequential instance CORETSEoO11 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(420) | Removing sequential instance CORETSElol1 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(471) | Removing sequential instance CORETSEIil1 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(9929) | Removing sequential instance block16 (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_lsram_2048to139264x8_4096s_0s_32s(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(9949) | Removing sequential instance block15 (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_lsram_2048to139264x8_4096s_0s_32s(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(9969) | Removing sequential instance block14 (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_lsram_2048to139264x8_4096s_0s_32s(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(9989) | Removing sequential instance block13 (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_lsram_2048to139264x8_4096s_0s_32s(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(10009) | Removing sequential instance block12 (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_lsram_2048to139264x8_4096s_0s_32s(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(10029) | Removing sequential instance block11 (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_lsram_2048to139264x8_4096s_0s_32s(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(10049) | Removing sequential instance block10 (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_lsram_2048to139264x8_4096s_0s_32s(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(10069) | Removing sequential instance block9 (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_lsram_2048to139264x8_4096s_0s_32s(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(10089) | Removing sequential instance block8 (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_lsram_2048to139264x8_4096s_0s_32s(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(10109) | Removing sequential instance block7 (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_lsram_2048to139264x8_4096s_0s_32s(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(10129) | Removing sequential instance block6 (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_lsram_2048to139264x8_4096s_0s_32s(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(10149) | Removing sequential instance block5 (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_lsram_2048to139264x8_4096s_0s_32s(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(10169) | Removing sequential instance block4 (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_lsram_2048to139264x8_4096s_0s_32s(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(10189) | Removing sequential instance block3 (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_lsram_2048to139264x8_4096s_0s_32s(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(10209) | Removing sequential instance block2 (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_lsram_2048to139264x8_4096s_0s_32s(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : pemgt.v(2778) | Removing sequential instance CORETSEIlOo (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : pecar.v(406) | Removing sequential instance CORETSEIol1 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(457) | Removing sequential instance CORETSEOil1 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(1099) | Removing sequential instance CORETSEio01 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(1143) | Removing sequential instance CORETSEli01 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(1085) | Removing sequential instance CORETSEoo01 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(1129) | Removing sequential instance CORETSEIi01 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN115 : coreahblite_slavestage.v(87) | Removing instance slave_arbiter (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_3(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_0(verilog) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_0(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. syn_allowed_resources : blockrams=109 set on top level netlist CoreTSE_M2S090 Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 192MB) Clock Summary ***************** Start Requested Requested Clock Clock Clock Clock Frequency Period Type Group Load ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ CLK1_PAD 50.0 MHz 20.000 declared default_clkgroup 0 CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 292 CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB 12.5 MHz 80.000 declared default_clkgroup 94 CoreTSE_M2S090_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_1 1 FCCC_0/GL0 50.0 MHz 20.000 generated (from CLK1_PAD) default_clkgroup 3072 FCCC_1/GL0 125.0 MHz 8.000 generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup 434 FCCC_2/GL0 125.0 MHz 8.000 generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]) default_clkgroup 354 FCCC_3/GL0 125.0 MHz 8.000 generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]) default_clkgroup 0 FCCC_3/GL1 125.0 MHz 8.000 generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]) default_clkgroup 1506 OSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 20.000 declared default_clkgroup 30 SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] 125.0 MHz 8.000 declared default_clkgroup 0 SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1] 125.0 MHz 8.000 declared default_clkgroup 0 System 100.0 MHz 10.000 system system_clkgroup 0 ================================================================================================================================================================================================ @W:MT530 : pemgt.v(1956) | Found inferred clock CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock which controls 292 sequential elements including CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEOII1.CORETSEOii1[7:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coretse_m2s090_serdes_if2_0_serdes_if2.v(103) | Found inferred clock CoreTSE_M2S090_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock which controls 1 sequential elements including SERDES_IF2_0.SERDESIF_INST. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\synthesis\CoreTSE_M2S090.sap. Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 184MB peak: 192MB) Encoding state machine arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 Encoding state machine arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_2(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 Encoding state machine arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_3(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 Encoding state machine ahbcurr_state[2:0] (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_AHBLSramIf_Z6(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine sramcurr_state[2:0] (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_SramCtrlIf_0s_4096s_4096s_512s_128s_32s_0s_0_1_2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine state[2:0] (in view: work.CoreConfigP_Z7(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z8(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sdif0_state[3:0] (in view: work.CoreResetP_Z8(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : coreresetp.v(1170) | There are no possible illegal states for state machine sdif0_state[3:0] (in view: work.CoreResetP_Z8(verilog)); safe FSM implementation is not required. Encoding state machine CORETSEo000I[3:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_DMATX_19s_0s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : dmatx.v(611) | There are no possible illegal states for state machine CORETSEo000I[3:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_DMATX_19s_0s(verilog)); safe FSM implementation is not required. Encoding state machine CORETSEii00I[3:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_DMATX_19s_0s(verilog)) original code -> new code 000 -> 00 100 -> 01 110 -> 10 111 -> 11 @N:MO225 : dmatx.v(1159) | There are no possible illegal states for state machine CORETSEii00I[3:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_DMATX_19s_0s(verilog)); safe FSM implementation is not required. Encoding state machine CORETSEii00I[3:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_DMARX_19s_0s(verilog)) original code -> new code 000 -> 00 100 -> 01 110 -> 10 111 -> 11 @N:MO225 : dmarx.v(1088) | There are no possible illegal states for state machine CORETSEii00I[3:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_DMARX_19s_0s(verilog)); safe FSM implementation is not required. Encoding state machine CORETSEo000I[3:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_DMARX_19s_0s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : dmarx.v(546) | There are no possible illegal states for state machine CORETSEo000I[3:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_DMARX_19s_0s(verilog)); safe FSM implementation is not required. Encoding state machine CORETSEOI1OI[5:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_AMCXTFIF_SYS_19s_11s_32s_2s_0s_0_0_1s(verilog)) original code -> new code 000001 -> 000001 000010 -> 000010 000100 -> 000100 001000 -> 001000 010000 -> 010000 100000 -> 100000 Encoding state machine genblk1\.CORETSEooIOI[4:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_AMCXRFIF_FAB_19s_12s_32s_2s_0_1s(verilog)) original code -> new code 0000 -> 00001 1000 -> 00010 1100 -> 00100 1110 -> 01000 1111 -> 10000 Encoding state machine CORETSEOloOI[5:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_AMCXTFIF_WTM_19s_12s_1s_0_0(verilog)) original code -> new code 000001 -> 000001 000010 -> 000010 000100 -> 000100 001000 -> 001000 010000 -> 010000 100000 -> 100000 Encoding state machine CORETSEo0o1[31:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s(verilog)) original code -> new code 00000 -> 00000000000000000000000000000001 00001 -> 00000000000000000000000000000010 00010 -> 00000000000000000000000000000100 00011 -> 00000000000000000000000000001000 00100 -> 00000000000000000000000000010000 00101 -> 00000000000000000000000000100000 00110 -> 00000000000000000000000001000000 00111 -> 00000000000000000000000010000000 01000 -> 00000000000000000000000100000000 01001 -> 00000000000000000000001000000000 01010 -> 00000000000000000000010000000000 01011 -> 00000000000000000000100000000000 01100 -> 00000000000000000001000000000000 01101 -> 00000000000000000010000000000000 01110 -> 00000000000000000100000000000000 01111 -> 00000000000000001000000000000000 10000 -> 00000000000000010000000000000000 10001 -> 00000000000000100000000000000000 10010 -> 00000000000001000000000000000000 10011 -> 00000000000010000000000000000000 10100 -> 00000000000100000000000000000000 10101 -> 00000000001000000000000000000000 10110 -> 00000000010000000000000000000000 10111 -> 00000000100000000000000000000000 11000 -> 00000001000000000000000000000000 11001 -> 00000010000000000000000000000000 11010 -> 00000100000000000000000000000000 11011 -> 00001000000000000000000000000000 11100 -> 00010000000000000000000000000000 11101 -> 00100000000000000000000000000000 11110 -> 01000000000000000000000000000000 11111 -> 10000000000000000000000000000000 Encoding state machine CORETSEIo10_1[3:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PEREX_PCS_0s_19s_1s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : perex_pcs.v(4925) | There are no possible illegal states for state machine CORETSEIo10_1[3:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PEREX_PCS_0s_19s_1s(verilog)); safe FSM implementation is not required. @N:BN362 : perfn_top.v(3798) | Removing sequential instance CORETSEOOI[0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PERFN_TOP_19s_0s_0_1s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : perfn_top.v(3798) | Removing sequential instance CORETSEOOI[1] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PERFN_TOP_19s_0s_0_1s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : ahblsramif.v(184) | Removing sequential instance HADDR_d[15] (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_AHBLSramIf_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : ahblsramif.v(184) | Removing sequential instance HADDR_d[16] (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_AHBLSramIf_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : ahblsramif.v(184) | Removing sequential instance HADDR_d[17] (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_AHBLSramIf_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : ahblsramif.v(184) | Removing sequential instance HADDR_d[18] (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_AHBLSramIf_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : ahblsramif.v(184) | Removing sequential instance HADDR_d[19] (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_AHBLSramIf_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @W:MF511 : | Found issues with constraints. Please check constraint checker report "D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\synthesis\CoreTSE_M2S090_cck.rpt" . Finished constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 203MB peak: 208MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 106MB peak: 208MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime # Tue Mar 14 15:02:44 2017 ###########################################################] Map & Optimize Report # Tue Mar 14 15:02:44 2017 Synopsys Generic Technology Mapper, Version map201609actrcp1, Build 005R, Built Jan 25 2017 01:01:33 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.09M-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 165MB peak: 167MB) @N:MO111 : tsmac_ahb_top.v(290) | Tristate driver CORETSEOl1lI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_TSMAC_AHB_TOP_Z10(verilog)) on net CORETSEOl1lI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_TSMAC_AHB_TOP_Z10(verilog)) has its enable tied to GND. @N:MO111 : tsmac_ahb_top.v(288) | Tristate driver CORETSEiI1lI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_TSMAC_AHB_TOP_Z10(verilog)) on net CORETSEiI1lI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_TSMAC_AHB_TOP_Z10(verilog)) has its enable tied to GND. @N:MO111 : tsmac_ahb_top.v(286) | Tristate driver CORETSEoI1lI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_TSMAC_AHB_TOP_Z10(verilog)) on net CORETSEoI1lI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_TSMAC_AHB_TOP_Z10(verilog)) has its enable tied to GND. @N:MO111 : tsmac_ahb_top.v(284) | Tristate driver CORETSElI1lI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_TSMAC_AHB_TOP_Z10(verilog)) on net CORETSElI1lI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_TSMAC_AHB_TOP_Z10(verilog)) has its enable tied to GND. @N:MO111 : tsmac_ahb_top.v(282) | Tristate driver CORETSEII1lI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_TSMAC_AHB_TOP_Z10(verilog)) on net CORETSEII1lI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_TSMAC_AHB_TOP_Z10(verilog)) has its enable tied to GND. @N:MO111 : coretse_ahb_top.v(245) | Tristate driver TSMAC_TXER_O (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP_19s_1s_11s_12s_1s_1s_1s_18s_0s(verilog)) on net TSMAC_TXER_O (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP_19s_1s_11s_12s_1s_1s_1s_18s_0s(verilog)) has its enable tied to GND. @N:MO111 : coretse_ahb_top.v(242) | Tristate driver TSMAC_TXEN_O (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP_19s_1s_11s_12s_1s_1s_1s_18s_0s(verilog)) on net TSMAC_TXEN_O (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP_19s_1s_11s_12s_1s_1s_1s_18s_0s(verilog)) has its enable tied to GND. @N:MO111 : coretse_ahb_top.v(239) | Tristate driver TSMAC_TXD_O_1 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP_19s_1s_11s_12s_1s_1s_1s_18s_0s(verilog)) on net TSMAC_TXD_O_1 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP_19s_1s_11s_12s_1s_1s_1s_18s_0s(verilog)) has its enable tied to GND. @N:MO111 : coretse_ahb_top.v(239) | Tristate driver TSMAC_TXD_O_2 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP_19s_1s_11s_12s_1s_1s_1s_18s_0s(verilog)) on net TSMAC_TXD_O_2 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP_19s_1s_11s_12s_1s_1s_1s_18s_0s(verilog)) has its enable tied to GND. @N:MO111 : coretse_ahb_top.v(239) | Tristate driver TSMAC_TXD_O_3 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP_19s_1s_11s_12s_1s_1s_1s_18s_0s(verilog)) on net TSMAC_TXD_O_3 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP_19s_1s_11s_12s_1s_1s_1s_18s_0s(verilog)) has its enable tied to GND. @W:BN132 : coreresetp.v(963) | Removing sequential instance CoreResetP_0.sdif3_spll_lock_q1 because it is equivalent to instance CoreResetP_0.sdif0_spll_lock_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(963) | Removing sequential instance CoreResetP_0.sdif3_spll_lock_q2 because it is equivalent to instance CoreResetP_0.sdif0_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(884) | Removing sequential instance CoreResetP_0.sdif1_areset_n_rcosc_q1 because it is equivalent to instance CoreResetP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(912) | Removing sequential instance CoreResetP_0.sdif3_areset_n_rcosc_q1 because it is equivalent to instance CoreResetP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(898) | Removing sequential instance CoreResetP_0.sdif2_areset_n_rcosc_q1 because it is equivalent to instance CoreResetP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(755) | Removing sequential instance CoreResetP_0.sm0_areset_n_q1 because it is equivalent to instance CoreResetP_0.sdif0_areset_n_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(912) | Removing sequential instance CoreResetP_0.sdif3_areset_n_rcosc because it is equivalent to instance CoreResetP_0.sdif2_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(898) | Removing sequential instance CoreResetP_0.sdif2_areset_n_rcosc because it is equivalent to instance CoreResetP_0.sdif1_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(884) | Removing sequential instance CoreResetP_0.sdif1_areset_n_rcosc because it is equivalent to instance CoreResetP_0.sdif0_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(797) | Removing sequential instance CoreResetP_0.sdif0_areset_n_clk_base because it is equivalent to instance CoreResetP_0.sm0_areset_n_clk_base. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:BN362 : pecar.v(951) | Removing sequential instance CORETSEilI1.CORETSEl101 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PE_MCXMAC_19s_0_0s_0s(verilog)) of type view:PrimLib.sdffr(prim) because it does not drive other instances. @N:BN362 : pecar.v(907) | Removing sequential instance CORETSEilI1.CORETSEI101 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PE_MCXMAC_19s_0_0s_0s(verilog)) of type view:PrimLib.sdffr(prim) because it does not drive other instances. @N:BN362 : petcr.v(206) | Removing sequential instance CORETSElIi0.CORETSEl1OI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_TBI_19s_0s_0s_1s(verilog)) of type view:PrimLib.sdffr(prim) because it does not drive other instances. Available hyper_sources - for debug and ip models None Found @W:FA239 : t8b10b.v(148) | ROM CORETSEiol0[5:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_T8B10B(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : t8b10b.v(148) | ROM CORETSEIil0[1:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_T8B10B(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : t8b10b.v(148) | ROM CORETSEOil0 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_T8B10B(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : t8b10b.v(148) | ROM CORETSEO0ol (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_T8B10B(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : t8b10b.v(148) | ROM CORETSEiol0[5:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_T8B10B(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : t8b10b.v(148) | Found ROM .delname. (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_T8B10B(verilog)) with 32 words by 6 bits. @W:FA239 : t8b10b.v(148) | ROM CORETSEIil0[1:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_T8B10B(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : t8b10b.v(148) | Found ROM .delname. (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_T8B10B(verilog)) with 32 words by 2 bits. @W:FA239 : t8b10b.v(148) | ROM CORETSEOil0 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_T8B10B(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : t8b10b.v(148) | Found ROM .delname. (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_T8B10B(verilog)) with 32 words by 1 bit. @W:FA239 : t8b10b.v(148) | ROM CORETSEO0ol (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_T8B10B(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : t8b10b.v(148) | Found ROM .delname. (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_T8B10B(verilog)) with 32 words by 1 bit. @W:FA239 : r10b8b.v(3418) | ROM CORETSEoiol (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(3418) | ROM CORETSEiiol (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(1261) | ROM CORETSEl0ol[2:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(1261) | ROM CORETSEI1ol[2:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(1261) | ROM CORETSEO1ol[1:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(268) | ROM CORETSEI0ol[1:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(3418) | ROM CORETSEoiol (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(3418) | Found ROM .delname. (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) with 16 words by 1 bit. @W:FA239 : r10b8b.v(3418) | ROM CORETSEiiol (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(3418) | Found ROM .delname. (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) with 16 words by 1 bit. @W:FA239 : r10b8b.v(1950) | ROM CORETSEi1ol[2:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1950) | Found ROM .delname. (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) with 12 words by 3 bits. @W:FA239 : r10b8b.v(1950) | ROM CORETSEIool (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1950) | Found ROM .delname. (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) with 12 words by 1 bit. @W:FA239 : r10b8b.v(1261) | ROM CORETSEl0ol[2:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1261) | Found ROM .delname. (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) with 14 words by 3 bits. @W:FA239 : r10b8b.v(1261) | ROM CORETSEI1ol[2:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1261) | Found ROM .delname. (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) with 14 words by 3 bits. @W:FA239 : r10b8b.v(1261) | ROM CORETSEO1ol[1:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1261) | Found ROM .delname. (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) with 14 words by 2 bits. @W:FA239 : r10b8b.v(268) | ROM CORETSEI0ol[1:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(268) | Found ROM .delname. (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) with 46 words by 2 bits. @W:FA239 : r10b8b.v(3418) | ROM CORETSEoiol (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(3418) | ROM CORETSEiiol (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(1261) | ROM CORETSEl0ol[2:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(1261) | ROM CORETSEI1ol[2:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(1261) | ROM CORETSEO1ol[1:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(268) | ROM CORETSEI0ol[1:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(1950) | ROM CORETSEi1ol[3:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1950) | Found ROM .delname. (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) with 12 words by 4 bits. @W:FA239 : r10b8b.v(3418) | ROM CORETSEoiol (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(3418) | Found ROM .delname. (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) with 16 words by 1 bit. @W:FA239 : r10b8b.v(3418) | ROM CORETSEiiol (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(3418) | Found ROM .delname. (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) with 16 words by 1 bit. @W:FA239 : r10b8b.v(1261) | ROM CORETSEl0ol[2:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1261) | Found ROM .delname. (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) with 14 words by 3 bits. @W:FA239 : r10b8b.v(1261) | ROM CORETSEI1ol[2:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1261) | Found ROM .delname. (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) with 14 words by 3 bits. @W:FA239 : r10b8b.v(1261) | ROM CORETSEO1ol[1:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1261) | Found ROM .delname. (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) with 14 words by 2 bits. @W:FA239 : r10b8b.v(268) | ROM CORETSEI0ol[1:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(268) | Found ROM .delname. (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) with 46 words by 2 bits. @N:BN362 : ahblsramif.v(390) | Removing sequential instance ahbsram_wdata_usram_d[31:0] (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_AHBLSramIf_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : pemgt.v(2239) | Removing sequential instance CORETSElII1[4:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : msgmii_cnvtxo.v(463) | Removing sequential instance CORETSEiioII (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_CNVTXO_19s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 169MB peak: 178MB) @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_0.regHADDR[20] (in view: work.CoreTSE_M2S090(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_0.regHADDR[21] (in view: work.CoreTSE_M2S090(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_0.regHADDR[22] (in view: work.CoreTSE_M2S090(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_0.regHADDR[23] (in view: work.CoreTSE_M2S090(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_0.regHADDR[24] (in view: work.CoreTSE_M2S090(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_0.regHADDR[25] (in view: work.CoreTSE_M2S090(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_0.regHADDR[26] (in view: work.CoreTSE_M2S090(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_0.regHADDR[27] (in view: work.CoreTSE_M2S090(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_1.matrix4x16.masterstage_0.regHSIZE[2] (in view view:work.CoreTSE_M2S090(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_1.matrix4x16.masterstage_1.SDATASELInt[16] (in view view:work.CoreTSE_M2S090(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_1.matrix4x16.masterstage_1.regHSIZE[2] (in view view:work.CoreTSE_M2S090(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_1.matrix4x16.masterstage_1.regHSIZE[0] (in view view:work.CoreTSE_M2S090(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_1.matrix4x16.masterstage_1.regHADDR[1] (in view view:work.CoreTSE_M2S090(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_1.matrix4x16.masterstage_1.regHADDR[0] (in view view:work.CoreTSE_M2S090(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_1.matrix4x16.masterstage_2.SDATASELInt[16] (in view view:work.CoreTSE_M2S090(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_1.matrix4x16.masterstage_2.regHSIZE[2] (in view view:work.CoreTSE_M2S090(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_1.matrix4x16.masterstage_2.regHSIZE[0] (in view view:work.CoreTSE_M2S090(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_1.matrix4x16.masterstage_2.regHADDR[1] (in view view:work.CoreTSE_M2S090(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_1.matrix4x16.masterstage_2.regHADDR[0] (in view view:work.CoreTSE_M2S090(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt[16] (in view view:work.CoreTSE_M2S090(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_1.matrix4x16.slavestage_3.masterDataInProg[3] (in view: work.CoreTSE_M2S090(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_1.matrix4x16.slavestage_3.masterDataInProg[2] (in view: work.CoreTSE_M2S090(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_1.matrix4x16.slavestage_3.masterDataInProg[1] (in view: work.CoreTSE_M2S090(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. Encoding state machine arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[15] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[12] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[11] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[7] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[3] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[0] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO197 : coreahblite_slavearbiter.v(449) | Removing FSM register arbRegSMCurrentState[14] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) because its output is a constant. @W:MO197 : coreahblite_slavearbiter.v(449) | Removing FSM register arbRegSMCurrentState[10] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) because its output is a constant. @W:MO197 : coreahblite_slavearbiter.v(449) | Removing FSM register arbRegSMCurrentState[6] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) because its output is a constant. @W:MO197 : coreahblite_slavearbiter.v(449) | Removing FSM register arbRegSMCurrentState[2] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) because its output is a constant. @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[1] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_2(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[12] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[8] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[4] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_3(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[15] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_3(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[12] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_3(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[11] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_3(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[7] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_3(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[3] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_3(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO197 : coreahblite_slavearbiter.v(449) | Removing FSM register arbRegSMCurrentState[14] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_3(verilog)) because its output is a constant. @W:MO197 : coreahblite_slavearbiter.v(449) | Removing FSM register arbRegSMCurrentState[10] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_3(verilog)) because its output is a constant. @W:MO197 : coreahblite_slavearbiter.v(449) | Removing FSM register arbRegSMCurrentState[6] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_3(verilog)) because its output is a constant. @W:MO197 : coreahblite_slavearbiter.v(449) | Removing FSM register arbRegSMCurrentState[2] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_3(verilog)) because its output is a constant. Encoding state machine ahbcurr_state[2:0] (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_AHBLSramIf_Z6(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:MO231 : ahblsramif.v(319) | Found counter in view:COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_AHBLSramIf_Z6(verilog) instance count[4:0] @N:BN362 : ahblsramif.v(184) | Removing sequential instance HADDR_d[15] (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_AHBLSramIf_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : ahblsramif.v(184) | Removing sequential instance HADDR_d[16] (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_AHBLSramIf_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : ahblsramif.v(184) | Removing sequential instance HADDR_d[17] (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_AHBLSramIf_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : ahblsramif.v(184) | Removing sequential instance HADDR_d[18] (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_AHBLSramIf_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : ahblsramif.v(184) | Removing sequential instance HADDR_d[19] (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_AHBLSramIf_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @W:MO160 : ahblsramif.v(310) | Register bit burst_count_reg[4] (in view view:COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_AHBLSramIf_Z6(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : ahblsramif.v(310) | Register bit burst_count_reg[3] (in view view:COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_AHBLSramIf_Z6(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : ahblsramif.v(310) | Register bit burst_count_reg[2] (in view view:COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_AHBLSramIf_Z6(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : ahblsramif.v(310) | Register bit burst_count_reg[1] (in view view:COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_AHBLSramIf_Z6(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine sramcurr_state[2:0] (in view: COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_SramCtrlIf_0s_4096s_4096s_512s_128s_32s_0s_0_1_2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine state[2:0] (in view: work.CoreConfigP_Z7(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @W:MO160 : coreconfigp.v(255) | Register bit paddr[16] (in view view:work.CoreConfigP_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z8(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sdif0_state[3:0] (in view: work.CoreResetP_Z8(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : coreresetp.v(1170) | There are no possible illegal states for state machine sdif0_state[3:0] (in view: work.CoreResetP_Z8(verilog)); safe FSM implementation is not required. @N:MO231 : coreresetp.v(1485) | Found counter in view:work.CoreResetP_Z8(verilog) instance count_sdif0[12:0] @N:FX403 : rx4096x36.v(139) | Property "block_ram" or "no_rw_check" found for RAM CORETSEI1O0I.CORETSEIIil[35:0] with specified coding style. Inferring block RAM. @W:FX107 : rx4096x36.v(139) | RAM CORETSEI1O0I.CORETSEIIil[35:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP_19s_1s_11s_12s_1s_1s_1s_18s_0s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. @N:FX403 : tx2048x40.v(139) | Property "block_ram" or "no_rw_check" found for RAM CORETSEO1O0I.CORETSEIIil[39:0] with specified coding style. Inferring block RAM. @W:FX107 : tx2048x40.v(139) | RAM CORETSEO1O0I.CORETSEIIil[39:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP_19s_1s_11s_12s_1s_1s_1s_18s_0s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. Encoding state machine CORETSEo000I[3:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_DMATX_19s_0s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : dmatx.v(611) | There are no possible illegal states for state machine CORETSEo000I[3:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_DMATX_19s_0s(verilog)); safe FSM implementation is not required. Encoding state machine CORETSEii00I[3:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_DMATX_19s_0s(verilog)) original code -> new code 000 -> 00 100 -> 01 110 -> 10 111 -> 11 @N:MO225 : dmatx.v(1159) | There are no possible illegal states for state machine CORETSEii00I[3:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_DMATX_19s_0s(verilog)); safe FSM implementation is not required. Encoding state machine CORETSEii00I[3:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_DMARX_19s_0s(verilog)) original code -> new code 000 -> 00 100 -> 01 110 -> 10 111 -> 11 @N:MO225 : dmarx.v(1088) | There are no possible illegal states for state machine CORETSEii00I[3:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_DMARX_19s_0s(verilog)); safe FSM implementation is not required. Encoding state machine CORETSEo000I[3:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_DMARX_19s_0s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : dmarx.v(546) | There are no possible illegal states for state machine CORETSEo000I[3:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_DMARX_19s_0s(verilog)); safe FSM implementation is not required. @N:MF179 : amcxtfif_fab.v(809) | Found 11 by 11 bit equality operator ('==') un3_CORETSEollOI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_AMCXTFIF_FAB_19s_11s_32s_2s_0_0_1s(verilog)) Encoding state machine CORETSEOI1OI[5:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_AMCXTFIF_SYS_19s_11s_32s_2s_0s_0_0_1s(verilog)) original code -> new code 000001 -> 000001 000010 -> 000010 000100 -> 000100 001000 -> 001000 010000 -> 010000 100000 -> 100000 @N:MF179 : amcxtfif_sys.v(2584) | Found 12 by 12 bit equality operator ('==') un1_CORETSEil1OI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_AMCXTFIF_SYS_19s_11s_32s_2s_0s_0_0_1s(verilog)) Encoding state machine genblk1\.CORETSEooIOI[4:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_AMCXRFIF_FAB_19s_12s_32s_2s_0_1s(verilog)) original code -> new code 0000 -> 00001 1000 -> 00010 1100 -> 00100 1110 -> 01000 1111 -> 10000 @N:MF179 : amcxrfif_fab.v(541) | Found 13 by 13 bit equality operator ('==') un4_CORETSEIlIOI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_AMCXRFIF_FAB_19s_12s_32s_2s_0_1s(verilog)) @N:MO231 : amcxrfif_sys.v(2334) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_AMCXRFIF_SYS_19s_0s_12s_32s_2s_0_0_0_1s(verilog) instance CORETSEiolOI[13:0] @N:MF179 : amcxrfif_sys.v(1440) | Found 12 by 12 bit equality operator ('==') un3_CORETSEollOI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_AMCXRFIF_SYS_19s_0s_12s_32s_2s_0_0_0_1s(verilog)) Encoding state machine CORETSEOloOI[5:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_AMCXTFIF_WTM_19s_12s_1s_0_0(verilog)) original code -> new code 000001 -> 000001 000010 -> 000010 000100 -> 000100 001000 -> 001000 010000 -> 010000 100000 -> 100000 @N:MO231 : amcxtfif_wtm.v(569) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_AMCXTFIF_WTM_19s_12s_1s_0_0(verilog) instance CORETSEIloOI[15:0] @N:MF179 : | Found 17 by 17 bit equality operator ('==') un12_CORETSEo00l (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PETFN_TOP_19s_0s_0_1s(verilog)) @N:MF179 : petfn_top.v(10178) | Found 16 by 16 bit equality operator ('==') un18_CORETSEo00l (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PETFN_TOP_19s_0s_0_1s(verilog)) @N:MF179 : petfn_top.v(4660) | Found 16 by 16 bit equality operator ('==') un3_CORETSEiOIl (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PETFN_TOP_19s_0s_0_1s(verilog)) @N:MF179 : petfn_top.v(5508) | Found 10 by 10 bit equality operator ('==') CORETSEl1Il (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PETFN_TOP_19s_0s_0_1s(verilog)) @N:MO231 : perfn_top.v(2564) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PERFN_TOP_19s_0s_0_1s(verilog) instance CORETSEool[14:0] @N:BN362 : perfn_top.v(3798) | Removing sequential instance CORETSEOOI[0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PERFN_TOP_19s_0s_0_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : perfn_top.v(3798) | Removing sequential instance CORETSEOOI[1] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PERFN_TOP_19s_0s_0_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:MF179 : | Found 17 by 17 bit equality operator ('==') un10_CORETSElO0 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PERFN_TOP_19s_0s_0_1s(verilog)) @N:MF179 : perfn_top.v(4521) | Found 16 by 16 bit equality operator ('==') un6_CORETSEiI1 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PERFN_TOP_19s_0s_0_1s(verilog)) Encoding state machine CORETSEo0o1[31:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s(verilog)) original code -> new code 00000 -> 00000000000000000000000000000001 00001 -> 00000000000000000000000000000010 00010 -> 00000000000000000000000000000100 00011 -> 00000000000000000000000000001000 00100 -> 00000000000000000000000000010000 00101 -> 00000000000000000000000000100000 00110 -> 00000000000000000000000001000000 00111 -> 00000000000000000000000010000000 01000 -> 00000000000000000000000100000000 01001 -> 00000000000000000000001000000000 01010 -> 00000000000000000000010000000000 01011 -> 00000000000000000000100000000000 01100 -> 00000000000000000001000000000000 01101 -> 00000000000000000010000000000000 01110 -> 00000000000000000100000000000000 01111 -> 00000000000000001000000000000000 10000 -> 00000000000000010000000000000000 10001 -> 00000000000000100000000000000000 10010 -> 00000000000001000000000000000000 10011 -> 00000000000010000000000000000000 10100 -> 00000000000100000000000000000000 10101 -> 00000000001000000000000000000000 10110 -> 00000000010000000000000000000000 10111 -> 00000000100000000000000000000000 11000 -> 00000001000000000000000000000000 11001 -> 00000010000000000000000000000000 11010 -> 00000100000000000000000000000000 11011 -> 00001000000000000000000000000000 11100 -> 00010000000000000000000000000000 11101 -> 00100000000000000000000000000000 11110 -> 01000000000000000000000000000000 11111 -> 10000000000000000000000000000000 @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSEoo0o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSEIi0o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSEli0o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSEoi0o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSEii0o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSEOO1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSEIO1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSElO1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSEoO1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSEiO1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSEOI1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSEII1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSElI1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSEll1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinchd.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSEol1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinchd.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSEil1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinchd.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSEO01o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinchd.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSEI01o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinchd.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSEl01o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinchd.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSEo01o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSEO11o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSEI11o.CORETSEl00o[11:0] @N:MO231 : pemstat_sincnf.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSEl11o.CORETSEl00o[11:0] @N:MO231 : pemstat_sincnf.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSEo11o.CORETSEl00o[11:0] @N:MO231 : pemstat_sincnf.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSEi11o.CORETSEl00o[11:0] @N:MO231 : pemstat_sincnf.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSEOo1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sincnf.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSEIo1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sincnf.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog) instance CORETSEiIlo.CORETSElo1o.CORETSEl00o[11:0] @W:MO160 : pemstat_eim.v(1986) | Register bit CORETSEIllo.CORETSEII0o[30] (in view view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : pemstat_eim.v(1986) | Register bit CORETSEIllo.CORETSEII0o[29] (in view view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : pemstat_eim.v(1986) | Register bit CORETSEIllo.CORETSEII0o[28] (in view view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : pemstat_eim.v(1986) | Register bit CORETSEIllo.CORETSEII0o[27] (in view view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : pemstat_eim.v(1986) | Register bit CORETSEIllo.CORETSEII0o[26] (in view view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : pemstat_eim.v(1986) | Register bit CORETSEIllo.CORETSEII0o[25] (in view view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : pemstat_eim.v(1986) | Register bit CORETSEIllo.CORETSEII0o[24] (in view view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO129 : pemstat_cntrl.v(2224) | Sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[36] is reduced to a combinational gate by constant propagation. @W:MO129 : pemstat_cntrl.v(2224) | Sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[37] is reduced to a combinational gate by constant propagation. @N:MO231 : pemstat_linc.v(137) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_LINC_1s_19s(verilog) instance CORETSEl00o[17:0] @N:MO231 : mmcxwol.v(1039) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_MMCXWOL_1s_19s(verilog) instance CORETSEIilII[4:0] @N:MO231 : mmcxwol.v(836) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_MMCXWOL_1s_19s(verilog) instance CORETSEiolII[4:0] @N:MO231 : msgmii_cnvtxo.v(312) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_CNVTXO_19s(verilog) instance CORETSEol1II[6:0] Encoding state machine CORETSEIo10_1[3:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PEREX_PCS_0s_19s_1s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : perex_pcs.v(4925) | There are no possible illegal states for state machine CORETSEIo10_1[3:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_PEREX_PCS_0s_19s_1s(verilog)); safe FSM implementation is not required. @N:MO231 : msgmii_peanx_top.v(3508) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_PEANX_TOP_1s_19s(verilog) instance CORETSEIiiII[20:0] @N:MF179 : msgmii_peanx_top.v(2473) | Found 15 by 15 bit equality operator ('==') CORETSEo1OlI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_PEANX_TOP_1s_19s(verilog)) @N:MF179 : msgmii_peanx_top.v(2764) | Found 16 by 16 bit equality operator ('==') CORETSEoiOlI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_PEANX_TOP_1s_19s(verilog)) @N:MF179 : msgmii_peanx_top.v(3094) | Found 15 by 15 bit equality operator ('==') un7_CORETSEoIIlI (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_PEANX_TOP_1s_19s(verilog)) @N:MO231 : msgmii_cnvrxi.v(539) | Found counter in view:work.CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_CNVRXI_19s(verilog) instance CORETSEol1II[5:0] Starting factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 187MB peak: 188MB) @N:BN362 : ahblsramif.v(184) | Removing sequential instance COREAHBLSRAM_0.U_CoreTSE_M2S090_COREAHBLSRAM_0_AHBLSramIf.HSIZE_d[2] (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_1.matrix4x16.slavestage_5.masterDataInProg[3] (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_1.matrix4x16.slavestage_2.masterDataInProg[0] (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_0.regHADDR[15] (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_0.regHADDR[19] (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_0.regHADDR[18] (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_0.regHADDR[17] (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_0.regHADDR[16] (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. Finished factoring (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 246MB peak: 264MB) @N:BN362 : petfn_top.v(10871) | Removing sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEoIoI[50] (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(10871) | Removing sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEoIoI[31] (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(10871) | Removing sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEoIoI[30] (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(9253) | Removing sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEoO0l (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(9154) | Removing sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSElO0l (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance CoreAHBLite_1.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[14] (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance CoreAHBLite_1.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[15] (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance CoreAHBLite_1.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[2] (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance CoreAHBLite_1.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[3] (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance CoreAHBLite_1.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[6] (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance CoreAHBLite_1.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[7] (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance CoreAHBLite_1.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[10] (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance CoreAHBLite_1.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[11] (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 232MB peak: 264MB) @W:FX739 : coretse_m2s090.v(632) | Removed BUFG instance CLKINT_0 because it is cascaded to another clock buffer (FCCC_3.GL0_INST). @N:BN362 : pemstat_sinc.v(240) | Removing sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEiIlo.CORETSEI11o.CORETSEIoOo (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : pemstat_sinc.v(240) | Removing sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEiIlo.CORETSEO11o.CORETSEIoOo (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 227MB peak: 285MB) @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance CoreAHBLite_1.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[5] (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. Starting Early Timing Optimization (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:20s; Memory used current: 231MB peak: 285MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:33s; CPU Time elapsed 0h:00m:33s; Memory used current: 250MB peak: 285MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:34s; CPU Time elapsed 0h:00m:34s; Memory used current: 246MB peak: 285MB) @N:MO106 : r10b8b.v(268) | Found ROM .delname. (in view: work.CoreTSE_M2S090(verilog)) with 46 words by 5 bits. @N:MO106 : r10b8b.v(268) | Found ROM .delname. (in view: work.CoreTSE_M2S090(verilog)) with 46 words by 5 bits. @N:MO106 : r10b8b.v(2472) | Found ROM .delname. (in view: work.CoreTSE_M2S090(verilog)) with 64 words by 1 bit. @N:MO106 : r10b8b.v(2472) | Found ROM .delname. (in view: work.CoreTSE_M2S090(verilog)) with 64 words by 1 bit. @N:MO106 : r10b8b.v(268) | Found ROM .delname. (in view: work.CoreTSE_M2S090(verilog)) with 46 words by 2 bits. @N:MO106 : r10b8b.v(268) | Found ROM .delname. (in view: work.CoreTSE_M2S090(verilog)) with 46 words by 1 bit. @N:MO106 : r10b8b.v(2472) | Found ROM .delname. (in view: work.CoreTSE_M2S090(verilog)) with 64 words by 1 bit. @N:MO106 : r10b8b.v(2472) | Found ROM .delname. (in view: work.CoreTSE_M2S090(verilog)) with 64 words by 1 bit. @N:MO106 : r10b8b.v(268) | Found ROM .delname. (in view: work.CoreTSE_M2S090(verilog)) with 46 words by 2 bits. @N:MO106 : r10b8b.v(268) | Found ROM .delname. (in view: work.CoreTSE_M2S090(verilog)) with 46 words by 1 bit. @N:BN362 : petfn_top.v(10211) | Removing sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEOl1 (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(10067) | Removing sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEl00l (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(6347) | Removing sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEil0l (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(3696) | Removing sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEOl0l (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(10871) | Removing sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEoIoI[23] (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(10871) | Removing sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEoIoI[22] (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(10871) | Removing sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEoIoI[21] (in view: work.CoreTSE_M2S090(verilog)) because it does not drive other instances. Finished preparing to map (Real Time elapsed 0h:00m:38s; CPU Time elapsed 0h:00m:38s; Memory used current: 248MB peak: 285MB) Finished technology mapping (Real Time elapsed 0h:00m:46s; CPU Time elapsed 0h:00m:45s; Memory used current: 285MB peak: 326MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:46s -4.29ns 10505 / 5282 2 0h:00m:46s -4.21ns 9939 / 5282 3 0h:00m:47s -4.21ns 9939 / 5282 4 0h:00m:47s -4.21ns 9948 / 5282 @N:FX271 : perex_pma.v(1926) | Replicating instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEoio0.CORETSElili (in view: work.CoreTSE_M2S090(verilog)) with 61 loads 3 times to improve timing. @N:FX271 : perex_pma.v(1574) | Replicating instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEoio0.CORETSEIoli[12] (in view: work.CoreTSE_M2S090(verilog)) with 15 loads 1 time to improve timing. @N:FX271 : perex_pma.v(1574) | Replicating instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEoio0.CORETSEIoli[11] (in view: work.CoreTSE_M2S090(verilog)) with 10 loads 1 time to improve timing. @N:FX271 : perex_pma.v(1574) | Replicating instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEoio0.CORETSEIoli[2] (in view: work.CoreTSE_M2S090(verilog)) with 8 loads 1 time to improve timing. @N:FX271 : perex_pma.v(1574) | Replicating instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEoio0.CORETSEIoli[1] (in view: work.CoreTSE_M2S090(verilog)) with 6 loads 1 time to improve timing. @N:FX271 : perex_pma.v(1574) | Replicating instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEoio0.CORETSEIoli[10] (in view: work.CoreTSE_M2S090(verilog)) with 4 loads 1 time to improve timing. @N:FX271 : perex_pma.v(1574) | Replicating instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEoio0.CORETSEIoli[13] (in view: work.CoreTSE_M2S090(verilog)) with 7 loads 1 time to improve timing. Timing driven replication report Added 9 Registers via timing driven replication Added 3 LUTs via timing driven replication 5 0h:00m:51s -3.75ns 9951 / 5291 6 0h:00m:51s -3.75ns 9952 / 5291 7 0h:00m:51s -3.75ns 9957 / 5291 @N:FX271 : pehst.v(1758) | Replicating instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiII1.CORETSEil[5] (in view: work.CoreTSE_M2S090(verilog)) with 7 loads 1 time to improve timing. @N:FX271 : pehst.v(1758) | Replicating instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiII1.CORETSEil[6] (in view: work.CoreTSE_M2S090(verilog)) with 6 loads 1 time to improve timing. Timing driven replication report Added 2 Registers via timing driven replication Added 0 LUTs via timing driven replication 8 0h:00m:52s -3.75ns 9950 / 5293 9 0h:00m:53s -3.75ns 9951 / 5293 10 0h:00m:53s -3.75ns 9952 / 5293 @N:FP130 : | Promoting Net CoreResetP_0_MSS_HPMS_READY on CLKINT I_2621 @N:FP130 : | Promoting Net CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEI0OI on CLKINT I_2622 @N:FP130 : | Promoting Net CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEOo1I_i on CLKINT I_2623 @N:FP130 : | Promoting Net CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEilOI_i on CLKINT I_2624 @N:FP130 : | Promoting Net CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEi0_i on CLKINT I_2625 @N:FP130 : | Promoting Net CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEooolI.CORETSEolii_i on CLKINT I_2626 @N:FP130 : | Promoting Net CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEooolI.CORETSEilii_i on CLKINT I_2627 @N:FP130 : | Promoting Net CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEooolI.CORETSEllii_i on CLKINT I_2628 @N:FP130 : | Promoting Net CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEooolI.CORETSEIlii_i on CLKINT I_2629 @N:FP130 : | Promoting Net CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEIl0II_i on CLKINT I_2630 @N:FP130 : | Promoting Net CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEOi0II on CLKINT I_2631 @N:FP130 : | Promoting Net PHY_MDC_c on CLKINT I_2632 @N:FP130 : | Promoting Net CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEOlo_i on CLKINT I_2633 @N:FP130 : | Promoting Net CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSElOI1_i on CLKINT I_2634 @N:FP130 : | Promoting Net CoreConfigP_0_APB_S_PRESET_N on CLKINT I_2635 @N:FP130 : | Promoting Net CoreConfigP_0_APB_S_PCLK on CLKINT I_2636 @N:FP130 : | Promoting Net CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEooolI.CORETSEO0ii_i on CLKINT I_2637 @N:FP130 : | Promoting Net CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEOO1l_i on CLKINT I_2638 @N:FP130 : | Promoting Net CoreResetP_0.sm0_areset_n_clk_base on CLKINT I_2639 @N:FP130 : | Promoting Net CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEOl0II_i on CLKINT I_2640 @N:FP130 : | Promoting Net CoreResetP_0.sdif0_areset_n_rcosc on CLKINT I_2641 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:55s; CPU Time elapsed 0h:00m:55s; Memory used current: 304MB peak: 326MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:56s; CPU Time elapsed 0h:00m:56s; Memory used current: 312MB peak: 326MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 3 non-gated/non-generated clock tree(s) driving 115 clock pin(s) of sequential element(s) 5 gated/generated clock tree(s) driving 5213 clock pin(s) of sequential element(s) 0 instances converted, 5213 sequential instances remain driven by gated/generated clocks ==================================================== Non-Gated/Non-Generated Clocks ==================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ---------------------------------------------------------------------------------------------------------------------------------------- ClockId0006 SERDES_IF2_0.refclk1_inbuf_diff INBUF_DIFF 1 SERDES_IF2_0.SERDESIF_INST ClockId0007 CoreTSE_M2S090_MSS_0.MSS_ADLIB_INST clock definition on MSS_075 92 SERDES_IF2_0.SERDESIF_INST ClockId0008 OSC_0.I_RCOSC_25_50MHZ clock definition on RCOSC_25_50MHZ 22 CoreResetP_0.count_sdif0[12] ======================================================================================================================================== =================================================================================================================================== Gated/Generated Clocks =================================================================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 FCCC_0.CCC_INST CCC 2869 CoreTSE_M2S090_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_075 ClockId0002 FCCC_3.CCC_INST CCC 1426 CORETSE_AHB_0.CORETSEi0ilI.CORETSEI1O0I.CORETSEIIil_CORETSEIIil_0_8 No gated clock conversion method for cell cell:ACG4.RAM1K18 ClockId0003 FCCC_1.CCC_INST CCC 441 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI.CORETSEo1O0I.CORETSEOOo0 No gated clock conversion method for cell cell:ACG4.SLE ClockId0004 FCCC_2.CCC_INST CCC 353 MON_ANX_0.DOUT[7] No gated clock conversion method for cell cell:ACG4.SLE ClockId0005 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEOII1.CORETSEI110 SLE 124 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEI0o0 No gated clock conversion method for cell cell:ACG4.SLE ============================================================================================================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:57s; CPU Time elapsed 0h:00m:57s; Memory used current: 232MB peak: 326MB) Writing Analyst data base D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\synthesis\synwork\CoreTSE_M2S090_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:59s; CPU Time elapsed 0h:00m:59s; Memory used current: 289MB peak: 326MB) Writing EDIF Netlist and constraint files @N:FX1056 : | Writing EDF file: D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\synthesis\CoreTSE_M2S090.edn @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF L-2016.09M-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:01m:01s; CPU Time elapsed 0h:01m:01s; Memory used current: 292MB peak: 326MB) Start final timing analysis (Real Time elapsed 0h:01m:02s; CPU Time elapsed 0h:01m:02s; Memory used current: 280MB peak: 326MB) @W:MT246 : coretse_m2s090_fccc_3_fccc.v(37) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N:MT615 : | Found clock CLK1_PAD with period 20.00ns @W:MT420 : | Found inferred clock CoreTSE_M2S090_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:SERDES_IF2_0.REFCLK1_OUT" @N:MT615 : | Found clock SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] with period 8.00ns @N:MT615 : | Found clock SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1] with period 8.00ns @N:MT615 : | Found clock OSC_0/I_RCOSC_25_50MHZ/CLKOUT with period 20.00ns @N:MT615 : | Found clock FCCC_3/GL0 with period 8.00ns @N:MT615 : | Found clock FCCC_3/GL1 with period 8.00ns @N:MT615 : | Found clock FCCC_2/GL0 with period 8.00ns @N:MT615 : | Found clock FCCC_1/GL0 with period 8.00ns @N:MT615 : | Found clock FCCC_0/GL0 with period 20.00ns @N:MT615 : | Found clock CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB with period 80.00ns @W:MT420 : | Found inferred clock CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEOII1.CORETSEI110" ##### START OF TIMING REPORT #####[ # Timing Report written on Tue Mar 14 15:03:47 2017 # Top view: CoreTSE_M2S090 Requested Frequency: 12.5 MHz Wire load mode: top Paths requested: 5 Constraint File(s): D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\designer\CoreTSE_M2S090\synthesis.fdc @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -1.739 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CLK1_PAD 50.0 MHz NA 20.000 NA NA declared default_clkgroup CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock 100.0 MHz 149.0 MHz 10.000 6.710 3.290 inferred Inferred_clkgroup_0 CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB 12.5 MHz 108.5 MHz 80.000 9.213 35.393 declared default_clkgroup CoreTSE_M2S090_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_1 FCCC_0/GL0 50.0 MHz 34.8 MHz 20.000 28.697 -1.470 generated (from CLK1_PAD) default_clkgroup FCCC_1/GL0 125.0 MHz 95.4 MHz 8.000 10.485 -0.794 generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup FCCC_2/GL0 125.0 MHz 148.8 MHz 8.000 6.719 2.347 generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]) default_clkgroup FCCC_3/GL0 125.0 MHz NA 8.000 NA NA generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]) default_clkgroup FCCC_3/GL1 125.0 MHz 87.1 MHz 8.000 11.479 -1.739 generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]) default_clkgroup OSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 431.2 MHz 20.000 2.319 17.681 declared default_clkgroup SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] 125.0 MHz NA 8.000 NA NA declared default_clkgroup SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1] 125.0 MHz NA 8.000 NA NA declared default_clkgroup System 100.0 MHz 477.6 MHz 10.000 2.094 7.906 system system_clkgroup ============================================================================================================================================================================================================================= @N:MT582 : | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 10.000 7.906 | No paths - | No paths - | No paths - CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB | 80.000 72.992 | No paths - | 40.000 38.066 | 40.000 35.393 CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB FCCC_0/GL0 | 20.000 False | No paths - | No paths - | No paths - OSC_0/I_RCOSC_25_50MHZ/CLKOUT OSC_0/I_RCOSC_25_50MHZ/CLKOUT | 20.000 17.681 | No paths - | No paths - | No paths - OSC_0/I_RCOSC_25_50MHZ/CLKOUT FCCC_0/GL0 | 20.000 False | No paths - | No paths - | No paths - FCCC_0/GL0 System | 20.000 18.929 | No paths - | No paths - | No paths - FCCC_0/GL0 CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB | 20.000 False | No paths - | No paths - | No paths - FCCC_0/GL0 OSC_0/I_RCOSC_25_50MHZ/CLKOUT | 20.000 False | No paths - | No paths - | No paths - FCCC_0/GL0 FCCC_0/GL0 | 20.000 4.219 | No paths - | No paths - | No paths - FCCC_0/GL0 FCCC_1/GL0 | 4.000 -1.242 | No paths - | No paths - | No paths - FCCC_0/GL0 FCCC_2/GL0 | 4.000 0.641 | No paths - | No paths - | No paths - FCCC_0/GL0 FCCC_3/GL1 | 4.000 -1.470 | No paths - | No paths - | No paths - FCCC_0/GL0 CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock | Diff grp - | No paths - | No paths - | No paths - FCCC_1/GL0 FCCC_1/GL0 | 8.000 -0.794 | No paths - | No paths - | No paths - FCCC_1/GL0 FCCC_2/GL0 | 8.000 2.442 | No paths - | No paths - | No paths - FCCC_1/GL0 FCCC_3/GL1 | 8.000 2.939 | No paths - | No paths - | No paths - FCCC_2/GL0 FCCC_1/GL0 | 8.000 5.417 | No paths - | No paths - | No paths - FCCC_2/GL0 FCCC_2/GL0 | 8.000 2.347 | No paths - | No paths - | No paths - FCCC_2/GL0 FCCC_3/GL1 | 8.000 6.676 | No paths - | No paths - | No paths - FCCC_2/GL0 CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock | Diff grp - | No paths - | No paths - | No paths - FCCC_3/GL1 FCCC_0/GL0 | 4.000 -1.739 | No paths - | No paths - | No paths - FCCC_3/GL1 FCCC_2/GL0 | 8.000 4.546 | No paths - | No paths - | No paths - FCCC_3/GL1 FCCC_3/GL1 | 8.000 1.438 | No paths - | No paths - | No paths - CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock FCCC_0/GL0 | Diff grp - | No paths - | No paths - | No paths - CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock FCCC_1/GL0 | Diff grp - | No paths - | No paths - | No paths - CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock FCCC_2/GL0 | Diff grp - | No paths - | No paths - | No paths - CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock | 10.000 3.290 | No paths - | No paths - | No paths - ===================================================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEIIoo[1] CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock SLE Q CORETSEIIoo[1] 0.094 3.290 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEIIoo[2] CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock SLE Q CORETSEIIoo[2] 0.094 3.308 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEoOoo[2] CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock SLE Q CORETSEoOoo[2] 0.094 3.409 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEoOoo[1] CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock SLE Q CORETSEoOoo[1] 0.076 3.482 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEIi1o[1] CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock SLE Q CORETSEIi1o[1] 0.094 3.720 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEIi1o[3] CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock SLE Q CORETSEIi1o[3] 0.076 3.863 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEIi1o[4] CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock SLE Q CORETSEIi1o[4] 0.094 3.893 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEIi1o[0] CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock SLE Q CORETSEIi1o[0] 0.076 3.909 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEIi1o[2] CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock SLE Q CORETSEIi1o[2] 0.076 3.932 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEoOoo[3] CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock SLE Q CORETSEoOoo[3] 0.094 4.041 ================================================================================================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEi0oo[14] CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock SLE D CORETSEo0oo[14] 9.778 3.290 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEi0oo[8] CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock SLE D CORETSEo0oo[8] 9.778 3.409 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEi0oo[1] CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock SLE D CORETSEo0oo[1] 9.778 3.544 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEi0oo[5] CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock SLE D CORETSEo0oo[5] 9.778 3.592 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEi0oo[10] CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock SLE D CORETSEo0oo[10] 9.778 3.870 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEi0oo[6] CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock SLE D CORETSEo0oo[6] 9.778 3.983 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEi0oo[11] CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock SLE D CORETSEo0oo[11] 9.778 3.988 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEi0oo[9] CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock SLE D CORETSEo0oo[9] 9.778 4.049 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEi0oo[0] CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock SLE D un1_CORETSEo0oo[0] 9.778 4.058 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEi0oo[2] CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock SLE D CORETSEo0oo[2] 9.778 4.065 ====================================================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 6.488 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 3.290 Number of logic level(s): 7 Starting point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEIIoo[1] / Q Ending point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEi0oo[14] / D The start point is clocked by CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock [rising] on pin CLK The end point is clocked by CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEIIoo[1] SLE Q Out 0.094 0.094 - CORETSEIIoo[1] Net - - 1.353 - 27 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEoooo_0_a2_3 CFG2 A In - 1.448 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEoooo_0_a2_3 CFG2 Y Out 0.087 1.534 - N_432 Net - - 0.648 - 5 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEOioo_0_a3_s CFG4 D In - 2.182 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEOioo_0_a3_s CFG4 Y Out 0.236 2.418 - N_445 Net - - 0.622 - 4 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEIOio_0_a2 CFG3 C In - 3.040 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEIOio_0_a2 CFG3 Y Out 0.177 3.216 - CORETSEIOio Net - - 0.793 - 15 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEo0oo_0_1_RNO_0[14] CFG4 C In - 4.010 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEo0oo_0_1_RNO_0[14] CFG4 Y Out 0.196 4.206 - r_m1_0_a2_5_1 Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEo0oo_0_1_RNO[14] CFG4 D In - 4.689 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEo0oo_0_1_RNO[14] CFG4 Y Out 0.250 4.939 - r_m1_0_a2_5_3 Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEo0oo_0_1[14] CFG4 D In - 5.422 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEo0oo_0_1[14] CFG4 Y Out 0.250 5.673 - CORETSEo0oo_0_1[14] Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEo0oo_0[14] CFG4 C In - 6.156 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEo0oo_0[14] CFG4 Y Out 0.194 6.350 - CORETSEo0oo[14] Net - - 0.138 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiOi0.CORETSEi0oo[14] SLE D In - 6.488 - ======================================================================================================================================================================= Total path delay (propagation time + setup) of 6.710 is 1.706(25.4%) logic and 5.003(74.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreConfigP_0.psel CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB SLE Q psel 0.094 35.393 CoreConfigP_0.state[1] CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB SLE Q state[1] 0.076 38.066 CoreConfigP_0.SDIF0_PENABLE CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB SLE Q CoreConfigP_0_SDIF0_APBmslave_PENABLE 0.094 38.200 CoreConfigP_0.paddr[14] CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB SLE Q CoreConfigP_0_SDIF0_APBmslave_PADDR[14] 0.094 38.370 CoreConfigP_0.paddr[15] CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB SLE Q paddr[15] 0.076 38.686 CoreConfigP_0.state[0] CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB SLE Q state[0] 0.076 38.713 SERDES_IF2_0.SERDESIF_INST CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PREADY CoreConfigP_0_SDIF0_APBmslave_PREADY 4.732 72.992 SERDES_IF2_0.SERDESIF_INST CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PRDATA[25] CoreConfigP_0_SDIF0_APBmslave_PRDATA[25] 5.348 73.178 SERDES_IF2_0.SERDESIF_INST CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PRDATA[8] CoreConfigP_0_SDIF0_APBmslave_PRDATA[8] 5.255 73.271 SERDES_IF2_0.SERDESIF_INST CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PRDATA[29] CoreConfigP_0_SDIF0_APBmslave_PRDATA[29] 5.235 73.291 =========================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SERDES_IF2_0.SERDESIF_INST CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PSEL CoreConfigP_0_SDIF0_APBmslave_PSELx 37.269 35.393 CoreConfigP_0.FIC_2_APB_M_PRDATA[0] CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB SLE D N_21_i 39.778 35.810 CoreConfigP_0.FIC_2_APB_M_PRDATA[1] CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB SLE D N_27_i 39.778 36.287 CoreConfigP_0.FIC_2_APB_M_PRDATA[16] CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB SLE D N_36_i 39.778 36.332 CoreConfigP_0.FIC_2_APB_M_PRDATA[17] CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB SLE D N_35_i 39.778 36.332 CoreConfigP_0.FIC_2_APB_M_PRDATA[18] CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB SLE D N_34_i 39.778 36.332 CoreConfigP_0.FIC_2_APB_M_PREADY CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB SLE EN N_43_i 39.706 36.902 CoreConfigP_0.state[1] CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB SLE D N_39_i 39.778 37.027 CoreConfigP_0.FIC_2_APB_M_PRDATA[2] CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB SLE D prdata[2] 39.778 37.724 CoreConfigP_0.FIC_2_APB_M_PRDATA[3] CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB SLE D prdata[3] 39.778 37.724 ========================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 40.000 - Setup time: 2.731 + Clock delay at ending point: 0.000 (ideal) = Required time: 37.269 - Propagation time: 1.876 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 35.393 Number of logic level(s): 1 Starting point: CoreConfigP_0.psel / Q Ending point: SERDES_IF2_0.SERDESIF_INST / APB_PSEL The start point is clocked by CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB [falling] on pin CLK The end point is clocked by CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB [rising] on pin APB_CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------- CoreConfigP_0.psel SLE Q Out 0.094 0.094 - psel Net - - 0.708 - 5 CoreConfigP_0.paddr_RNI9N8P_0[14] CFG3 A In - 0.802 - CoreConfigP_0.paddr_RNI9N8P_0[14] CFG3 Y Out 0.076 0.878 - CoreConfigP_0_SDIF0_APBmslave_PSELx Net - - 0.998 - 35 SERDES_IF2_0.SERDESIF_INST SERDESIF_075 APB_PSEL In - 1.876 - ============================================================================================================== Total path delay (propagation time + setup) of 4.607 is 2.901(63.0%) logic and 1.706(37.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: FCCC_0/GL0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiII1.CORETSEil[3] FCCC_0/GL0 SLE Q CORETSEil[3] 0.094 -1.470 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiII1.CORETSEil_fast[5] FCCC_0/GL0 SLE Q CORETSEil_fast[5] 0.094 -1.465 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiII1.CORETSEil[2] FCCC_0/GL0 SLE Q CORETSEil[2] 0.094 -1.387 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiII1.CORETSEil_fast[6] FCCC_0/GL0 SLE Q CORETSEil_fast[6] 0.094 -1.378 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiII1.CORETSEil[4] FCCC_0/GL0 SLE Q CORETSEil[4] 0.094 -1.375 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiII1.CORETSEil[5] FCCC_0/GL0 SLE Q CORETSEil[5] 0.094 -1.243 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEOIiII.CORETSEOi0II FCCC_0/GL0 SLE Q CORETSEOi0II_0 0.094 -1.242 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEooolI.CORETSEl1ii.CORETSEi1oi FCCC_0/GL0 SLE Q CORETSEi1oi 0.076 -0.895 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiII1.CORETSEiI[0] FCCC_0/GL0 SLE Q CORETSEo0llI[0] 0.094 -0.877 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiII1.CORETSEiI[1] FCCC_0/GL0 SLE Q CORETSEo0llI[1] 0.094 -0.845 =============================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEo10 FCCC_0/GL0 SLE D N_546_i 3.778 -1.470 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEIiI FCCC_0/GL0 SLE D CORETSEOoI 3.778 -1.411 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEo01 FCCC_0/GL0 SLE D CORETSEl01 3.778 -1.411 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEOo0 FCCC_0/GL0 SLE D CORETSEl10 3.778 -1.377 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEOOl FCCC_0/GL0 SLE D CORETSEioI 3.778 -1.376 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEi10 FCCC_0/GL0 SLE D CORETSEI10 3.778 -1.376 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEOOo0 FCCC_0/GL0 SLE D CORETSEOOo0_0 3.778 -1.242 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEooolI.CORETSEi0ii.CORETSElllOI[0] FCCC_0/GL0 SLE EN CORETSEoilOI 3.707 -0.895 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEooolI.CORETSEi0ii.CORETSElllOI[1] FCCC_0/GL0 SLE EN CORETSEoilOI 3.707 -0.895 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEooolI.CORETSEi0ii.CORETSElllOI[2] FCCC_0/GL0 SLE EN CORETSEoilOI 3.707 -0.895 ================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.248 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.470 Number of logic level(s): 6 Starting point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiII1.CORETSEil[3] / Q Ending point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEo10 / D The start point is clocked by FCCC_0/GL0 [rising] on pin CLK The end point is clocked by FCCC_3/GL1 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiII1.CORETSEil[3] SLE Q Out 0.094 0.094 - CORETSEil[3] Net - - 0.943 - 20 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un6_CORETSElIl_0_c4_a0_1 CFG2 A In - 1.037 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un6_CORETSElIl_0_c4_a0_1 CFG2 Y Out 0.087 1.124 - un6_CORETSElIl_0_c4_a0_1 Net - - 0.648 - 5 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un6_CORETSElIl_0_c6_a0 CFG4 D In - 1.772 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un6_CORETSElIl_0_c6_a0 CFG4 Y Out 0.236 2.008 - un12_CORETSElIl_6 Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un12_CORETSElIl_axb_7_i CFG2 A In - 2.491 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un12_CORETSElIl_axb_7_i CFG2 Y Out 0.087 2.578 - un12_CORETSElIl_axb_7_i Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un12_CORETSElIl_cry_7 ARI1 C In - 3.062 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un12_CORETSElIl_cry_7 ARI1 FCO Out 0.207 3.269 - un12_CORETSElIl_cry_7 Net - - 0.869 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un1_CORETSElIl[0] CFG3 A In - 4.138 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un1_CORETSElIl[0] CFG3 Y Out 0.067 4.205 - N_716 Net - - 0.670 - 6 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEo10_RNO CFG4 D In - 4.875 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEo10_RNO CFG4 Y Out 0.236 5.111 - N_546_i Net - - 0.138 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEo10 SLE D In - 5.248 - ==================================================================================================================================================================== Total path delay (propagation time + setup) of 5.470 is 1.237(22.6%) logic and 4.233(77.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.243 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.465 Number of logic level(s): 8 Starting point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiII1.CORETSEil_fast[5] / Q Ending point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEo10 / D The start point is clocked by FCCC_0/GL0 [rising] on pin CLK The end point is clocked by FCCC_3/GL1 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiII1.CORETSEil_fast[5] SLE Q Out 0.094 0.094 - CORETSEil_fast[5] Net - - 0.637 - 3 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un6_CORETSElIl_0_ac0_7_0_a0_0 CFG2 A In - 0.732 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un6_CORETSElIl_0_ac0_7_0_a0_0 CFG2 Y Out 0.087 0.819 - un6_CORETSElIl_0_ac0_7_0_a0_0 Net - - 0.706 - 8 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un17_CORETSElIl\.un17_CORETSElIl_ac0_7_0_a0 CFG4 D In - 1.525 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un17_CORETSElIl\.un17_CORETSElIl_ac0_7_0_a0 CFG4 Y Out 0.236 1.761 - un22_CORETSElIl_5 Net - - 0.590 - 3 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un22_CORETSElIl_axb_5_i CFG2 A In - 2.350 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un22_CORETSElIl_axb_5_i CFG2 Y Out 0.087 2.438 - un22_CORETSElIl_axb_5_i Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un22_CORETSElIl_cry_5 ARI1 C In - 2.921 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un22_CORETSElIl_cry_5 ARI1 FCO Out 0.207 3.128 - un22_CORETSElIl_cry_5 Net - - 0.000 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un22_CORETSElIl_cry_6 ARI1 FCI In - 3.128 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un22_CORETSElIl_cry_6 ARI1 FCO Out 0.013 3.141 - un22_CORETSElIl_cry_6 Net - - 0.000 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un22_CORETSElIl_cry_7 ARI1 FCI In - 3.141 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un22_CORETSElIl_cry_7 ARI1 FCO Out 0.013 3.154 - un22_CORETSElIl_cry_7 Net - - 0.869 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un1_CORETSElIl[0] CFG3 C In - 4.023 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un1_CORETSElIl[0] CFG3 Y Out 0.177 4.199 - N_716 Net - - 0.670 - 6 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEo10_RNO CFG4 D In - 4.869 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEo10_RNO CFG4 Y Out 0.236 5.105 - N_546_i Net - - 0.138 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEo10 SLE D In - 5.243 - ======================================================================================================================================================================================= Total path delay (propagation time + setup) of 5.465 is 1.372(25.1%) logic and 4.093(74.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.230 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.452 Number of logic level(s): 7 Starting point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiII1.CORETSEil_fast[5] / Q Ending point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEo10 / D The start point is clocked by FCCC_0/GL0 [rising] on pin CLK The end point is clocked by FCCC_3/GL1 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiII1.CORETSEil_fast[5] SLE Q Out 0.094 0.094 - CORETSEil_fast[5] Net - - 0.637 - 3 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un6_CORETSElIl_0_ac0_7_0_a0_0 CFG2 A In - 0.732 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un6_CORETSElIl_0_ac0_7_0_a0_0 CFG2 Y Out 0.087 0.819 - un6_CORETSElIl_0_ac0_7_0_a0_0 Net - - 0.706 - 8 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un17_CORETSElIl\.un17_CORETSElIl_ac0_7_0_a0 CFG4 D In - 1.525 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un17_CORETSElIl\.un17_CORETSElIl_ac0_7_0_a0 CFG4 Y Out 0.236 1.761 - un22_CORETSElIl_5 Net - - 0.590 - 3 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un22_CORETSElIl_axb_6_i CFG2 A In - 2.350 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un22_CORETSElIl_axb_6_i CFG2 Y Out 0.087 2.438 - un22_CORETSElIl_axb_6_i Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un22_CORETSElIl_cry_6 ARI1 C In - 2.921 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un22_CORETSElIl_cry_6 ARI1 FCO Out 0.207 3.128 - un22_CORETSElIl_cry_6 Net - - 0.000 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un22_CORETSElIl_cry_7 ARI1 FCI In - 3.128 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un22_CORETSElIl_cry_7 ARI1 FCO Out 0.013 3.141 - un22_CORETSElIl_cry_7 Net - - 0.869 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un1_CORETSElIl[0] CFG3 C In - 4.010 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un1_CORETSElIl[0] CFG3 Y Out 0.177 4.186 - N_716 Net - - 0.670 - 6 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEo10_RNO CFG4 D In - 4.856 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEo10_RNO CFG4 Y Out 0.236 5.092 - N_546_i Net - - 0.138 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEo10 SLE D In - 5.230 - ======================================================================================================================================================================================= Total path delay (propagation time + setup) of 5.452 is 1.359(24.9%) logic and 4.093(75.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.217 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.439 Number of logic level(s): 6 Starting point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiII1.CORETSEil_fast[5] / Q Ending point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEo10 / D The start point is clocked by FCCC_0/GL0 [rising] on pin CLK The end point is clocked by FCCC_3/GL1 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiII1.CORETSEil_fast[5] SLE Q Out 0.094 0.094 - CORETSEil_fast[5] Net - - 0.637 - 3 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un6_CORETSElIl_0_ac0_7_0_a0_0 CFG2 A In - 0.732 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un6_CORETSElIl_0_ac0_7_0_a0_0 CFG2 Y Out 0.087 0.819 - un6_CORETSElIl_0_ac0_7_0_a0_0 Net - - 0.706 - 8 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un17_CORETSElIl\.un17_CORETSElIl_ac0_7_0_a0 CFG4 D In - 1.525 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un17_CORETSElIl\.un17_CORETSElIl_ac0_7_0_a0 CFG4 Y Out 0.236 1.761 - un22_CORETSElIl_5 Net - - 0.590 - 3 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un22_CORETSElIl_axb_7_i CFG2 A In - 2.350 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un22_CORETSElIl_axb_7_i CFG2 Y Out 0.087 2.438 - un22_CORETSElIl_axb_7_i Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un22_CORETSElIl_cry_7 ARI1 C In - 2.921 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un22_CORETSElIl_cry_7 ARI1 FCO Out 0.207 3.128 - un22_CORETSElIl_cry_7 Net - - 0.869 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un1_CORETSElIl[0] CFG3 C In - 3.997 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un1_CORETSElIl[0] CFG3 Y Out 0.177 4.174 - N_716 Net - - 0.670 - 6 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEo10_RNO CFG4 D In - 4.843 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEo10_RNO CFG4 Y Out 0.236 5.079 - N_546_i Net - - 0.138 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEo10 SLE D In - 5.217 - ======================================================================================================================================================================================= Total path delay (propagation time + setup) of 5.439 is 1.346(24.8%) logic and 4.093(75.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.189 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.411 Number of logic level(s): 6 Starting point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiII1.CORETSEil[3] / Q Ending point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEo01 / D The start point is clocked by FCCC_0/GL0 [rising] on pin CLK The end point is clocked by FCCC_3/GL1 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiII1.CORETSEil[3] SLE Q Out 0.094 0.094 - CORETSEil[3] Net - - 0.943 - 20 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un6_CORETSElIl_0_c4_a0_1 CFG2 A In - 1.037 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un6_CORETSElIl_0_c4_a0_1 CFG2 Y Out 0.087 1.124 - un6_CORETSElIl_0_c4_a0_1 Net - - 0.648 - 5 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un6_CORETSElIl_0_c6_a0 CFG4 D In - 1.772 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un6_CORETSElIl_0_c6_a0 CFG4 Y Out 0.236 2.008 - un12_CORETSElIl_6 Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un12_CORETSElIl_axb_7_i CFG2 A In - 2.491 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un12_CORETSElIl_axb_7_i CFG2 Y Out 0.087 2.578 - un12_CORETSElIl_axb_7_i Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un12_CORETSElIl_cry_7 ARI1 C In - 3.062 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un12_CORETSElIl_cry_7 ARI1 FCO Out 0.207 3.269 - un12_CORETSElIl_cry_7 Net - - 0.869 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un1_CORETSElIl[0] CFG3 A In - 4.138 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.un1_CORETSElIl[0] CFG3 Y Out 0.067 4.205 - N_716 Net - - 0.670 - 6 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEl01_0_0 CFG4 C In - 4.875 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEl01_0_0 CFG4 Y Out 0.177 5.051 - CORETSEl01 Net - - 0.138 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEo01 SLE D In - 5.189 - ==================================================================================================================================================================== Total path delay (propagation time + setup) of 5.411 is 1.178(21.8%) logic and 4.233(78.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: FCCC_1/GL0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEi0io[2] FCCC_1/GL0 SLE Q CORETSEi0io[2] 0.076 -0.794 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEoio0.CORETSElili_fast FCCC_1/GL0 SLE Q CORETSElili_fast 0.094 -0.772 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEi0io[8] FCCC_1/GL0 SLE Q CORETSEi0io[8] 0.076 -0.674 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEi0io[9] FCCC_1/GL0 SLE Q CORETSEi0io[9] 0.094 -0.650 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEoio0.CORETSEIoli_fast[12] FCCC_1/GL0 SLE Q CORETSEIoli_fast[12] 0.094 -0.644 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEi0io[3] FCCC_1/GL0 SLE Q CORETSEi0io[3] 0.076 -0.616 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEi0io[13] FCCC_1/GL0 SLE Q CORETSEi0io[13] 0.094 -0.580 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEoio0.CORETSEIoli_fast[10] FCCC_1/GL0 SLE Q CORETSEIoli_fast[10] 0.094 -0.579 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEi0io[11] FCCC_1/GL0 SLE Q CORETSEi0io[11] 0.094 -0.573 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEoio0.CORETSEIoli_fast[11] FCCC_1/GL0 SLE Q CORETSEIoli_fast[11] 0.094 -0.562 =================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEllI[4] FCCC_1/GL0 SLE D CORETSEIlI[4] 7.778 -0.794 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEllI[5] FCCC_1/GL0 SLE D CORETSEIlI[5] 7.778 -0.794 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEllI[7] FCCC_1/GL0 SLE D CORETSEIlI[7] 7.778 -0.794 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEIIol[11] FCCC_1/GL0 SLE D CORETSEl0io[5] 7.778 -0.772 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEi0io[26] FCCC_1/GL0 SLE D CORETSEOiol_0_1_iv_i[2] 7.778 -0.772 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEi0io[27] FCCC_1/GL0 SLE D CORETSEOiol_0_1_iv_i[3] 7.778 -0.772 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEi0io[28] FCCC_1/GL0 SLE D CORETSEOiol_0_0_iv_i[4] 7.778 -0.772 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEi0io[29] FCCC_1/GL0 SLE D CORETSEOiol_0_0_iv_i[5] 7.778 -0.772 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEi0io[31] FCCC_1/GL0 SLE D CORETSEOiol_0_0_iv_i[7] 7.778 -0.772 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEllI[10] FCCC_1/GL0 SLE D CORETSEIlI[10] 7.778 -0.769 ================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 8.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.778 - Propagation time: 8.572 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.794 Number of logic level(s): 10 Starting point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEi0io[2] / Q Ending point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEllI[4] / D The start point is clocked by FCCC_1/GL0 [rising] on pin CLK The end point is clocked by FCCC_1/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEi0io[2] SLE Q Out 0.076 0.076 - CORETSEi0io[2] Net - - 0.827 - 5 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEliio_5 CFG4 D In - 0.903 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEliio_5 CFG4 Y Out 0.236 1.139 - CORETSEliio_5 Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEliio_6 CFG4 D In - 1.622 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEliio_6 CFG4 Y Out 0.236 1.858 - CORETSEliio_6 Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEliio CFG4 D In - 2.341 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEliio CFG4 Y Out 0.236 2.577 - CORETSEliio Net - - 0.736 - 10 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.un1_CORETSEoIli CFG4 C In - 3.313 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.un1_CORETSEoIli CFG4 Y Out 0.177 3.489 - un1_CORETSEoIli Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEoIli CFG3 B In - 3.973 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEoIli CFG3 Y Out 0.143 4.116 - CORETSEoIli Net - - 0.622 - 4 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.un2_CORETSEIIli CFG4 D In - 4.737 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.un2_CORETSEIIli CFG4 Y Out 0.284 5.021 - un2_CORETSEIIli Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEIIli CFG4 C In - 5.505 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEIIli CFG4 Y Out 0.182 5.687 - CORETSEIIli Net - - 0.706 - 8 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEl0li_5[0] CFG4 D In - 6.393 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEl0li_5[0] CFG4 Y Out 0.250 6.643 - CORETSEl0li_5[0] Net - - 0.590 - 3 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.un22_CORETSEIlI CFG4 D In - 7.233 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.un22_CORETSEIlI CFG4 Y Out 0.276 7.509 - un22_CORETSEIlI Net - - 0.689 - 7 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEIlI[4] CFG4 D In - 8.198 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEIlI[4] CFG4 Y Out 0.236 8.434 - CORETSEIlI[4] Net - - 0.138 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEllI[4] SLE D In - 8.572 - ============================================================================================================================================================== Total path delay (propagation time + setup) of 8.794 is 2.554(29.0%) logic and 6.240(71.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 8.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.778 - Propagation time: 8.572 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.794 Number of logic level(s): 10 Starting point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEi0io[2] / Q Ending point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEllI[7] / D The start point is clocked by FCCC_1/GL0 [rising] on pin CLK The end point is clocked by FCCC_1/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEi0io[2] SLE Q Out 0.076 0.076 - CORETSEi0io[2] Net - - 0.827 - 5 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEliio_5 CFG4 D In - 0.903 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEliio_5 CFG4 Y Out 0.236 1.139 - CORETSEliio_5 Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEliio_6 CFG4 D In - 1.622 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEliio_6 CFG4 Y Out 0.236 1.858 - CORETSEliio_6 Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEliio CFG4 D In - 2.341 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEliio CFG4 Y Out 0.236 2.577 - CORETSEliio Net - - 0.736 - 10 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.un1_CORETSEoIli CFG4 C In - 3.313 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.un1_CORETSEoIli CFG4 Y Out 0.177 3.489 - un1_CORETSEoIli Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEoIli CFG3 B In - 3.973 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEoIli CFG3 Y Out 0.143 4.116 - CORETSEoIli Net - - 0.622 - 4 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.un2_CORETSEIIli CFG4 D In - 4.737 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.un2_CORETSEIIli CFG4 Y Out 0.284 5.021 - un2_CORETSEIIli Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEIIli CFG4 C In - 5.505 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEIIli CFG4 Y Out 0.182 5.687 - CORETSEIIli Net - - 0.706 - 8 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEl0li_5[0] CFG4 D In - 6.393 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEl0li_5[0] CFG4 Y Out 0.250 6.643 - CORETSEl0li_5[0] Net - - 0.590 - 3 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.un22_CORETSEIlI CFG4 D In - 7.233 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.un22_CORETSEIlI CFG4 Y Out 0.276 7.509 - un22_CORETSEIlI Net - - 0.689 - 7 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEIlI[7] CFG4 D In - 8.198 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEIlI[7] CFG4 Y Out 0.236 8.434 - CORETSEIlI[7] Net - - 0.138 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEllI[7] SLE D In - 8.572 - ============================================================================================================================================================== Total path delay (propagation time + setup) of 8.794 is 2.554(29.0%) logic and 6.240(71.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 8.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.778 - Propagation time: 8.572 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.794 Number of logic level(s): 10 Starting point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEi0io[2] / Q Ending point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEllI[5] / D The start point is clocked by FCCC_1/GL0 [rising] on pin CLK The end point is clocked by FCCC_1/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEi0io[2] SLE Q Out 0.076 0.076 - CORETSEi0io[2] Net - - 0.827 - 5 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEliio_5 CFG4 D In - 0.903 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEliio_5 CFG4 Y Out 0.236 1.139 - CORETSEliio_5 Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEliio_6 CFG4 D In - 1.622 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEliio_6 CFG4 Y Out 0.236 1.858 - CORETSEliio_6 Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEliio CFG4 D In - 2.341 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEliio CFG4 Y Out 0.236 2.577 - CORETSEliio Net - - 0.736 - 10 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.un1_CORETSEoIli CFG4 C In - 3.313 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.un1_CORETSEoIli CFG4 Y Out 0.177 3.489 - un1_CORETSEoIli Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEoIli CFG3 B In - 3.973 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEoIli CFG3 Y Out 0.143 4.116 - CORETSEoIli Net - - 0.622 - 4 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.un2_CORETSEIIli CFG4 D In - 4.737 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.un2_CORETSEIIli CFG4 Y Out 0.284 5.021 - un2_CORETSEIIli Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEIIli CFG4 C In - 5.505 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEIIli CFG4 Y Out 0.182 5.687 - CORETSEIIli Net - - 0.706 - 8 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEl0li_5[0] CFG4 D In - 6.393 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEl0li_5[0] CFG4 Y Out 0.250 6.643 - CORETSEl0li_5[0] Net - - 0.590 - 3 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.un22_CORETSEIlI CFG4 D In - 7.233 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.un22_CORETSEIlI CFG4 Y Out 0.276 7.509 - un22_CORETSEIlI Net - - 0.689 - 7 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEIlI[5] CFG4 D In - 8.198 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEIlI[5] CFG4 Y Out 0.236 8.434 - CORETSEIlI[5] Net - - 0.138 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEllI[5] SLE D In - 8.572 - ============================================================================================================================================================== Total path delay (propagation time + setup) of 8.794 is 2.554(29.0%) logic and 6.240(71.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 8.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.778 - Propagation time: 8.550 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.772 Number of logic level(s): 10 Starting point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEoio0.CORETSElili_fast / Q Ending point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEIIol[11] / D The start point is clocked by FCCC_1/GL0 [rising] on pin CLK The end point is clocked by FCCC_1/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEoio0.CORETSElili_fast SLE Q Out 0.094 0.094 - CORETSElili_fast Net - - 0.676 - 4 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEoio0.CORETSEooo0[2] CFG3 B In - 0.770 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEoio0.CORETSEooo0[2] CFG3 Y Out 0.143 0.914 - CORETSEooo0[2] Net - - 0.990 - 51 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEIiol.g0_9 CFG4 D In - 1.903 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEIiol.g0_9 CFG4 Y Out 0.250 2.153 - g1_0 Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEIiol.g0_5 CFG4 D In - 2.636 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEIiol.g0_5 CFG4 Y Out 0.250 2.887 - i5_mux_0_0 Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEIiol.g0_4 CFG3 C In - 3.370 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEIiol.g0_4 CFG3 Y Out 0.182 3.552 - CORETSEIiol Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEiOol_0_1[1] CFG4 D In - 4.035 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEiOol_0_1[1] CFG4 Y Out 0.250 4.285 - CORETSEiOol_0_1[1] Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEiOol_0[1] CFG4 D In - 4.769 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEiOol_0[1] CFG4 Y Out 0.250 5.019 - CORETSEiOol[1] Net - - 0.670 - 6 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEo1li.un12_CORETSEo1ol CFG4 C In - 5.689 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEo1li.un12_CORETSEo1ol CFG4 Y Out 0.196 5.885 - un12_CORETSEo1ol Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEo1ol CFG4 D In - 6.368 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEo1ol CFG4 Y Out 0.276 6.644 - CORETSEo1ol Net - - 0.761 - 12 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEoool51[0] CFG3 B In - 7.405 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEoool51[0] CFG3 Y Out 0.125 7.529 - CORETSEoool51[0] Net - - 0.689 - 7 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEIIol_f0[2] CFG3 C In - 8.219 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEIIol_f0[2] CFG3 Y Out 0.194 8.412 - CORETSEl0io[5] Net - - 0.138 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEIIol[11] SLE D In - 8.550 - =========================================================================================================================================================================== Total path delay (propagation time + setup) of 8.772 is 2.433(27.7%) logic and 6.339(72.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 8.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.778 - Propagation time: 8.550 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.772 Number of logic level(s): 10 Starting point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEoio0.CORETSElili_fast / Q Ending point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEi0io[28] / D The start point is clocked by FCCC_1/GL0 [rising] on pin CLK The end point is clocked by FCCC_1/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEoio0.CORETSElili_fast SLE Q Out 0.094 0.094 - CORETSElili_fast Net - - 0.676 - 4 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEoio0.CORETSEooo0[2] CFG3 B In - 0.770 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEoio0.CORETSEooo0[2] CFG3 Y Out 0.143 0.914 - CORETSEooo0[2] Net - - 0.990 - 51 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEIiol.g0_9 CFG4 D In - 1.903 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEIiol.g0_9 CFG4 Y Out 0.250 2.153 - g1_0 Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEIiol.g0_5 CFG4 D In - 2.636 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEIiol.g0_5 CFG4 Y Out 0.250 2.887 - i5_mux_0_0 Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEIiol.g0_4 CFG3 C In - 3.370 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEIiol.g0_4 CFG3 Y Out 0.182 3.552 - CORETSEIiol Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEiOol_0_1[1] CFG4 D In - 4.035 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEiOol_0_1[1] CFG4 Y Out 0.250 4.285 - CORETSEiOol_0_1[1] Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEiOol_0[1] CFG4 D In - 4.769 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEiOol_0[1] CFG4 Y Out 0.250 5.019 - CORETSEiOol[1] Net - - 0.670 - 6 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEo1li.un12_CORETSEo1ol CFG4 C In - 5.689 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEo1li.un12_CORETSEo1ol CFG4 Y Out 0.196 5.885 - un12_CORETSEo1ol Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEo1ol CFG4 D In - 6.368 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEo1ol CFG4 Y Out 0.276 6.644 - CORETSEo1ol Net - - 0.761 - 12 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEoool51[0] CFG3 B In - 7.405 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEoool51[0] CFG3 Y Out 0.125 7.529 - CORETSEoool51[0] Net - - 0.689 - 7 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEoool51_RNITUE21[0] CFG3 C In - 8.219 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEoool51_RNITUE21[0] CFG3 Y Out 0.194 8.412 - CORETSEOiol_0_0_iv_i[4] Net - - 0.138 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEiio0.CORETSEi0io[28] SLE D In - 8.550 - =================================================================================================================================================================================== Total path delay (propagation time + setup) of 8.772 is 2.433(27.7%) logic and 6.339(72.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: FCCC_2/GL0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------ CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEO00I[0] FCCC_2/GL0 SLE Q CORETSEO00I[0] 0.094 2.347 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEO00I[2] FCCC_2/GL0 SLE Q CORETSEO00I[2] 0.094 2.413 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEO00I[1] FCCC_2/GL0 SLE Q CORETSEO00I[1] 0.094 2.443 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEO00I[5] FCCC_2/GL0 SLE Q CORETSEO00I[5] 0.094 2.695 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEIl0I FCCC_2/GL0 SLE Q CORETSEIl0I 0.076 2.698 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEo1lI FCCC_2/GL0 SLE Q CORETSEo1lI 0.094 2.714 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEO00I[6] FCCC_2/GL0 SLE Q CORETSEO00I[6] 0.094 2.727 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEOI0I FCCC_2/GL0 SLE Q CORETSEOI0I 0.094 2.771 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEOOi0.CORETSEilIlI[8] FCCC_2/GL0 SLE Q CORETSEilIlI[8] 0.076 2.885 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEO00I[4] FCCC_2/GL0 SLE Q CORETSEO00I[4] 0.094 2.895 ======================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEol0I[9] FCCC_2/GL0 SLE D CORETSEll0I[9] 7.778 2.347 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEol0I[6] FCCC_2/GL0 SLE D CORETSEll0I[6] 7.778 2.378 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEol0I[7] FCCC_2/GL0 SLE D CORETSEll0I[7] 7.778 2.378 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEol0I[8] FCCC_2/GL0 SLE D CORETSEll0I[8] 7.778 2.487 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEI10I FCCC_2/GL0 SLE D CORETSEO10I_i_i 7.848 2.714 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEoOlI FCCC_2/GL0 SLE D CORETSEOOlI 7.848 2.785 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEOOi0.CORETSEilIlI[4] FCCC_2/GL0 SLE D CORETSEolIlI[4] 7.778 2.885 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEOOi0.CORETSEilIlI[7] FCCC_2/GL0 SLE D CORETSEolIlI[7] 7.778 2.885 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEOOi0.CORETSEilIlI[8] FCCC_2/GL0 SLE D CORETSEolIlI[8] 7.778 2.885 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSEOOi0.CORETSEilIlI[9] FCCC_2/GL0 SLE D CORETSEolIlI[9] 7.778 2.885 ========================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 8.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.778 - Propagation time: 5.431 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 2.347 Number of logic level(s): 6 Starting point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEO00I[0] / Q Ending point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEol0I[9] / D The start point is clocked by FCCC_2/GL0 [rising] on pin CLK The end point is clocked by FCCC_2/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEO00I[0] SLE Q Out 0.094 0.094 - CORETSEO00I[0] Net - - 0.876 - 14 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEOi0I.m38 CFG3 C In - 0.970 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEOi0I.m38 CFG3 Y Out 0.196 1.166 - N_287 Net - - 0.548 - 2 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEOi0I.m66_1_2 CFG4 D In - 1.714 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEOi0I.m66_1_2 CFG4 Y Out 0.276 1.990 - m66_1_2 Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEOi0I.m66 CFG4 D In - 2.473 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEOi0I.m66 CFG4 Y Out 0.284 2.757 - CORETSEO0ol Net - - 0.670 - 6 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEOi0I.un1_CORETSEoI0I_1[0] CFG4 C In - 3.427 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEOi0I.un1_CORETSEoI0I_1[0] CFG4 Y Out 0.194 3.621 - un1_CORETSEoI0I_1[0] Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEOi0I.CORETSElO00236_RNID4A34[0] CFG4 D In - 4.104 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEOi0I.CORETSElO00236_RNID4A34[0] CFG4 Y Out 0.284 4.388 - un1_N_3_mux_0 Net - - 0.622 - 4 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEOi0I.CORETSElO00_iv[6] CFG4 D In - 5.010 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEOi0I.CORETSElO00_iv[6] CFG4 Y Out 0.284 5.293 - CORETSEll0I[9] Net - - 0.138 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEi01lI\.CORETSEo1O0I.CORETSEoIiII.CORETSElio0.CORETSEol0I[9] SLE D In - 5.431 - ==================================================================================================================================================================================== Total path delay (propagation time + setup) of 5.653 is 1.834(32.4%) logic and 3.820(67.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: FCCC_3/GL1 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEOiI1.CORETSEoo[7] FCCC_3/GL1 SLE Q CORETSEoo[7] 0.094 -1.739 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEOiI1.CORETSEoo[4] FCCC_3/GL1 SLE Q CORETSEoo[4] 0.094 -1.635 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEOiI1.CORETSEoo[1] FCCC_3/GL1 SLE Q CORETSEoo[1] 0.094 -1.577 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEOiI1.CORETSEoo[6] FCCC_3/GL1 SLE Q CORETSEoo[6] 0.076 -1.540 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEOiI1.CORETSEoo[0] FCCC_3/GL1 SLE Q CORETSEoo[0] 0.094 -1.535 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEoIoI[7] FCCC_3/GL1 SLE Q CORETSEoIoI[7] 0.094 -1.524 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEOiI1.CORETSEoo[2] FCCC_3/GL1 SLE Q CORETSEoo[2] 0.094 -1.475 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEoIoI[4] FCCC_3/GL1 SLE Q CORETSEoIoI[4] 0.094 -1.420 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEoIoI[1] FCCC_3/GL1 SLE Q CORETSEoIoI[1] 0.094 -1.388 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEoIoI[0] FCCC_3/GL1 SLE Q CORETSEoIoI[0] 0.094 -1.346 ===================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[10] FCCC_3/GL1 SLE D CORETSEoolo[10] 3.778 -1.739 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[11] FCCC_3/GL1 SLE D CORETSEoolo[11] 3.778 -1.739 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[12] FCCC_3/GL1 SLE D CORETSEoolo[12] 3.778 -1.739 CoreTSE_M2S090_MSS_0.MSS_ADLIB_INST FCCC_3/GL1 MSS_075 F_HM0_RDATA[2] CoreTSE_M2S090_MSS_0_FIC_0_AHB_MASTER_HRDATA[2] 2.802 -1.120 CoreTSE_M2S090_MSS_0.MSS_ADLIB_INST FCCC_3/GL1 MSS_075 F_HM0_RDATA[22] CoreTSE_M2S090_MSS_0_FIC_0_AHB_MASTER_HRDATA[22] 2.744 -0.996 CoreTSE_M2S090_MSS_0.MSS_ADLIB_INST FCCC_3/GL1 MSS_075 F_HM0_RDATA[29] CoreTSE_M2S090_MSS_0_FIC_0_AHB_MASTER_HRDATA[29] 2.941 -0.934 CoreTSE_M2S090_MSS_0.MSS_ADLIB_INST FCCC_3/GL1 MSS_075 F_HM0_RDATA[18] CoreTSE_M2S090_MSS_0_FIC_0_AHB_MASTER_HRDATA[18] 2.817 -0.891 CoreTSE_M2S090_MSS_0.MSS_ADLIB_INST FCCC_3/GL1 MSS_075 F_HM0_RDATA[19] CoreTSE_M2S090_MSS_0_FIC_0_AHB_MASTER_HRDATA[19] 2.994 -0.873 CoreTSE_M2S090_MSS_0.MSS_ADLIB_INST FCCC_3/GL1 MSS_075 F_HM0_RDATA[30] CoreTSE_M2S090_MSS_0_FIC_0_AHB_MASTER_HRDATA[30] 2.938 -0.862 CoreTSE_M2S090_MSS_0.MSS_ADLIB_INST FCCC_3/GL1 MSS_075 F_HM0_RDATA[26] CoreTSE_M2S090_MSS_0_FIC_0_AHB_MASTER_HRDATA[26] 2.948 -0.860 ========================================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.517 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.739 Number of logic level(s): 7 Starting point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEOiI1.CORETSEoo[7] / Q Ending point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[10] / D The start point is clocked by FCCC_3/GL1 [rising] on pin CLK The end point is clocked by FCCC_0/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEOiI1.CORETSEoo[7] SLE Q Out 0.094 0.094 - CORETSEoo[7] Net - - 0.735 - 6 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEiolo[7] CFG4 B In - 0.830 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEiolo[7] CFG4 Y Out 0.143 0.972 - CORETSEiolo[7] Net - - 0.670 - 6 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_3[0] CFG4 D In - 1.642 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_3[0] CFG4 Y Out 0.276 1.918 - CORETSEoolo_3[0] Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_4[0] CFG4 C In - 2.401 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_4[0] CFG4 Y Out 0.177 2.578 - CORETSEoolo_4[0] Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo[0] CFG4 D In - 3.061 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo[0] CFG4 Y Out 0.236 3.297 - CORETSEoolo[0] Net - - 0.548 - 2 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a2_2_N_4L6 CFG4 B In - 3.845 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a2_2_N_4L6 CFG4 Y Out 0.125 3.969 - CORETSEoolo_0_a2_2_1[12] Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a2_2[12] CFG4 C In - 4.453 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a2_2[12] CFG4 Y Out 0.194 4.646 - N_132 Net - - 0.590 - 3 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a3[10] CFG4 B In - 5.236 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a3[10] CFG4 Y Out 0.143 5.380 - CORETSEoolo[10] Net - - 0.138 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[10] SLE D In - 5.517 - ====================================================================================================================================================================== Total path delay (propagation time + setup) of 5.739 is 1.609(28.0%) logic and 4.130(72.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.517 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.739 Number of logic level(s): 7 Starting point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEOiI1.CORETSEoo[7] / Q Ending point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[12] / D The start point is clocked by FCCC_3/GL1 [rising] on pin CLK The end point is clocked by FCCC_0/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEOiI1.CORETSEoo[7] SLE Q Out 0.094 0.094 - CORETSEoo[7] Net - - 0.735 - 6 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEiolo[7] CFG4 B In - 0.830 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEiolo[7] CFG4 Y Out 0.143 0.972 - CORETSEiolo[7] Net - - 0.670 - 6 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_3[0] CFG4 D In - 1.642 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_3[0] CFG4 Y Out 0.276 1.918 - CORETSEoolo_3[0] Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_4[0] CFG4 C In - 2.401 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_4[0] CFG4 Y Out 0.177 2.578 - CORETSEoolo_4[0] Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo[0] CFG4 D In - 3.061 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo[0] CFG4 Y Out 0.236 3.297 - CORETSEoolo[0] Net - - 0.548 - 2 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a2_2_N_4L6 CFG4 B In - 3.845 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a2_2_N_4L6 CFG4 Y Out 0.125 3.969 - CORETSEoolo_0_a2_2_1[12] Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a2_2[12] CFG4 C In - 4.453 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a2_2[12] CFG4 Y Out 0.194 4.646 - N_132 Net - - 0.590 - 3 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a3[12] CFG4 B In - 5.236 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a3[12] CFG4 Y Out 0.143 5.380 - CORETSEoolo[12] Net - - 0.138 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[12] SLE D In - 5.517 - ====================================================================================================================================================================== Total path delay (propagation time + setup) of 5.739 is 1.609(28.0%) logic and 4.130(72.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.517 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.739 Number of logic level(s): 7 Starting point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEOiI1.CORETSEoo[7] / Q Ending point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[11] / D The start point is clocked by FCCC_3/GL1 [rising] on pin CLK The end point is clocked by FCCC_0/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEOiI1.CORETSEoo[7] SLE Q Out 0.094 0.094 - CORETSEoo[7] Net - - 0.735 - 6 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEiolo[7] CFG4 B In - 0.830 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEiolo[7] CFG4 Y Out 0.143 0.972 - CORETSEiolo[7] Net - - 0.670 - 6 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_3[0] CFG4 D In - 1.642 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_3[0] CFG4 Y Out 0.276 1.918 - CORETSEoolo_3[0] Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_4[0] CFG4 C In - 2.401 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_4[0] CFG4 Y Out 0.177 2.578 - CORETSEoolo_4[0] Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo[0] CFG4 D In - 3.061 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo[0] CFG4 Y Out 0.236 3.297 - CORETSEoolo[0] Net - - 0.548 - 2 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a2_2_N_4L6 CFG4 B In - 3.845 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a2_2_N_4L6 CFG4 Y Out 0.125 3.969 - CORETSEoolo_0_a2_2_1[12] Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a2_2[12] CFG4 C In - 4.453 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a2_2[12] CFG4 Y Out 0.194 4.646 - N_132 Net - - 0.590 - 3 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a3[11] CFG4 B In - 5.236 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a3[11] CFG4 Y Out 0.143 5.380 - CORETSEoolo[11] Net - - 0.138 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[11] SLE D In - 5.517 - ====================================================================================================================================================================== Total path delay (propagation time + setup) of 5.739 is 1.609(28.0%) logic and 4.130(72.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.413 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.635 Number of logic level(s): 7 Starting point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEOiI1.CORETSEoo[4] / Q Ending point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[10] / D The start point is clocked by FCCC_3/GL1 [rising] on pin CLK The end point is clocked by FCCC_0/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEOiI1.CORETSEoo[4] SLE Q Out 0.094 0.094 - CORETSEoo[4] Net - - 0.735 - 6 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEiolo[4] CFG4 B In - 0.830 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEiolo[4] CFG4 Y Out 0.143 0.972 - CORETSEiolo[4] Net - - 0.648 - 5 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_3[0] CFG4 C In - 1.620 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_3[0] CFG4 Y Out 0.194 1.814 - CORETSEoolo_3[0] Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_4[0] CFG4 C In - 2.297 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_4[0] CFG4 Y Out 0.177 2.474 - CORETSEoolo_4[0] Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo[0] CFG4 D In - 2.957 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo[0] CFG4 Y Out 0.236 3.193 - CORETSEoolo[0] Net - - 0.548 - 2 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a2_2_N_4L6 CFG4 B In - 3.741 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a2_2_N_4L6 CFG4 Y Out 0.125 3.865 - CORETSEoolo_0_a2_2_1[12] Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a2_2[12] CFG4 C In - 4.349 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a2_2[12] CFG4 Y Out 0.194 4.543 - N_132 Net - - 0.590 - 3 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a3[10] CFG4 B In - 5.132 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a3[10] CFG4 Y Out 0.143 5.276 - CORETSEoolo[10] Net - - 0.138 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[10] SLE D In - 5.413 - ====================================================================================================================================================================== Total path delay (propagation time + setup) of 5.635 is 1.527(27.1%) logic and 4.108(72.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.413 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.635 Number of logic level(s): 7 Starting point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEOiI1.CORETSEoo[4] / Q Ending point: CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[12] / D The start point is clocked by FCCC_3/GL1 [rising] on pin CLK The end point is clocked by FCCC_0/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEiOI1.CORETSEOiI1.CORETSEoo[4] SLE Q Out 0.094 0.094 - CORETSEoo[4] Net - - 0.735 - 6 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEiolo[4] CFG4 B In - 0.830 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEiolo[4] CFG4 Y Out 0.143 0.972 - CORETSEiolo[4] Net - - 0.648 - 5 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_3[0] CFG4 C In - 1.620 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_3[0] CFG4 Y Out 0.194 1.814 - CORETSEoolo_3[0] Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_4[0] CFG4 C In - 2.297 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_4[0] CFG4 Y Out 0.177 2.474 - CORETSEoolo_4[0] Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo[0] CFG4 D In - 2.957 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo[0] CFG4 Y Out 0.236 3.193 - CORETSEoolo[0] Net - - 0.548 - 2 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a2_2_N_4L6 CFG4 B In - 3.741 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a2_2_N_4L6 CFG4 Y Out 0.125 3.865 - CORETSEoolo_0_a2_2_1[12] Net - - 0.483 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a2_2[12] CFG4 C In - 4.349 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a2_2[12] CFG4 Y Out 0.194 4.543 - N_132 Net - - 0.590 - 3 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a3[12] CFG4 B In - 5.132 - CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEoolo_0_a3[12] CFG4 Y Out 0.143 5.276 - CORETSEoolo[12] Net - - 0.138 - 1 CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI\.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[12] SLE D In - 5.413 - ====================================================================================================================================================================== Total path delay (propagation time + setup) of 5.635 is 1.527(27.1%) logic and 4.108(72.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: OSC_0/I_RCOSC_25_50MHZ/CLKOUT ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------ CoreResetP_0.count_sdif0[0] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[0] 0.094 17.681 CoreResetP_0.count_sdif0[1] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[1] 0.094 17.746 CoreResetP_0.count_sdif0[2] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[2] 0.094 17.760 CoreResetP_0.count_sdif0[3] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[3] 0.094 17.774 CoreResetP_0.count_sdif0[4] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[4] 0.094 17.789 CoreResetP_0.count_sdif0[5] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[5] 0.094 17.803 CoreResetP_0.count_sdif0[6] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[6] 0.094 17.817 CoreResetP_0.count_sdif0[7] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[7] 0.094 17.831 CoreResetP_0.count_sdif0[8] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[8] 0.094 17.845 CoreResetP_0.count_sdif0[9] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[9] 0.094 17.858 ======================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------- CoreResetP_0.count_sdif0[12] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[12] 19.778 17.681 CoreResetP_0.count_sdif0[11] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[11] 19.778 17.695 CoreResetP_0.count_sdif0[10] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[10] 19.778 17.709 CoreResetP_0.count_sdif0[9] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[9] 19.778 17.724 CoreResetP_0.count_sdif0[8] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[8] 19.778 17.738 CoreResetP_0.count_sdif0[7] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[7] 19.778 17.752 CoreResetP_0.count_sdif0[6] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[6] 19.778 17.766 CoreResetP_0.count_sdif0[5] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[5] 19.778 17.780 CoreResetP_0.count_sdif0[4] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[4] 19.778 17.794 CoreResetP_0.count_sdif0[3] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[3] 19.778 17.809 ============================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 19.778 - Propagation time: 2.097 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 17.681 Number of logic level(s): 13 Starting point: CoreResetP_0.count_sdif0[0] / Q Ending point: CoreResetP_0.count_sdif0[12] / D The start point is clocked by OSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] on pin CLK The end point is clocked by OSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------- CoreResetP_0.count_sdif0[0] SLE Q Out 0.094 0.094 - count_sdif0[0] Net - - 0.637 - 3 CoreResetP_0.count_sdif0_s_2511 ARI1 B In - 0.732 - CoreResetP_0.count_sdif0_s_2511 ARI1 FCO Out 0.174 0.906 - count_sdif0_s_2511_FCO Net - - 0.000 - 1 CoreResetP_0.count_sdif0_cry[1] ARI1 FCI In - 0.906 - CoreResetP_0.count_sdif0_cry[1] ARI1 FCO Out 0.014 0.920 - count_sdif0_cry[1] Net - - 0.000 - 1 CoreResetP_0.count_sdif0_cry[2] ARI1 FCI In - 0.920 - CoreResetP_0.count_sdif0_cry[2] ARI1 FCO Out 0.014 0.935 - count_sdif0_cry[2] Net - - 0.000 - 1 CoreResetP_0.count_sdif0_cry[3] ARI1 FCI In - 0.935 - CoreResetP_0.count_sdif0_cry[3] ARI1 FCO Out 0.014 0.949 - count_sdif0_cry[3] Net - - 0.000 - 1 CoreResetP_0.count_sdif0_cry[4] ARI1 FCI In - 0.949 - CoreResetP_0.count_sdif0_cry[4] ARI1 FCO Out 0.014 0.963 - count_sdif0_cry[4] Net - - 0.000 - 1 CoreResetP_0.count_sdif0_cry[5] ARI1 FCI In - 0.963 - CoreResetP_0.count_sdif0_cry[5] ARI1 FCO Out 0.014 0.977 - count_sdif0_cry[5] Net - - 0.000 - 1 CoreResetP_0.count_sdif0_cry[6] ARI1 FCI In - 0.977 - CoreResetP_0.count_sdif0_cry[6] ARI1 FCO Out 0.014 0.991 - count_sdif0_cry[6] Net - - 0.000 - 1 CoreResetP_0.count_sdif0_cry[7] ARI1 FCI In - 0.991 - CoreResetP_0.count_sdif0_cry[7] ARI1 FCO Out 0.014 1.006 - count_sdif0_cry[7] Net - - 0.000 - 1 CoreResetP_0.count_sdif0_cry[8] ARI1 FCI In - 1.006 - CoreResetP_0.count_sdif0_cry[8] ARI1 FCO Out 0.014 1.020 - count_sdif0_cry[8] Net - - 0.000 - 1 CoreResetP_0.count_sdif0_cry[9] ARI1 FCI In - 1.020 - CoreResetP_0.count_sdif0_cry[9] ARI1 FCO Out 0.014 1.034 - count_sdif0_cry[9] Net - - 0.000 - 1 CoreResetP_0.count_sdif0_cry[10] ARI1 FCI In - 1.034 - CoreResetP_0.count_sdif0_cry[10] ARI1 FCO Out 0.014 1.048 - count_sdif0_cry[10] Net - - 0.000 - 1 CoreResetP_0.count_sdif0_cry[11] ARI1 FCI In - 1.048 - CoreResetP_0.count_sdif0_cry[11] ARI1 FCO Out 0.014 1.062 - count_sdif0_cry[11] Net - - 0.000 - 1 CoreResetP_0.count_sdif0_s[12] ARI1 FCI In - 1.062 - CoreResetP_0.count_sdif0_s[12] ARI1 S Out 0.063 1.126 - count_sdif0_s[12] Net - - 0.971 - 1 CoreResetP_0.count_sdif0[12] SLE D In - 2.097 - =============================================================================================== Total path delay (propagation time + setup) of 2.319 is 0.710(30.6%) logic and 1.609(69.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------- FCCC_1.CCC_INST System CCC LOCK FCCC_1_LOCK 0.000 7.906 FCCC_2.CCC_INST System CCC LOCK FCCC_2_LOCK 0.000 7.973 ===================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------- FCCC_3.CCC_INST System CCC NGMUX0_ARST_N PHY_RST_c 10.000 7.906 FCCC_3.CCC_INST System CCC NGMUX1_ARST_N PHY_RST_c 10.000 7.906 ============================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 10.000 - Propagation time: 2.094 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 7.906 Number of logic level(s): 1 Starting point: FCCC_1.CCC_INST / LOCK Ending point: FCCC_3.CCC_INST / NGMUX0_ARST_N The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- FCCC_1.CCC_INST CCC LOCK Out 0.000 0.000 - FCCC_1_LOCK Net - - 0.971 - 1 AND2_0 AND2 B In - 0.971 - AND2_0 AND2 Y Out 0.143 1.114 - PHY_RST_c Net - - 0.980 - 3 FCCC_3.CCC_INST CCC NGMUX0_ARST_N In - 2.094 - ======================================================================================= Total path delay (propagation time + setup) of 2.094 is 0.143(6.8%) logic and 1.951(93.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied @W:MT447 : synthesis.fdc(19) | Timing constraint (from [get_cells { CoreResetP_0.MSS_HPMS_READY_int }] to [get_cells { CoreResetP_0.sm0_areset_n_rcosc CoreResetP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(20) | Timing constraint (from [get_cells { CoreResetP_0.MSS_HPMS_READY_int CoreResetP_0.SDIF*_PERST_N_re }] to [get_cells { CoreResetP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT443 : synthesis.fdc(22) | Timing constraint (through [get_nets { CoreConfigP_0.FIC_2_APB_M_PSEL CoreConfigP_0.FIC_2_APB_M_PENABLE }] to [get_cells { CoreConfigP_0.FIC_2_APB_M_PREADY* CoreConfigP_0.state[0] }]) (max delay 0.000000) was not applied to the design because none of the paths specified by the constraint exist in the design Finished final timing analysis (Real Time elapsed 0h:01m:03s; CPU Time elapsed 0h:01m:02s; Memory used current: 281MB peak: 326MB) Finished timing report (Real Time elapsed 0h:01m:03s; CPU Time elapsed 0h:01m:02s; Memory used current: 281MB peak: 326MB) --------------------------------------- Resource Usage Report for CoreTSE_M2S090 Mapping to part: m2s090tsfbga484-1 Cell usage: AND2 1 use CCC 4 uses CLKINT 27 uses MSS_075 1 use RCOSC_25_50MHZ 1 use RCOSC_25_50MHZ_FAB 1 use SERDESIF_075 1 use SYSRESET 1 use CFG1 24 uses CFG2 1234 uses CFG3 1778 uses CFG4 5558 uses Carry cells: ARI1 1473 uses - used for arithmetic functions ARI1 41 uses - used for Wide-Mux implementation Total ARI1 1514 uses Sequential Cells: SLE 5293 uses DSP Blocks: 0 of 84 (0%) I/O ports: 44 I/O primitives: 26 BIBUF 5 uses INBUF 4 uses INBUF_DIFF 1 use OUTBUF 13 uses TRIBUFF 3 uses Global Clock Buffers: 27 of 8 (337%) RAM/ROM usage summary Total Block RAMs (RAM1K18) : 16 of 109 (14%) Total LUTs: 10108 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 576; LUTs = 576; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 5293 + 0 + 576 + 0 = 5869; Total number of LUTs after P&R: 10108 + 0 + 576 + 0 = 10684; Mapper successful! At Mapper Exit (Real Time elapsed 0h:01m:03s; CPU Time elapsed 0h:01m:02s; Memory used current: 61MB peak: 326MB) Process took 0h:01m:03s realtime, 0h:01m:02s cputime # Tue Mar 14 15:03:47 2017 ###########################################################]