@W: BN132 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Removing sequential instance CoreResetP_0.sdif3_spll_lock_q1 because it is equivalent to instance CoreResetP_0.sdif0_spll_lock_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Removing sequential instance CoreResetP_0.sdif3_spll_lock_q2 because it is equivalent to instance CoreResetP_0.sdif0_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":884:4:884:9|Removing sequential instance CoreResetP_0.sdif1_areset_n_rcosc_q1 because it is equivalent to instance CoreResetP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":912:4:912:9|Removing sequential instance CoreResetP_0.sdif3_areset_n_rcosc_q1 because it is equivalent to instance CoreResetP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":898:4:898:9|Removing sequential instance CoreResetP_0.sdif2_areset_n_rcosc_q1 because it is equivalent to instance CoreResetP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":755:4:755:9|Removing sequential instance CoreResetP_0.sm0_areset_n_q1 because it is equivalent to instance CoreResetP_0.sdif0_areset_n_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":912:4:912:9|Removing sequential instance CoreResetP_0.sdif3_areset_n_rcosc because it is equivalent to instance CoreResetP_0.sdif2_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":898:4:898:9|Removing sequential instance CoreResetP_0.sdif2_areset_n_rcosc because it is equivalent to instance CoreResetP_0.sdif1_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":884:4:884:9|Removing sequential instance CoreResetP_0.sdif1_areset_n_rcosc because it is equivalent to instance CoreResetP_0.sdif0_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":797:4:797:9|Removing sequential instance CoreResetP_0.sdif0_areset_n_clk_base because it is equivalent to instance CoreResetP_0.sm0_areset_n_clk_base. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\t8b10b.v":148:0:148:3|ROM CORETSEiol0[5:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_T8B10B(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\t8b10b.v":148:0:148:3|ROM CORETSEIil0[1:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_T8B10B(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\t8b10b.v":148:0:148:3|ROM CORETSEOil0 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_T8B10B(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\t8b10b.v":148:0:148:3|ROM CORETSEO0ol (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_T8B10B(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\t8b10b.v":148:0:148:3|ROM CORETSEiol0[5:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_T8B10B(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\t8b10b.v":148:0:148:3|ROM CORETSEIil0[1:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_T8B10B(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\t8b10b.v":148:0:148:3|ROM CORETSEOil0 (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_T8B10B(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\t8b10b.v":148:0:148:3|ROM CORETSEO0ol (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_T8B10B(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":3418:0:3418:3|ROM CORETSEoiol (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":3418:0:3418:3|ROM CORETSEiiol (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":1261:0:1261:3|ROM CORETSEl0ol[2:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":1261:0:1261:3|ROM CORETSEI1ol[2:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":1261:0:1261:3|ROM CORETSEO1ol[1:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":268:0:268:3|ROM CORETSEI0ol[1:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":3418:0:3418:3|ROM CORETSEoiol (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":3418:0:3418:3|ROM CORETSEiiol (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":1950:0:1950:4|ROM CORETSEi1ol[2:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":1950:0:1950:4|ROM CORETSEIool (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":1261:0:1261:3|ROM CORETSEl0ol[2:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":1261:0:1261:3|ROM CORETSEI1ol[2:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":1261:0:1261:3|ROM CORETSEO1ol[1:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":268:0:268:3|ROM CORETSEI0ol[1:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":3418:0:3418:3|ROM CORETSEoiol (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":3418:0:3418:3|ROM CORETSEiiol (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":1261:0:1261:3|ROM CORETSEl0ol[2:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":1261:0:1261:3|ROM CORETSEI1ol[2:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":1261:0:1261:3|ROM CORETSEO1ol[1:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":268:0:268:3|ROM CORETSEI0ol[1:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":1950:0:1950:4|ROM CORETSEi1ol[3:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":3418:0:3418:3|ROM CORETSEoiol (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":3418:0:3418:3|ROM CORETSEiiol (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":1261:0:1261:3|ROM CORETSEl0ol[2:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":1261:0:1261:3|ROM CORETSEI1ol[2:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":1261:0:1261:3|ROM CORETSEO1ol[1:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\r10b8b.v":268:0:268:3|ROM CORETSEI0ol[1:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_0.regHSIZE[2] (in view view:work.CoreTSE_M2S090(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_1.SDATASELInt[16] (in view view:work.CoreTSE_M2S090(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_1.regHSIZE[2] (in view view:work.CoreTSE_M2S090(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_1.regHSIZE[0] (in view view:work.CoreTSE_M2S090(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_1.regHADDR[1] (in view view:work.CoreTSE_M2S090(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_1.regHADDR[0] (in view view:work.CoreTSE_M2S090(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_2.SDATASELInt[16] (in view view:work.CoreTSE_M2S090(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_2.regHSIZE[2] (in view view:work.CoreTSE_M2S090(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_2.regHSIZE[0] (in view view:work.CoreTSE_M2S090(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_2.regHADDR[1] (in view view:work.CoreTSE_M2S090(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_2.regHADDR[0] (in view view:work.CoreTSE_M2S090(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt[16] (in view view:work.CoreTSE_M2S090(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[15] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[12] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[11] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[7] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[3] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[0] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO197 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing FSM register arbRegSMCurrentState[14] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) because its output is a constant.
@W: MO197 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing FSM register arbRegSMCurrentState[10] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) because its output is a constant.
@W: MO197 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing FSM register arbRegSMCurrentState[6] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) because its output is a constant.
@W: MO197 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing FSM register arbRegSMCurrentState[2] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) because its output is a constant.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[1] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[12] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[8] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[4] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[15] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_3(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[12] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_3(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[11] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_3(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[7] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_3(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[3] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_3(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO197 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing FSM register arbRegSMCurrentState[14] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_3(verilog)) because its output is a constant.
@W: MO197 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing FSM register arbRegSMCurrentState[10] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_3(verilog)) because its output is a constant.
@W: MO197 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing FSM register arbRegSMCurrentState[6] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_3(verilog)) because its output is a constant.
@W: MO197 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing FSM register arbRegSMCurrentState[2] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_3(verilog)) because its output is a constant.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coreahblsram_0\rtl\vlog\core\ahblsramif.v":310:0:310:5|Register bit burst_count_reg[4] (in view view:COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_AHBLSramIf_Z6(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coreahblsram_0\rtl\vlog\core\ahblsramif.v":310:0:310:5|Register bit burst_count_reg[3] (in view view:COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_AHBLSramIf_Z6(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coreahblsram_0\rtl\vlog\core\ahblsramif.v":310:0:310:5|Register bit burst_count_reg[2] (in view view:COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_AHBLSramIf_Z6(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coreahblsram_0\rtl\vlog\core\ahblsramif.v":310:0:310:5|Register bit burst_count_reg[1] (in view view:COREAHBLSRAM_LIB.CoreTSE_M2S090_COREAHBLSRAM_0_AHBLSramIf_Z6(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":255:4:255:9|Register bit paddr[16] (in view view:work.CoreConfigP_Z7(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: FX107 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\rx4096x36.v":139:0:139:5|RAM CORETSEI1O0I.CORETSEIIil[35:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP_19s_1s_11s_12s_1s_1s_1s_18s_0s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\tx2048x40.v":139:0:139:5|RAM CORETSEO1O0I.CORETSEIIil[39:0] (in view: work.CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP_19s_1s_11s_12s_1s_1s_1s_18s_0s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\pemstat_eim.v":1986:0:1986:5|Register bit CORETSEIllo.CORETSEII0o[30] (in view view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\pemstat_eim.v":1986:0:1986:5|Register bit CORETSEIllo.CORETSEII0o[29] (in view view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\pemstat_eim.v":1986:0:1986:5|Register bit CORETSEIllo.CORETSEII0o[28] (in view view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\pemstat_eim.v":1986:0:1986:5|Register bit CORETSEIllo.CORETSEII0o[27] (in view view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\pemstat_eim.v":1986:0:1986:5|Register bit CORETSEIllo.CORETSEII0o[26] (in view view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\pemstat_eim.v":1986:0:1986:5|Register bit CORETSEIllo.CORETSEII0o[25] (in view view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\pemstat_eim.v":1986:0:1986:5|Register bit CORETSEIllo.CORETSEII0o[24] (in view view:work.CoreTSE_M2S090_CORETSE_AHB_0_PEMSTAT_19s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO129 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\pemstat_cntrl.v":2224:0:2224:5|Sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[36] is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_ahb_0\rtl\vlog\obfuscated\pemstat_cntrl.v":2224:0:2224:5|Sequential instance CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEoiolI.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[37] is reduced to a combinational gate by constant propagation.
@W: FX739 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\coretse_m2s090.v":632:7:632:14|Removed BUFG instance CLKINT_0 because it is cascaded to another clock buffer (FCCC_3.GL0_INST).
@W: MT246 :"d:\11.8\m2s_dg0637_liberov11p7sp2__df\libero\coretse_m2s090\component\work\coretse_m2s090\fccc_3\coretse_m2s090_fccc_3_fccc.v":37:36:37:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock CoreTSE_M2S090_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:SERDES_IF2_0.REFCLK1_OUT"
@W: MT420 |Found inferred clock CoreTSE_M2S090_CORETSE_AHB_0_PEMGT_1s_19s|CORETSEI110_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:CORETSE_AHB_0.CORETSEi0ilI.CORETSEIoilI.CORETSEioolI.CORETSEOII1.CORETSEI110"
@W: MT447 :"d:/11.8/m2s_dg0637_liberov11p7sp2__df/libero/coretse_m2s090/designer/coretse_m2s090/synthesis.fdc":19:0:19:0|Timing constraint (from [get_cells { CoreResetP_0.MSS_HPMS_READY_int }] to [get_cells { CoreResetP_0.sm0_areset_n_rcosc CoreResetP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"d:/11.8/m2s_dg0637_liberov11p7sp2__df/libero/coretse_m2s090/designer/coretse_m2s090/synthesis.fdc":20:0:20:0|Timing constraint (from [get_cells { CoreResetP_0.MSS_HPMS_READY_int CoreResetP_0.SDIF*_PERST_N_re }] to [get_cells { CoreResetP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT443 :"d:/11.8/m2s_dg0637_liberov11p7sp2__df/libero/coretse_m2s090/designer/coretse_m2s090/synthesis.fdc":22:0:22:0|Timing constraint (through [get_nets { CoreConfigP_0.FIC_2_APB_M_PSEL CoreConfigP_0.FIC_2_APB_M_PENABLE }] to [get_cells { CoreConfigP_0.FIC_2_APB_M_PREADY* CoreConfigP_0.state[0] }]) (max delay 0.000000) was not applied to the design because none of the paths specified by the constraint exist in the design 
