@W: CG775 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":23:7:23:17|Found Component CoreAHBLite in library COREAHBLITE_LIB
@W: CL177 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":625:0:625:5|Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":625:0:625:5|Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":625:0:625:5|Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
@W: CG775 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v":29:7:29:48|Found Component CoreTSE_M2S090_COREAHBLSRAM_0_COREAHBLSRAM in library COREAHBLSRAM_LIB
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\AHBLSramIf.v":148:14:148:28|Object sramahb_ack_cnt is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\AHBLSramIf.v":184:3:184:8|Pruning unused register HWDATA_d[31:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\AHBLSramIf.v":184:3:184:8|Pruning unused register HTRANS_d[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\AHBLSramIf.v":184:3:184:8|Pruning unused register HBURST_d[2:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\AHBLSramIf.v":184:3:184:8|Pruning unused register HSEL_d. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\AHBLSramIf.v":184:3:184:8|Pruning unused register HREADYIN_d. Make sure that there are no unused intermediate registers.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":364:35:364:44|Object writeAddr0 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":365:35:365:44|Object writeAddr1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":366:35:366:44|Object writeAddr2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":367:35:367:44|Object writeAddr3 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":368:35:368:44|Object writeAddr4 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":369:35:369:44|Object writeAddr5 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":370:35:370:44|Object writeAddr6 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":371:35:371:44|Object writeAddr7 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":372:35:372:44|Object writeAddr8 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":373:35:373:44|Object writeAddr9 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":374:35:374:45|Object writeAddr10 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":375:35:375:45|Object writeAddr11 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":376:35:376:45|Object writeAddr12 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":377:35:377:45|Object writeAddr13 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":378:35:378:45|Object writeAddr14 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":379:35:379:45|Object writeAddr15 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":380:35:380:45|Object writeAddr16 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":381:35:381:45|Object writeAddr17 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":382:35:382:45|Object writeAddr18 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":383:35:383:45|Object writeAddr19 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":384:35:384:45|Object writeAddr20 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":385:35:385:45|Object writeAddr21 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":386:35:386:45|Object writeAddr22 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":387:35:387:45|Object writeAddr23 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":388:35:388:45|Object writeAddr24 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":389:35:389:45|Object writeAddr25 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":390:35:390:45|Object writeAddr26 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":391:35:391:45|Object writeAddr27 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":392:35:392:45|Object writeAddr28 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":393:35:393:45|Object writeAddr29 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":394:35:394:45|Object writeAddr30 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":395:35:395:45|Object writeAddr31 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":396:35:396:45|Object writeAddr32 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":397:35:397:45|Object writeAddr33 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":398:35:398:45|Object writeAddr34 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":399:35:399:45|Object writeAddr35 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":400:35:400:45|Object writeAddr36 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":401:35:401:45|Object writeAddr37 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":402:35:402:45|Object writeAddr38 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":403:35:403:45|Object writeAddr39 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":404:35:404:45|Object writeAddr40 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":405:35:405:45|Object writeAddr41 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":406:35:406:45|Object writeAddr42 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":407:35:407:45|Object writeAddr43 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":408:35:408:45|Object writeAddr44 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":409:35:409:45|Object writeAddr45 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":410:35:410:45|Object writeAddr46 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":411:35:411:45|Object writeAddr47 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":412:35:412:45|Object writeAddr48 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":413:35:413:45|Object writeAddr49 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":414:35:414:45|Object writeAddr50 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":415:35:415:45|Object writeAddr51 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":416:35:416:45|Object writeAddr52 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":417:35:417:45|Object writeAddr53 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":418:35:418:45|Object writeAddr54 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":419:35:419:45|Object writeAddr55 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":420:35:420:45|Object writeAddr56 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":421:35:421:45|Object writeAddr57 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":422:35:422:45|Object writeAddr58 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":423:35:423:45|Object writeAddr59 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":424:35:424:45|Object writeAddr60 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":425:35:425:45|Object writeAddr61 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":426:35:426:45|Object writeAddr62 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":427:35:427:45|Object writeAddr63 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":428:35:428:45|Object writeAddr64 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":429:35:429:45|Object writeAddr65 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":430:35:430:45|Object writeAddr66 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":431:35:431:45|Object writeAddr67 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":432:35:432:45|Object writeAddr68 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":434:35:434:43|Object readAddr0 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":435:35:435:43|Object readAddr1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":436:35:436:43|Object readAddr2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":437:35:437:43|Object readAddr3 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":438:35:438:43|Object readAddr4 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":439:35:439:43|Object readAddr5 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":440:35:440:43|Object readAddr6 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":441:35:441:43|Object readAddr7 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":442:35:442:43|Object readAddr8 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":443:35:443:43|Object readAddr9 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":444:35:444:44|Object readAddr10 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":445:35:445:44|Object readAddr11 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":446:35:446:44|Object readAddr12 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":447:35:447:44|Object readAddr13 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":448:35:448:44|Object readAddr14 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":449:35:449:44|Object readAddr15 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":450:35:450:44|Object readAddr16 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":451:35:451:44|Object readAddr17 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":452:35:452:44|Object readAddr18 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":453:35:453:44|Object readAddr19 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":454:35:454:44|Object readAddr20 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":455:35:455:44|Object readAddr21 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":456:35:456:44|Object readAddr22 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":457:35:457:44|Object readAddr23 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":458:35:458:44|Object readAddr24 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":459:35:459:44|Object readAddr25 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":460:35:460:44|Object readAddr26 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":461:35:461:44|Object readAddr27 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":462:35:462:44|Object readAddr28 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":463:35:463:44|Object readAddr29 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":464:35:464:44|Object readAddr30 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":465:35:465:44|Object readAddr31 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":466:35:466:44|Object readAddr32 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":467:35:467:44|Object readAddr33 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":468:35:468:44|Object readAddr34 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":469:35:469:44|Object readAddr35 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":470:35:470:44|Object readAddr36 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":471:35:471:44|Object readAddr37 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":472:35:472:44|Object readAddr38 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":473:35:473:44|Object readAddr39 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":474:35:474:44|Object readAddr40 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":475:35:475:44|Object readAddr41 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":476:35:476:44|Object readAddr42 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":477:35:477:44|Object readAddr43 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":478:35:478:44|Object readAddr44 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":479:35:479:44|Object readAddr45 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":480:35:480:44|Object readAddr46 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":481:35:481:44|Object readAddr47 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":482:35:482:44|Object readAddr48 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":483:35:483:44|Object readAddr49 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":484:35:484:44|Object readAddr50 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":485:35:485:44|Object readAddr51 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":486:35:486:44|Object readAddr52 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":487:35:487:44|Object readAddr53 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":488:35:488:44|Object readAddr54 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":489:35:489:44|Object readAddr55 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":490:35:490:44|Object readAddr56 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":491:35:491:44|Object readAddr57 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":492:35:492:44|Object readAddr58 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":493:35:493:44|Object readAddr59 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":494:35:494:44|Object readAddr60 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":495:35:495:44|Object readAddr61 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":496:35:496:44|Object readAddr62 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":497:35:497:44|Object readAddr63 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":498:35:498:44|Object readAddr64 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":499:35:499:44|Object readAddr65 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":500:35:500:44|Object readAddr66 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":501:35:501:44|Object readAddr67 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":502:35:502:44|Object readAddr68 is declared but not assigned. Either assign a value or remove the declaration.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9909:10:9909:16|Removing instance block17 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9889:9:9889:15|Removing instance block18 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9868:10:9868:16|Removing instance block19 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9848:9:9848:15|Removing instance block20 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9827:9:9827:15|Removing instance block21 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9807:9:9807:15|Removing instance block22 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9786:9:9786:15|Removing instance block23 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9765:9:9765:15|Removing instance block24 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9744:9:9744:15|Removing instance block25 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9724:9:9724:15|Removing instance block26 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9704:9:9704:15|Removing instance block27 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9683:9:9683:15|Removing instance block28 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9662:9:9662:15|Removing instance block29 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9640:9:9640:15|Removing instance block30 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9619:9:9619:15|Removing instance block31 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9599:9:9599:15|Removing instance block32 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9578:9:9578:15|Removing instance block33 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9558:9:9558:15|Removing instance block34 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9538:9:9538:15|Removing instance block35 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9517:10:9517:16|Removing instance block36 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9497:9:9497:15|Removing instance block37 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9477:9:9477:15|Removing instance block38 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9456:9:9456:15|Removing instance block39 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9435:9:9435:15|Removing instance block40 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9415:9:9415:15|Removing instance block41 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9394:9:9394:15|Removing instance block42 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9373:9:9373:15|Removing instance block43 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9352:9:9352:15|Removing instance block44 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9331:9:9331:15|Removing instance block45 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9310:9:9310:15|Removing instance block46 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9289:9:9289:15|Removing instance block47 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9268:9:9268:15|Removing instance block48 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9247:9:9247:15|Removing instance block49 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9226:9:9226:15|Removing instance block50 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9205:9:9205:15|Removing instance block51 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9184:9:9184:15|Removing instance block52 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9163:9:9163:15|Removing instance block53 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9142:9:9142:15|Removing instance block54 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9121:9:9121:15|Removing instance block55 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9100:9:9100:15|Removing instance block56 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9079:9:9079:15|Removing instance block57 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9058:9:9058:15|Removing instance block58 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9037:9:9037:15|Removing instance block59 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":9016:9:9016:15|Removing instance block60 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":8995:9:8995:15|Removing instance block61 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":8974:9:8974:15|Removing instance block62 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":8953:9:8953:15|Removing instance block63 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":8933:9:8933:15|Removing instance block64 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":8913:9:8913:15|Removing instance block65 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":8893:9:8893:15|Removing instance block66 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":8872:9:8872:15|Removing instance block67 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":8851:9:8851:15|Removing instance block68 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":586:4:586:9|Pruning unused register ckRdAddr[15:9]. Make sure that there are no unused intermediate registers.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":103:31:103:49|Object ahbsram_wdata_upd_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":104:31:104:51|Object u_ahbsram_wdata_upd_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":111:31:111:42|Removing wire u_BUSY_all_0, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":112:31:112:42|Removing wire u_BUSY_all_1, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":113:31:113:42|Removing wire u_BUSY_all_2, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":114:31:114:42|Removing wire u_BUSY_all_3, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":116:31:116:42|Removing wire l_BUSY_all_1, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":117:31:117:42|Removing wire l_BUSY_all_2, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":118:31:118:42|Removing wire l_BUSY_all_3, as there is no assignment to it.
@W: CL113 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v":626:4:626:9|Feedback mux created for signal soft_reset_reg[16:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL250 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v":626:4:626:9|All reachable assignments to soft_reset_reg[16:0] assign 0, register removed by optimization
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1517:4:1517:9|Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers.
@W: CL177 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL190 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\dmarx.v":302:0:302:11|Object CORETSEI100I is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\dma_dual.v":397:0:397:11|Removing wire CORETSEoOl0I, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\dma_dual.v":400:0:400:11|Removing wire CORETSEiOl0I, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\dma_dual.v":424:0:424:11|Removing wire CORETSEiIl0I, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\dma_dual.v":426:0:426:11|Removing wire CORETSEOll0I, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\dma_dual.v":565:0:565:10|Removing wire CORETSEOO10, as there is no assignment to it.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\dma_dual.v":573:0:573:10|Object CORETSEIO10 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\dma_dual.v":581:0:581:10|Removing wire CORETSElO10, as there is no assignment to it.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\dma_dual.v":589:0:589:10|Object CORETSEoO10 is declared but not assigned. Either assign a value or remove the declaration.
@W: CL265 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\dma_dual.v":1572:0:1572:5|Removing unused bit 5 of CORETSEI0l0I[9:0]. Either assign all bits or reduce the width of the signal.
@W: CL265 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\dma_dual.v":1572:0:1572:5|Removing unused bit 2 of CORETSEI0l0I[9:0]. Either assign all bits or reduce the width of the signal.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\tsm_sysreg.v":216:0:216:10|Removing wire CORETSEoi00, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\tsm_sysreg.v":219:0:219:10|Removing wire CORETSEii00, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\tsm_sysreg.v":227:0:227:10|Removing wire CORETSEOO10, as there is no assignment to it.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\tsm_sysreg.v":235:0:235:10|Object CORETSEIO10 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\tsm_sysreg.v":243:0:243:10|Removing wire CORETSElO10, as there is no assignment to it.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\tsm_sysreg.v":251:0:251:10|Object CORETSEoO10 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxtfif_sys.v":546:0:546:11|Object CORETSEiOoOI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxtfif_sys.v":549:0:549:11|Object CORETSEOIoOI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxtfif_sys.v":552:0:552:11|Object CORETSEIIoOI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxtfif_sys.v":562:0:562:11|Object CORETSElIoOI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxtfif_sys.v":572:0:572:11|Object CORETSEoIoOI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxtfif_sys.v":588:0:588:11|Object CORETSEiIoOI is declared but not assigned. Either assign a value or remove the declaration.
@W: CL271 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxtfif_sys.v":2068:0:2068:5|Pruning unused bits 1 to 0 of genblk2.CORETSEl01OI[13:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL271 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxtfif_sys.v":1583:0:1583:5|Pruning unused bits 13 to 2 of CORETSEo01OI[13:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL271 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxtfif_sys.v":1553:0:1553:5|Pruning unused bits 1 to 0 of CORETSEI01OI[13:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL271 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxtfif_sys.v":1484:0:1484:5|Pruning unused bits 1 to 0 of CORETSEO01OI[13:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL265 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxtfif_sys.v":2019:0:2019:5|Removing unused bit 38 of genblk2.CORETSEI11OI[39:0]. Either assign all bits or reduce the width of the signal.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxrfif_fab.v":636:0:636:5|Pruning unused register CORETSEiiIOI. Make sure that there are no unused intermediate registers.
@W: CL190 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxrfif_fab.v":2168:0:2168:5|Optimizing register bit CORETSEoloi[36] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxrfif_fab.v":2168:0:2168:5|Optimizing register bit CORETSEoloi[37] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxrfif_fab.v":2168:0:2168:5|Optimizing register bit CORETSEoloi[38] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxrfif_fab.v":2168:0:2168:5|Optimizing register bit CORETSEoloi[39] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxrfif_fab.v":2168:0:2168:5|Pruning register bits 39 to 36 of CORETSEoloi[39:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxrfif_fab.v":1532:0:1532:5|Pruning unused register CORETSEl0IOI. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxrfif_sys.v":2075:0:2075:5|Pruning unused register CORETSEoI0OI. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxrfif_sys.v":1783:0:1783:5|Pruning unused register CORETSElI0OI[14:0]. Make sure that there are no unused intermediate registers.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxfif_hst.v":909:0:909:11|Removing wire CORETSEo1OOI, as there is no assignment to it.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petfn_top.v":423:0:423:10|Object CORETSEl0oI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petfn_top.v":426:0:426:10|Removing wire CORETSEo0oI, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petfn_top.v":450:0:450:10|Removing wire CORETSEiOlI, as there is no assignment to it.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petfn_top.v":510:0:510:10|Object CORETSEiOiI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petfn_top.v":513:0:513:10|Object CORETSEOIiI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petfn_top.v":532:0:532:10|Object CORETSEOliI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petfn_top.v":534:0:534:10|Object CORETSEIliI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petfn_top.v":537:0:537:10|Object CORETSElliI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petfn_top.v":539:0:539:10|Object CORETSEoliI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petfn_top.v":977:0:977:10|Removing wire CORETSEOOll, as there is no assignment to it.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petfn_top.v":4448:0:4448:5|Pruning unused register CORETSEioiI[15:0]. Make sure that there are no unused intermediate registers.
@W: CL190 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petfn_top.v":4128:0:4128:5|Optimizing register bit CORETSEooOl[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petfn_top.v":4128:0:4128:5|Optimizing register bit CORETSEooOl[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petfn_top.v":4128:0:4128:5|Pruning register bits 6 to 5 of CORETSEooOl[6:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perfn_top.v":348:0:348:9|Removing wire CORETSEI0I, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perfn_top.v":655:0:655:9|Removing wire CORETSEOI1, as there is no assignment to it.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perfn_top.v":658:0:658:9|Object CORETSEII1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pehst.v":613:0:613:10|Object CORETSEOlI1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pehst.v":709:0:709:10|Object CORETSEIlI1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pehst.v":714:0:714:10|Object CORETSEllI1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pehst.v":716:0:716:10|Object CORETSEolI1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pehst.v":2022:0:2022:5|Pruning unused register CORETSEllo1. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pehst.v":1990:0:1990:5|Pruning unused register CORETSEIlo1. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pehst.v":1958:0:1958:5|Pruning unused register CORETSEOlo1. Make sure that there are no unused intermediate registers.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pe_mcxmac.v":681:0:681:10|Removing wire CORETSEllO1, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pe_mcxmac.v":684:0:684:10|Removing wire CORETSEOio0, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pe_mcxmac.v":687:0:687:10|Removing wire CORETSEiIo0, as there is no assignment to it.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\sib_sync_2flp.v":77:0:77:10|Object CORETSEolO0 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_cntrl.v":113:0:113:10|Removing wire CORETSElllo, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_cntrl.v":115:0:115:10|Removing wire CORETSEollo, as there is no assignment to it.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_cntrl.v":118:0:118:10|Object CORETSEillo is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_cntrl.v":120:0:120:10|Object CORETSEO0lo is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_cntrl.v":129:0:129:10|Object CORETSEi0lo is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_cntrl.v":131:0:131:10|Object CORETSEO1lo is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\tsmac_ahb_top.v":282:0:282:11|Removing wire CORETSEII1lI, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\tsmac_ahb_top.v":284:0:284:11|Removing wire CORETSElI1lI, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\tsmac_ahb_top.v":286:0:286:11|Removing wire CORETSEoI1lI, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\tsmac_ahb_top.v":288:0:288:11|Removing wire CORETSEiI1lI, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\tsmac_ahb_top.v":290:0:290:11|Removing wire CORETSEOl1lI, as there is no assignment to it.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\tx2048x40.v":93:0:93:10|Object CORETSElOil is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\rx4096x36.v":93:0:93:10|Object CORETSElOil is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\msgmii_cnvtxi.v":364:0:364:5|Pruning unused register CORETSEO0oII[3:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petex_top.v":690:0:690:5|Pruning unused register CORETSEO1II. Make sure that there are no unused intermediate registers.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perex_pma.v":219:0:219:10|Object CORETSEiOo0 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perex_pma.v":188:0:188:10|Object CORETSEiO0i is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perex_pma.v":196:0:196:10|Object CORETSEOI0i is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perex_pma.v":199:0:199:10|Object CORETSEII0i is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perex_pma.v":202:0:202:10|Object CORETSElI0i is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perex_pma.v":205:0:205:10|Object CORETSEoI0i is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perex_pma.v":213:0:213:10|Object CORETSEiI0i is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perex_pma.v":216:0:216:10|Removing wire CORETSEOl0i, as there is no assignment to it.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perex_pma.v":222:0:222:10|Object CORETSEIl0i is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perex_pma.v":2085:0:2085:5|Pruning unused register CORETSEll0i. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perex_pma.v":1890:0:1890:5|Pruning unused register CORETSEIili. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perex_pma.v":1854:0:1854:5|Pruning unused register CORETSEOili. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perex_pma.v":1818:0:1818:5|Pruning unused register CORETSEioli. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perex_pcs.v":4321:0:4321:5|Pruning unused register CORETSElIli. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perex_pcs.v":4260:0:4260:5|Pruning unused register CORETSEOIli. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perex_pcs.v":4101:0:4101:5|Pruning unused register CORETSEI1lI. Make sure that there are no unused intermediate registers.
@W: CL265 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perex_pcs.v":1303:0:1303:5|Removing unused bit 3 of CORETSEoIol[3:0]. Either assign all bits or reduce the width of the signal.
@W: CL265 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perex_pcs.v":1303:0:1303:5|Removing unused bit 1 of CORETSEoIol[3:0]. Either assign all bits or reduce the width of the signal.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\msgmii_peanx_top.v":3121:0:3121:5|Pruning unused register CORETSEiIIlI. Make sure that there are no unused intermediate registers.
@W: CL265 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\msgmii_peanx_top.v":3041:0:3041:5|Removing unused bit 14 of CORETSElIIlI[15:0]. Either assign all bits or reduce the width of the signal.
@W: CL265 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\msgmii_peanx_top.v":2437:0:2437:5|Removing unused bit 14 of CORETSEl1OlI[15:0]. Either assign all bits or reduce the width of the signal.
@W: CL177 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\msgmii_peanx_top.v":2361:0:2361:5|Sharing sequential element CORETSEI0OlI. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petbm.v":2544:0:2544:5|Pruning unused register CORETSEIIio. Make sure that there are no unused intermediate registers.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petcr.v":145:0:145:10|Object CORETSEIiOI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petcr.v":147:0:147:10|Object CORETSEliOI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petcr.v":150:0:150:10|Removing wire CORETSEoiOI, as there is no assignment to it.
@W: CL177 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petcr.v":319:0:319:5|Sharing sequential element CORETSEooOI. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petcr.v":422:0:422:5|Sharing sequential element CORETSEoOII. Add a syn_preserve attribute to the element to prevent sharing.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\msgmii_tbi.v":411:0:411:10|Removing wire CORETSEIio0, as there is no assignment to it.
@W: CL169 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\msgmii_cnvrxi.v":496:0:496:5|Pruning unused register CORETSEIl1II[1:0]. Make sure that there are no unused intermediate registers.
@W: CG781 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\CoreTSE_AHB_top.v":1291:0:1291:0|Input CORETSEoO1lI on instance CORETSEIoilI is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\CoreTSE_AHB_top.v":1295:0:1295:0|Input CORETSEiO1lI on instance CORETSEIoilI is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\CoreTSE_AHB_top.v":1299:0:1299:0|Input CORETSEOI1lI on instance CORETSEIoilI is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\CoreTSE_AHB_top.v":1303:0:1303:0|Input CORETSEIO1lI on instance CORETSEIoilI is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\CoreTSE_AHB_top.v":1307:0:1307:0|Input CORETSElO1lI on instance CORETSEIoilI is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\CoreTSE_AHB_top.v":592:0:592:11|Removing wire CORETSEl0llI, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\CoreTSE_AHB_top.v":609:0:609:11|Removing wire CORETSEioIlI, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\CoreTSE_AHB_top.v":717:0:717:11|Removing wire CORETSEIoolI, as there is no assignment to it.
@W: CG781 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\CoreTSE_AHB.v":691:0:691:0|Input AHBS_HPROT_I on instance CORETSEi0ilI is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CL157 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\OSC_0\CoreTSE_M2S090_OSC_0_OSC.v":15:7:15:24|*Output RCOSC_25_50MHZ_CCC has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\OSC_0\CoreTSE_M2S090_OSC_0_OSC.v":17:7:17:20|*Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\OSC_0\CoreTSE_M2S090_OSC_0_OSC.v":18:7:18:20|*Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\OSC_0\CoreTSE_M2S090_OSC_0_OSC.v":19:7:19:16|*Output XTLOSC_CCC has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\OSC_0\CoreTSE_M2S090_OSC_0_OSC.v":20:7:20:16|*Output XTLOSC_O2F has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090_MSS\CoreTSE_M2S090_MSS.v":71:14:71:31|Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\CoreTSE_AHB.v":286:0:286:4|Input port bits 2 to 1 of HSIZE[2:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\CoreTSE_AHB.v":294:0:294:5|Input port bits 2 to 1 of HBURST[2:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL177 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petcr.v":333:0:333:5|Sharing sequential element CORETSEioOI. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petcr.v":436:0:436:5|Sharing sequential element CORETSEiOII. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL190 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petbm.v":714:0:714:5|Optimizing register bit CORETSEIi1o[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petbm.v":714:0:714:5|Pruning register bit 5 of CORETSEIi1o[5:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\msgmii_peanx_top.v":113:0:113:10|Input port bit 14 of CORETSEo0o0[15:0] is unused
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\msgmii_peanx_top.v":113:0:113:10|Input port bit 11 of CORETSEo0o0[15:0] is unused
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\CoreTSE_AHB_top.v":287:0:287:11|Input port bits 31 to 10 of AHBS_HADDR_I[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\CoreTSE_AHB_top.v":287:0:287:11|Input port bits 1 to 0 of AHBS_HADDR_I[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL157 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\CoreTSE_AHB_top.v":239:0:239:10|*Output TSMAC_TXD_O has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\CoreTSE_AHB_top.v":242:0:242:11|*Output TSMAC_TXEN_O has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\CoreTSE_AHB_top.v":245:0:245:11|*Output TSMAC_TXER_O has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_eim.v":156:0:156:10|Input port bits 24 to 20 of CORETSEo1Oo[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_store.v":181:0:181:10|Input port bit 31 of CORETSEOllo[31:0] is unused
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_sincnf.v":44:0:44:10|Input port bits 30 to 12 of CORETSEOllo[30:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_sadd.v":54:0:54:10|Input port bits 30 to 12 of CORETSEOllo[30:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_sinchd.v":44:0:44:10|Input port bits 30 to 12 of CORETSEOllo[30:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_sinc.v":44:0:44:10|Input port bits 30 to 12 of CORETSEOllo[30:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_ladd.v":54:0:54:10|Input port bits 30 to 24 of CORETSEOllo[30:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_linc.v":44:0:44:10|Input port bits 30 to 18 of CORETSEOllo[30:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_cntrl.v":51:0:51:8|Input port bit 22 of CORETSEoo[30:0] is unused
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_cntrl.v":51:0:51:8|Input port bits 17 to 16 of CORETSEoo[30:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_cntrl.v":62:0:62:10|Input port bits 31 to 30 of CORETSEoIoI[51:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_cntrl.v":62:0:62:10|Input port bits 23 to 21 of CORETSEoIoI[51:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL157 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\tsmac_ahb_top.v":282:0:282:11|*Output CORETSEII1lI has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\tsmac_ahb_top.v":284:0:284:11|*Output CORETSElI1lI has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\tsmac_ahb_top.v":286:0:286:11|*Output CORETSEoI1lI has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\tsmac_ahb_top.v":288:0:288:11|*Output CORETSEiI1lI has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\tsmac_ahb_top.v":290:0:290:11|*Output CORETSEOl1lI has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\permc_top.v":98:0:98:8|Input port bit 0 of CORETSEiI[1:0] is unused
@W: CL138 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perfn_top.v":3490:0:3490:5|Removing register 'CORETSEOo' because it is only assigned 0 or its original value.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perfn_top.v":147:0:147:8|Input port bits 1 to 0 of CORETSEil[7:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petfn_top.v":219:0:219:10|Input port bits 1 to 0 of CORETSEil1I[6:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petfn_top.v":221:0:221:10|Input port bits 1 to 0 of CORETSEO01I[6:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petfn_top.v":223:0:223:10|Input port bits 1 to 0 of CORETSEI01I[6:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petfn_top.v":231:0:231:10|Input port bits 9 to 6 of CORETSEl01I[9:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petmc_top.v":113:0:113:8|Input port bit 0 of CORETSEiI[1:0] is unused
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxrfif_sys.v":239:0:239:10|Input port bits 39 to 36 of CORETSEoIii[39:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxrfif_fab.v":128:0:128:10|Input port bit 12 of CORETSEiIii[13:0] is unused
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\slave.v":74:0:74:5|Input port bit 0 of HTRANS[1:0] is unused
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\dmarx.v":95:0:95:5|Input port bits 1 to 0 of HRDATA[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL177 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v":69:28:69:32|Input port bits 31 to 20 of HADDR[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":64:26:64:34|Input port bits 15 to 13 of writeAddr[15:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":65:26:65:33|Input port bits 15 to 13 of readAddr[15:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":65:26:65:33|Input port bits 8 to 0 of readAddr[15:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":78:29:78:40|Input port bits 19 to 18 of ahbsram_addr[19:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL156 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":118:31:118:42|*Input l_BUSY_all_3 to expression [or] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":120:15:120:23|Input port bit 0 of HTRANS_M0[1:0] is unused
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":131:15:131:23|Input port bit 0 of HTRANS_M1[1:0] is unused
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":142:15:142:23|Input port bit 0 of HTRANS_M2[1:0] is unused
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":153:15:153:23|Input port bit 0 of HTRANS_M3[1:0] is unused
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":163:15:163:22|Input port bit 1 of HRESP_S0[1:0] is unused
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":176:15:176:22|Input port bit 1 of HRESP_S1[1:0] is unused
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":189:15:189:22|Input port bit 1 of HRESP_S2[1:0] is unused
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":202:15:202:22|Input port bit 1 of HRESP_S3[1:0] is unused
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":215:15:215:22|Input port bit 1 of HRESP_S4[1:0] is unused
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":228:15:228:22|Input port bit 1 of HRESP_S5[1:0] is unused
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":241:15:241:22|Input port bit 1 of HRESP_S6[1:0] is unused
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":254:15:254:22|Input port bit 1 of HRESP_S7[1:0] is unused
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":267:15:267:22|Input port bit 1 of HRESP_S8[1:0] is unused
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":280:15:280:22|Input port bit 1 of HRESP_S9[1:0] is unused
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":293:15:293:23|Input port bit 1 of HRESP_S10[1:0] is unused
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":306:15:306:23|Input port bit 1 of HRESP_S11[1:0] is unused
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":319:15:319:23|Input port bit 1 of HRESP_S12[1:0] is unused
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":332:15:332:23|Input port bit 1 of HRESP_S13[1:0] is unused
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":345:15:345:23|Input port bit 1 of HRESP_S14[1:0] is unused
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":358:15:358:23|Input port bit 1 of HRESP_S15[1:0] is unused
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":371:15:371:23|Input port bit 1 of HRESP_S16[1:0] is unused
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":42:16:42:25|Input port bits 16 to 6 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":42:16:42:25|Input port bits 4 to 3 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":42:16:42:25|Input port bits 1 to 0 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:21|Input port bits 16 to 6 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:21|Input port bits 4 to 3 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:21|Input port bits 1 to 0 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":42:16:42:25|Input port bits 16 to 6 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":42:16:42:25|Input port bit 4 of SDATAREADY[16:0] is unused
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":42:16:42:25|Input port bits 2 to 0 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:21|Input port bits 16 to 6 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:21|Input port bit 4 of SHRESP[16:0] is unused
@W: CL246 :"D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:21|Input port bits 2 to 0 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size.

