// REVISION    : $Revision: 1.1 $
//         Mentor Graphics Corporation Proprietary and Confidential
//         Copyright Mentor Graphics Corporation and Licensors 2004
`timescale 1ps/1ps
module
CoreTSE_M2S090_CORETSE_AHB_0_ARFQUE
(
CORETSEoIilI
,
CORETSEiIilI
,
CORETSElI1i
,
CORETSEoO1i
,
CORETSEiO1i
,
CORETSEOI1i
,
CORETSEII1i
,
CORETSEOlilI
,
CORETSEoi0i
,
CORETSEIlilI
,
CORETSEllilI
,
CORETSEolilI
,
CORETSEililI
,
CORETSEO0ilI
)
;
input
CORETSEoIilI
;
input
CORETSEiIilI
;
input
CORETSElI1i
;
input
[
31
:
0
]
CORETSEoO1i
;
input
CORETSEiO1i
;
input
CORETSEOI1i
;
input
[
1
:
0
]
CORETSEII1i
;
input
CORETSEOlilI
;
output
CORETSEoi0i
;
output
CORETSEIlilI
;
output
[
31
:
0
]
CORETSEllilI
;
output
CORETSEolilI
;
output
CORETSEililI
;
output
[
1
:
0
]
CORETSEO0ilI
;
parameter
CORETSEOII
=
1
;
parameter
FAMILY
=
19
;
reg
[
35
:
0
]
CORETSEI0ilI
;
reg
[
35
:
0
]
CORETSEl0ilI
;
reg
[
1
:
0
]
CORETSEo0ilI
;
wire
CORETSElo1
;
wire
CORETSEoo1
;
assign
CORETSElo1
=
(
FAMILY
==
25
)
?
1
'b
0
:
CORETSEiIilI
;
assign
CORETSEoo1
=
(
FAMILY
==
25
)
?
CORETSEiIilI
:
1
'b
0
;
always
@
(
posedge
CORETSEoIilI
or
negedge
CORETSElo1
)
begin
if
(
~
(
CORETSElo1
||
CORETSEoo1
)
)
CORETSEI0ilI
<=
#
CORETSEOII
36
'h
0
;
else
if
(
CORETSElI1i
&
CORETSEoi0i
)
CORETSEI0ilI
<=
#
CORETSEOII
{
CORETSEiO1i
,
CORETSEOI1i
,
CORETSEII1i
,
CORETSEoO1i
}
;
end
always
@
(
posedge
CORETSEoIilI
or
negedge
CORETSElo1
)
begin
if
(
~
(
CORETSElo1
||
CORETSEoo1
)
)
CORETSEo0ilI
[
0
]
<=
#
CORETSEOII
1
'b
0
;
else
if
(
(
CORETSElI1i
&
CORETSEoi0i
)
&
~
(
CORETSEIlilI
&
CORETSEOlilI
)
&
CORETSEo0ilI
[
1
]
)
CORETSEo0ilI
[
0
]
<=
#
CORETSEOII
1
'b
1
;
else
if
(
~
(
CORETSElI1i
&
CORETSEoi0i
)
&
(
CORETSEIlilI
&
CORETSEOlilI
)
)
CORETSEo0ilI
[
0
]
<=
#
CORETSEOII
1
'b
0
;
end
always
@
(
posedge
CORETSEoIilI
or
negedge
CORETSElo1
)
begin
if
(
~
(
CORETSElo1
||
CORETSEoo1
)
)
CORETSEl0ilI
<=
#
CORETSEOII
36
'h
0
;
else
if
(
(
CORETSEIlilI
&
CORETSEOlilI
)
&
CORETSEo0ilI
[
0
]
)
CORETSEl0ilI
<=
#
CORETSEOII
CORETSEI0ilI
;
else
if
(
(
CORETSEIlilI
&
CORETSEOlilI
)
&
~
CORETSEo0ilI
[
0
]
)
CORETSEl0ilI
<=
#
CORETSEOII
{
CORETSEiO1i
,
CORETSEOI1i
,
CORETSEII1i
,
CORETSEoO1i
}
;
else
if
(
~
CORETSEo0ilI
[
1
]
&
CORETSEo0ilI
[
0
]
)
CORETSEl0ilI
<=
#
CORETSEOII
CORETSEI0ilI
;
else
if
(
~
CORETSEo0ilI
[
1
]
&
~
CORETSEo0ilI
[
0
]
)
CORETSEl0ilI
<=
#
CORETSEOII
{
CORETSEiO1i
,
CORETSEOI1i
,
CORETSEII1i
,
CORETSEoO1i
}
;
end
always
@
(
posedge
CORETSEoIilI
or
negedge
CORETSElo1
)
begin
if
(
~
(
CORETSElo1
||
CORETSEoo1
)
)
CORETSEo0ilI
[
1
]
<=
#
CORETSEOII
1
'b
0
;
else
if
(
CORETSEo0ilI
[
0
]
|
(
(
CORETSElI1i
&
CORETSEoi0i
)
&
~
(
CORETSEIlilI
&
CORETSEOlilI
)
)
)
CORETSEo0ilI
[
1
]
<=
#
CORETSEOII
1
'b
1
;
else
if
(
(
~
(
CORETSElI1i
&
CORETSEoi0i
)
&
(
CORETSEIlilI
&
CORETSEOlilI
)
)
)
CORETSEo0ilI
[
1
]
<=
#
CORETSEOII
1
'b
0
;
end
assign
{
CORETSEolilI
,
CORETSEililI
,
CORETSEO0ilI
,
CORETSEllilI
}
=
CORETSEl0ilI
;
assign
CORETSEIlilI
=
CORETSEo0ilI
[
1
]
;
assign
CORETSEoi0i
=
~
CORETSEo0ilI
[
0
]
;
endmodule
