// REVISION    : $Revision: 1.1 $
// Mentor Graphics Corporation Proprietary and Confidential
// Copyright 2007 Mentor Graphics Corporation and Licensors
`timescale 1ps/1ps
module
CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_CNVTXI
(
CORETSEIl0II
,
CORETSEIli0
,
CORETSEli0II
,
CORETSEOloI
,
CORETSEIIII
,
CORETSEoIII
,
CORETSElIoII
,
CORETSEoIoII
,
CORETSEiIoII
,
CORETSEOloII
,
CORETSEIloII
,
CORETSElloII
)
;
parameter
FAMILY
=
19
;
input
CORETSEIl0II
;
input
CORETSEIli0
;
input
[
1
:
0
]
CORETSEli0II
;
input
[
7
:
0
]
CORETSEOloI
;
input
CORETSEIIII
;
input
CORETSEoIII
;
input
[
2
:
0
]
CORETSElIoII
;
output
[
7
:
0
]
CORETSEoIoII
;
output
CORETSEiIoII
;
output
CORETSEOloII
;
output
CORETSEIloII
;
output
[
2
:
0
]
CORETSElloII
;
`define CORETSEOII  \
# \
1
reg
[
7
:
0
]
CORETSEoloII
;
reg
[
3
:
0
]
CORETSEiloII
;
reg
[
3
:
0
]
CORETSEO0oII
;
reg
[
2
:
0
]
CORETSEI0oII
;
reg
[
1
:
0
]
CORETSEl0oII
;
reg
[
3
:
0
]
CORETSEo0oII
;
wire
[
9
:
0
]
CORETSEi0oII
;
wire
[
2
:
0
]
CORETSEO1oII
;
reg
[
9
:
0
]
CORETSEI1oII
;
reg
[
9
:
0
]
CORETSEl1oII
;
reg
[
9
:
0
]
CORETSEo1oII
;
reg
[
9
:
0
]
CORETSEi1oII
;
reg
[
9
:
0
]
CORETSEOooII
;
reg
[
9
:
0
]
CORETSEIooII
;
reg
[
9
:
0
]
CORETSElooII
;
reg
[
9
:
0
]
CORETSEoooII
;
wire
[
9
:
0
]
CORETSEli1II
;
reg
[
2
:
0
]
CORETSElloII
;
wire
CORETSEiooII
;
wire
CORETSEOioII
;
reg
CORETSEIloII
;
reg
[
2
:
0
]
CORETSEIioII
;
wire
CORETSElo1
;
wire
CORETSEoo1
;
assign
CORETSElo1
=
(
FAMILY
==
25
)
?
1
'b
0
:
CORETSEIl0II
;
assign
CORETSEoo1
=
(
FAMILY
==
25
)
?
CORETSEIl0II
:
1
'b
0
;
always
@
(
posedge
CORETSEIli0
or
posedge
CORETSElo1
)
begin
if
(
CORETSEoo1
||
CORETSElo1
)
CORETSEoloII
<=
`CORETSEOII
8
'h
00
;
else
CORETSEoloII
<=
`CORETSEOII
CORETSEOloI
;
end
always
@
(
posedge
CORETSEIli0
or
posedge
CORETSElo1
)
begin
if
(
CORETSEoo1
||
CORETSElo1
)
CORETSEiloII
<=
`CORETSEOII
4
'h
0
;
else
CORETSEiloII
<=
`CORETSEOII
CORETSEoloII
[
3
:
0
]
;
end
always
@
(
posedge
CORETSEIli0
or
posedge
CORETSElo1
)
begin
if
(
CORETSEoo1
||
CORETSElo1
)
CORETSEO0oII
<=
`CORETSEOII
4
'h
0
;
else
CORETSEO0oII
<=
`CORETSEOII
CORETSEiloII
;
end
always
@
(
posedge
CORETSEIli0
or
posedge
CORETSElo1
)
begin
if
(
CORETSEoo1
||
CORETSElo1
)
CORETSEI0oII
<=
`CORETSEOII
3
'h
0
;
else
CORETSEI0oII
<=
`CORETSEOII
{
CORETSEI0oII
[
1
:
0
]
,
CORETSEIIII
}
;
end
always
@
(
posedge
CORETSEIli0
or
posedge
CORETSElo1
)
begin
if
(
CORETSEoo1
||
CORETSElo1
)
CORETSEl0oII
<=
`CORETSEOII
2
'h
0
;
else
CORETSEl0oII
<=
`CORETSEOII
{
CORETSEl0oII
[
0
]
,
CORETSEoIII
}
;
end
always
@
(
posedge
CORETSEIli0
or
posedge
CORETSElo1
)
begin
if
(
CORETSEoo1
||
CORETSElo1
)
CORETSEo0oII
<=
`CORETSEOII
4
'h
0
;
else
if
(
~
(
~
CORETSEI0oII
[
1
]
&
CORETSEI0oII
[
0
]
&
CORETSEo0oII
[
0
]
&
(
CORETSEli0II
!=
2
'b
10
)
)
)
CORETSEo0oII
<=
`CORETSEOII
CORETSEo0oII
+
4
'h
1
;
end
assign
CORETSEi0oII
=
(
{
10
{
CORETSEli0II
==
2
'b
10
}
}
&
{
CORETSEl0oII
[
0
]
,
CORETSEI0oII
[
0
]
,
CORETSEoloII
}
)
|
(
{
10
{
(
CORETSEli0II
!=
2
'b
10
)
&
CORETSEo0oII
[
0
]
}
}
&
{
(
CORETSEl0oII
[
1
]
|
CORETSEl0oII
[
0
]
)
,
(
CORETSEI0oII
[
1
]
|
CORETSEI0oII
[
0
]
)
,
CORETSEoloII
[
3
:
0
]
,
CORETSEiloII
[
3
:
0
]
}
)
;
assign
CORETSEO1oII
=
(
{
3
{
(
CORETSEli0II
==
2
'b
10
)
}
}
&
CORETSEo0oII
[
2
:
0
]
)
|
(
{
3
{
(
CORETSEli0II
!=
2
'b
10
)
}
}
&
CORETSEo0oII
[
3
:
1
]
)
;
always
@
(
posedge
CORETSEIli0
or
posedge
CORETSElo1
)
begin
if
(
CORETSEoo1
||
CORETSElo1
)
begin
CORETSEI1oII
<=
`CORETSEOII
10
'h
000
;
CORETSEl1oII
<=
`CORETSEOII
10
'h
000
;
CORETSEo1oII
<=
`CORETSEOII
10
'h
000
;
CORETSEi1oII
<=
`CORETSEOII
10
'h
000
;
CORETSEOooII
<=
`CORETSEOII
10
'h
000
;
CORETSEIooII
<=
`CORETSEOII
10
'h
000
;
CORETSElooII
<=
`CORETSEOII
10
'h
000
;
CORETSEoooII
<=
`CORETSEOII
10
'h
000
;
end
else
case
(
CORETSEO1oII
)
3
'h
0
:
CORETSEI1oII
<=
`CORETSEOII
CORETSEi0oII
;
3
'h
1
:
CORETSEl1oII
<=
`CORETSEOII
CORETSEi0oII
;
3
'h
2
:
CORETSEo1oII
<=
`CORETSEOII
CORETSEi0oII
;
3
'h
3
:
CORETSEi1oII
<=
`CORETSEOII
CORETSEi0oII
;
3
'h
4
:
CORETSEOooII
<=
`CORETSEOII
CORETSEi0oII
;
3
'h
5
:
CORETSEIooII
<=
`CORETSEOII
CORETSEi0oII
;
3
'h
6
:
CORETSElooII
<=
`CORETSEOII
CORETSEi0oII
;
3
'h
7
:
CORETSEoooII
<=
`CORETSEOII
CORETSEi0oII
;
default
:
CORETSEI1oII
<=
`CORETSEOII
CORETSEi0oII
;
endcase
end
assign
CORETSEiooII
=
(
(
(
CORETSEli0II
==
2
'b
10
)
&
(
CORETSEI0oII
[
0
]
==
1
'b
1
)
)
|
(
(
CORETSEli0II
!=
2
'b
10
)
&
(
CORETSEI0oII
[
1
]
==
1
'b
1
)
)
|
(
~
CORETSEIloII
&
~
(
|
CORETSEIioII
)
&
CORETSEo0oII
[
0
]
)
&
~
(
|
CORETSEI0oII
)
)
;
assign
CORETSEOioII
=
(
(
(
CORETSEli0II
==
2
'b
10
)
&
(
CORETSEI0oII
[
1
:
0
]
==
2
'b
10
)
)
|
(
(
CORETSEli0II
!=
2
'b
10
)
&
(
CORETSEI0oII
[
2
:
1
]
==
2
'b
10
)
)
|
(
CORETSEIloII
&
CORETSEIioII
[
0
]
)
)
;
always
@
(
posedge
CORETSEIli0
or
posedge
CORETSElo1
)
begin
if
(
CORETSEoo1
||
CORETSElo1
)
CORETSEIloII
<=
`CORETSEOII
1
'b
0
;
else
if
(
CORETSEiooII
)
CORETSEIloII
<=
`CORETSEOII
1
'b
1
;
else
if
(
CORETSEOioII
)
CORETSEIloII
<=
`CORETSEOII
1
'b
0
;
end
always
@
(
posedge
CORETSEIli0
or
posedge
CORETSElo1
)
begin
if
(
CORETSEoo1
||
CORETSElo1
)
CORETSEIioII
<=
`CORETSEOII
3
'h
0
;
else
CORETSEIioII
<=
`CORETSEOII
{
CORETSEIioII
[
1
:
0
]
,
CORETSEIloII
}
;
end
always
@
(
posedge
CORETSEIli0
or
posedge
CORETSElo1
)
begin
if
(
CORETSEoo1
||
CORETSElo1
)
CORETSElloII
<=
`CORETSEOII
3
'h
0
;
else
if
(
~
CORETSEIloII
&
CORETSEiooII
&
(
CORETSEli0II
==
2
'b
10
)
)
CORETSElloII
<=
`CORETSEOII
CORETSEO1oII
;
else
if
(
~
CORETSEIloII
&
CORETSEiooII
&
(
CORETSEli0II
!=
2
'b
10
)
)
CORETSElloII
<=
`CORETSEOII
CORETSEO1oII
+
3
'h
5
;
end
assign
CORETSEli1II
=
{
10
{
(
CORETSElIoII
==
3
'h
0
)
}
}
&
CORETSEI1oII
|
{
10
{
(
CORETSElIoII
==
3
'h
1
)
}
}
&
CORETSEl1oII
|
{
10
{
(
CORETSElIoII
==
3
'h
2
)
}
}
&
CORETSEo1oII
|
{
10
{
(
CORETSElIoII
==
3
'h
3
)
}
}
&
CORETSEi1oII
|
{
10
{
(
CORETSElIoII
==
3
'h
4
)
}
}
&
CORETSEOooII
|
{
10
{
(
CORETSElIoII
==
3
'h
5
)
}
}
&
CORETSEIooII
|
{
10
{
(
CORETSElIoII
==
3
'h
6
)
}
}
&
CORETSElooII
|
{
10
{
(
CORETSElIoII
==
3
'h
7
)
}
}
&
CORETSEoooII
;
assign
CORETSEoIoII
=
CORETSEli1II
[
7
:
0
]
;
assign
CORETSEiIoII
=
CORETSEli1II
[
8
]
;
assign
CORETSEOloII
=
CORETSEli1II
[
9
]
;
endmodule
