//                        Proprietary and Confidential 
// REVISION    : $Revision: 1.8 $ 
module
CoreTSE_M2S090_CORETSE_AHB_0_SI_SAL
(
input
CORETSElIil,
input
CORETSEoIil,
input
[
6
:
0
]
CORETSEiIil,
input
CORETSEOlil,
input
CORETSEIlil,
input
CORETSEllil,
input
CORETSEolil,
input
CORETSEilil,
input
[
5
:
0
]
CORETSEO0il,
input
[
31
:
0
]
CORETSEI0il,
input
[
31
:
0
]
CORETSEl0il,
input
[
31
:
0
]
CORETSEo0il,
input
[
31
:
0
]
CORETSEi0il,
output
CORETSEO1il,
output
CORETSEI1il
)
;
parameter
FAMILY
=
19
;
wire
[
7
:
0
]
CORETSEl1il
;
wire
CORETSEo1il
;
reg
CORETSEi1il
;
wire
CORETSEOoil
;
reg
CORETSEIoil
;
reg
CORETSEloil
;
wire
CORETSEooil
;
wire
CORETSEioil
;
wire
CORETSEOiil
;
assign
CORETSEioil
=
(
FAMILY
==
25
)
?
1
'b
0
:
CORETSEoIil
;
assign
CORETSEOiil
=
(
FAMILY
==
25
)
?
CORETSEoIil
:
1
'b
0
;
assign
CORETSEO1il
=
CORETSEloil
;
assign
CORETSEl1il
=
{
8
{
~
CORETSEiIil
[
6
]
&
~
CORETSEiIil
[
5
]
&
~
CORETSEiIil
[
4
]
&
~
CORETSEiIil
[
3
]
}
}
&
CORETSEI0il
[
7
:
0
]
|
{
8
{
~
CORETSEiIil
[
6
]
&
~
CORETSEiIil
[
5
]
&
~
CORETSEiIil
[
4
]
&
CORETSEiIil
[
3
]
}
}
&
CORETSEI0il
[
15
:
8
]
|
{
8
{
~
CORETSEiIil
[
6
]
&
~
CORETSEiIil
[
5
]
&
CORETSEiIil
[
4
]
&
~
CORETSEiIil
[
3
]
}
}
&
CORETSEI0il
[
23
:
16
]
|
{
8
{
~
CORETSEiIil
[
6
]
&
~
CORETSEiIil
[
5
]
&
CORETSEiIil
[
4
]
&
CORETSEiIil
[
3
]
}
}
&
CORETSEI0il
[
31
:
24
]
|
{
8
{
~
CORETSEiIil
[
6
]
&
CORETSEiIil
[
5
]
&
~
CORETSEiIil
[
4
]
&
~
CORETSEiIil
[
3
]
}
}
&
CORETSEl0il
[
7
:
0
]
|
{
8
{
~
CORETSEiIil
[
6
]
&
CORETSEiIil
[
5
]
&
~
CORETSEiIil
[
4
]
&
CORETSEiIil
[
3
]
}
}
&
CORETSEl0il
[
15
:
8
]
|
{
8
{
~
CORETSEiIil
[
6
]
&
CORETSEiIil
[
5
]
&
CORETSEiIil
[
4
]
&
~
CORETSEiIil
[
3
]
}
}
&
CORETSEl0il
[
23
:
16
]
|
{
8
{
~
CORETSEiIil
[
6
]
&
CORETSEiIil
[
5
]
&
CORETSEiIil
[
4
]
&
CORETSEiIil
[
3
]
}
}
&
CORETSEl0il
[
31
:
24
]
|
{
8
{
CORETSEiIil
[
6
]
&
~
CORETSEiIil
[
5
]
&
~
CORETSEiIil
[
4
]
&
~
CORETSEiIil
[
3
]
}
}
&
CORETSEo0il
[
7
:
0
]
|
{
8
{
CORETSEiIil
[
6
]
&
~
CORETSEiIil
[
5
]
&
~
CORETSEiIil
[
4
]
&
CORETSEiIil
[
3
]
}
}
&
CORETSEo0il
[
15
:
8
]
|
{
8
{
CORETSEiIil
[
6
]
&
~
CORETSEiIil
[
5
]
&
CORETSEiIil
[
4
]
&
~
CORETSEiIil
[
3
]
}
}
&
CORETSEo0il
[
23
:
16
]
|
{
8
{
CORETSEiIil
[
6
]
&
~
CORETSEiIil
[
5
]
&
CORETSEiIil
[
4
]
&
CORETSEiIil
[
3
]
}
}
&
CORETSEo0il
[
31
:
24
]
|
{
8
{
CORETSEiIil
[
6
]
&
CORETSEiIil
[
5
]
&
~
CORETSEiIil
[
4
]
&
~
CORETSEiIil
[
3
]
}
}
&
CORETSEi0il
[
7
:
0
]
|
{
8
{
CORETSEiIil
[
6
]
&
CORETSEiIil
[
5
]
&
~
CORETSEiIil
[
4
]
&
CORETSEiIil
[
3
]
}
}
&
CORETSEi0il
[
15
:
8
]
|
{
8
{
CORETSEiIil
[
6
]
&
CORETSEiIil
[
5
]
&
CORETSEiIil
[
4
]
&
~
CORETSEiIil
[
3
]
}
}
&
CORETSEi0il
[
23
:
16
]
|
{
8
{
CORETSEiIil
[
6
]
&
CORETSEiIil
[
5
]
&
CORETSEiIil
[
4
]
&
CORETSEiIil
[
3
]
}
}
&
CORETSEi0il
[
31
:
24
]
;
assign
CORETSEo1il
=
(
(
~
CORETSEiIil
[
2
]
&
~
CORETSEiIil
[
1
]
&
~
CORETSEiIil
[
0
]
)
&
CORETSEl1il
[
0
]
)
|
(
(
~
CORETSEiIil
[
2
]
&
~
CORETSEiIil
[
1
]
&
CORETSEiIil
[
0
]
)
&
CORETSEl1il
[
1
]
)
|
(
(
~
CORETSEiIil
[
2
]
&
CORETSEiIil
[
1
]
&
~
CORETSEiIil
[
0
]
)
&
CORETSEl1il
[
2
]
)
|
(
(
~
CORETSEiIil
[
2
]
&
CORETSEiIil
[
1
]
&
CORETSEiIil
[
0
]
)
&
CORETSEl1il
[
3
]
)
|
(
(
CORETSEiIil
[
2
]
&
~
CORETSEiIil
[
1
]
&
~
CORETSEiIil
[
0
]
)
&
CORETSEl1il
[
4
]
)
|
(
(
CORETSEiIil
[
2
]
&
~
CORETSEiIil
[
1
]
&
CORETSEiIil
[
0
]
)
&
CORETSEl1il
[
5
]
)
|
(
(
CORETSEiIil
[
2
]
&
CORETSEiIil
[
1
]
&
~
CORETSEiIil
[
0
]
)
&
CORETSEl1il
[
6
]
)
|
(
(
CORETSEiIil
[
2
]
&
CORETSEiIil
[
1
]
&
CORETSEiIil
[
0
]
)
&
CORETSEl1il
[
7
]
)
;
always
@
(
posedge
CORETSElIil
or
negedge
CORETSEioil
)
begin
if
(
!
(
CORETSEioil
||
CORETSEOiil
)
)
CORETSEi1il
<=
1
'b
0
;
else
if
(
CORETSEOlil
)
CORETSEi1il
<=
CORETSEo1il
;
else
CORETSEi1il
<=
CORETSEi1il
;
end
assign
CORETSEIiil
=
(
CORETSEO0il
[
0
]
&
CORETSEolil
)
|
(
CORETSEO0il
[
1
]
&
CORETSEllil
)
|
(
CORETSEO0il
[
2
]
&
CORETSEIlil
)
|
(
CORETSEO0il
[
3
]
)
|
(
CORETSEO0il
[
4
]
&
CORETSEi1il
&
!
CORETSEllil
&
!
CORETSEolil
)
|
(
CORETSEO0il
[
5
]
&
CORETSEi1il
&
CORETSEllil
&
!
CORETSEolil
)
;
always
@
(
posedge
CORETSElIil
or
negedge
CORETSEioil
)
begin
if
(
!
(
CORETSEioil
||
CORETSEOiil
)
)
begin
CORETSEIoil
<=
1
'b
0
;
CORETSEloil
<=
1
'b
0
;
end
else
begin
CORETSEIoil
<=
CORETSEOoil
;
CORETSEloil
<=
CORETSEooil
;
end
end
assign
CORETSEOoil
=
~
CORETSEIiil
;
assign
CORETSEI1il
=
CORETSEIoil
;
assign
CORETSEooil
=
CORETSEilil
&
CORETSEIoil
|
~
CORETSEilil
&
CORETSEloil
;
endmodule
