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<doc>
<title>Timing Report Min Delay Analysis
</title>
<text>SmartTime Version 11.8.0.26</text>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.8 (Version 11.8.0.26)</text>
<text>Date: Tue Mar 14 15:47:18 2017
</text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>CoreTSE_M2S090</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2S090TS</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>484 FBGA</cell>
</row>
<row>
 <cell>Temperature Range</cell>
 <cell>0 - 85 C</cell>
</row>
<row>
 <cell>Voltage Range</cell>
 <cell>1.14 - 1.26 V</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Design State</cell>
 <cell>Post-Layout</cell>
</row>
<row>
 <cell>Data source</cell>
 <cell>Production</cell>
</row>
<row>
 <cell>Min Operating Conditions</cell>
 <cell>BEST - 1.26 V - 0 C</cell>
</row>
<row>
 <cell>Max Operating Conditions</cell>
 <cell>WORST - 1.14 V - 85 C</cell>
</row>
<row>
 <cell>Scenario for Timing Analysis</cell>
 <cell>timing_analysis</cell>
</row>
</table>
<text></text>
<section>
<name>Summary</name>
<table>
<header>
 <cell>Clock Domain</cell>
 <cell>Period (ns)</cell>
 <cell>Frequency (MHz)</cell>
 <cell>Required Period (ns)</cell>
 <cell>Required Frequency (MHz)</cell>
 <cell>External Setup (ns)</cell>
 <cell>External Hold (ns)</cell>
 <cell>Min Clock-To-Out (ns)</cell>
 <cell>Max Clock-To-Out (ns)</cell>
</header>
<row>
 <cell>CLK1_PAD</cell>
 <cell>1.600</cell>
 <cell>625.000</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEI110:Q</cell>
 <cell>6.901</cell>
 <cell>144.907</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>FCCC_0/GL0</cell>
 <cell>13.814</cell>
 <cell>72.390</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>3.946</cell>
 <cell>-1.871</cell>
 <cell>6.477</cell>
 <cell>14.949</cell>
</row>
<row>
 <cell>FCCC_1/GL0</cell>
 <cell>7.312</cell>
 <cell>136.761</cell>
 <cell>8.000</cell>
 <cell>125.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>FCCC_2/GL0</cell>
 <cell>4.820</cell>
 <cell>207.469</cell>
 <cell>8.000</cell>
 <cell>125.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>8.401</cell>
 <cell>13.654</cell>
</row>
<row>
 <cell>FCCC_3/GL0</cell>
 <cell>2.538</cell>
 <cell>394.011</cell>
 <cell>8.000</cell>
 <cell>125.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ/CLKOUT</cell>
 <cell>3.249</cell>
 <cell>307.787</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB</cell>
 <cell>19.636</cell>
 <cell>50.927</cell>
 <cell>80.000</cell>
 <cell>12.500</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1]</cell>
 <cell>1.818</cell>
 <cell>550.055</cell>
 <cell>8.000</cell>
 <cell>125.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]</cell>
 <cell>1.142</cell>
 <cell>875.657</cell>
 <cell>8.000</cell>
 <cell>125.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>FCCC_3/GL1</cell>
 <cell>2.538</cell>
 <cell>394.011</cell>
 <cell>8.000</cell>
 <cell>125.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
<text></text>
<table>
<header>
 <cell></cell>
 <cell>Min Delay (ns)</cell>
 <cell>Max Delay (ns)</cell>
</header>
<row>
 <cell>Input to Output</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
</section>
<section>
<name>Clock Domain CLK1_PAD</name>
<text>Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin FCCC_0/CLK1_PAD_INST/U_IOPAD:PAD</text>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEI110:Q</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiOi0/CORETSEOloo[6]:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiOi0/CORETSEiI[1]:D</cell>
 <cell>0.325</cell>
 <cell></cell>
 <cell>2.799</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiOi0/CORETSEIIoo[4]:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiOi0/CORETSEIIoo[4]:D</cell>
 <cell>0.318</cell>
 <cell></cell>
 <cell>2.796</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiOi0/CORETSEoOoo[1]:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiOi0/CORETSEoOoo[2]:D</cell>
 <cell>0.331</cell>
 <cell></cell>
 <cell>2.809</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiOi0/CORETSEOloo[5]:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiOi0/CORETSEi1o0[5]:D</cell>
 <cell>0.339</cell>
 <cell></cell>
 <cell>2.814</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiOi0/CORETSEOloo[5]:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiOi0/CORETSEiOOI:D</cell>
 <cell>0.340</cell>
 <cell></cell>
 <cell>2.815</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiOi0/CORETSEOloo[6]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiOi0/CORETSEiI[1]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.799</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEI110:Q</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEI110:Q</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEI110_inferred_clock_RNICOHA:An</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEI110</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.254</cell>
 <cell>1.254</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEI110_inferred_clock_RNICOHA:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.249</cell>
 <cell>1.503</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEI110_inferred_clock_RNICOHA/U0_RGB1_RGB4:An</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEI110_inferred_clock_RNICOHA/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.403</cell>
 <cell>1.906</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEI110_inferred_clock_RNICOHA/U0_RGB1_RGB4:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.212</cell>
 <cell>2.118</cell>
 <cell>10</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiOi0/CORETSEOloo[6]:CLK</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEI110_inferred_clock_RNICOHA/U0_RGB1_RGB4_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.356</cell>
 <cell>2.474</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiOi0/CORETSEOloo[6]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.058</cell>
 <cell>2.532</cell>
 <cell>6</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiOi0/CORETSEiI[1]:D</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSEiOi0/CORETSEOloo[6]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.267</cell>
 <cell>2.799</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.799</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEI110:Q</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEI110:Q</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEI110_inferred_clock_RNICOHA:An</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEI110</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.254</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEI110_inferred_clock_RNICOHA:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.249</cell>
 <cell>N/C</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEI110_inferred_clock_RNICOHA/U0_RGB1_RGB4:An</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEI110_inferred_clock_RNICOHA/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.403</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEI110_inferred_clock_RNICOHA/U0_RGB1_RGB4:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.212</cell>
 <cell>N/C</cell>
 <cell>10</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiOi0/CORETSEiI[1]:CLK</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEI110_inferred_clock_RNICOHA/U0_RGB1_RGB4_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.367</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiOi0/CORETSEiI[1]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain FCCC_0/GL0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CoreResetP_0/release_sdif3_core_q1:CLK</cell>
 <cell>CoreResetP_0/release_sdif3_core_clk_base:D</cell>
 <cell>0.315</cell>
 <cell>0.295</cell>
 <cell>3.657</cell>
 <cell>3.362</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CoreResetP_0/sdif0_areset_n_q1:CLK</cell>
 <cell>CoreResetP_0/sm0_areset_n_clk_base:D</cell>
 <cell>0.310</cell>
 <cell>0.298</cell>
 <cell>3.631</cell>
 <cell>3.333</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEoiolI.CORETSEIOilI/CORETSEo1l0.CORETSEOol0/CORETSEoOl0.CORETSEOiI0[0]:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEoiolI.CORETSEIOilI/CORETSEo1l0.CORETSEOol0/CORETSEoOl0.CORETSEIiI0[0]:D</cell>
 <cell>0.319</cell>
 <cell>0.300</cell>
 <cell>3.643</cell>
 <cell>3.343</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEi0o0I/CORETSEO0o0I/CORETSEii1lI[0]:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEi0o0I/CORETSEO0o0I/CORETSEii1lI[1]:D</cell>
 <cell>0.319</cell>
 <cell>0.301</cell>
 <cell>3.649</cell>
 <cell>3.348</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEiii1:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEo110:D</cell>
 <cell>0.315</cell>
 <cell>0.304</cell>
 <cell>3.642</cell>
 <cell>3.338</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CoreResetP_0/release_sdif3_core_q1:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CoreResetP_0/release_sdif3_core_clk_base:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.657</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.362</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.295</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.107</cell>
 <cell>2.107</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.133</cell>
 <cell>2.240</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.118</cell>
 <cell>2.358</cell>
 <cell>33</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB30:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.414</cell>
 <cell>2.772</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB30:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.212</cell>
 <cell>2.984</cell>
 <cell>17</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/release_sdif3_core_q1:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB30_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.358</cell>
 <cell>3.342</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/release_sdif3_core_q1:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.058</cell>
 <cell>3.400</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/release_sdif3_core_clk_base:D</cell>
 <cell>net</cell>
 <cell>CoreResetP_0/release_sdif3_core_q1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.257</cell>
 <cell>3.657</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.657</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.107</cell>
 <cell>2.107</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.133</cell>
 <cell>2.240</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.118</cell>
 <cell>2.358</cell>
 <cell>33</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB30:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.414</cell>
 <cell>2.772</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB30:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.212</cell>
 <cell>2.984</cell>
 <cell>17</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/release_sdif3_core_clk_base:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB30_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.378</cell>
 <cell>3.362</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/release_sdif3_core_clk_base:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.362</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.362</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
 <cell>External Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>PHY_MDIO</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEOii1[0]:D</cell>
 <cell>5.297</cell>
 <cell></cell>
 <cell>5.297</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>-1.871</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: PHY_MDIO</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEOii1[0]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.297</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PHY_MDIO</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>BIBUF_0/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>PHY_MDIO</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>BIBUF_0/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_BI</cell>
 <cell>+</cell>
 <cell>1.542</cell>
 <cell>1.542</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>BIBUF_0/U0/U_IOINFF:A</cell>
 <cell>net</cell>
 <cell>BIBUF_0/U0/YIN1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.003</cell>
 <cell>1.545</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>BIBUF_0/U0/U_IOINFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOINFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.056</cell>
 <cell>1.601</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiOi0/CORETSEoo10_0_a3_1:A</cell>
 <cell>net</cell>
 <cell>BIBUF_0_Y</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.072</cell>
 <cell>3.673</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiOi0/CORETSEoo10_0_a3_1:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2</cell>
 <cell>+</cell>
 <cell>0.113</cell>
 <cell>3.786</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEioi1[0]:B</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/N_401</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.326</cell>
 <cell>5.112</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEioi1[0]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.135</cell>
 <cell>5.247</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEOii1[0]:D</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEioi1[0]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.050</cell>
 <cell>5.297</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.297</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.171</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.137</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.122</cell>
 <cell>N/C</cell>
 <cell>33</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB19:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.417</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB19:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.218</cell>
 <cell>N/C</cell>
 <cell>88</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEOii1[0]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB19_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.361</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEOII1/CORETSEOii1[0]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Clock to Output</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Clock to Out (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CoreTSE_M2S090_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>MMUART_1_TXD</cell>
 <cell>3.021</cell>
 <cell></cell>
 <cell>6.477</cell>
 <cell></cell>
 <cell>6.477</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CoreTSE_M2S090_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>SPI_0_DO</cell>
 <cell>3.622</cell>
 <cell></cell>
 <cell>7.078</cell>
 <cell></cell>
 <cell>7.078</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEi0o0I/CORETSEilo0I/CORETSEI0l0I[4]:CLK</cell>
 <cell>TSM_INTR</cell>
 <cell>3.757</cell>
 <cell></cell>
 <cell>7.085</cell>
 <cell></cell>
 <cell>7.085</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEi0o0I/CORETSEilo0I/CORETSEI0l0I[7]:CLK</cell>
 <cell>TSM_INTR</cell>
 <cell>3.961</cell>
 <cell></cell>
 <cell>7.289</cell>
 <cell></cell>
 <cell>7.289</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEi0o0I/CORETSEilo0I/CORETSEI0l0I[3]:CLK</cell>
 <cell>TSM_INTR</cell>
 <cell>4.199</cell>
 <cell></cell>
 <cell>7.520</cell>
 <cell></cell>
 <cell>7.520</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CoreTSE_M2S090_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MMUART_1_TXD</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.477</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.107</cell>
 <cell>2.107</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.133</cell>
 <cell>2.240</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.118</cell>
 <cell>2.358</cell>
 <cell>33</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.412</cell>
 <cell>2.770</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.212</cell>
 <cell>2.982</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreTSE_M2S090_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.273</cell>
 <cell>3.255</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreTSE_M2S090_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.140</cell>
 <cell>3.395</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreTSE_M2S090_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>CoreTSE_M2S090_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.061</cell>
 <cell>3.456</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreTSE_M2S090_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MSS_075_IP</cell>
 <cell>+</cell>
 <cell>1.345</cell>
 <cell>4.801</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreTSE_M2S090_MSS_0/MMUART_1_TXD_PAD/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>CoreTSE_M2S090_MSS_0/MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.077</cell>
 <cell>4.878</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreTSE_M2S090_MSS_0/MMUART_1_TXD_PAD/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>1.599</cell>
 <cell>6.477</cell>
 <cell>0</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MMUART_1_TXD</cell>
 <cell>net</cell>
 <cell>MMUART_1_TXD</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>6.477</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.477</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.107</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MMUART_1_TXD</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CoreResetP_0/sm0_areset_n_clk_base:CLK</cell>
 <cell>CoreResetP_0/release_sdif3_core_clk_base:ALn</cell>
 <cell>0.680</cell>
 <cell>0.640</cell>
 <cell>4.002</cell>
 <cell>3.362</cell>
 <cell>0.000</cell>
 <cell>-0.040</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CoreResetP_0/sm0_areset_n_clk_base:CLK</cell>
 <cell>CoreResetP_0/release_sdif2_core_clk_base:ALn</cell>
 <cell>0.680</cell>
 <cell>0.640</cell>
 <cell>4.002</cell>
 <cell>3.362</cell>
 <cell>0.000</cell>
 <cell>-0.040</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CoreResetP_0/sm0_areset_n_clk_base:CLK</cell>
 <cell>CoreResetP_0/SDIF_RELEASED_int:ALn</cell>
 <cell>0.680</cell>
 <cell>0.640</cell>
 <cell>4.002</cell>
 <cell>3.362</cell>
 <cell>0.000</cell>
 <cell>-0.040</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CoreResetP_0/sm0_areset_n_clk_base:CLK</cell>
 <cell>CoreResetP_0/sdif0_state[1]:ALn</cell>
 <cell>0.680</cell>
 <cell>0.640</cell>
 <cell>4.002</cell>
 <cell>3.362</cell>
 <cell>0.000</cell>
 <cell>-0.040</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CoreResetP_0/sm0_areset_n_clk_base:CLK</cell>
 <cell>CoreResetP_0/release_sdif2_core_q1:ALn</cell>
 <cell>0.680</cell>
 <cell>0.640</cell>
 <cell>4.002</cell>
 <cell>3.362</cell>
 <cell>0.000</cell>
 <cell>-0.040</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CoreResetP_0/sm0_areset_n_clk_base:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CoreResetP_0/release_sdif3_core_clk_base:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.002</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.362</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.640</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.107</cell>
 <cell>2.107</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.133</cell>
 <cell>2.240</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.118</cell>
 <cell>2.358</cell>
 <cell>33</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB29:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.413</cell>
 <cell>2.771</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB29:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.212</cell>
 <cell>2.983</cell>
 <cell>8</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/sm0_areset_n_clk_base:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB29_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.339</cell>
 <cell>3.322</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/sm0_areset_n_clk_base:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.058</cell>
 <cell>3.380</cell>
 <cell>29</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/release_sdif3_core_clk_base:ALn</cell>
 <cell>net</cell>
 <cell>CoreResetP_0/sm0_areset_n_clk_base_0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.622</cell>
 <cell>4.002</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.002</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.107</cell>
 <cell>2.107</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.133</cell>
 <cell>2.240</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.118</cell>
 <cell>2.358</cell>
 <cell>33</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB30:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.414</cell>
 <cell>2.772</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB30:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.212</cell>
 <cell>2.984</cell>
 <cell>17</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/release_sdif3_core_clk_base:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB30_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.378</cell>
 <cell>3.362</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/release_sdif3_core_clk_base:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.362</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.362</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET OSC_0/I_RCOSC_25_50MHZ/CLKOUT to FCCC_0/GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB to FCCC_0/GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_3/GL0 to FCCC_0/GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_3/GL1 to FCCC_0/GL0</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain FCCC_1/GL0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiio0/CORETSEllI[13]:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEiIiII/CORETSEiI1II[13]:D</cell>
 <cell>0.307</cell>
 <cell>0.290</cell>
 <cell>5.059</cell>
 <cell>4.769</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiio0/CORETSEi0li:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiio0/CORETSEO1li:D</cell>
 <cell>0.316</cell>
 <cell>0.297</cell>
 <cell>5.046</cell>
 <cell>4.749</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEoio0/CORETSEi1li[6]:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEoio0/CORETSEOoli[6]:D</cell>
 <cell>0.311</cell>
 <cell>0.300</cell>
 <cell>5.065</cell>
 <cell>4.765</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEoio0/CORETSEi1li[8]:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEoio0/CORETSEOoli[8]:D</cell>
 <cell>0.313</cell>
 <cell>0.300</cell>
 <cell>5.074</cell>
 <cell>4.774</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEiIiII/CORETSElOoII[2]:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEiIiII/CORETSEoOoII[2]:D</cell>
 <cell>0.313</cell>
 <cell>0.302</cell>
 <cell>5.069</cell>
 <cell>4.767</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiio0/CORETSEllI[13]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEiIiII/CORETSEiI1II[13]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.059</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>4.769</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.290</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.518</cell>
 <cell>3.518</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.132</cell>
 <cell>3.650</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.118</cell>
 <cell>3.768</cell>
 <cell>14</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB3:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.412</cell>
 <cell>4.180</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB3:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.212</cell>
 <cell>4.392</cell>
 <cell>61</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiio0/CORETSEllI[13]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB3_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.360</cell>
 <cell>4.752</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiio0/CORETSEllI[13]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.062</cell>
 <cell>4.814</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEiIiII/CORETSEiI1II[13]:D</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoi0II[13]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.245</cell>
 <cell>5.059</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.059</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.518</cell>
 <cell>3.518</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.132</cell>
 <cell>3.650</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.118</cell>
 <cell>3.768</cell>
 <cell>14</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB3:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.412</cell>
 <cell>4.180</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB3:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.212</cell>
 <cell>4.392</cell>
 <cell>61</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEiIiII/CORETSEiI1II[13]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB3_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.377</cell>
 <cell>4.769</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEiIiII/CORETSEiI1II[13]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>4.769</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.769</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElIi0/CORETSEo0OI[0]:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiio0/CORETSEi0io[8]:ALn</cell>
 <cell>2.506</cell>
 <cell>2.468</cell>
 <cell>7.237</cell>
 <cell>4.769</cell>
 <cell>0.000</cell>
 <cell>-0.038</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElIi0/CORETSEo0OI[0]:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEiIiII/CORETSEiI1II[13]:ALn</cell>
 <cell>2.506</cell>
 <cell>2.468</cell>
 <cell>7.237</cell>
 <cell>4.769</cell>
 <cell>0.000</cell>
 <cell>-0.038</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElIi0/CORETSEo0OI[0]:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEiIiII/CORETSEiI1II[14]:ALn</cell>
 <cell>2.506</cell>
 <cell>2.468</cell>
 <cell>7.237</cell>
 <cell>4.769</cell>
 <cell>0.000</cell>
 <cell>-0.038</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElIi0/CORETSEo0OI[0]:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiio0/CORETSEi0io[12]:ALn</cell>
 <cell>2.506</cell>
 <cell>2.468</cell>
 <cell>7.237</cell>
 <cell>4.769</cell>
 <cell>0.000</cell>
 <cell>-0.038</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElIi0/CORETSEo0OI[0]:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiio0/CORETSEIIol[11]:ALn</cell>
 <cell>2.498</cell>
 <cell>2.468</cell>
 <cell>7.229</cell>
 <cell>4.761</cell>
 <cell>0.000</cell>
 <cell>-0.030</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElIi0/CORETSEo0OI[0]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiio0/CORETSEi0io[8]:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.237</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>4.769</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.468</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.518</cell>
 <cell>3.518</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.132</cell>
 <cell>3.650</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.118</cell>
 <cell>3.768</cell>
 <cell>14</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB12:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.417</cell>
 <cell>4.185</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB12:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.212</cell>
 <cell>4.397</cell>
 <cell>32</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElIi0/CORETSEo0OI[0]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB12_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.334</cell>
 <cell>4.731</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElIi0/CORETSEo0OI[0]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.072</cell>
 <cell>4.803</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElIi0/CORETSEIOII:A</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSElIi0/CORETSEo0OI</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.397</cell>
 <cell>5.200</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElIi0/CORETSEIOII:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.058</cell>
 <cell>5.258</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElIi0/CORETSEIOII_RNI9N2A:An</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSElIi0/CORETSEIOII</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.749</cell>
 <cell>6.007</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElIi0/CORETSEIOII_RNI9N2A:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.257</cell>
 <cell>6.264</cell>
 <cell>14</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSElIi0/CORETSEIOII_RNI9N2A/U0_RGB1_RGB3:An</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSElIi0/CORETSEIOII_RNI9N2A/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.412</cell>
 <cell>6.676</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSElIi0/CORETSEIOII_RNI9N2A/U0_RGB1_RGB3:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.165</cell>
 <cell>6.841</cell>
 <cell>61</cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiio0/CORETSEi0io[8]:ALn</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSElIi0/CORETSEIOII_RNI9N2A/U0_RGB1_RGB3_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.396</cell>
 <cell>7.237</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.237</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.518</cell>
 <cell>3.518</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.132</cell>
 <cell>3.650</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.118</cell>
 <cell>3.768</cell>
 <cell>14</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB3:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.412</cell>
 <cell>4.180</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB3:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.212</cell>
 <cell>4.392</cell>
 <cell>61</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiio0/CORETSEi0io[8]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB3_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.377</cell>
 <cell>4.769</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiio0/CORETSEi0io[8]:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>4.769</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.769</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_0/GL0 to FCCC_1/GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] to FCCC_1/GL0</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEoio0/CORETSEi1li[4]:D</cell>
 <cell>5.080</cell>
 <cell>0.315</cell>
 <cell>5.080</cell>
 <cell>4.765</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEoio0/CORETSEOoli[10]:D</cell>
 <cell>5.126</cell>
 <cell>0.360</cell>
 <cell>5.126</cell>
 <cell>4.766</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEoio0/CORETSEi1li[3]:D</cell>
 <cell>5.128</cell>
 <cell>0.362</cell>
 <cell>5.128</cell>
 <cell>4.766</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEoio0/CORETSEi1li[2]:D</cell>
 <cell>5.119</cell>
 <cell>0.362</cell>
 <cell>5.119</cell>
 <cell>4.757</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEoio0/CORETSEOoli[15]:D</cell>
 <cell>5.128</cell>
 <cell>0.363</cell>
 <cell>5.128</cell>
 <cell>4.765</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEoio0/CORETSEi1li[4]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.080</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>4.765</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.315</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXDATA[34]</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SERDESIF_075_IP</cell>
 <cell>+</cell>
 <cell>-0.185</cell>
 <cell>-0.185</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSEoio0/CORETSEOoli_5[14]_CFG1D_TEST4:A</cell>
 <cell>net</cell>
 <cell>SERDES_IF2_0_EPCS_3_RX_DATA[4]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.310</cell>
 <cell>2.125</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSEoio0/CORETSEOoli_5[14]_CFG1D_TEST4:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.248</cell>
 <cell>2.373</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSEoio0/CORETSEOoli_5[14]_CFG1D_TEST3:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSEoio0/CORETSEOoli_5[14]_CFG1D_TEST_net4</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.136</cell>
 <cell>2.509</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSEoio0/CORETSEOoli_5[14]_CFG1D_TEST3:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.248</cell>
 <cell>2.757</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSEoio0/CORETSEOoli_5[14]_CFG1D_TEST2:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSEoio0/CORETSEOoli_5[14]_CFG1D_TEST_net3</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.200</cell>
 <cell>2.957</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSEoio0/CORETSEOoli_5[14]_CFG1D_TEST2:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.248</cell>
 <cell>3.205</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSEoio0/CORETSEOoli_5[14]_CFG1D_TEST1:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSEoio0/CORETSEOoli_5[14]_CFG1D_TEST_net2</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.136</cell>
 <cell>3.341</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSEoio0/CORETSEOoli_5[14]_CFG1D_TEST1:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.248</cell>
 <cell>3.589</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSEoio0/CORETSEOoli_5[14]_CFG1D_TEST0:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSEoio0/CORETSEOoli_5[14]_CFG1D_TEST_net1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.201</cell>
 <cell>3.790</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSEoio0/CORETSEOoli_5[14]_CFG1D_TEST0:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.248</cell>
 <cell>4.038</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSEoio0/CORETSEOoli_5[14]_CFG1D_TEST:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSEoio0/CORETSEOoli_5[14]_CFG1D_TEST_net0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.136</cell>
 <cell>4.174</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSEoio0/CORETSEOoli_5[14]_CFG1D_TEST:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.248</cell>
 <cell>4.422</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEoio0/CORETSEOoli_5[14]:B</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSEoio0/CORETSEOoli_5[14]_CFG1D_TEST_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.498</cell>
 <cell>4.920</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEoio0/CORETSEOoli_5[14]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.109</cell>
 <cell>5.029</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEoio0/CORETSEi1li[4]:D</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSEoio0/CORETSEOoli_5[14]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.051</cell>
 <cell>5.080</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.080</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.518</cell>
 <cell>3.518</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.132</cell>
 <cell>3.650</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.118</cell>
 <cell>3.768</cell>
 <cell>14</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB11:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.413</cell>
 <cell>4.181</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB11:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.212</cell>
 <cell>4.393</cell>
 <cell>15</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEoio0/CORETSEi1li[4]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB11_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.372</cell>
 <cell>4.765</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEoio0/CORETSEi1li[4]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>4.765</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.765</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET FCCC_2/GL0 to FCCC_1/GL0</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEOOi0/CORETSEOlII[1]:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiio0/CORETSEllio[1]:D</cell>
 <cell>0.557</cell>
 <cell>0.672</cell>
 <cell>5.439</cell>
 <cell>4.767</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEOOi0/CORETSEOlII[0]:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiio0/CORETSEllio[0]:D</cell>
 <cell>0.646</cell>
 <cell>0.782</cell>
 <cell>5.528</cell>
 <cell>4.746</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElio0/CORETSEi00I[9]:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEoio0/CORETSEi1li[9]:D</cell>
 <cell>1.412</cell>
 <cell>1.531</cell>
 <cell>6.295</cell>
 <cell>4.764</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElio0/CORETSEi00I[5]:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEoio0/CORETSEOoli[15]:D</cell>
 <cell>1.438</cell>
 <cell>1.560</cell>
 <cell>6.325</cell>
 <cell>4.765</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElio0/CORETSEi00I[8]:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEoio0/CORETSEi1li[8]:D</cell>
 <cell>1.500</cell>
 <cell>1.614</cell>
 <cell>6.387</cell>
 <cell>4.773</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEOOi0/CORETSEOlII[1]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiio0/CORETSEllio[1]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.439</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>4.767</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.672</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.662</cell>
 <cell>3.662</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.133</cell>
 <cell>3.795</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.118</cell>
 <cell>3.913</cell>
 <cell>6</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB5:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.404</cell>
 <cell>4.317</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB5:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.212</cell>
 <cell>4.529</cell>
 <cell>24</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEOOi0/CORETSEOlII[1]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB5_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.353</cell>
 <cell>4.882</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEOOi0/CORETSEOlII[1]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.072</cell>
 <cell>4.954</cell>
 <cell>14</cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiio0/CORETSEllio[1]:D</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSEOlII[1]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.485</cell>
 <cell>5.439</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.439</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.518</cell>
 <cell>3.518</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.132</cell>
 <cell>3.650</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.118</cell>
 <cell>3.768</cell>
 <cell>14</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB7:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.414</cell>
 <cell>4.182</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB7:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.212</cell>
 <cell>4.394</cell>
 <cell>29</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiio0/CORETSEllio[1]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB7_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.373</cell>
 <cell>4.767</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEiio0/CORETSEllio[1]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>4.767</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.767</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Clock Domain FCCC_2/GL0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEl1O0I[5]:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEl1O0I[6]:D</cell>
 <cell>0.315</cell>
 <cell>0.297</cell>
 <cell>5.209</cell>
 <cell>4.912</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEOOi0/CORETSEo1IlI/CORETSEl1l1:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSEOOi0/CORETSEo1IlI/CORETSEoiI1:D</cell>
 <cell>0.316</cell>
 <cell>0.298</cell>
 <cell>5.194</cell>
 <cell>4.896</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElio0/CORETSEl1II[7]:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElio0/CORETSEl00I[7]:D</cell>
 <cell>0.320</cell>
 <cell>0.300</cell>
 <cell>5.229</cell>
 <cell>4.929</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEiOiII[9]:CLK</cell>
 <cell>MON_ANX_0/DOUT[9]:D</cell>
 <cell>0.319</cell>
 <cell>0.300</cell>
 <cell>5.199</cell>
 <cell>4.899</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSElIiII/CORETSEIioII[0]:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSElIiII/CORETSEIioII[1]:D</cell>
 <cell>0.313</cell>
 <cell>0.301</cell>
 <cell>5.222</cell>
 <cell>4.921</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEl1O0I[5]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEl1O0I[6]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.209</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>4.912</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.297</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.662</cell>
 <cell>3.662</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.133</cell>
 <cell>3.795</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.118</cell>
 <cell>3.913</cell>
 <cell>13</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB6:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.418</cell>
 <cell>4.331</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB6:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.212</cell>
 <cell>4.543</cell>
 <cell>8</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEl1O0I[5]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB6_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.351</cell>
 <cell>4.894</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEl1O0I[5]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.058</cell>
 <cell>4.952</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEl1O0I[6]:D</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEl1O0I[5]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.257</cell>
 <cell>5.209</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.209</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.662</cell>
 <cell>3.662</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.133</cell>
 <cell>3.795</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.118</cell>
 <cell>3.913</cell>
 <cell>13</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB6:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.418</cell>
 <cell>4.331</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB6:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.212</cell>
 <cell>4.543</cell>
 <cell>8</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEl1O0I[6]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB6_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.369</cell>
 <cell>4.912</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEl1O0I[6]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>4.912</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.912</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Clock to Out (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MON_ANX_0/DOUT[6]:CLK</cell>
 <cell>DOUT[6]</cell>
 <cell>3.532</cell>
 <cell></cell>
 <cell>8.401</cell>
 <cell></cell>
 <cell>8.401</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>MON_ANX_0/DOUT[9]:CLK</cell>
 <cell>DOUT[9]</cell>
 <cell>3.540</cell>
 <cell></cell>
 <cell>8.427</cell>
 <cell></cell>
 <cell>8.427</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>MON_ANX_0/DOUT[0]:CLK</cell>
 <cell>DOUT[0]</cell>
 <cell>3.540</cell>
 <cell></cell>
 <cell>8.427</cell>
 <cell></cell>
 <cell>8.427</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>MON_ANX_0/DOUT[5]:CLK</cell>
 <cell>DOUT[5]</cell>
 <cell>3.590</cell>
 <cell></cell>
 <cell>8.455</cell>
 <cell></cell>
 <cell>8.455</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>MON_ANX_0/DOUT[7]:CLK</cell>
 <cell>DOUT[7]</cell>
 <cell>3.603</cell>
 <cell></cell>
 <cell>8.479</cell>
 <cell></cell>
 <cell>8.479</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MON_ANX_0/DOUT[6]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: DOUT[6]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>8.401</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.662</cell>
 <cell>3.662</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.133</cell>
 <cell>3.795</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.118</cell>
 <cell>3.913</cell>
 <cell>6</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB13:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.407</cell>
 <cell>4.320</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB13:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.212</cell>
 <cell>4.532</cell>
 <cell>21</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MON_ANX_0/DOUT[6]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB13_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.337</cell>
 <cell>4.869</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MON_ANX_0/DOUT[6]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.072</cell>
 <cell>4.941</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>DOUT_obuf[6]/U0/U_IOOUTFF:A</cell>
 <cell>net</cell>
 <cell>DOUT_c[6]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.197</cell>
 <cell>6.138</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>DOUT_obuf[6]/U0/U_IOOUTFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOOUTFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.229</cell>
 <cell>6.367</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>DOUT_obuf[6]/U0/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>DOUT_obuf[6]/U0/DOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.052</cell>
 <cell>6.419</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>DOUT_obuf[6]/U0/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>1.982</cell>
 <cell>8.401</cell>
 <cell>0</cell>
 <cell>f</cell>
</row>
<row>
 <cell>DOUT[6]</cell>
 <cell>net</cell>
 <cell>DOUT[6]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>8.401</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>8.401</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.662</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>DOUT[6]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEOIiII/CORETSEl00II:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSElIiII/CORETSEOOiII:ALn</cell>
 <cell>0.851</cell>
 <cell>0.824</cell>
 <cell>5.745</cell>
 <cell>4.921</cell>
 <cell>0.000</cell>
 <cell>-0.027</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEOIiII/CORETSEl00II:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSElIiII/CORETSEol1II[1]:ALn</cell>
 <cell>0.851</cell>
 <cell>0.824</cell>
 <cell>5.745</cell>
 <cell>4.921</cell>
 <cell>0.000</cell>
 <cell>-0.027</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEOIiII/CORETSEl00II:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSElIiII/CORETSEol1II[0]:ALn</cell>
 <cell>0.851</cell>
 <cell>0.824</cell>
 <cell>5.745</cell>
 <cell>4.921</cell>
 <cell>0.000</cell>
 <cell>-0.027</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEOIiII/CORETSEl00II:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSElIiII/CORETSEIioII[1]:ALn</cell>
 <cell>0.851</cell>
 <cell>0.824</cell>
 <cell>5.745</cell>
 <cell>4.921</cell>
 <cell>0.000</cell>
 <cell>-0.027</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEOIiII/CORETSEl00II:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSElIiII/CORETSEIioII[0]:ALn</cell>
 <cell>0.851</cell>
 <cell>0.824</cell>
 <cell>5.745</cell>
 <cell>4.921</cell>
 <cell>0.000</cell>
 <cell>-0.027</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEOIiII/CORETSEl00II:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSElIiII/CORETSEOOiII:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.745</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>4.921</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.824</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.662</cell>
 <cell>3.662</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.133</cell>
 <cell>3.795</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.118</cell>
 <cell>3.913</cell>
 <cell>13</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB3:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.413</cell>
 <cell>4.326</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB3:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.213</cell>
 <cell>4.539</cell>
 <cell>10</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEOIiII/CORETSEl00II:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB3_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.355</cell>
 <cell>4.894</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEOIiII/CORETSEl00II:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.072</cell>
 <cell>4.966</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEOIiII/un1_CORETSEOl0II:A</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEOIiII/CORETSEl00II</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.287</cell>
 <cell>5.253</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEOIiII/un1_CORETSEOl0II:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2</cell>
 <cell>+</cell>
 <cell>0.099</cell>
 <cell>5.352</cell>
 <cell>24</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSElIiII/CORETSEOOiII:ALn</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEOIiII/un1_CORETSEOl0II</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.393</cell>
 <cell>5.745</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.745</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.662</cell>
 <cell>3.662</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.133</cell>
 <cell>3.795</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.118</cell>
 <cell>3.913</cell>
 <cell>13</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.414</cell>
 <cell>4.327</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB2:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.213</cell>
 <cell>4.540</cell>
 <cell>13</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSElIiII/CORETSEOOiII:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB2_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.381</cell>
 <cell>4.921</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSElIiII/CORETSEOOiII:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>4.921</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.921</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_0/GL0 to FCCC_2/GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_1/GL0 to FCCC_2/GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1] to FCCC_2/GL0</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1]</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEl1O0I[0]:D</cell>
 <cell>5.313</cell>
 <cell>0.456</cell>
 <cell>5.313</cell>
 <cell>4.857</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEl1O0I[0]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.313</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>4.857</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.456</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1]</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_READY[1]</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SERDESIF_075_IP</cell>
 <cell>+</cell>
 <cell>0.407</cell>
 <cell>0.407</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEl1O0I[0]_CFG1D_TEST5:A</cell>
 <cell>net</cell>
 <cell>SERDES_IF2_0_EPCS_3_READY</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.156</cell>
 <cell>2.563</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEl1O0I[0]_CFG1D_TEST5:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.231</cell>
 <cell>2.794</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEl1O0I[0]_CFG1D_TEST4:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEl1O0I[0]_CFG1D_TEST_net5</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.130</cell>
 <cell>2.924</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEl1O0I[0]_CFG1D_TEST4:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.231</cell>
 <cell>3.155</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEl1O0I[0]_CFG1D_TEST3:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEl1O0I[0]_CFG1D_TEST_net4</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.205</cell>
 <cell>3.360</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEl1O0I[0]_CFG1D_TEST3:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.231</cell>
 <cell>3.591</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEl1O0I[0]_CFG1D_TEST2:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEl1O0I[0]_CFG1D_TEST_net3</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.130</cell>
 <cell>3.721</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEl1O0I[0]_CFG1D_TEST2:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.231</cell>
 <cell>3.952</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEl1O0I[0]_CFG1D_TEST1:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEl1O0I[0]_CFG1D_TEST_net2</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.204</cell>
 <cell>4.156</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEl1O0I[0]_CFG1D_TEST1:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.231</cell>
 <cell>4.387</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEl1O0I[0]_CFG1D_TEST0:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEl1O0I[0]_CFG1D_TEST_net1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.130</cell>
 <cell>4.517</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEl1O0I[0]_CFG1D_TEST0:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.231</cell>
 <cell>4.748</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEl1O0I[0]_CFG1D_TEST:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEl1O0I[0]_CFG1D_TEST_net0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.207</cell>
 <cell>4.955</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEl1O0I[0]_CFG1D_TEST:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.231</cell>
 <cell>5.186</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEl1O0I[0]:D</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEl1O0I[0]_CFG1D_TEST_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.127</cell>
 <cell>5.313</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.313</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.662</cell>
 <cell>3.662</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.133</cell>
 <cell>3.795</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.118</cell>
 <cell>3.913</cell>
 <cell>13</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB17:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.388</cell>
 <cell>4.301</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB17:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.213</cell>
 <cell>4.514</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEl1O0I[0]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB17_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.343</cell>
 <cell>4.857</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEl1O0I[0]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>4.857</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.857</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET FCCC_3/GL0 to FCCC_2/GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_3/GL1 to FCCC_2/GL0</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain FCCC_3/GL0</name>
<text>Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin CORETSE_AHB_0/CORETSEi0ilI/CORETSEI1O0I/CORETSEIIil_CORETSEIIil_0_0/INST_RAM1K18_IP:B_CLK</text>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_0/GL0 to FCCC_3/GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_1/GL0 to FCCC_3/GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_2/GL0 to FCCC_3/GL0</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSElIiII/CORETSEIO1II:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEiOI1/CORETSEloI1/CORETSEOooI:D</cell>
 <cell>1.581</cell>
 <cell>0.463</cell>
 <cell>6.482</cell>
 <cell>6.019</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSElIiII/CORETSEIO1II:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEiOI1/CORETSEloI1/CORETSEOooI:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.482</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>6.019</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.463</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.662</cell>
 <cell>3.662</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.133</cell>
 <cell>3.795</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.118</cell>
 <cell>3.913</cell>
 <cell>13</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.414</cell>
 <cell>4.327</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB2:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.213</cell>
 <cell>4.540</cell>
 <cell>13</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSElIiII/CORETSEIO1II:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB2_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.361</cell>
 <cell>4.901</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSElIiII/CORETSEIO1II:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.058</cell>
 <cell>4.959</cell>
 <cell>3</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEiIiII_inst_2/CORETSEII1II_CFG1A_TEST:A</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEIO1II</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.583</cell>
 <cell>5.542</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEiIiII_inst_2/CORETSEII1II_CFG1A_TEST:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1A_TEST</cell>
 <cell>+</cell>
 <cell>0.050</cell>
 <cell>5.592</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEiIiII_inst_2/CORETSEII1II_CFG1D_TEST:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEiIiII_inst_2/CORETSEII1II_CFG1A_TEST_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.206</cell>
 <cell>5.798</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEiIiII_inst_2/CORETSEII1II_CFG1D_TEST:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.231</cell>
 <cell>6.029</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEiIiII_inst_2/CORETSEII1II_CFG1C_TEST:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEiIiII_inst_2/CORETSEII1II_CFG1D_TEST_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.157</cell>
 <cell>6.186</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEiIiII_inst_2/CORETSEII1II_CFG1C_TEST:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1C_TEST</cell>
 <cell>+</cell>
 <cell>0.135</cell>
 <cell>6.321</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEiIiII/CORETSEII1II:B</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEiIiII_inst_2/CORETSEII1II_CFG1C_TEST_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.062</cell>
 <cell>6.383</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEiIiII/CORETSEII1II:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2</cell>
 <cell>+</cell>
 <cell>0.050</cell>
 <cell>6.433</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEiOI1/CORETSEloI1/CORETSEOooI:D</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEii0I</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.049</cell>
 <cell>6.482</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.482</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_3/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_3/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.675</cell>
 <cell>2.675</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_3/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_3/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.133</cell>
 <cell>2.808</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_3/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.118</cell>
 <cell>2.926</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_3/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>FCCC_3/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.387</cell>
 <cell>3.313</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_3/GL0_INST/U0_RGB1:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.213</cell>
 <cell>3.526</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_3/CCC_INST/IP_INTERFACE_1:A</cell>
 <cell>net</cell>
 <cell>FCCC_3/CLKINT_0_Y</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.273</cell>
 <cell>3.799</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_3/CCC_INST/IP_INTERFACE_1:IPA</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.130</cell>
 <cell>3.929</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_3/CCC_INST/INST_CCC_IP:CLK1</cell>
 <cell>net</cell>
 <cell>FCCC_3/CCC_INST/CLK1_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.029</cell>
 <cell>3.958</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_3/CCC_INST/INST_CCC_IP:GL1</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CCC_IP</cell>
 <cell>+</cell>
 <cell>0.823</cell>
 <cell>4.781</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_3/GL1_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_3/GL1_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.133</cell>
 <cell>4.914</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_3/GL1_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.118</cell>
 <cell>5.032</cell>
 <cell>29</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_3/GL1_INST/U0_RGB1_RGB22:An</cell>
 <cell>net</cell>
 <cell>FCCC_3/GL1_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.411</cell>
 <cell>5.443</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_3/GL1_INST/U0_RGB1_RGB22:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.213</cell>
 <cell>5.656</cell>
 <cell>61</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEiOI1/CORETSEloI1/CORETSEOooI:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_3/GL1_INST/U0_RGB1_RGB22_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.363</cell>
 <cell>6.019</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEiOI1/CORETSEloI1/CORETSEOooI:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>6.019</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.019</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET FCCC_3/GL1 to FCCC_3/GL0</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain OSC_0/I_RCOSC_25_50MHZ/CLKOUT</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CoreResetP_0/sm0_areset_n_rcosc_q1:CLK</cell>
 <cell>CoreResetP_0/sm0_areset_n_rcosc:D</cell>
 <cell>0.317</cell>
 <cell>0.307</cell>
 <cell>5.379</cell>
 <cell>5.072</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CoreResetP_0/count_sdif0_enable_q1:CLK</cell>
 <cell>CoreResetP_0/count_sdif0_enable_rcosc:D</cell>
 <cell>0.323</cell>
 <cell>0.312</cell>
 <cell>5.387</cell>
 <cell>5.075</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CoreResetP_0/count_sdif0[5]:CLK</cell>
 <cell>CoreResetP_0/count_sdif0[5]:D</cell>
 <cell>0.434</cell>
 <cell>0.434</cell>
 <cell>5.520</cell>
 <cell>5.086</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CoreResetP_0/count_sdif0[8]:CLK</cell>
 <cell>CoreResetP_0/count_sdif0[8]:D</cell>
 <cell>0.437</cell>
 <cell>0.437</cell>
 <cell>5.515</cell>
 <cell>5.078</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CoreResetP_0/count_sdif0[4]:CLK</cell>
 <cell>CoreResetP_0/count_sdif0[4]:D</cell>
 <cell>0.439</cell>
 <cell>0.439</cell>
 <cell>5.516</cell>
 <cell>5.077</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CoreResetP_0/sm0_areset_n_rcosc_q1:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CoreResetP_0/sm0_areset_n_rcosc:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.379</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>5.072</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.307</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ/CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>OSC_0/N_RCOSC_25_50MHZ_CLKOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.311</cell>
 <cell>1.311</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.102</cell>
 <cell>1.413</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>OSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.432</cell>
 <cell>3.845</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>4.095</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.407</cell>
 <cell>4.502</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.212</cell>
 <cell>4.714</cell>
 <cell>22</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/sm0_areset_n_rcosc_q1:CLK</cell>
 <cell>net</cell>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.348</cell>
 <cell>5.062</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/sm0_areset_n_rcosc_q1:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.058</cell>
 <cell>5.120</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/sm0_areset_n_rcosc:D</cell>
 <cell>net</cell>
 <cell>CoreResetP_0/sm0_areset_n_rcosc_q1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.259</cell>
 <cell>5.379</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.379</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ/CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>OSC_0/N_RCOSC_25_50MHZ_CLKOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.311</cell>
 <cell>1.311</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.102</cell>
 <cell>1.413</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>OSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.432</cell>
 <cell>3.845</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>4.095</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.407</cell>
 <cell>4.502</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.212</cell>
 <cell>4.714</cell>
 <cell>22</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>net</cell>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.358</cell>
 <cell>5.072</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/sm0_areset_n_rcosc:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>5.072</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.072</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CoreResetP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>CoreResetP_0/count_sdif0[7]:ALn</cell>
 <cell>0.443</cell>
 <cell>0.423</cell>
 <cell>5.520</cell>
 <cell>5.097</cell>
 <cell>0.000</cell>
 <cell>-0.020</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CoreResetP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>CoreResetP_0/count_sdif0[5]:ALn</cell>
 <cell>0.443</cell>
 <cell>0.423</cell>
 <cell>5.520</cell>
 <cell>5.097</cell>
 <cell>0.000</cell>
 <cell>-0.020</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CoreResetP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>CoreResetP_0/count_sdif0[1]:ALn</cell>
 <cell>0.443</cell>
 <cell>0.423</cell>
 <cell>5.520</cell>
 <cell>5.097</cell>
 <cell>0.000</cell>
 <cell>-0.020</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CoreResetP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>CoreResetP_0/count_sdif0[9]:ALn</cell>
 <cell>0.443</cell>
 <cell>0.423</cell>
 <cell>5.520</cell>
 <cell>5.097</cell>
 <cell>0.000</cell>
 <cell>-0.020</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CoreResetP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>CoreResetP_0/count_sdif0[11]:ALn</cell>
 <cell>0.443</cell>
 <cell>0.423</cell>
 <cell>5.520</cell>
 <cell>5.097</cell>
 <cell>0.000</cell>
 <cell>-0.020</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CoreResetP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CoreResetP_0/count_sdif0[7]:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.520</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>5.097</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.423</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ/CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>OSC_0/N_RCOSC_25_50MHZ_CLKOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.311</cell>
 <cell>1.311</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.102</cell>
 <cell>1.413</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>OSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.432</cell>
 <cell>3.845</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>4.095</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.407</cell>
 <cell>4.502</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.212</cell>
 <cell>4.714</cell>
 <cell>22</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>net</cell>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.363</cell>
 <cell>5.077</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/sdif0_areset_n_rcosc:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.058</cell>
 <cell>5.135</cell>
 <cell>15</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/count_sdif0[7]:ALn</cell>
 <cell>net</cell>
 <cell>CoreResetP_0/sdif0_areset_n_rcosc_0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.385</cell>
 <cell>5.520</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.520</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ/CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>OSC_0/N_RCOSC_25_50MHZ_CLKOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.311</cell>
 <cell>1.311</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.102</cell>
 <cell>1.413</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>OSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.432</cell>
 <cell>3.845</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>4.095</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.407</cell>
 <cell>4.502</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.212</cell>
 <cell>4.714</cell>
 <cell>22</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/count_sdif0[7]:CLK</cell>
 <cell>net</cell>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.383</cell>
 <cell>5.097</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/count_sdif0[7]:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>5.097</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.097</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_0/GL0 to OSC_0/I_RCOSC_25_50MHZ/CLKOUT</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CoreConfigP_0/SDIF_RELEASED_q1:CLK</cell>
 <cell>CoreConfigP_0/SDIF_RELEASED_q2:D</cell>
 <cell>0.319</cell>
 <cell>0.316</cell>
 <cell>3.829</cell>
 <cell>3.513</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CoreConfigP_0/state[1]:CLK</cell>
 <cell>CoreConfigP_0/FIC_2_APB_M_PREADY:D</cell>
 <cell>0.360</cell>
 <cell>0.357</cell>
 <cell>3.881</cell>
 <cell>3.524</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CoreConfigP_0/INIT_DONE_q1:CLK</cell>
 <cell>CoreConfigP_0/INIT_DONE_q2:D</cell>
 <cell>0.402</cell>
 <cell>0.384</cell>
 <cell>3.905</cell>
 <cell>3.521</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CoreConfigP_0/state[1]:CLK</cell>
 <cell>CoreConfigP_0/state[0]:D</cell>
 <cell>0.435</cell>
 <cell>0.423</cell>
 <cell>3.956</cell>
 <cell>3.533</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CoreConfigP_0/SDIF_RELEASED_q2:CLK</cell>
 <cell>CoreConfigP_0/FIC_2_APB_M_PRDATA[1]:D</cell>
 <cell>0.445</cell>
 <cell>0.426</cell>
 <cell>3.947</cell>
 <cell>3.521</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CoreConfigP_0/SDIF_RELEASED_q1:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CoreConfigP_0/SDIF_RELEASED_q2:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.829</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.513</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.316</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>CoreTSE_M2S090_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreTSE_M2S090_MSS_0/MSS_ADLIB_INST_RNIPDL7:An</cell>
 <cell>net</cell>
 <cell>CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.284</cell>
 <cell>2.284</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CoreTSE_M2S090_MSS_0/MSS_ADLIB_INST_RNIPDL7:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>2.534</cell>
 <cell>7</cell>
 <cell>f</cell>
</row>
<row>
 <cell>CoreTSE_M2S090_MSS_0/MSS_ADLIB_INST_RNIPDL7/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>CoreTSE_M2S090_MSS_0/MSS_ADLIB_INST_RNIPDL7/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.404</cell>
 <cell>2.938</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CoreTSE_M2S090_MSS_0/MSS_ADLIB_INST_RNIPDL7/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.212</cell>
 <cell>3.150</cell>
 <cell>9</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreConfigP_0/SDIF_RELEASED_q1:CLK</cell>
 <cell>net</cell>
 <cell>CoreTSE_M2S090_MSS_0/MSS_ADLIB_INST_RNIPDL7/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.360</cell>
 <cell>3.510</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreConfigP_0/SDIF_RELEASED_q1:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.058</cell>
 <cell>3.568</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreConfigP_0/SDIF_RELEASED_q2:D</cell>
 <cell>net</cell>
 <cell>CoreConfigP_0/SDIF_RELEASED_q1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.261</cell>
 <cell>3.829</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.829</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>CoreTSE_M2S090_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreTSE_M2S090_MSS_0/MSS_ADLIB_INST_RNIPDL7:An</cell>
 <cell>net</cell>
 <cell>CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.284</cell>
 <cell>2.284</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CoreTSE_M2S090_MSS_0/MSS_ADLIB_INST_RNIPDL7:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>2.534</cell>
 <cell>7</cell>
 <cell>f</cell>
</row>
<row>
 <cell>CoreTSE_M2S090_MSS_0/MSS_ADLIB_INST_RNIPDL7/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>CoreTSE_M2S090_MSS_0/MSS_ADLIB_INST_RNIPDL7/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.404</cell>
 <cell>2.938</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CoreTSE_M2S090_MSS_0/MSS_ADLIB_INST_RNIPDL7/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.212</cell>
 <cell>3.150</cell>
 <cell>9</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreConfigP_0/SDIF_RELEASED_q2:CLK</cell>
 <cell>net</cell>
 <cell>CoreTSE_M2S090_MSS_0/MSS_ADLIB_INST_RNIPDL7/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.363</cell>
 <cell>3.513</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreConfigP_0/SDIF_RELEASED_q2:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.513</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.513</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_0/GL0 to CoreTSE_M2S090_MSS_0/CLK_CONFIG_APB</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1]</name>
<text>Info: The maximum frequency of this clock domain is limited by the period of pin SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]</text>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]</name>
<text>Info: The maximum frequency of this clock domain is limited by the period of pin SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1]</text>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_2/GL0 to SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElio0/CORETSEi00I[2]:CLK</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[22]</cell>
 <cell>3.108</cell>
 <cell>9.346</cell>
 <cell>7.996</cell>
 <cell>-1.350</cell>
 <cell>-1.350</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElio0/CORETSEi00I[4]:CLK</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[24]</cell>
 <cell>3.179</cell>
 <cell>9.427</cell>
 <cell>8.062</cell>
 <cell>-1.365</cell>
 <cell>-1.365</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElio0/CORETSEi00I[1]:CLK</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[21]</cell>
 <cell>3.261</cell>
 <cell>9.503</cell>
 <cell>8.149</cell>
 <cell>-1.354</cell>
 <cell>-1.354</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElio0/CORETSEi00I[9]:CLK</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[29]</cell>
 <cell>3.314</cell>
 <cell>9.507</cell>
 <cell>8.197</cell>
 <cell>-1.310</cell>
 <cell>-1.310</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElio0/CORETSEi00I[8]:CLK</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[28]</cell>
 <cell>3.355</cell>
 <cell>9.597</cell>
 <cell>8.242</cell>
 <cell>-1.355</cell>
 <cell>-1.355</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElio0/CORETSEi00I[2]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[22]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.996</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>-1.350</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>9.346</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.662</cell>
 <cell>3.662</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.133</cell>
 <cell>3.795</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.118</cell>
 <cell>3.913</cell>
 <cell>13</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB16:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.420</cell>
 <cell>4.333</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB16:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.213</cell>
 <cell>4.546</cell>
 <cell>7</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElio0/CORETSEi00I[2]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB16_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.342</cell>
 <cell>4.888</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElio0/CORETSEi00I[2]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.058</cell>
 <cell>4.946</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElio0/CORETSEI0II[2]:C</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEoIiII_inst_1/CORETSElio0/CORETSEi00I[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.206</cell>
 <cell>5.152</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEoIiII/CORETSElio0/CORETSEI0II[2]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>5.258</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/IP_INTERFACE_202:B</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0_TCG[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.559</cell>
 <cell>7.817</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/IP_INTERFACE_202:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.140</cell>
 <cell>7.957</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[22]</cell>
 <cell>net</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/EPCS_TXDATA_net[22]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.039</cell>
 <cell>7.996</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.996</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1]</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[22]</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SERDESIF_075_IP</cell>
 <cell>+</cell>
 <cell>-1.350</cell>
 <cell>-1.350</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-1.350</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Clock Domain FCCC_3/GL1</name>
<text>Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin CORETSE_AHB_0/CORETSEi0ilI/CORETSEI1O0I/CORETSEIIil_CORETSEIIil_0_0/INST_RAM1K18_IP:B_CLK</text>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_0/GL0 to FCCC_3/GL1</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_1/GL0 to FCCC_3/GL1</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_2/GL0 to FCCC_3/GL1</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSElIiII/CORETSEIO1II:CLK</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEiOI1/CORETSEloI1/CORETSEOooI:D</cell>
 <cell>1.581</cell>
 <cell>0.463</cell>
 <cell>6.482</cell>
 <cell>6.019</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSElIiII/CORETSEIO1II:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEiOI1/CORETSEloI1/CORETSEOooI:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.482</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>6.019</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.463</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.662</cell>
 <cell>3.662</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.133</cell>
 <cell>3.795</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.118</cell>
 <cell>3.913</cell>
 <cell>13</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.414</cell>
 <cell>4.327</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB2:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.213</cell>
 <cell>4.540</cell>
 <cell>13</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSElIiII/CORETSEIO1II:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB2_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.361</cell>
 <cell>4.901</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSElIiII/CORETSEIO1II:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.058</cell>
 <cell>4.959</cell>
 <cell>3</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEiIiII_inst_2/CORETSEII1II_CFG1A_TEST:A</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEIO1II</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.583</cell>
 <cell>5.542</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEiIiII_inst_2/CORETSEII1II_CFG1A_TEST:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1A_TEST</cell>
 <cell>+</cell>
 <cell>0.050</cell>
 <cell>5.592</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEiIiII_inst_2/CORETSEII1II_CFG1D_TEST:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEiIiII_inst_2/CORETSEII1II_CFG1A_TEST_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.206</cell>
 <cell>5.798</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEiIiII_inst_2/CORETSEII1II_CFG1D_TEST:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.231</cell>
 <cell>6.029</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEiIiII_inst_2/CORETSEII1II_CFG1C_TEST:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEiIiII_inst_2/CORETSEII1II_CFG1D_TEST_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.157</cell>
 <cell>6.186</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEiIiII_inst_2/CORETSEII1II_CFG1C_TEST:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1C_TEST</cell>
 <cell>+</cell>
 <cell>0.135</cell>
 <cell>6.321</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEiIiII/CORETSEII1II:B</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI_CORETSEo1O0I/CORETSEiIiII_inst_2/CORETSEII1II_CFG1C_TEST_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.062</cell>
 <cell>6.383</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEi01lI.CORETSEo1O0I/CORETSEiIiII/CORETSEII1II:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2</cell>
 <cell>+</cell>
 <cell>0.050</cell>
 <cell>6.433</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEiOI1/CORETSEloI1/CORETSEOooI:D</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEii0I</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.049</cell>
 <cell>6.482</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.482</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_3/GL1</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_3/CCC_INST/INST_CCC_IP:GL1</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>4.781</cell>
 <cell>4.781</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_3/GL1_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_3/GL1_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.133</cell>
 <cell>4.914</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_3/GL1_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.118</cell>
 <cell>5.032</cell>
 <cell>29</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_3/GL1_INST/U0_RGB1_RGB22:An</cell>
 <cell>net</cell>
 <cell>FCCC_3/GL1_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.411</cell>
 <cell>5.443</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_3/GL1_INST/U0_RGB1_RGB22:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.213</cell>
 <cell>5.656</cell>
 <cell>61</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEiOI1/CORETSEloI1/CORETSEOooI:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_3/GL1_INST/U0_RGB1_RGB22_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.363</cell>
 <cell>6.019</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CORETSEi0ilI/CORETSEIoilI/CORETSEioolI/CORETSEiOI1/CORETSEloI1/CORETSEOooI:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>6.019</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.019</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET FCCC_3/GL0 to FCCC_3/GL1</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set Pin to Pin</name>
<section>
<name>SET Input to Output</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set User Sets</name>
</section>
</doc>
