//===========================================================================
`timescale 1ps / 1ps
module testbench (); 

`include "../../../../../coreparameters.v"

wire        mdi;         
wire        rstbp;       
wire [31:0] ahb_hwdata;  
wire  [9:2] ahb_haddr;   
wire        ahb_hsel;    
wire  [1:0] ahb_htrans;  
wire        ahb_hwrite;  
wire        ahb_txhgrant;
wire        ahb_rxhgrant;
wire  [1:0] ahb_txhrespm;
wire  [1:0] ahb_rxhrespm;
wire [31:0] ahb_txhrdatam;
wire [31:0] ahb_rxhrdatam;
wire        ahb_hreadyi;  
wire        hresetn;   
wire        hclk;      
wire        mdc;       
wire        mdo;       
wire        mdoen;     
wire [31:0] ahb_hrdata;  
wire  [1:0] ahb_hresp;  
wire        ahb_hreadyo;  
wire        ahb_txhbusreq;
wire  [1:0] ahb_txhtransm;
wire [31:2] ahb_txhaddrm; 
wire [31:0] ahb_txhaddrm_w;
wire        ahb_txhwritem; 
wire [31:0] ahb_txhwdatam; 
wire        ahb_rxhbusreq; 
wire  [1:0] ahb_rxhtransm; 
wire [31:2] ahb_rxhaddrm;  
wire [31:0] ahb_rxhaddrm_w;
wire        ahb_rxhwritem; 
wire [31:0] ahb_rxhwdatam; 
wire [9:0] tcg_dut ;   
wire [9:0] rcg_dut  ;   
wire [9:0] anx_state;
assign ahb_txhaddrm = ahb_txhaddrm_w [31 :2];
assign ahb_rxhaddrm = ahb_rxhaddrm_w [31 :2];

  CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB
  #(
     .FAMILY(FAMILY),
     .GMII_TBI(GMII_TBI),
     .PACKET_SIZE (PACKET_SIZE),
     .SAL  (SAL  ),
     .WoL  (WoL  ),
     .STATS(STATS),
     .MDIO_PHYID(MDIO_PHYID)
    )
   tsmac_sgmii_top_dut
  (
    .TBI_TX_CLK(tbi_tx_clk),
    .TBI_RX_CLK(tbi_rx_clk),
    .GTXCLK(tbi_tx_clk),   
    .TXCLK(tx_clk),    
    .RXCLK(rx_clk),    
    .STBP(rstbp), 
    .CRS  (),    
    .COL  (),    
    .RXDV (),    
    .RXD  (),    
    .RXER (),    
    .TXEN (),    
    .TXD  (),    
    .TXER (),    
    .TBI_RX_READY(1'b1),
    .TBI_TX_VALID(),
    .SIGNAL_DETECT(1'b1),
    .RCG(rcg_dut),     
    .TCG(tcg_dut ),    
    .HRESETN    (hresetn),
    .HCLK       (hclk),   
    .HREADY(1'b1   ),     
    .HWDATA(ahb_hwdata),
    .HADDR ({22'b0, ahb_haddr[9:2],2'b0}),
    .HSEL  (ahb_hsel     ),         
    .HTRANS(ahb_htrans   ),         
    .HWRITE(ahb_hwrite   ),         
    .HRDATA(ahb_hrdata   ),         
    .HRESP (ahb_hresp    ),         
    .HREADYOUT(ahb_hreadyo   ),     
    .HBURST(),
    .HMASTLOCK(),
    .HSIZE(),

    // TX-DMA AHB-Master interface signals
    .TXHGRANT(ahb_txhgrant),  
    .TXHRESP (ahb_txhrespm),  
    .TXHRDATA(ahb_txhrdatam), 
    .TXHBUSREQ(ahb_txhbusreq),
    .TXHTRANS(ahb_txhtransm), 
    .TXHADDR (ahb_txhaddrm_w),
    .TXHWRITE(ahb_txhwritem), 
    .TXHWDATA(ahb_txhwdatam), 
    .TXHREADY(1'b1),              
    .TXHBURST(),
    .TXHLOCK(),
    .TXHSIZE(),
  
    // RX-DMA AHB-MASter interface signals
    .RXHGRANT (ahb_rxhgrant),  
    .RXHRESP (ahb_rxhrespm),   
    .RXHRDATA(ahb_rxhrdatam ), 
    .RXHBUSREQ(ahb_rxhbusreq ),
    .RXHTRANS(ahb_rxhtransm ), 
    .RXHADDR (ahb_rxhaddrm_w), 
    .RXHWRITE(ahb_rxhwritem ), 
    .RXHWDATA(ahb_rxhwdatam),  
    .RXHREADY(1'b1),               
    .RXHLOCK(),
    .RXHBURST(),
    .RXHSIZE(),
    
    // Management interface MDIO signals
    .MDI(mdi ),         
    .MDC(mdc ),         
    .MDO(mdo ),         
    .MDOEN(mdoen),      
    .TSM_CONTROL(),     
    .TSM_INTR(),        
    .ANX_STATE(anx_state),
    .SYNC(),
    .RCG_ERROR(),
	.RX_SLIP(),
    .TBI_RX_VALID(1'b1)


  );


// Test environment instasnce 


CoreTSE_ahb_tb  Coretse_ahb_tb_inst
(
   .mdc(mdc),             
   .mdo(mdo),             
   .mdoen(mdoen),         
   .ahb_hrdata(ahb_hrdata),   
   .ahb_hresp(ahb_hresp),     
   .ahb_hreadyo(ahb_hreadyo), 
   .ahb_txhbusreq(ahb_txhbusreq),
   .ahb_txhtransm(ahb_txhtransm),
   .ahb_txhaddrm (ahb_txhaddrm), 
   .ahb_txhwritem(ahb_txhwritem),
   .ahb_txhwdatam(ahb_txhwdatam),
   .ahb_rxhbusreq(ahb_rxhbusreq),
   .ahb_rxhtransm(ahb_rxhtransm),
   .ahb_rxhaddrm (ahb_rxhaddrm), 
   .ahb_rxhwritem(ahb_rxhwritem),
   .ahb_rxhwdatam(ahb_rxhwdatam),
   .mdi(mdi),             
   .rstbp(rstbp),         
   .ahb_hwdata(ahb_hwdata), 
   .ahb_haddr(ahb_haddr),   
   .ahb_hsel(ahb_hsel),     
   .ahb_htrans(ahb_htrans), 
   .ahb_hwrite(ahb_hwrite), 
   .ahb_txhgrant(ahb_txhgrant),  
   .ahb_rxhgrant(ahb_rxhgrant),  
   .ahb_txhrespm(ahb_txhrespm),  
   .ahb_rxhrespm(ahb_rxhrespm),  
   .ahb_txhrdatam(ahb_txhrdatam),
   .ahb_rxhrdatam(ahb_rxhrdatam),
   .ahb_hreadyi(ahb_hreadyi),    
   .hresetn(hresetn),     
   .hclk(hclk),           
   .tcg_dut(tcg_dut),
   .rcg_dut (rcg_dut),
   .tbi_tx_clk(tbi_tx_clk),
   .tbi_rx_clk(tbi_rx_clk),
   .tx_clk(tx_clk),
   .rx_clk(rx_clk),
   .phyid(MDIO_PHYID[4:0]),
   .anx_state(anx_state)
);

endmodule
