module
CoreTSE_M2S090_CORETSE_AHB_0_CORETSE_AHB_TOP
(
RSTBP_I
,
TXCLK_I
,
RXCLK_I
,
GTXCLK_I
,
TBI_TX_CLK
,
TBI_RX_CLK
,
TSMAC_RCG_I
,
TSMAC_TCG_O
,
SIGNAL_DETECT_I
,
TSMAC_TXD_O
,
TSMAC_TXEN_O
,
TSMAC_TXER_O
,
TSMAC_RXD_I
,
TSMAC_RXDV_I
,
TSMAC_RXER_I
,
TSMAC_CRS_I
,
TSMAC_COL_I
,
HRESET_NI
,
HCLK_I
,
AHBS_HWDATA_I
,
AHBS_HADDR_I
,
AHBS_HSEL_I
,
AHBS_HTRANS_I
,
AHBS_HWRITE_I
,
AHBS_HRDATA_O
,
AHBS_HRESP_O
,
AHBS_HREADY_O
,
AHBS_HREADY_I
,
AHBM_TXHGRANT_I
,
AHBM_TXHREADY_I
,
AHBM_TXHRESPM_I
,
AHBM_TXHRDATAM_I
,
AHBM_TXHBUSREQ_O
,
AHBM_TXHSEL_O
,
AHBM_TXHTRANSM_O
,
AHBM_TXHADDRM_O
,
AHBM_TXHWRITEM_O
,
AHBM_TXHWDATAM_O
,
AHBM_RXHGRANT_I
,
AHBM_RXHREADY_I
,
AHBM_RXHRESPM_I
,
AHBM_RXHRDATAM_I
,
AHBM_RXHBUSREQ_O
,
AHBM_RXHSEL_O
,
AHBM_RXHTRANSM_O
,
AHBM_RXHADDRM_O
,
AHBM_RXHWRITEM_O
,
AHBM_RXHWDATAM_O
,
MGMT_MDI_I
,
MGMT_MDC_O
,
MGMT_MDO_O
,
MGMT_MDOEN_O
,
AHBS_HBURST_I
,
AHBS_HMASTLOCK_I
,
AHBS_HPROT_I
,
AHBS_HSIZE_I
,
AHBM_TXHBURST_O
,
AHBM_RXHBURST_O
,
AHBM_TXMASTLOCK_O
,
AHBM_RXMASTLOCK_O
,
AHBM_TXHSIZE_O
,
AHBM_RXHSIZE_O
,
AHBM_TXHSPLIT_O
,
AHBM_RXHSPLIT_O
,
TBI_READY_I
,
TBI_TXVAL_O
,
CORETSEO1ilI
,
TSM_CONTROL_O
,
TSM_INTR_O
,
ANX_STATE_O
,
SYNC_O
,
RUDINV
,
RX_SLIP
)
;
parameter
FAMILY
=
19
;
parameter
GMII_TBI
=
0
;
parameter
TABITS
=
12
;
parameter
RABITS
=
12
;
parameter
MCXMAC_SAL_ON
=
1
;
parameter
MCXMAC_WOL_ON
=
1
;
parameter
MCXMAC_STATS_ON
=
1
;
parameter
MDIO_PHYID
=
18
;
parameter
SLIP_ENABLE
=
1
;
input
RSTBP_I
;
input
TXCLK_I
;
input
RXCLK_I
;
input
GTXCLK_I
;
input
TBI_RX_CLK
;
input
TBI_TX_CLK
;
input
[
9
:
0
]
TSMAC_RCG_I
;
output
[
9
:
0
]
TSMAC_TCG_O
;
input
SIGNAL_DETECT_I
;
output
[
7
:
0
]
TSMAC_TXD_O
;
output
TSMAC_TXEN_O
;
output
TSMAC_TXER_O
;
input
[
7
:
0
]
TSMAC_RXD_I
;
input
TSMAC_RXDV_I
;
input
TSMAC_RXER_I
;
input
TSMAC_CRS_I
;
input
TSMAC_COL_I
;
input
HRESET_NI
;
input
HCLK_I
;
input
[
31
:
0
]
AHBS_HWDATA_I
;
input
[
31
:
0
]
AHBS_HADDR_I
;
input
AHBS_HSEL_I
;
input
[
1
:
0
]
AHBS_HTRANS_I
;
input
AHBS_HWRITE_I
;
output
[
31
:
0
]
AHBS_HRDATA_O
;
output
[
1
:
0
]
AHBS_HRESP_O
;
output
AHBS_HREADY_O
;
input
AHBS_HREADY_I
;
input
AHBM_TXHGRANT_I
;
input
AHBM_TXHREADY_I
;
input
[
1
:
0
]
AHBM_TXHRESPM_I
;
input
[
31
:
0
]
AHBM_TXHRDATAM_I
;
output
AHBM_TXHBUSREQ_O
;
output
AHBM_TXHSEL_O
;
output
[
1
:
0
]
AHBM_TXHTRANSM_O
;
output
[
31
:
0
]
AHBM_TXHADDRM_O
;
output
AHBM_TXHWRITEM_O
;
output
[
31
:
0
]
AHBM_TXHWDATAM_O
;
input
AHBM_RXHGRANT_I
;
input
AHBM_RXHREADY_I
;
input
[
1
:
0
]
AHBM_RXHRESPM_I
;
input
[
31
:
0
]
AHBM_RXHRDATAM_I
;
output
AHBM_RXHBUSREQ_O
;
output
AHBM_RXHSEL_O
;
output
[
1
:
0
]
AHBM_RXHTRANSM_O
;
output
[
31
:
0
]
AHBM_RXHADDRM_O
;
output
AHBM_RXHWRITEM_O
;
output
[
31
:
0
]
AHBM_RXHWDATAM_O
;
input
MGMT_MDI_I
;
output
MGMT_MDC_O
;
output
MGMT_MDO_O
;
output
MGMT_MDOEN_O
;
output
[
31
:
0
]
TSM_CONTROL_O
;
output
[
2
:
0
]
TSM_INTR_O
;
input
TBI_READY_I
;
input
CORETSEO1ilI
;
output
TBI_TXVAL_O
;
input
AHBS_HBURST_I
;
input
AHBS_HMASTLOCK_I
;
input
AHBS_HPROT_I
;
input
AHBS_HSIZE_I
;
output
[
2
:
0
]
AHBM_TXHBURST_O
;
output
[
2
:
0
]
AHBM_RXHBURST_O
;
output
AHBM_TXMASTLOCK_O
;
output
AHBM_RXMASTLOCK_O
;
output
[
2
:
0
]
AHBM_TXHSIZE_O
;
output
[
2
:
0
]
AHBM_RXHSIZE_O
;
output
AHBM_TXHSPLIT_O
;
output
AHBM_RXHSPLIT_O
;
output
[
9
:
0
]
ANX_STATE_O
;
output
SYNC_O
;
output
RUDINV
;
output
RX_SLIP
;
wire
CORETSEI1ilI
;
wire
CORETSEl1ilI
;
wire
CORETSEo1ilI
;
wire
CORETSEi1ilI
;
wire
[
7
:
0
]
CORETSEOloI
;
wire
[
7
:
0
]
CORETSEOI
;
wire
CORETSEIIII
;
wire
CORETSEi
;
wire
CORETSEoIII
;
wire
CORETSEII
;
wire
CORETSEii0I
;
wire
CORETSElI
;
wire
CORETSEl0llI
;
wire
[
1
:
0
]
CORETSEo0llI
;
wire
CORETSEIl1lI
;
wire
CORETSEol1lI
;
wire
CORETSEioIlI
;
wire
CORETSEOiIlI
;
wire
CORETSEIiIlI
;
wire
CORETSEliIlI
;
wire
[
TABITS
-
1
:
0
]
CORETSEoiIlI
;
wire
[
39
:
0
]
CORETSEiiIlI
;
wire
[
TABITS
-
1
:
0
]
CORETSEOOllI
;
wire
[
39
:
0
]
CORETSEIOllI
;
wire
CORETSElOllI
;
wire
CORETSEoOllI
;
wire
CORETSEiOllI
;
wire
[
RABITS
-
1
:
0
]
CORETSEOIllI
;
wire
[
35
:
0
]
CORETSEIIllI
;
wire
[
RABITS
-
1
:
0
]
CORETSElIllI
;
wire
[
35
:
0
]
CORETSEoIllI
;
wire
[
7
:
0
]
CORETSEOoilI
;
wire
[
31
:
0
]
CORETSEli00
,
CORETSEIoolI
;
assign
TSM_CONTROL_O
=
CORETSEli00
;
assign
MGMT_MDC_O
=
CORETSEl1ilI
;
assign
MGMT_MDO_O
=
CORETSEo1ilI
;
assign
MGMT_MDOEN_O
=
CORETSEi1ilI
;
assign
TSM_INTR_O
[
2
:
0
]
=
{
CORETSEOoilI
[
3
]
,
CORETSEOoilI
[
1
]
,
CORETSEOoilI
[
0
]
}
;
assign
AHBM_RXHADDRM_O
[
1
:
0
]
=
2
'b
00
;
assign
AHBM_TXHADDRM_O
[
1
:
0
]
=
2
'b
00
;
assign
AHBM_TXHBURST_O
=
3
'b
001
;
assign
AHBM_RXHBURST_O
=
3
'b
001
;
assign
AHBM_TXMASTLOCK_O
=
1
'b
0
;
assign
AHBM_RXMASTLOCK_O
=
1
'b
0
;
assign
AHBM_TXHSIZE_O
=
2
'b
10
;
assign
AHBM_RXHSIZE_O
=
2
'b
10
;
assign
AHBM_TXHSPLIT_O
=
1
'b
0
;
assign
AHBM_RXHSPLIT_O
=
1
'b
0
;
assign
AHBM_TXHBUSREQ_O
=
1
'b
1
;
assign
AHBM_RXHBUSREQ_O
=
1
'b
1
;
CoreTSE_M2S090_CORETSE_AHB_0_TSMAC_AHB_TOP
#
(
.FAMILY
(
FAMILY
)
,
.TABITS
(
TABITS
)
,
.RABITS
(
RABITS
)
,
.MCXMAC_SAL_ON
(
MCXMAC_SAL_ON
)
,
.MCXMAC_WOL_ON
(
MCXMAC_WOL_ON
)
,
.MCXMAC_STATS_ON
(
MCXMAC_STATS_ON
)
,
.CORETSEI
(
0
)
,
.CORETSEO
(
0
)
,
.CORETSEIi0I
(
0
)
,
.CORETSEoO00
(
0
)
,
.CORETSEo1llI
(
1
)
,
.CORETSEi1llI
(
2
)
,
.CORETSEOollI
(
1
)
,
.CORETSEIollI
(
2
)
,
.CORETSElollI
(
18
)
,
.CORETSEoollI
(
18
)
,
.CORETSEiollI
(
5
)
,
.CORETSEOillI
(
5
)
)
CORETSEIoilI
(
.CORETSEOIl0
(
TXCLK_I
)
,
.CORETSEoIl0
(
RXCLK_I
)
,
.CORETSElillI
(
RSTBP_I
)
,
.CORETSEoillI
(
CORETSElI
)
,
.CORETSEiillI
(
CORETSEii0I
)
,
.CORETSEOO0lI
(
CORETSEi
)
,
.CORETSEIO0lI
(
CORETSEOI
)
,
.CORETSElO0lI
(
CORETSEII
)
,
.CORETSEoO0lI
(
CORETSEIIII
)
,
.CORETSEiO0lI
(
CORETSEOloI
)
,
.CORETSEOI0lI
(
CORETSEoIII
)
,
.CORETSEloilI
(
HRESET_NI
)
,
.CORETSEoO0II
(
HCLK_I
)
,
.CORETSEooilI
(
AHBS_HREADY_I
)
,
.CORETSEioilI
(
AHBS_HWDATA_I
)
,
.CORETSEOiilI
(
AHBS_HADDR_I
[
9
:
2
]
)
,
.CORETSEIiilI
(
AHBS_HSEL_I
)
,
.CORETSEliilI
(
AHBS_HTRANS_I
)
,
.CORETSEoiilI
(
AHBS_HWRITE_I
)
,
.CORETSEiiilI
(
AHBS_HRDATA_O
)
,
.CORETSEOOO0I
(
AHBS_HRESP_O
)
,
.CORETSEIOO0I
(
AHBS_HREADY_O
)
,
.CORETSElOO0I
(
AHBM_TXHGRANT_I
)
,
.CORETSEoOO0I
(
AHBM_TXHREADY_I
)
,
.CORETSEiOO0I
(
AHBM_TXHRESPM_I
)
,
.CORETSEOIO0I
(
AHBM_TXHRDATAM_I
)
,
.CORETSEIIO0I
(
AHBM_TXHSEL_O
)
,
.CORETSElIO0I
(
AHBM_TXHTRANSM_O
)
,
.CORETSEoIO0I
(
AHBM_TXHADDRM_O
[
31
:
2
]
)
,
.CORETSEiIO0I
(
AHBM_TXHWRITEM_O
)
,
.CORETSEOlO0I
(
AHBM_TXHWDATAM_O
)
,
.CORETSEIlO0I
(
AHBM_RXHGRANT_I
)
,
.CORETSEllO0I
(
AHBM_RXHREADY_I
)
,
.CORETSEolO0I
(
AHBM_RXHRESPM_I
)
,
.CORETSEilO0I
(
AHBM_RXHRDATAM_I
)
,
.CORETSEO0O0I
(
AHBM_RXHSEL_O
)
,
.CORETSEI0O0I
(
AHBM_RXHTRANSM_O
)
,
.CORETSEl0O0I
(
AHBM_RXHADDRM_O
[
31
:
2
]
)
,
.CORETSEo0O0I
(
AHBM_RXHWRITEM_O
)
,
.CORETSEi0O0I
(
AHBM_RXHWDATAM_O
)
,
.CORETSEII0lI
(
CORETSEI1ilI
)
,
.CORETSEoI0lI
(
CORETSEl1ilI
)
,
.CORETSEiI0lI
(
CORETSEo1ilI
)
,
.CORETSEOl0lI
(
CORETSEi1ilI
)
,
.CORETSEl10lI
(
CORETSEOiIlI
)
,
.CORETSEo10lI
(
CORETSEIiIlI
)
,
.CORETSEi10lI
(
CORETSEliIlI
)
,
.CORETSEOo0lI
(
CORETSEoiIlI
)
,
.CORETSEIo0lI
(
CORETSEiiIlI
)
,
.CORETSElo0lI
(
CORETSEOOllI
)
,
.CORETSEoo0lI
(
CORETSEIOllI
)
,
.CORETSEio0lI
(
CORETSElOllI
)
,
.CORETSEOi0lI
(
CORETSEoOllI
)
,
.CORETSEIi0lI
(
CORETSEiOllI
)
,
.CORETSEli0lI
(
CORETSEOIllI
)
,
.CORETSEoi0lI
(
CORETSEIIllI
)
,
.CORETSEii0lI
(
CORETSElIllI
)
,
.CORETSEOO1lI
(
CORETSEoIllI
)
,
.CORETSEo0llI
(
CORETSEo0llI
)
,
.CORETSEIl1lI
(
CORETSEIl1lI
)
,
.CORETSEll1lI
(
CORETSEll1lI
)
,
.CORETSEol1lI
(
CORETSEol1lI
)
,
.CORETSEil1lI
(
)
,
.CORETSEO01lI
(
)
,
.CORETSEI01lI
(
)
,
.CORETSEoO1lI
(
)
,
.CORETSEiO1lI
(
)
,
.CORETSEOI1lI
(
)
,
.CORETSEIO1lI
(
)
,
.CORETSElO1lI
(
)
,
.CORETSEII1lI
(
)
,
.CORETSElI1lI
(
)
,
.CORETSEoI1lI
(
)
,
.CORETSEiI1lI
(
)
,
.CORETSEOl1lI
(
)
,
.CORETSEOl00
(
32
'b
0
)
,
.CORETSEI000
(
CORETSEli00
)
,
.CORETSEl1llI
(
CORETSEOoilI
)
)
;
CoreTSE_M2S090_CORETSE_AHB_0_TX2048X40
#
(
.TABITS
(
TABITS
)
)
CORETSEO1O0I
(
.clk_wr
(
CORETSEOiIlI
)
,
.clk_rd
(
CORETSEIiIlI
)
,
.weL
(
CORETSEliIlI
)
,
.a_wr
(
CORETSEoiIlI
)
,
.din
(
CORETSEiiIlI
)
,
.a_rd
(
CORETSEOOllI
)
,
.dout
(
CORETSEIOllI
)
)
;
CoreTSE_M2S090_CORETSE_AHB_0_RX4096X36
#
(
.RABITS
(
RABITS
)
)
CORETSEI1O0I
(
.clk_wr
(
CORETSElOllI
)
,
.clk_rd
(
CORETSEoOllI
)
,
.weL
(
CORETSEiOllI
)
,
.a_wr
(
CORETSEOIllI
)
,
.din
(
CORETSEIIllI
)
,
.a_rd
(
CORETSElIllI
)
,
.dout
(
CORETSEoIllI
)
)
;
generate
if
(
GMII_TBI
==
1
)
begin
:
CORETSEi01lI
reg
[
8
:
0
]
CORETSEl1O0I
;
assign
TBI_TXVAL_O
=
CORETSEl1O0I
[
8
]
;
always
@
(
posedge
TBI_TX_CLK
)
CORETSEl1O0I
<=
{
CORETSEl1O0I
[
7
:
0
]
,
TBI_READY_I
}
;
CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_CORE
#
(
.CORETSEI
(
0
)
,
.MDIO_PHYID
(
MDIO_PHYID
)
,
.SLIP_ENABLE
(
SLIP_ENABLE
)
)
CORETSEo1O0I
(
.CORETSEoO0II
(
HCLK_I
)
,
.CORETSEI10i
(
~
HRESET_NI
)
,
.CORETSElI0II
(
TBI_TX_CLK
)
,
.CORETSEIli0
(
TXCLK_I
)
,
.CORETSEoli0
(
RXCLK_I
)
,
.CORETSElIOI
(
TBI_RX_CLK
)
,
.CORETSEoI0II
(
1
'b
0
)
,
.CORETSEO00II
(
)
,
.CORETSEiI0II
(
1
'b
0
)
,
.CORETSEIIOI
(
1
'b
0
)
,
.CORETSEOIOI
(
1
'b
0
)
,
.CORETSEol0II
(
)
,
.CORETSEil0II
(
)
,
.CORETSEolOI
(
)
,
.CORETSEllOI
(
)
,
.CORETSEiioII
(
)
,
.CORETSEIlOI
(
RSTBP_I
)
,
.CORETSEI0II
(
TSMAC_TCG_O
)
,
.CORETSEOloI
(
CORETSEOloI
)
,
.CORETSEIIII
(
CORETSEIIII
)
,
.CORETSEoIII
(
CORETSEoIII
)
,
.CORETSEi010
(
TSMAC_RCG_I
)
,
.CORETSEOI
(
CORETSEOI
)
,
.CORETSEi
(
CORETSEi
)
,
.CORETSEII
(
CORETSEII
)
,
.CORETSEII1II
(
CORETSEii0I
)
,
.CORETSElI
(
CORETSElI
)
,
.CORETSEoOiII
(
)
,
.CORETSEO110
(
SIGNAL_DETECT_I
)
,
.CORETSEoo10
(
CORETSEI1ilI
)
,
.CORETSEI110
(
CORETSEl1ilI
)
,
.CORETSEl110
(
CORETSEo1ilI
)
,
.CORETSEo110
(
CORETSEi1ilI
)
,
.CORETSEi110
(
MGMT_MDI_I
)
,
.CORETSEli0II
(
CORETSEo0llI
)
,
.CORETSEiOiII
(
ANX_STATE_O
)
,
.CORETSEOIol
(
SYNC_O
)
,
.CORETSEIOo0
(
RUDINV
)
,
.CORETSElOo0
(
TBI_READY_I
)
,
.RX_SLIP
(
RX_SLIP
)
,
.TBI_RX_VALID
(
CORETSEO1ilI
)
)
;
end
else
begin
assign
TBI_TXVAL_O
=
1
'b
0
;
assign
TSMAC_TXD_O
=
CORETSEOloI
;
assign
TSMAC_TXEN_O
=
CORETSEIIII
;
assign
TSMAC_TXER_O
=
CORETSEoIII
;
assign
CORETSEOI
=
TSMAC_RXD_I
;
assign
CORETSEi
=
TSMAC_RXDV_I
;
assign
CORETSEII
=
TSMAC_RXER_I
;
assign
CORETSElI
=
TSMAC_CRS_I
;
assign
CORETSEii0I
=
TSMAC_COL_I
;
assign
CORETSEI1ilI
=
MGMT_MDI_I
;
end
endgenerate
endmodule
