set_device -family {SmartFusion2} -die {M2S090TS}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\msgmii_clkrst.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\msgmii_cnvrxi.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\msgmii_cnvrxo.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\msgmii_cnvtxi.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\msgmii_cnvtxo.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\peanx_sync.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\msgmii_peanx_top.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\r10b8b.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perex_pcs.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perex_pma.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petbm.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petcr.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\t8b10b.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petex_top.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\msgmii_tbi.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\msgmii_core.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\rx4096x36.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxfif_clkrst.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxfif_hst.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxrfif_fab.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxrfif_sys.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxtfif_fab.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxtfif_sys.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxtfif_wtm.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\amcxfif.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\arfque.v}
 add_include_path  {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\decoder.v}
 add_include_path  {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\dmarx.v}
 add_include_path  {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\dmatx.v}
 add_include_path  {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\dma_dual.v}
 add_include_path  {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\slave.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\tsm_sysreg.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\mahbe_dual.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\mmcxwol.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_cntrl.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_eim.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_ladd.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_linc.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_sadd.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_sinc.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_sinchd.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_sincnf.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat_store.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemstat.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pecar.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pehst.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pemgt.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pecrc.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\perfn_top.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\permc_top.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petfn_top.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\petmc_top.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pe_mcxmac_core.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\pe_mcxmac.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\sib_sync_2flp.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\sib_sync_pulse.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\si_sal.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\tsmac_ahb_top.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\tx2048x40.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\CoreTSE_AHB_top.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CORETSE_AHB_0\rtl\vlog\obfuscated\CoreTSE_AHB.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\FCCC_0\CoreTSE_M2S090_FCCC_0_FCCC.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\FCCC_1\CoreTSE_M2S090_FCCC_1_FCCC.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\FCCC_2\CoreTSE_M2S090_FCCC_2_FCCC.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\FCCC_3\CoreTSE_M2S090_FCCC_3_FCCC.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090_MSS\CoreTSE_M2S090_MSS.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\OSC_0\CoreTSE_M2S090_OSC_0_OSC.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\SERDES_IF2_0\CoreTSE_M2S090_SERDES_IF2_0_SERDES_IF2.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\hdl\MON_ANX.v}
read_verilog -mode verilog_2k -lib COREAHBLITE_LIB {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v}
read_verilog -mode verilog_2k -lib COREAHBLITE_LIB {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v}
read_verilog -mode verilog_2k -lib COREAHBLITE_LIB {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v}
read_verilog -mode verilog_2k -lib COREAHBLITE_LIB {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v}
read_verilog -mode verilog_2k -lib COREAHBLITE_LIB {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v}
read_verilog -mode verilog_2k -lib COREAHBLITE_LIB {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v}
read_verilog -mode verilog_2k -lib COREAHBLITE_LIB {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v}
read_verilog -mode verilog_2k -lib COREAHBLSRAM_LIB {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\AHBLSramIf.v}
read_verilog -mode verilog_2k -lib COREAHBLSRAM_LIB {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v}
read_verilog -mode verilog_2k -lib COREAHBLSRAM_LIB {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\usram_128to9216x8.v}
read_verilog -mode verilog_2k -lib COREAHBLSRAM_LIB {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v}
read_verilog -mode verilog_2k -lib COREAHBLSRAM_LIB {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v}
read_verilog -mode verilog_2k {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\CoreTSE_M2S090.v}
set_top_level {CoreTSE_M2S090}
read_sdc -component {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\FCCC_0\CoreTSE_M2S090_FCCC_0_FCCC.sdc}
read_sdc -component {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\FCCC_1\CoreTSE_M2S090_FCCC_1_FCCC.sdc}
read_sdc -component {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\FCCC_2\CoreTSE_M2S090_FCCC_2_FCCC.sdc}
read_sdc -component {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\FCCC_3\CoreTSE_M2S090_FCCC_3_FCCC.sdc}
read_sdc -component {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\OSC_0\CoreTSE_M2S090_OSC_0_OSC.sdc}
read_sdc -component {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090\SERDES_IF2_0\CoreTSE_M2S090_SERDES_IF2_0_SERDES_IF2.sdc}
read_sdc -component {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\component\work\CoreTSE_M2S090_MSS\CoreTSE_M2S090_MSS.sdc}
derive_constraints
write_sdc {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\constraint\CoreTSE_M2S090_derived_constraints.sdc}
write_pdc {D:\11.8\m2s_dg0637_liberov11p7sp2__df\Libero\CoreTSE_M2S090\constraint\fp\CoreTSE_M2S090_derived_constraints.pdc}
