//                        Proprietary and Confidential                          
//                  Copyright (c) 2013 All Rights Reserved                     
// REVISION    : $Revision: 1.5 $                                                  
module
CoreTSE_M2S090_CORETSE_AHB_0_SIB_SYNC_2FLP
#
(
parameter
CORETSEO0I0
=
1
,
parameter
FAMILY
=
19
,
parameter
CORETSEI0I0
=
0
)
(
input
CORETSEo0I0,
input
CORETSEi0I0,
input
CORETSEO1I0,
input
CORETSEI1I0,
input
[
CORETSEO0I0
-
1
:
0
]
CORETSEl1I0,
output
[
CORETSEO0I0
-
1
:
0
]
CORETSEo1I0
)
;
reg
[
CORETSEO0I0
-
1
:
0
]
CORETSEOiI0
,
CORETSEIiI0
,
CORETSEliI0
;
wire
CORETSEoiI0
,
CORETSEiiI0
;
wire
CORETSEOOl0
,
CORETSEIOl0
;
integer
CORETSEolO0
;
assign
CORETSEoiI0
=
(
FAMILY
==
25
)
?
1
'b
0
:
CORETSEO1I0
;
assign
CORETSEOOl0
=
(
FAMILY
==
25
)
?
CORETSEO1I0
:
1
'b
0
;
assign
CORETSEiiI0
=
(
FAMILY
==
25
)
?
1
'b
0
:
CORETSEI1I0
;
assign
CORETSEIOl0
=
(
FAMILY
==
25
)
?
CORETSEI1I0
:
1
'b
0
;
generate
if
(
CORETSEI0I0
==
1
)
begin
:
CORETSElOl0
always
@
(
posedge
CORETSEo0I0
or
negedge
CORETSEoiI0
)
begin
if
(
~
(
CORETSEoiI0
||
CORETSEOOl0
)
)
CORETSEliI0
<=
0
;
else
CORETSEliI0
<=
CORETSEl1I0
;
end
always
@
(
posedge
CORETSEi0I0
or
negedge
CORETSEiiI0
)
begin
if
(
~
(
CORETSEiiI0
||
CORETSEIOl0
)
)
begin
CORETSEOiI0
<=
0
;
CORETSEIiI0
<=
0
;
end
else
begin
CORETSEOiI0
<=
CORETSEliI0
;
CORETSEIiI0
<=
CORETSEOiI0
;
end
end
end
else
begin
:
CORETSEoOl0
always
@
(
posedge
CORETSEo0I0
)
CORETSEliI0
<=
CORETSEl1I0
;
always
@
(
posedge
CORETSEi0I0
)
begin
CORETSEOiI0
<=
CORETSEliI0
;
CORETSEIiI0
<=
CORETSEOiI0
;
end
end
endgenerate
assign
CORETSEo1I0
=
CORETSEIiI0
;
endmodule
