//               centralization improves synthesis and layout development 
// REVISION    : $Revision: 1.1 $
// Mentor Graphics Corporation Proprietary and Confidential
// Copyright 2007 Mentor Graphics Corporation and Licensors
`timescale 1ps/1ps
module
CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_CLKRST
(
CORETSEoO0II
,
CORETSEiO0II
,
CORETSEOI0II
,
CORETSEII0II
,
CORETSEI10i
,
CORETSEIlOI
,
CORETSElI0II
,
CORETSEIli0
,
CORETSEoli0
,
CORETSEoI0II
,
CORETSEiI0II
,
CORETSEOl0II
,
CORETSEIl0II
,
CORETSEll0II
,
CORETSEol0II
,
CORETSEil0II
,
CORETSEO00II
)
;
input
CORETSEoO0II
;
input
CORETSEiO0II
;
input
CORETSEOI0II
;
output
CORETSEII0II
;
input
CORETSEI10i
;
input
CORETSEIlOI
;
input
CORETSElI0II
;
input
CORETSEIli0
;
input
CORETSEoli0
;
input
CORETSEoI0II
;
input
CORETSEiI0II
;
output
CORETSEOl0II
;
output
CORETSEIl0II
;
output
CORETSEll0II
;
output
CORETSEol0II
;
output
CORETSEil0II
;
output
CORETSEO00II
;
`define CORETSEOII  \
# \
1
reg
CORETSEI00II
;
reg
CORETSEl00II
;
reg
CORETSEo00II
;
reg
CORETSEi00II
;
reg
CORETSEO10II
;
reg
CORETSEI10II
;
reg
CORETSEl10II
;
reg
CORETSEo10II
;
reg
CORETSEi10II
;
reg
CORETSEOo0II
;
reg
CORETSEIo0II
;
reg
CORETSElo0II
;
wire
CORETSEoo0II
;
reg
CORETSEO00II
;
reg
CORETSEio0II
;
reg
CORETSEOi0II
;
wire
CORETSEIi0II
;
assign
CORETSEII0II
=
CORETSEOi0II
;
always
@
(
posedge
CORETSEoO0II
)
begin
if
(
CORETSEOI0II
)
CORETSEio0II
<=
`CORETSEOII
1
'b
0
;
else
CORETSEio0II
<=
`CORETSEOII
CORETSEiO0II
;
end
assign
CORETSEIi0II
=
(
CORETSEiO0II
&
~
CORETSEio0II
)
?
1
'b
0
:
CORETSEOi0II
;
always
@
(
posedge
CORETSEoO0II
)
begin
if
(
CORETSEOI0II
)
CORETSEOi0II
<=
`CORETSEOII
1
'b
1
;
else
CORETSEOi0II
<=
`CORETSEOII
CORETSEIi0II
;
end
always
@
(
posedge
CORETSElI0II
)
begin
CORETSEI00II
<=
`CORETSEOII
CORETSEI10i
;
end
always
@
(
posedge
CORETSElI0II
)
begin
CORETSEl00II
<=
`CORETSEOII
CORETSEI00II
;
end
assign
CORETSEOl0II
=
CORETSEIlOI
?
CORETSEI10i
:
(
CORETSEI10i
|
CORETSEl00II
)
;
always
@
(
posedge
CORETSEoli0
)
begin
CORETSEO10II
<=
`CORETSEOII
CORETSEI10i
;
end
always
@
(
posedge
CORETSEoli0
)
begin
CORETSEI10II
<=
`CORETSEOII
CORETSEO10II
;
end
assign
CORETSEll0II
=
CORETSEIlOI
?
CORETSEI10i
:
(
CORETSEI10i
|
CORETSEI10II
)
;
always
@
(
posedge
CORETSEIli0
)
begin
CORETSEo00II
<=
`CORETSEOII
CORETSEI10i
;
end
always
@
(
posedge
CORETSEIli0
)
begin
CORETSEi00II
<=
`CORETSEOII
CORETSEo00II
;
end
assign
CORETSEIl0II
=
CORETSEIlOI
?
CORETSEI10i
:
(
CORETSEI10i
|
CORETSEi00II
)
;
always
@
(
posedge
CORETSEoI0II
)
begin
CORETSEl10II
<=
`CORETSEOII
CORETSEI10i
;
end
always
@
(
posedge
CORETSEoI0II
)
begin
CORETSEo10II
<=
`CORETSEOII
CORETSEl10II
;
end
assign
CORETSEol0II
=
CORETSEIlOI
?
CORETSEI10i
:
(
CORETSEI10i
|
CORETSEo10II
)
;
always
@
(
posedge
CORETSEiI0II
)
begin
CORETSEi10II
<=
`CORETSEOII
CORETSEI10i
;
end
always
@
(
posedge
CORETSEiI0II
)
begin
CORETSEOo0II
<=
`CORETSEOII
CORETSEi10II
;
end
assign
CORETSEil0II
=
CORETSEIlOI
?
CORETSEI10i
:
(
CORETSEI10i
|
CORETSEOo0II
)
;
always
@
(
negedge
CORETSEiI0II
)
begin
CORETSEIo0II
<=
`CORETSEOII
CORETSEI10i
;
end
always
@
(
negedge
CORETSEiI0II
)
begin
CORETSElo0II
<=
`CORETSEOII
CORETSEIo0II
;
end
assign
CORETSEoo0II
=
CORETSEIlOI
?
CORETSEI10i
:
(
CORETSEI10i
|
CORETSElo0II
)
;
always
@
(
negedge
CORETSEiI0II
or
posedge
CORETSEoo0II
)
begin
if
(
CORETSEoo0II
)
CORETSEO00II
<=
`CORETSEOII
1
'b
0
;
else
CORETSEO00II
<=
`CORETSEOII
~
CORETSEO00II
;
end
endmodule
