// REVISION    : $Revision: 1.1 $
// Mentor Graphics Corporation Proprietary and Confidential
// Copyright 2007 Mentor Graphics Corporation and Licensors
`timescale 1ps/1ps
module
CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_CNVTXO
(
CORETSEOl0II
,
CORETSElI0II
,
CORETSEli0II
,
CORETSEoIoII
,
CORETSEiIoII
,
CORETSEOloII
,
CORETSEIloII
,
CORETSElloII
,
CORETSElIoII
,
CORETSElioII
,
CORETSEIO1II
,
CORETSEoioII
,
CORETSEiioII
)
;
parameter
FAMILY
=
19
;
input
CORETSEOl0II
;
input
CORETSElI0II
;
input
[
1
:
0
]
CORETSEli0II
;
input
[
7
:
0
]
CORETSEoIoII
;
input
CORETSEiIoII
;
input
CORETSEOloII
;
input
CORETSEIloII
;
input
[
2
:
0
]
CORETSElloII
;
output
[
2
:
0
]
CORETSElIoII
;
output
[
7
:
0
]
CORETSElioII
;
output
CORETSEIO1II
;
output
CORETSEoioII
;
output
CORETSEiioII
;
`define CORETSEOII  \
# \
1
reg
[
2
:
0
]
CORETSElIoII
;
reg
[
7
:
0
]
CORETSElioII
;
reg
CORETSEIO1II
;
reg
CORETSEoioII
;
reg
[
2
:
0
]
CORETSEIioII
;
reg
CORETSEOOiII
;
wire
CORETSEIOiII
;
reg
[
6
:
0
]
CORETSEol1II
;
wire
CORETSElOiII
;
reg
CORETSEiioII
;
wire
CORETSElo1
;
wire
CORETSEoo1
;
assign
CORETSElo1
=
(
FAMILY
==
25
)
?
1
'b
0
:
CORETSEOl0II
;
assign
CORETSEoo1
=
(
FAMILY
==
25
)
?
CORETSEOl0II
:
1
'b
0
;
always
@
(
posedge
CORETSElI0II
or
posedge
CORETSElo1
)
begin
if
(
CORETSEoo1
||
CORETSElo1
)
CORETSEIioII
<=
`CORETSEOII
3
'h
0
;
else
CORETSEIioII
<=
`CORETSEOII
{
CORETSEIioII
[
1
:
0
]
,
CORETSEIloII
}
;
end
always
@
(
posedge
CORETSElI0II
or
posedge
CORETSElo1
)
begin
if
(
CORETSEoo1
||
CORETSElo1
)
CORETSEOOiII
<=
`CORETSEOII
1
'b
0
;
else
if
(
CORETSElOiII
)
CORETSEOOiII
<=
`CORETSEOII
1
'b
0
;
else
if
(
CORETSEIioII
[
2
:
1
]
==
2
'b
01
)
CORETSEOOiII
<=
`CORETSEOII
1
'b
1
;
end
assign
CORETSEIOiII
=
(
(
CORETSEIioII
[
2
:
1
]
==
2
'b
01
)
|
CORETSEOOiII
)
&
~
CORETSEiIoII
;
always
@
(
posedge
CORETSElI0II
or
posedge
CORETSElo1
)
begin
if
(
CORETSEoo1
||
CORETSElo1
)
CORETSEol1II
<=
`CORETSEOII
7
'd
00
;
else
if
(
(
CORETSEli0II
==
2
'b
00
)
&
CORETSElOiII
)
CORETSEol1II
<=
`CORETSEOII
7
'd
99
;
else
if
(
(
CORETSEli0II
==
2
'b
01
)
&
CORETSElOiII
)
CORETSEol1II
<=
`CORETSEOII
7
'd
09
;
else
if
(
CORETSEli0II
==
2
'b
10
)
CORETSEol1II
<=
`CORETSEOII
7
'd
00
;
else
CORETSEol1II
<=
`CORETSEOII
CORETSEol1II
-
7
'h
1
;
end
assign
CORETSElOiII
=
(
CORETSEol1II
==
7
'h
00
)
;
always
@
(
posedge
CORETSElI0II
or
posedge
CORETSElo1
)
begin
if
(
CORETSEoo1
||
CORETSElo1
)
CORETSElIoII
<=
`CORETSEOII
3
'h
0
;
else
if
(
CORETSElOiII
&
CORETSEIOiII
)
CORETSElIoII
<=
`CORETSEOII
CORETSElloII
;
else
if
(
CORETSElOiII
)
CORETSElIoII
<=
`CORETSEOII
CORETSElIoII
+
3
'h
1
;
end
always
@
(
posedge
CORETSElI0II
or
posedge
CORETSElo1
)
begin
if
(
CORETSEoo1
||
CORETSElo1
)
CORETSEiioII
<=
`CORETSEOII
1
'b
0
;
else
CORETSEiioII
<=
`CORETSEOII
~
CORETSEiioII
;
end
always
@
(
posedge
CORETSElI0II
or
posedge
CORETSElo1
)
begin
if
(
CORETSEoo1
||
CORETSElo1
)
CORETSElioII
<=
`CORETSEOII
8
'h
0
;
else
CORETSElioII
<=
`CORETSEOII
CORETSEoIoII
;
end
always
@
(
posedge
CORETSElI0II
or
posedge
CORETSElo1
)
begin
if
(
CORETSEoo1
||
CORETSElo1
)
CORETSEIO1II
<=
`CORETSEOII
1
'b
0
;
else
CORETSEIO1II
<=
`CORETSEOII
CORETSEiIoII
;
end
always
@
(
posedge
CORETSElI0II
or
posedge
CORETSElo1
)
begin
if
(
CORETSEoo1
||
CORETSElo1
)
CORETSEoioII
<=
`CORETSEOII
1
'b
0
;
else
CORETSEoioII
<=
`CORETSEOII
CORETSEOloII
;
end
endmodule
