// REVISION    : $Revision: 1.1 $
// Mentor Graphics Corporation Proprietary and Confidential
// Copyright 2007 Mentor Graphics Corporation and Licensors
`timescale 1ps/1ps
module
CoreTSE_M2S090_CORETSE_AHB_0_MSGMII_CNVRXO
(
CORETSEll0II
,
CORETSEoli0
,
CORETSEli0II
,
CORETSEoO1II
,
CORETSEiO1II
,
CORETSEOI1II
,
CORETSElI1II
,
CORETSEoI1II
,
CORETSEOI
,
CORETSEi
,
CORETSEII
,
CORETSElO1II
)
;
parameter
FAMILY
=
19
;
input
CORETSEll0II
;
input
CORETSEoli0
;
input
[
1
:
0
]
CORETSEli0II
;
input
[
7
:
0
]
CORETSEoO1II
;
input
CORETSEiO1II
;
input
CORETSEOI1II
;
input
CORETSElI1II
;
input
[
3
:
0
]
CORETSEoI1II
;
output
[
7
:
0
]
CORETSEOI
;
output
CORETSEi
;
output
CORETSEII
;
output
[
3
:
0
]
CORETSElO1II
;
`define CORETSEOII  \
# \
1
reg
[
7
:
0
]
CORETSEOI
;
reg
CORETSEi
;
reg
CORETSEII
;
reg
[
3
:
0
]
CORETSElO1II
;
reg
CORETSEiOoII
;
reg
[
2
:
0
]
CORETSEOOoII
;
wire
CORETSEOIoII
;
wire
[
7
:
0
]
CORETSEIIoII
;
wire
CORETSElo1
;
wire
CORETSEoo1
;
assign
CORETSElo1
=
(
FAMILY
==
25
)
?
1
'b
0
:
CORETSEll0II
;
assign
CORETSEoo1
=
(
FAMILY
==
25
)
?
CORETSEll0II
:
1
'b
0
;
always
@
(
posedge
CORETSEoli0
or
posedge
CORETSElo1
)
begin
if
(
CORETSEoo1
||
CORETSElo1
)
CORETSEOOoII
<=
`CORETSEOII
3
'h
0
;
else
CORETSEOOoII
<=
`CORETSEOII
{
CORETSEOOoII
[
1
:
0
]
,
CORETSElI1II
}
;
end
assign
CORETSEOIoII
=
CORETSEOOoII
[
1
]
&
~
CORETSEOOoII
[
2
]
;
always
@
(
posedge
CORETSEoli0
or
posedge
CORETSElo1
)
begin
if
(
CORETSEoo1
||
CORETSElo1
)
CORETSEiOoII
<=
`CORETSEOII
1
'b
0
;
else
if
(
CORETSEOIoII
&
~
CORETSEiO1II
)
CORETSEiOoII
<=
`CORETSEOII
1
'b
1
;
else
CORETSEiOoII
<=
`CORETSEOII
~
CORETSEiOoII
;
end
always
@
(
posedge
CORETSEoli0
or
posedge
CORETSElo1
)
begin
if
(
CORETSEoo1
||
CORETSElo1
)
CORETSElO1II
<=
`CORETSEOII
4
'h
4
;
else
if
(
(
CORETSEli0II
==
2
'b
10
)
&
CORETSEOIoII
&
~
CORETSEiO1II
)
CORETSElO1II
<=
`CORETSEOII
{
CORETSEoI1II
[
2
:
0
]
,
1
'b
0
}
;
else
if
(
(
CORETSEli0II
!=
2
'b
10
)
&
CORETSEOIoII
&
~
CORETSEiO1II
)
CORETSElO1II
<=
`CORETSEOII
CORETSEoI1II
;
else
if
(
(
~
CORETSEiOoII
)
|
(
CORETSEli0II
==
2
'b
10
)
)
CORETSElO1II
<=
`CORETSEOII
CORETSElO1II
+
4
'h
1
;
end
assign
CORETSEIIoII
=
{
8
{
(
CORETSEli0II
==
2
'h
2
)
}
}
&
CORETSEoO1II
|
{
8
{
(
CORETSEli0II
!=
2
'h
2
)
&
CORETSEiOoII
}
}
&
{
4
'h
0
,
CORETSEoO1II
[
3
:
0
]
}
|
{
8
{
(
CORETSEli0II
!=
2
'h
2
)
&
~
CORETSEiOoII
}
}
&
{
4
'h
0
,
CORETSEoO1II
[
7
:
4
]
}
;
always
@
(
posedge
CORETSEoli0
or
posedge
CORETSElo1
)
begin
if
(
CORETSEoo1
||
CORETSElo1
)
CORETSEOI
<=
`CORETSEOII
8
'h
0
;
else
CORETSEOI
<=
`CORETSEOII
CORETSEIIoII
;
end
always
@
(
posedge
CORETSEoli0
or
posedge
CORETSElo1
)
begin
if
(
CORETSEoo1
||
CORETSElo1
)
CORETSEi
<=
`CORETSEOII
1
'b
0
;
else
CORETSEi
<=
`CORETSEOII
CORETSEiO1II
;
end
always
@
(
posedge
CORETSEoli0
or
posedge
CORETSElo1
)
begin
if
(
CORETSEoo1
||
CORETSElo1
)
CORETSEII
<=
`CORETSEOII
1
'b
0
;
else
CORETSEII
<=
`CORETSEOII
CORETSEOI1II
;
end
endmodule
