#Build: Synplify Pro (R) R-2020.09M-SP1-1, Build 100R, Feb 17 2021 #install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro #OS: Windows 8 6.2 #Hostname: HYD-LT-I62935 # Mon Jun 7 21:12:18 2021 #Implementation: synthesis Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys HDL Compiler, Version comp202009synp2, Build 102R, Built Feb 17 2021 10:19:36, @ @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Verilog Compiler, Version comp202009synp2, Build 147R, Built Mar 17 2021 10:14:42, @ @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @I::"C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro\lib\generic\smartfusion2.v" (library work) @I::"C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\work\Demo_sb\CCC_0\Demo_sb_CCC_0_FCCC.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\work\Demo_sb\FABOSC_0\Demo_sb_FABOSC_0_OSC.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\work\Demo_sb_MSS\Demo_sb_MSS.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_muxptob3.v" (library COREAPB3_LIB) @I::"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_iaddr_reg.v" (library COREAPB3_LIB) @I::"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v" (library COREAPB3_LIB) @I::"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\work\Demo_sb\Demo_sb.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\hdl\MUX4_4.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\work\top\FCCC_0\top_FCCC_0_FCCC.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\work\top\FCCC_1\top_FCCC_1_FCCC.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\work\top\SERDES_IF2_0\top_SERDES_IF2_0_SERDES_IF2_syn.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\work\top\SERDES_IF2_0\top_SERDES_IF2_0_SERDES_IF2.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_clockmux.v" (library CORESPI_LIB) @I::"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v" (library CORESPI_LIB) @W:CG1337 : spi_chanctrl.v(805) | Net resetn_rx_s is not declared. @I::"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v" (library CORESPI_LIB) @I::"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v" (library CORESPI_LIB) @N:CG347 : spi_rf.v(160) | Read a parallel_case directive. @N:CG347 : spi_rf.v(223) | Read a parallel_case directive. @I::"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_control.v" (library CORESPI_LIB) @N:CG347 : spi_control.v(69) | Read a parallel_case directive. @I::"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v" (library CORESPI_LIB) @I::"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v" (library CORESPI_LIB) @I::"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\work\top\top.v" (library work) Verilog syntax check successful! Options changed - recompiling Selecting top level module top @N:CG775 : corespi.v(27) | Component CORESPI not found in library "work" or "__hyper__lib__", but found in library CORESPI_LIB @N:CG364 : smartfusion2.v(126) | Synthesizing module AND2 in library work. Running optimization stage 1 on AND2 ....... Finished optimization stage 1 on AND2 (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB) @N:CG364 : smartfusion2.v(286) | Synthesizing module BIBUF in library work. Running optimization stage 1 on BIBUF ....... Finished optimization stage 1 on BIBUF (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB) @N:CG364 : spi_rf.v(31) | Synthesizing module spi_rf in library CORESPI_LIB. APB_DWIDTH=32'b00000000000000000000000000100000 CFG_CLK=32'b00000000000000000000000000001001 ZEROS=32'b00000000000000000000000000000000 Generated name = spi_rf_32s_9s_0 Running optimization stage 1 on spi_rf_32s_9s_0 ....... @W:CL208 : spi_rf.v(134) | All reachable assignments to bit 3 of control2[7:0] assign 0, register removed by optimization. Finished optimization stage 1 on spi_rf_32s_9s_0 (CPU Time 0h:00m:00s, Memory Used current: 97MB peak: 97MB) @N:CG364 : spi_control.v(24) | Synthesizing module spi_control in library CORESPI_LIB. CFG_FRAME_SIZE=32'b00000000000000000000000000001000 Generated name = spi_control_8s Running optimization stage 1 on spi_control_8s ....... Finished optimization stage 1 on spi_control_8s (CPU Time 0h:00m:00s, Memory Used current: 97MB peak: 97MB) @N:CG364 : spi_fifo.v(25) | Synthesizing module spi_fifo in library CORESPI_LIB. CFG_FRAME_SIZE=32'b00000000000000000000000000001000 CFG_FIFO_DEPTH=32'b00000000000000000000000000100000 PTR_WIDTH=32'b00000000000000000000000000000101 Generated name = spi_fifo_8s_32s_5 Running optimization stage 1 on spi_fifo_8s_32s_5 ....... Finished optimization stage 1 on spi_fifo_8s_32s_5 (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 100MB) @N:CG364 : spi_clockmux.v(24) | Synthesizing module spi_clockmux in library CORESPI_LIB. Running optimization stage 1 on spi_clockmux ....... Finished optimization stage 1 on spi_clockmux (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 100MB) @N:CG364 : spi_chanctrl.v(29) | Synthesizing module spi_chanctrl in library CORESPI_LIB. SPH=1'b0 SPO=1'b0 SPS=1'b1 CFG_MODE=32'b00000000000000000000000000000000 CFG_CLKRATE=32'b00000000000000000000000000001001 CFG_FRAME_SIZE=32'b00000000000000000000000000001000 CFG_FIFO_DEPTH=32'b00000000000000000000000000000100 MTX_IDLE1=4'b0000 MTX_IDLE2=4'b0001 MTX_MOTSTART=4'b0010 MTX_TISTART1=4'b0011 MTX_TISTART2=4'b0100 MTX_NSCSTART1=4'b0101 MTX_NSCSTART2=4'b0110 MTX_SHIFT1=4'b0111 MTX_SHIFT2=4'b1000 MTX_END=4'b1001 STXS_IDLE=1'b0 STXS_SHIFT=1'b1 MOTMODE=1'b1 TIMODE=1'b0 NSCMODE=1'b0 MOTNOSSEL=1'b1 NSCNOSSEL=1'b0 cfg_framesizeM1=32'b00000000000000000000000000000111 Generated name = spi_chanctrl_Z1 @W:CG1340 : spi_chanctrl.v(416) | Index into variable txfifo_dhold could be out of range ; a simulation mismatch is possible. @W:CG133 : spi_chanctrl.v(195) | Object resetn_rx_d is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : spi_chanctrl.v(196) | Removing wire resetn_rx_p, as there is no assignment to it. @W:CG360 : spi_chanctrl.v(200) | Removing wire resetn_rx_r, as there is no assignment to it. @W:CG133 : spi_chanctrl.v(222) | Object stxs_txready_at_ssel_temp is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on spi_chanctrl_Z1 ....... @W:CL169 : spi_chanctrl.v(1130) | Pruning unused register msrxs_ssel. Make sure that there are no unused intermediate registers. @W:CL169 : spi_chanctrl.v(823) | Pruning unused register stxs_oen. Make sure that there are no unused intermediate registers. @W:CL169 : spi_chanctrl.v(719) | Pruning unused register spi_ssel_neg. Make sure that there are no unused intermediate registers. @W:CL169 : spi_chanctrl.v(416) | Pruning unused register mtx_bitcnt[4:0]. Make sure that there are no unused intermediate registers. @W:CL169 : spi_chanctrl.v(416) | Pruning unused register mtx_ssel. Make sure that there are no unused intermediate registers. @W:CL177 : spi_chanctrl.v(343) | Sharing sequential element cfg_enable_P1. Add a syn_preserve attribute to the element to prevent sharing. Finished optimization stage 1 on spi_chanctrl_Z1 (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB) @N:CG364 : spi.v(29) | Synthesizing module spi in library CORESPI_LIB. APB_DWIDTH=32'b00000000000000000000000000100000 CFG_FRAME_SIZE=32'b00000000000000000000000000001000 CFG_FIFO_DEPTH=32'b00000000000000000000000000100000 CFG_CLK=32'b00000000000000000000000000001001 SPO=1'b0 SPH=1'b0 SPS=1'b1 CFG_MODE=32'b00000000000000000000000000000000 Generated name = spi_32s_8s_32s_9s_0_0_1_0s Running optimization stage 1 on spi_32s_8s_32s_9s_0_0_1_0s ....... Finished optimization stage 1 on spi_32s_8s_32s_9s_0_0_1_0s (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB) @N:CG364 : corespi.v(27) | Synthesizing module CORESPI in library CORESPI_LIB. APB_DWIDTH=32'b00000000000000000000000000100000 CFG_FRAME_SIZE=32'b00000000000000000000000000001000 CFG_FIFO_DEPTH=32'b00000000000000000000000000100000 CFG_CLK=32'b00000000000000000000000000001001 CFG_MODE=32'b00000000000000000000000000000000 CFG_MOT_MODE=32'b00000000000000000000000000000000 CFG_MOT_SSEL=32'b00000000000000000000000000000001 CFG_TI_NSC_CUSTOM=32'b00000000000000000000000000000000 CFG_TI_NSC_FRC=32'b00000000000000000000000000000000 CFG_TI_JMB_FRAMES=32'b00000000000000000000000000000000 CFG_NSC_OPERATION=32'b00000000000000000000000000000000 SPS=1'b1 SPO=1'b0 SPH=1'b0 Generated name = CORESPI_Z2 Running optimization stage 1 on CORESPI_Z2 ....... Finished optimization stage 1 on CORESPI_Z2 (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB) @N:CG775 : coreapb3.v(31) | Component CoreAPB3 not found in library "work" or "__hyper__lib__", but found in library COREAPB3_LIB @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC in library work. Running optimization stage 1 on VCC ....... Finished optimization stage 1 on VCC (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB) @N:CG364 : smartfusion2.v(372) | Synthesizing module GND in library work. Running optimization stage 1 on GND ....... Finished optimization stage 1 on GND (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB) @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT in library work. Running optimization stage 1 on CLKINT ....... Finished optimization stage 1 on CLKINT (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB) @N:CG364 : smartfusion2.v(729) | Synthesizing module CCC in library work. Running optimization stage 1 on CCC ....... Finished optimization stage 1 on CCC (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB) @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF in library work. Running optimization stage 1 on INBUF ....... Finished optimization stage 1 on INBUF (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB) @N:CG364 : Demo_sb_CCC_0_FCCC.v(5) | Synthesizing module Demo_sb_CCC_0_FCCC in library work. Running optimization stage 1 on Demo_sb_CCC_0_FCCC ....... Finished optimization stage 1 on Demo_sb_CCC_0_FCCC (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB) @N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3 in library COREAPB3_LIB. Running optimization stage 1 on COREAPB3_MUXPTOB3 ....... Finished optimization stage 1 on COREAPB3_MUXPTOB3 (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB) @N:CG364 : coreapb3.v(31) | Synthesizing module CoreAPB3 in library COREAPB3_LIB. APB_DWIDTH=6'b100000 IADDR_OPTION=32'b00000000000000000000000000000000 APBSLOT0ENABLE=1'b1 APBSLOT1ENABLE=1'b0 APBSLOT2ENABLE=1'b0 APBSLOT3ENABLE=1'b0 APBSLOT4ENABLE=1'b0 APBSLOT5ENABLE=1'b0 APBSLOT6ENABLE=1'b0 APBSLOT7ENABLE=1'b0 APBSLOT8ENABLE=1'b0 APBSLOT9ENABLE=1'b0 APBSLOT10ENABLE=1'b0 APBSLOT11ENABLE=1'b0 APBSLOT12ENABLE=1'b0 APBSLOT13ENABLE=1'b0 APBSLOT14ENABLE=1'b0 APBSLOT15ENABLE=1'b0 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 MADDR_BITS=6'b010000 UPR_NIBBLE_POSN=4'b0011 FAMILY=32'b00000000000000000000000000010011 SYNC_RESET=32'b00000000000000000000000000000000 IADDR_NOTINUSE=32'b00000000000000000000000000000000 IADDR_EXTERNAL=32'b00000000000000000000000000000001 IADDR_SLOT0=32'b00000000000000000000000000000010 IADDR_SLOT1=32'b00000000000000000000000000000011 IADDR_SLOT2=32'b00000000000000000000000000000100 IADDR_SLOT3=32'b00000000000000000000000000000101 IADDR_SLOT4=32'b00000000000000000000000000000110 IADDR_SLOT5=32'b00000000000000000000000000000111 IADDR_SLOT6=32'b00000000000000000000000000001000 IADDR_SLOT7=32'b00000000000000000000000000001001 IADDR_SLOT8=32'b00000000000000000000000000001010 IADDR_SLOT9=32'b00000000000000000000000000001011 IADDR_SLOT10=32'b00000000000000000000000000001100 IADDR_SLOT11=32'b00000000000000000000000000001101 IADDR_SLOT12=32'b00000000000000000000000000001110 IADDR_SLOT13=32'b00000000000000000000000000001111 IADDR_SLOT14=32'b00000000000000000000000000010000 IADDR_SLOT15=32'b00000000000000000000000000010001 SL0=16'b0000000000000001 SL1=16'b0000000000000000 SL2=16'b0000000000000000 SL3=16'b0000000000000000 SL4=16'b0000000000000000 SL5=16'b0000000000000000 SL6=16'b0000000000000000 SL7=16'b0000000000000000 SL8=16'b0000000000000000 SL9=16'b0000000000000000 SL10=16'b0000000000000000 SL11=16'b0000000000000000 SL12=16'b0000000000000000 SL13=16'b0000000000000000 SL14=16'b0000000000000000 SL15=16'b0000000000000000 SC=16'b0000000000000000 SC_qual=16'b0000000000000000 Generated name = CoreAPB3_Z3 @W:CG360 : coreapb3.v(244) | Removing wire IA_PRDATA, as there is no assignment to it. Running optimization stage 1 on CoreAPB3_Z3 ....... Finished optimization stage 1 on CoreAPB3_Z3 (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB) @N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP in library work. FAMILY=32'b00000000000000000000000000010011 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000001 VERSION_MAJOR=32'b00000000000000000000000000000111 VERSION_MINOR=32'b00000000000000000000000000000000 VERSION_MAJOR_VECTOR=16'b0000000000000111 VERSION_MINOR_VECTOR=16'b0000000000000000 S0=2'b00 S1=2'b01 S2=2'b10 Generated name = CoreConfigP_Z4 Running optimization stage 1 on CoreConfigP_Z4 ....... @W:CL207 : coreconfigp.v(461) | All reachable assignments to SDIF1_PENABLE assign 0, register removed by optimization. Finished optimization stage 1 on CoreConfigP_Z4 (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP in library work. FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000001 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z5 Running optimization stage 1 on CoreResetP_Z5 ....... @W:CL169 : coreresetp.v(1613) | Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1581) | Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1549) | Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1517) | Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1365) | Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1300) | Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1235) | Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1089) | Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers. @W:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : coreresetp.v(1089) | Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers. Finished optimization stage 1 on CoreResetP_Z5 (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) @N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF in library work. Running optimization stage 1 on TRIBUFF ....... Finished optimization stage 1 on TRIBUFF (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) @N:CG364 : Demo_sb_MSS_syn.v(5) | Synthesizing module MSS_075 in library work. Running optimization stage 1 on MSS_075 ....... Finished optimization stage 1 on MSS_075 (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) @N:CG364 : Demo_sb_MSS.v(9) | Synthesizing module Demo_sb_MSS in library work. Running optimization stage 1 on Demo_sb_MSS ....... Finished optimization stage 1 on Demo_sb_MSS (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB in library work. Running optimization stage 1 on RCOSC_25_50MHZ_FAB ....... Finished optimization stage 1 on RCOSC_25_50MHZ_FAB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ in library work. Running optimization stage 1 on RCOSC_25_50MHZ ....... Finished optimization stage 1 on RCOSC_25_50MHZ (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) @N:CG364 : Demo_sb_FABOSC_0_OSC.v(5) | Synthesizing module Demo_sb_FABOSC_0_OSC in library work. Running optimization stage 1 on Demo_sb_FABOSC_0_OSC ....... @W:CL318 : Demo_sb_FABOSC_0_OSC.v(15) | *Output RCOSC_25_50MHZ_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. Finished optimization stage 1 on Demo_sb_FABOSC_0_OSC (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) @N:CG364 : smartfusion2.v(720) | Synthesizing module SYSRESET in library work. Running optimization stage 1 on SYSRESET ....... Finished optimization stage 1 on SYSRESET (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) @N:CG364 : Demo_sb.v(9) | Synthesizing module Demo_sb in library work. Running optimization stage 1 on Demo_sb ....... Finished optimization stage 1 on Demo_sb (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) @N:CG364 : top_FCCC_0_FCCC.v(5) | Synthesizing module top_FCCC_0_FCCC in library work. Running optimization stage 1 on top_FCCC_0_FCCC ....... Finished optimization stage 1 on top_FCCC_0_FCCC (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) @N:CG364 : top_FCCC_1_FCCC.v(5) | Synthesizing module top_FCCC_1_FCCC in library work. Running optimization stage 1 on top_FCCC_1_FCCC ....... Finished optimization stage 1 on top_FCCC_1_FCCC (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) @N:CG364 : MUX4_4.v(21) | Synthesizing module MUX4_4 in library work. @W:CG296 : MUX4_4.v(25) | Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list. @W:CG290 : MUX4_4.v(30) | Referenced variable MSS_SPI0_DO is not in sensitivity list. @W:CG290 : MUX4_4.v(31) | Referenced variable MSS_SPI0_CLK is not in sensitivity list. @W:CG290 : MUX4_4.v(32) | Referenced variable MSS_SPI0_SS0 is not in sensitivity list. @W:CG290 : MUX4_4.v(37) | Referenced variable CoreSPI_D0 is not in sensitivity list. @W:CG290 : MUX4_4.v(38) | Referenced variable CoreSPI_CLK is not in sensitivity list. @W:CG290 : MUX4_4.v(39) | Referenced variable CoreSPI_SS0 is not in sensitivity list. Running optimization stage 1 on MUX4_4 ....... Finished optimization stage 1 on MUX4_4 (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) @N:CG364 : smartfusion2.v(320) | Synthesizing module INBUF_DIFF in library work. Running optimization stage 1 on INBUF_DIFF ....... Finished optimization stage 1 on INBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) @N:CG364 : top_SERDES_IF2_0_SERDES_IF2_syn.v(5) | Synthesizing module SERDESIF_075 in library work. Running optimization stage 1 on SERDESIF_075 ....... Finished optimization stage 1 on SERDESIF_075 (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) @N:CG364 : top_SERDES_IF2_0_SERDES_IF2.v(5) | Synthesizing module top_SERDES_IF2_0_SERDES_IF2 in library work. Running optimization stage 1 on top_SERDES_IF2_0_SERDES_IF2 ....... Finished optimization stage 1 on top_SERDES_IF2_0_SERDES_IF2 (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 103MB) @N:CG364 : top.v(9) | Synthesizing module top in library work. Running optimization stage 1 on top ....... Finished optimization stage 1 on top (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 103MB) Running optimization stage 2 on top ....... Finished optimization stage 2 on top (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 103MB) Running optimization stage 2 on top_SERDES_IF2_0_SERDES_IF2 ....... Finished optimization stage 2 on top_SERDES_IF2_0_SERDES_IF2 (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 103MB) Running optimization stage 2 on SERDESIF_075 ....... Finished optimization stage 2 on SERDESIF_075 (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 103MB) Running optimization stage 2 on INBUF_DIFF ....... Finished optimization stage 2 on INBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 103MB) Running optimization stage 2 on MUX4_4 ....... Finished optimization stage 2 on MUX4_4 (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 103MB) Running optimization stage 2 on top_FCCC_1_FCCC ....... Finished optimization stage 2 on top_FCCC_1_FCCC (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 103MB) Running optimization stage 2 on top_FCCC_0_FCCC ....... Finished optimization stage 2 on top_FCCC_0_FCCC (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 103MB) Running optimization stage 2 on Demo_sb ....... Finished optimization stage 2 on Demo_sb (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 103MB) Running optimization stage 2 on SYSRESET ....... Finished optimization stage 2 on SYSRESET (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 103MB) Running optimization stage 2 on Demo_sb_FABOSC_0_OSC ....... @N:CL159 : Demo_sb_FABOSC_0_OSC.v(14) | Input XTL is unused. Finished optimization stage 2 on Demo_sb_FABOSC_0_OSC (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 103MB) Running optimization stage 2 on RCOSC_25_50MHZ ....... Finished optimization stage 2 on RCOSC_25_50MHZ (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 103MB) Running optimization stage 2 on RCOSC_25_50MHZ_FAB ....... Finished optimization stage 2 on RCOSC_25_50MHZ_FAB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 103MB) Running optimization stage 2 on Demo_sb_MSS ....... Finished optimization stage 2 on Demo_sb_MSS (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 103MB) Running optimization stage 2 on MSS_075 ....... Finished optimization stage 2 on MSS_075 (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 103MB) Running optimization stage 2 on TRIBUFF ....... Finished optimization stage 2 on TRIBUFF (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 103MB) Running optimization stage 2 on CoreResetP_Z5 ....... @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state. Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state. Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state. Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state. Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state. Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @N:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused. @N:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused. @N:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused. @N:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused. @N:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused. @N:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused. @N:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused. @N:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused. @N:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused. @N:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused. @N:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused. @N:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused. @N:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused. @N:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused. Finished optimization stage 2 on CoreResetP_Z5 (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 103MB) Running optimization stage 2 on CoreConfigP_Z4 ....... @N:CL201 : coreconfigp.v(447) | Trying to extract state machine for register state. Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL159 : coreconfigp.v(71) | Input SDIF1_PREADY is unused. @N:CL159 : coreconfigp.v(72) | Input SDIF1_PSLVERR is unused. Finished optimization stage 2 on CoreConfigP_Z4 (CPU Time 0h:00m:00s, Memory Used current: 103MB peak: 113MB) Running optimization stage 2 on CoreAPB3_Z3 ....... @N:CL159 : coreapb3.v(72) | Input IADDR is unused. @N:CL159 : coreapb3.v(73) | Input PRESETN is unused. @N:CL159 : coreapb3.v(74) | Input PCLK is unused. @N:CL159 : coreapb3.v(105) | Input PRDATAS1 is unused. @N:CL159 : coreapb3.v(106) | Input PRDATAS2 is unused. @N:CL159 : coreapb3.v(107) | Input PRDATAS3 is unused. @N:CL159 : coreapb3.v(108) | Input PRDATAS4 is unused. @N:CL159 : coreapb3.v(109) | Input PRDATAS5 is unused. @N:CL159 : coreapb3.v(110) | Input PRDATAS6 is unused. @N:CL159 : coreapb3.v(111) | Input PRDATAS7 is unused. @N:CL159 : coreapb3.v(112) | Input PRDATAS8 is unused. @N:CL159 : coreapb3.v(113) | Input PRDATAS9 is unused. @N:CL159 : coreapb3.v(114) | Input PRDATAS10 is unused. @N:CL159 : coreapb3.v(115) | Input PRDATAS11 is unused. @N:CL159 : coreapb3.v(116) | Input PRDATAS12 is unused. @N:CL159 : coreapb3.v(117) | Input PRDATAS13 is unused. @N:CL159 : coreapb3.v(118) | Input PRDATAS14 is unused. @N:CL159 : coreapb3.v(119) | Input PRDATAS15 is unused. @N:CL159 : coreapb3.v(122) | Input PREADYS1 is unused. @N:CL159 : coreapb3.v(123) | Input PREADYS2 is unused. @N:CL159 : coreapb3.v(124) | Input PREADYS3 is unused. @N:CL159 : coreapb3.v(125) | Input PREADYS4 is unused. @N:CL159 : coreapb3.v(126) | Input PREADYS5 is unused. @N:CL159 : coreapb3.v(127) | Input PREADYS6 is unused. @N:CL159 : coreapb3.v(128) | Input PREADYS7 is unused. @N:CL159 : coreapb3.v(129) | Input PREADYS8 is unused. @N:CL159 : coreapb3.v(130) | Input PREADYS9 is unused. @N:CL159 : coreapb3.v(131) | Input PREADYS10 is unused. @N:CL159 : coreapb3.v(132) | Input PREADYS11 is unused. @N:CL159 : coreapb3.v(133) | Input PREADYS12 is unused. @N:CL159 : coreapb3.v(134) | Input PREADYS13 is unused. @N:CL159 : coreapb3.v(135) | Input PREADYS14 is unused. @N:CL159 : coreapb3.v(136) | Input PREADYS15 is unused. @N:CL159 : coreapb3.v(139) | Input PSLVERRS1 is unused. @N:CL159 : coreapb3.v(140) | Input PSLVERRS2 is unused. @N:CL159 : coreapb3.v(141) | Input PSLVERRS3 is unused. @N:CL159 : coreapb3.v(142) | Input PSLVERRS4 is unused. @N:CL159 : coreapb3.v(143) | Input PSLVERRS5 is unused. @N:CL159 : coreapb3.v(144) | Input PSLVERRS6 is unused. @N:CL159 : coreapb3.v(145) | Input PSLVERRS7 is unused. @N:CL159 : coreapb3.v(146) | Input PSLVERRS8 is unused. @N:CL159 : coreapb3.v(147) | Input PSLVERRS9 is unused. @N:CL159 : coreapb3.v(148) | Input PSLVERRS10 is unused. @N:CL159 : coreapb3.v(149) | Input PSLVERRS11 is unused. @N:CL159 : coreapb3.v(150) | Input PSLVERRS12 is unused. @N:CL159 : coreapb3.v(151) | Input PSLVERRS13 is unused. @N:CL159 : coreapb3.v(152) | Input PSLVERRS14 is unused. @N:CL159 : coreapb3.v(153) | Input PSLVERRS15 is unused. Finished optimization stage 2 on CoreAPB3_Z3 (CPU Time 0h:00m:00s, Memory Used current: 103MB peak: 113MB) Running optimization stage 2 on COREAPB3_MUXPTOB3 ....... Finished optimization stage 2 on COREAPB3_MUXPTOB3 (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 113MB) Running optimization stage 2 on Demo_sb_CCC_0_FCCC ....... Finished optimization stage 2 on Demo_sb_CCC_0_FCCC (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 113MB) Running optimization stage 2 on INBUF ....... Finished optimization stage 2 on INBUF (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 113MB) Running optimization stage 2 on CCC ....... Finished optimization stage 2 on CCC (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 113MB) Running optimization stage 2 on CLKINT ....... Finished optimization stage 2 on CLKINT (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 113MB) Running optimization stage 2 on GND ....... Finished optimization stage 2 on GND (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 113MB) Running optimization stage 2 on VCC ....... Finished optimization stage 2 on VCC (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 113MB) Running optimization stage 2 on CORESPI_Z2 ....... Finished optimization stage 2 on CORESPI_Z2 (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 113MB) Running optimization stage 2 on spi_32s_8s_32s_9s_0_0_1_0s ....... @W:CL246 : spi.v(70) | Input port bits 1 to 0 of PADDR[6:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on spi_32s_8s_32s_9s_0_0_1_0s (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 113MB) Running optimization stage 2 on spi_chanctrl_Z1 ....... @W:CL190 : spi_chanctrl.v(823) | Optimizing register bit stxs_bitsel[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : spi_chanctrl.v(823) | Pruning register bit 4 of stxs_bitsel[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL190 : spi_chanctrl.v(823) | Optimizing register bit stxs_bitsel[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : spi_chanctrl.v(823) | Pruning register bit 3 of stxs_bitsel[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL201 : spi_chanctrl.v(416) | Trying to extract state machine for register mtx_state. Extracted state machine for register mtx_state State machine has 6 reachable states with original encodings of: 0000 0001 0010 0111 1000 1001 @N:CL159 : spi_chanctrl.v(54) | Input txfifo_count is unused. @N:CL159 : spi_chanctrl.v(59) | Input rxfifo_count is unused. Finished optimization stage 2 on spi_chanctrl_Z1 (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 113MB) Running optimization stage 2 on spi_clockmux ....... Finished optimization stage 2 on spi_clockmux (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 113MB) Running optimization stage 2 on spi_fifo_8s_32s_5 ....... @N:CL134 : spi_fifo.v(101) | Found RAM fifo_mem_q, depth=32, width=1 @N:CL134 : spi_fifo.v(101) | Found RAM fifo_mem_q, depth=32, width=8 Finished optimization stage 2 on spi_fifo_8s_32s_5 (CPU Time 0h:00m:00s, Memory Used current: 105MB peak: 113MB) Running optimization stage 2 on spi_control_8s ....... @N:CL159 : spi_control.v(27) | Input aresetn is unused. @N:CL159 : spi_control.v(28) | Input sresetn is unused. @N:CL159 : spi_control.v(34) | Input cfg_master is unused. @N:CL159 : spi_control.v(35) | Input rx_fifo_empty is unused. @N:CL159 : spi_control.v(36) | Input tx_fifo_empty is unused. Finished optimization stage 2 on spi_control_8s (CPU Time 0h:00m:00s, Memory Used current: 105MB peak: 113MB) Running optimization stage 2 on spi_rf_32s_9s_0 ....... @W:CL246 : spi_rf.v(42) | Input port bits 31 to 8 of wrdata[31:0] are unused. Assign logic for all port bits or change the input port size. @N:CL159 : spi_rf.v(52) | Input tx_fifo_read is unused. @N:CL159 : spi_rf.v(55) | Input rx_fifo_full is unused. @N:CL159 : spi_rf.v(56) | Input rx_fifo_full_next is unused. @N:CL159 : spi_rf.v(58) | Input rx_fifo_empty_next is unused. @N:CL159 : spi_rf.v(61) | Input tx_fifo_full_next is unused. @N:CL159 : spi_rf.v(62) | Input tx_fifo_empty is unused. @N:CL159 : spi_rf.v(63) | Input tx_fifo_empty_next is unused. Finished optimization stage 2 on spi_rf_32s_9s_0 (CPU Time 0h:00m:00s, Memory Used current: 105MB peak: 113MB) Running optimization stage 2 on BIBUF ....... Finished optimization stage 2 on BIBUF (CPU Time 0h:00m:00s, Memory Used current: 105MB peak: 113MB) Running optimization stage 2 on AND2 ....... Finished optimization stage 2 on AND2 (CPU Time 0h:00m:00s, Memory Used current: 105MB peak: 113MB) For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 105MB peak: 113MB) Process took 0h:00m:07s realtime, 0h:00m:07s cputime Process completed successfully. # Mon Jun 7 21:12:26 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202009synp2, Build 102R, Built Feb 17 2021 10:19:36, @ @N: : | Running in 64-bit mode File C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\bin64\syn_nfilter.exe changed - recompiling File C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\synthesis\synwork\layer0.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Mon Jun 7 21:12:27 2021 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: top_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 24MB peak: 33MB) Process took 0h:00m:08s realtime, 0h:00m:08s cputime Process completed successfully. # Mon Jun 7 21:12:27 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202009synp2, Build 102R, Built Feb 17 2021 10:19:36, @ @N: : | Running in 64-bit mode File C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\bin64\syn_nfilter.exe changed - recompiling File C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\synthesis\synwork\top_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Mon Jun 7 21:12:28 2021 ###########################################################] Premap Report # Mon Jun 7 21:12:29 2021 Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Generic Technology Pre-mapping, Version map202009act, Build 069R, Built Mar 17 2021 10:25:05, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB) Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 131MB) Reading constraint file: C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\designer\top\synthesis.fdc Linked File: top_scck.rpt @W:MF499 : | Found issues with constraints. Check report file C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\synthesis\top_scck.rpt. @W:BN544 : synthesis.fdc(13) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology @W:BN544 : synthesis.fdc(14) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology @W:BN544 : synthesis.fdc(15) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology @W:BN544 : synthesis.fdc(16) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology @W:BN309 : | One or more non-fatal issues found in constraints; Please run Constraint Check for analysis @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 137MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 138MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) @W:BN132 : coreresetp.v(1089) | Removing sequential instance Demo_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance Demo_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MO111 : demo_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_sb_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_sb_fabosc_0_osc.v(15) | Tristate driver RCOSC_25_50MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net RCOSC_25_50MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @W:MO129 : coreresetp.v(676) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance Demo_sb_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance Demo_sb_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(1388) | Sequential instance Demo_sb_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation. @N:BN362 : spi_fifo.v(111) | Removing sequential instance full_next_out (in view: CORESPI_LIB.spi_fifo_8s_32s_5_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : spi_fifo.v(111) | Removing sequential instance empty_next_out (in view: CORESPI_LIB.spi_fifo_8s_32s_5_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : spi_fifo.v(111) | Removing sequential instance full_next_out (in view: CORESPI_LIB.spi_fifo_8s_32s_5_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : spi_fifo.v(111) | Removing sequential instance empty_next_out (in view: CORESPI_LIB.spi_fifo_8s_32s_5_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance MDDR_PENABLE (in view: work.CoreConfigP_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE (in view: work.CoreConfigP_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE (in view: work.CoreConfigP_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF3_PENABLE (in view: work.CoreConfigP_Z4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : spi_chanctrl.v(630) | Removing sequential instance mtx_spi_data_oen (in view: CORESPI_LIB.spi_chanctrl_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 (in view: work.CoreResetP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : spi_chanctrl.v(416) | Removing sequential instance mtx_oen (in view: CORESPI_LIB.spi_chanctrl_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:FX1184 : | Applying syn_allowed_resources blockrams=109 on top level netlist top Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB) @W:MT686 : synthesis.fdc(13) | No path from master pin (-source) to source of clock Demo_sb_0/CCC_0/GL0 @W:MT686 : synthesis.fdc(14) | No path from master pin (-source) to source of clock FCCC_0/GL0 @W:MT686 : synthesis.fdc(15) | No path from master pin (-source) to source of clock FCCC_0/GL1 @W:MT686 : synthesis.fdc(16) | No path from master pin (-source) to source of clock FCCC_1/GL0 Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 0 - CLK0_PAD 50.0 MHz 20.000 declared default_clkgroup 0 1 . Demo_sb_0/CCC_0/GL0 100.0 MHz 10.000 generated (from CLK0_PAD) default_clkgroup 282 0 - Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB 25.0 MHz 40.000 declared default_clkgroup 111 0 - Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 20.000 declared default_clkgroup 30 0 - SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] 125.0 MHz 8.000 declared default_clkgroup 0 1 . FCCC_0/GL0 62.5 MHz 16.000 generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup 1 1 . FCCC_0/GL1 62.5 MHz 16.000 generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup 1 0 - SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1] 125.0 MHz 8.000 declared default_clkgroup 0 1 . FCCC_1/GL0 125.0 MHz 8.000 generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]) default_clkgroup 1 0 - top_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 1 ============================================================================================================================================================================================ Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CLK0_PAD 0 CLK0_PAD(port) - - Demo_sb_0.CCC_0.CLK0_PAD_INST.I(IBUF) Demo_sb_0/CCC_0/GL0 282 Demo_sb_0.CCC_0.CCC_INST.GL0(CCC) Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST.CLK_BASE - Demo_sb_0.CCC_0.GL0_INST.I(BUFG) Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB 111 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST.CLK_CONFIG_APB(MSS_075) SERDES_IF2_0.SERDESIF_INST.APB_CLK - Demo_sb_0.CORECONFIGP_0.un1_FIC_2_APB_M_PCLK.I[0](inv) Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 30 Demo_sb_0.FABOSC_0.I_RCOSC_25_50MHZ.CLKOUT(RCOSC_25_50MHZ) Demo_sb_0.CORERESETP_0.count_sdif0_enable_q1.C - Demo_sb_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB.A(RCOSC_25_50MHZ_FAB) SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] 0 SERDES_IF2_0.SERDESIF_INST.EPCS_RXCLK[1](SERDESIF_075) - - - FCCC_0/GL0 1 FCCC_0.CCC_INST.GL0(CCC) Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST.RX_CLKPF - FCCC_0.GL0_INST.I(BUFG) FCCC_0/GL1 1 FCCC_0.CCC_INST.GL1(CCC) Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST.TX_CLKPF - FCCC_0.GL1_INST.I(BUFG) SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1] 0 SERDES_IF2_0.SERDESIF_INST.EPCS_TXCLK[1](SERDESIF_075) - - - FCCC_1/GL0 1 FCCC_1.CCC_INST.GL0(CCC) Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST.GTX_CLKPF - FCCC_1.GL0_INST.I(BUFG) top_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock 1 SERDES_IF2_0.refclk1_inbuf_diff.Y(INBUF_DIFF) SERDES_IF2_0.SERDESIF_INST.REFCLK1 - - ============================================================================================================================================================================================================================================================================ @W:MT530 : top_serdes_if2_0_serdes_if2.v(103) | Found inferred clock top_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock which controls 1 sequential elements including SERDES_IF2_0.SERDESIF_INST. This clock has no specified timing constraint which may adversely impact design performance. @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\synthesis\top.sap. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB) Encoding state machine mtx_state[5:0] (in view: CORESPI_LIB.spi_chanctrl_Z1(verilog)) original code -> new code 0000 -> 000001 0001 -> 000010 0010 -> 000100 0111 -> 001000 1000 -> 010000 1001 -> 100000 Encoding state machine state[2:0] (in view: work.CoreConfigP_Z4(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z5(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sdif0_state[3:0] (in view: work.CoreResetP_Z5(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : coreresetp.v(1170) | There are no possible illegal states for state machine sdif0_state[3:0] (in view: work.CoreResetP_Z5(verilog)); safe FSM implementation is not required. Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB) @W:MF511 : | Found issues with constraints. Please check constraint checker report "C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\synthesis\top_cck.rpt" . Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 89MB peak: 176MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Jun 7 21:12:31 2021 ###########################################################] Map & Optimize Report # Mon Jun 7 21:12:31 2021 Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Generic Technology Mapper, Version map202009act, Build 069R, Built Mar 17 2021 10:25:05, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 123MB peak: 130MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 130MB) @W:BN309 : | One or more non-fatal issues found in constraints; Please run Constraint Check for analysis Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 166MB peak: 166MB) @N:MO111 : demo_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_sb_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_sb_fabosc_0_osc.v(15) | Tristate driver RCOSC_25_50MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net RCOSC_25_50MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @W:BN132 : coreresetp.v(963) | Removing sequential instance Demo_sb_0.CORERESETP_0.sdif3_spll_lock_q1 because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif0_spll_lock_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(963) | Removing sequential instance Demo_sb_0.CORERESETP_0.sdif3_spll_lock_q2 because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif0_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance. #### START OF SSF LOG MESSAGES #### #### END OF SSF LOG MESSAGES #### Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB) @W:FX107 : spi_fifo.v(101) | RAM fifo_mem_q[8:0] (in view: CORESPI_LIB.spi_fifo_8s_32s_5_1(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. @W:FX107 : spi_fifo.v(101) | RAM fifo_mem_q[8:0] (in view: CORESPI_LIB.spi_fifo_8s_32s_5_0(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. Encoding state machine mtx_state[5:0] (in view: CORESPI_LIB.spi_chanctrl_Z1(verilog)) original code -> new code 0000 -> 000001 0001 -> 000010 0010 -> 000100 0111 -> 001000 1000 -> 010000 1001 -> 100000 @N:MO231 : spi_chanctrl.v(823) | Found counter in view:CORESPI_LIB.spi_chanctrl_Z1(verilog) instance stxs_bitcnt[4:0] @N:MO231 : spi_chanctrl.v(286) | Found counter in view:CORESPI_LIB.spi_chanctrl_Z1(verilog) instance spi_clk_count[7:0] Encoding state machine CORECONFIGP_0.state[2:0] (in view: work.Demo_sb(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @W:MO160 : coreconfigp.v(255) | Register bit CORECONFIGP_0.paddr[16] (in view view:work.Demo_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z5(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sdif0_state[3:0] (in view: work.CoreResetP_Z5(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : coreresetp.v(1170) | There are no possible illegal states for state machine sdif0_state[3:0] (in view: work.CoreResetP_Z5(verilog)); safe FSM implementation is not required. @N:MO231 : coreresetp.v(1485) | Found counter in view:work.CoreResetP_Z5(verilog) instance count_sdif0[12:0] @W:BN132 : coreresetp.v(1089) | Removing instance Demo_sb_0.CORERESETP_0.SDIF_READY_int because it is equivalent to instance Demo_sb_0.CORERESETP_0.sm0_state[6]. To keep the instance, apply constraint syn_preserve=1 on the instance. Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 174MB peak: 174MB) @W:BN132 : coreresetp.v(496) | Removing instance Demo_sb_0.CORERESETP_0.POWER_ON_RESET_N_q1 because it is equivalent to instance CORESPI_0.USPI.UCC.ssel_rx_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(496) | Removing instance Demo_sb_0.CORERESETP_0.POWER_ON_RESET_N_clk_base because it is equivalent to instance CORESPI_0.USPI.UCC.ssel_rx_q2. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:BN362 : coreresetp.v(1170) | Removing sequential instance Demo_sb_0.CORERESETP_0.SDIF0_CORE_RESET_N_0 (in view: work.top(verilog)) because it does not drive other instances. Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB) Available hyper_sources - for debug and ip models None Found Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 178MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 179MB peak: 179MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 179MB peak: 180MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 179MB peak: 180MB) @N:BN362 : spi_chanctrl.v(286) | Removing sequential instance CORESPI_0.USPI.UCC.spi_clk_next (in view: work.top(verilog)) because it does not drive other instances. Finished preparing to map (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 179MB peak: 180MB) Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 179MB peak: 180MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:03s -0.76ns 520 / 392 2 0h:00m:03s -0.76ns 500 / 392 3 0h:00m:03s -0.09ns 500 / 392 4 0h:00m:04s -0.07ns 515 / 392 5 0h:00m:04s 0.13ns 516 / 392 6 0h:00m:04s 0.13ns 516 / 392 @N:FP130 : | Promoting Net POWER_ON_RESET_N_arst on CLKINT I_253 @N:FP130 : | Promoting Net Demo_sb_0.FIC_2_APB_M_PRESET_N_arst on CLKINT I_254 @N:FP130 : | Promoting Net Demo_sb_0_INIT_APB_S_PCLK on CLKINT I_255 @N:FP130 : | Promoting Net CORESPI_0.USPI.UCC.un1_resetn_tx_i on CLKINT I_256 @N:FP130 : | Promoting Net Demo_sb_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT I_257 @N:FP130 : | Promoting Net Demo_sb_0.CORERESETP_0.sdif0_areset_n_rcosc on CLKINT I_258 @N:FP130 : | Promoting Net Demo_sb_0.CORERESETP_0.sm0_areset_n_arst on CLKINT I_259 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:05s; Memory used current: 184MB peak: 184MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 184MB peak: 185MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 3 non-gated/non-generated clock tree(s) driving 140 clock pin(s) of sequential element(s) 4 gated/generated clock tree(s) driving 260 clock pin(s) of sequential element(s) 0 instances converted, 260 sequential instances remain driven by gated/generated clocks ============================================================ Non-Gated/Non-Generated Clocks ============================================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0005 SERDES_IF2_0.refclk1_inbuf_diff INBUF_DIFF 1 SERDES_IF2_0.SERDESIF_INST ClockId0006 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST clock definition on MSS_075 109 Demo_sb_0.CORECONFIGP_0.soft_reset_reg[11] ClockId0007 Demo_sb_0.FABOSC_0.I_RCOSC_25_50MHZ clock definition on RCOSC_25_50MHZ 30 Demo_sb_0.CORERESETP_0.release_sdif0_core ========================================================================================================================================================= =============================================================================== Gated/Generated Clocks ================================================================================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 Demo_sb_0.CCC_0.CCC_INST CCC 257 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_075 ClockId0002 FCCC_0.CCC_INST CCC 1 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_075 ClockId0003 FCCC_0.CCC_INST CCC 1 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_075 ClockId0004 FCCC_1.CCC_INST CCC 1 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_075 ======================================================================================================================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 151MB peak: 185MB) Writing Analyst data base C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\synthesis\synwork\top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 183MB peak: 185MB) Writing Verilog Simulation files @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF @W:BW156 : | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 184MB peak: 185MB) Finished Writing Netlists (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 184MB peak: 185MB) Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 181MB peak: 185MB) @W:MT246 : top_fccc_1_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N:MT615 : | Found clock CLK0_PAD with period 20.00ns @N:MT615 : | Found clock Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB with period 40.00ns @N:MT615 : | Found clock Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT with period 20.00ns @N:MT615 : | Found clock SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] with period 8.00ns @N:MT615 : | Found clock SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1] with period 8.00ns @N:MT615 : | Found clock Demo_sb_0/CCC_0/GL0 with period 10.00ns @N:MT615 : | Found clock FCCC_0/GL0 with period 16.00ns @N:MT615 : | Found clock FCCC_0/GL1 with period 16.00ns @N:MT615 : | Found clock FCCC_1/GL0 with period 8.00ns @W:MT420 : | Found inferred clock top_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock with period 10.00ns. Please declare a user-defined clock on net SERDES_IF2_0.REFCLK1_OUT. ##### START OF TIMING REPORT #####[ # Timing report written on Mon Jun 7 21:12:38 2021 # Top view: top Requested Frequency: 25.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\designer\top\synthesis.fdc @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: 1.517 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CLK0_PAD 50.0 MHz NA 20.000 NA NA declared default_clkgroup Demo_sb_0/CCC_0/GL0 100.0 MHz 117.9 MHz 10.000 8.483 1.517 generated (from CLK0_PAD) default_clkgroup Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB 25.0 MHz 106.7 MHz 40.000 9.375 15.313 declared default_clkgroup Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 502.7 MHz 20.000 1.989 18.011 declared default_clkgroup FCCC_0/GL0 62.5 MHz NA 16.000 NA NA generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup FCCC_0/GL1 62.5 MHz NA 16.000 NA NA generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup FCCC_1/GL0 125.0 MHz NA 8.000 NA NA generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]) default_clkgroup SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] 125.0 MHz NA 8.000 NA NA declared default_clkgroup SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1] 125.0 MHz NA 8.000 NA NA declared default_clkgroup top_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_0 System 100.0 MHz NA 10.000 NA NA system system_clkgroup =============================================================================================================================================================================================================== Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB | 40.000 33.819 | No paths - | 20.000 18.228 | 20.000 15.313 Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB Demo_sb_0/CCC_0/GL0 | 10.000 False | No paths - | No paths - | No paths - Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 20.000 18.011 | No paths - | No paths - | No paths - Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Demo_sb_0/CCC_0/GL0 | 10.000 False | No paths - | No paths - | No paths - Demo_sb_0/CCC_0/GL0 Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB | 10.000 False | No paths - | No paths - | No paths - Demo_sb_0/CCC_0/GL0 Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 10.000 False | No paths - | No paths - | No paths - Demo_sb_0/CCC_0/GL0 Demo_sb_0/CCC_0/GL0 | 10.000 1.517 | No paths - | No paths - | No paths - ================================================================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: Demo_sb_0/CCC_0/GL0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------- Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST Demo_sb_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[14] Demo_sb_0_AMBA_SLAVE_0_PADDR[14] 3.012 1.517 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST Demo_sb_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[4] Demo_sb_0_AMBA_SLAVE_0_PADDR[4] 3.187 1.529 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST Demo_sb_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[13] Demo_sb_0_AMBA_SLAVE_0_PADDR[13] 3.017 1.549 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST Demo_sb_0/CCC_0/GL0 MSS_075 F_HM0_SEL Demo_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx 3.083 1.718 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST Demo_sb_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[3] Demo_sb_0_AMBA_SLAVE_0_PADDR[3] 3.035 1.861 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST Demo_sb_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[5] Demo_sb_0_AMBA_SLAVE_0_PADDR[5] 3.021 1.880 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST Demo_sb_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[12] Demo_sb_0_AMBA_SLAVE_0_PADDR[12] 3.046 1.881 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST Demo_sb_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[6] Demo_sb_0_AMBA_SLAVE_0_PADDR[6] 3.131 1.888 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST Demo_sb_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[15] Demo_sb_0_AMBA_SLAVE_0_PADDR[15] 3.056 1.908 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST Demo_sb_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[2] Demo_sb_0_AMBA_SLAVE_0_PADDR[2] 3.014 1.917 ================================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------- Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST Demo_sb_0/CCC_0/GL0 MSS_075 F_HM0_RDATA[2] AMBA_SLAVE_0_PRDATAS0_m[2] 8.802 1.517 CORESPI_0.USPI.URXF.empty_out Demo_sb_0/CCC_0/GL0 SLE D empty_out_2 9.778 1.567 CORESPI_0.USPI.UTXF.wr_pointer_q[1] Demo_sb_0/CCC_0/GL0 SLE D wr_pointer_q_3[1] 9.778 1.571 CORESPI_0.USPI.UTXF.wr_pointer_q[4] Demo_sb_0/CCC_0/GL0 SLE D wr_pointer_q_3[4] 9.778 1.571 CORESPI_0.USPI.URXF.rd_pointer_q[1] Demo_sb_0/CCC_0/GL0 SLE D rd_pointer_q_3[1] 9.778 1.586 CORESPI_0.USPI.URXF.full_out Demo_sb_0/CCC_0/GL0 SLE D full_out_2 9.778 1.628 CORESPI_0.USPI.UTXF.wr_pointer_q[0] Demo_sb_0/CCC_0/GL0 SLE D wr_pointer_q_3[0] 9.778 1.631 CORESPI_0.USPI.UTXF.wr_pointer_q[3] Demo_sb_0/CCC_0/GL0 SLE D wr_pointer_q_3[3] 9.778 1.631 CORESPI_0.USPI.URXF.rd_pointer_q[0] Demo_sb_0/CCC_0/GL0 SLE D rd_pointer_q_3[0] 9.778 1.646 CORESPI_0.USPI.URXF.rd_pointer_q[2] Demo_sb_0/CCC_0/GL0 SLE D rd_pointer_q_3[2] 9.778 1.646 =================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 1.198 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.802 - Propagation time: 7.285 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 1.517 Number of logic level(s): 5 Starting point: Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[14] Ending point: Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[2] The start point is clocked by Demo_sb_0/CCC_0/GL0 [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK_BASE The end point is clocked by Demo_sb_0/CCC_0/GL0 [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK_BASE Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------ Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST MSS_075 F_HM0_ADDR[14] Out 3.012 3.012 r - Demo_sb_0_AMBA_SLAVE_0_PADDR[14] Net - - 0.216 - 1 Demo_sb_0.CoreAPB3_0.iPSELS_1_0[0] CFG2 B In - 3.228 r - Demo_sb_0.CoreAPB3_0.iPSELS_1_0[0] CFG2 Y Out 0.125 3.353 f - iPSELS_1[0] Net - - 0.216 - 1 Demo_sb_0.CoreAPB3_0.iPSELS[0] CFG4 C In - 3.569 f - Demo_sb_0.CoreAPB3_0.iPSELS[0] CFG4 Y Out 0.182 3.751 f - Demo_sb_0_AMBA_SLAVE_0_PSELx Net - - 0.920 - 10 CORESPI_0.USPI.UCON.N_75_i CFG2 A In - 4.671 f - CORESPI_0.USPI.UCON.N_75_i CFG2 Y Out 0.076 4.747 f - N_75_i Net - - 0.958 - 11 CORESPI_0.USPI.URF.prdata_2[2] CFG4 D In - 5.705 f - CORESPI_0.USPI.URF.prdata_2[2] CFG4 Y Out 0.250 5.955 f - AMBA_SLAVE_0_PRDATAS0_m_1[2] Net - - 0.216 - 1 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST_RNO_1 CFG4 B In - 6.171 f - Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST_RNO_1 CFG4 Y Out 0.143 6.314 f - AMBA_SLAVE_0_PRDATAS0_m[2] Net - - 0.971 - 1 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST MSS_075 F_HM0_RDATA[2] In - 7.285 f - ======================================================================================================================== Total path delay (propagation time + setup) of 8.483 is 4.986(58.8%) logic and 3.498(41.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Demo_sb_0.CORECONFIGP_0.psel Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE Q psel 0.094 15.313 Demo_sb_0.CORECONFIGP_0.SDIF0_PENABLE Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE Q Demo_sb_0_SDIF0_INIT_APB_PENABLE 0.094 18.200 Demo_sb_0.CORECONFIGP_0.state[1] Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE Q state[1] 0.076 18.228 Demo_sb_0.CORECONFIGP_0.state[0] Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE Q state[0] 0.076 18.634 Demo_sb_0.CORECONFIGP_0.paddr[15] Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE Q Demo_sb_0_SDIF0_INIT_APB_PADDR[15] 0.076 18.695 SERDES_IF2_0.SERDESIF_INST Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PREADY Demo_sb_0_SDIF0_INIT_APB_PREADY 4.732 33.819 SERDES_IF2_0.SERDESIF_INST Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PRDATA[25] Demo_sb_0_SDIF0_INIT_APB_PRDATA[25] 5.348 33.855 SERDES_IF2_0.SERDESIF_INST Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PRDATA[29] Demo_sb_0_SDIF0_INIT_APB_PRDATA[29] 5.235 33.968 SERDES_IF2_0.SERDESIF_INST Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PRDATA[24] Demo_sb_0_SDIF0_INIT_APB_PRDATA[24] 5.230 33.973 SERDES_IF2_0.SERDESIF_INST Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PRDATA[28] Demo_sb_0_SDIF0_INIT_APB_PRDATA[28] 5.217 33.986 =================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SERDES_IF2_0.SERDESIF_INST Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PSEL Demo_sb_0_SDIF0_INIT_APB_PSELx 17.269 15.313 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[0] Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[0] 19.778 16.700 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[1] Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[1] 19.778 16.700 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[2] Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[2] 19.778 16.700 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[3] Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[3] 19.778 16.700 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[4] Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[4] 19.778 16.700 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[5] Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[5] 19.778 16.700 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[6] Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[6] 19.778 16.700 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[7] Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[7] 19.778 16.700 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[8] Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[8] 19.778 16.700 ================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 2.731 + Clock delay at ending point: 0.000 (ideal) = Required time: 17.269 - Propagation time: 1.956 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 15.313 Number of logic level(s): 1 Starting point: Demo_sb_0.CORECONFIGP_0.psel / Q Ending point: SERDES_IF2_0.SERDESIF_INST / APB_PSEL The start point is clocked by Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB [falling] (rise=0.000 fall=20.000 period=40.000) on pin CLK The end point is clocked by Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB [rising] (rise=0.000 fall=20.000 period=40.000) on pin APB_CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------- Demo_sb_0.CORECONFIGP_0.psel SLE Q Out 0.094 0.094 f - psel Net - - 0.648 - 3 Demo_sb_0.CORECONFIGP_0.R_SDIF0_PSEL CFG2 A In - 0.742 f - Demo_sb_0.CORECONFIGP_0.R_SDIF0_PSEL CFG2 Y Out 0.076 0.818 f - Demo_sb_0_SDIF0_INIT_APB_PSELx Net - - 1.138 - 35 SERDES_IF2_0.SERDESIF_INST SERDESIF_075 APB_PSEL In - 1.956 f - =============================================================================================================== Total path delay (propagation time + setup) of 4.687 is 2.901(61.9%) logic and 1.787(38.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------- Demo_sb_0.CORERESETP_0.count_sdif0[0] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[0] 0.076 18.011 Demo_sb_0.CORERESETP_0.count_sdif0[1] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[1] 0.076 18.295 Demo_sb_0.CORERESETP_0.count_sdif0[3] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[3] 0.076 18.314 Demo_sb_0.CORERESETP_0.count_sdif0[6] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[6] 0.094 18.350 Demo_sb_0.CORERESETP_0.count_sdif0[2] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[2] 0.094 18.378 Demo_sb_0.CORERESETP_0.count_sdif0[7] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[7] 0.076 18.386 Demo_sb_0.CORERESETP_0.count_sdif0[8] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[8] 0.094 18.418 Demo_sb_0.CORERESETP_0.count_sdif0[9] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[9] 0.076 18.423 Demo_sb_0.CORERESETP_0.count_sdif0[4] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[4] 0.076 18.454 Demo_sb_0.CORERESETP_0.count_sdif0[11] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[11] 0.094 18.457 ================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------- Demo_sb_0.CORERESETP_0.release_sdif0_core Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE EN release_sdif0_core6 19.706 18.011 Demo_sb_0.CORERESETP_0.count_sdif0[12] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[12] 19.778 18.425 Demo_sb_0.CORERESETP_0.count_sdif0[11] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[11] 19.778 18.440 Demo_sb_0.CORERESETP_0.count_sdif0[10] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[10] 19.778 18.454 Demo_sb_0.CORERESETP_0.count_sdif0[9] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[9] 19.778 18.468 Demo_sb_0.CORERESETP_0.count_sdif0[8] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[8] 19.778 18.482 Demo_sb_0.CORERESETP_0.count_sdif0[7] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[7] 19.778 18.497 Demo_sb_0.CORERESETP_0.count_sdif0[6] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[6] 19.778 18.511 Demo_sb_0.CORERESETP_0.count_sdif0[5] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[5] 19.778 18.525 Demo_sb_0.CORERESETP_0.count_sdif0[4] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[4] 19.778 18.539 ========================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 0.294 + Clock delay at ending point: 0.000 (ideal) = Required time: 19.706 - Propagation time: 1.696 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 18.011 Number of logic level(s): 2 Starting point: Demo_sb_0.CORERESETP_0.count_sdif0[0] / Q Ending point: Demo_sb_0.CORERESETP_0.release_sdif0_core / EN The start point is clocked by Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK The end point is clocked by Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------- Demo_sb_0.CORERESETP_0.count_sdif0[0] SLE Q Out 0.076 0.076 r - count_sdif0[0] Net - - 0.648 - 3 Demo_sb_0.CORERESETP_0.release_sdif0_core6_8 CFG4 D In - 0.724 r - Demo_sb_0.CORERESETP_0.release_sdif0_core6_8 CFG4 Y Out 0.284 1.008 f - release_sdif0_core6_8 Net - - 0.216 - 1 Demo_sb_0.CORERESETP_0.release_sdif0_core6 CFG4 D In - 1.224 f - Demo_sb_0.CORERESETP_0.release_sdif0_core6 CFG4 Y Out 0.250 1.474 f - release_sdif0_core6 Net - - 0.221 - 1 Demo_sb_0.CORERESETP_0.release_sdif0_core SLE EN In - 1.696 f - =========================================================================================================== Total path delay (propagation time + setup) of 1.989 is 0.904(45.4%) logic and 1.085(54.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied @W:MT447 : synthesis.fdc(19) | Timing constraint (from [get_cells { Demo_sb_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { Demo_sb_0.CORERESETP_0.sm0_areset_n_rcosc Demo_sb_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(20) | Timing constraint (from [get_cells { Demo_sb_0.CORERESETP_0.MSS_HPMS_READY_int Demo_sb_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { Demo_sb_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(22) | Timing constraint (through [get_pins { Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST.CONFIG_PRESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(23) | Timing constraint (through [get_pins { Demo_sb_0.SYSRESET_POR.POWER_ON_RESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(24) | Timing constraint (from [get_pins { Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST.GTX_CLKPF }] to [get_pins { SERDES_IF2_0.SERDESIF_INST.EPCS_TXDATA[*] }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT443 : synthesis.fdc(25) | Timing constraint (through [get_nets { Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PSEL Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PENABLE }] to [get_cells { Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PREADY* Demo_sb_0.CORECONFIGP_0.state[0] }]) (max delay 0.000000) was not applied to the design because none of the paths specified by the constraint exist in the design None Finished final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 182MB peak: 185MB) Finished timing report (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 182MB peak: 185MB) --------------------------------------- Resource Usage Report for top Mapping to part: m2s090tsfbga484-1 Cell usage: AND2 1 use CCC 3 uses CLKINT 12 uses MSS_075 1 use RCOSC_25_50MHZ 1 use RCOSC_25_50MHZ_FAB 1 use SERDESIF_075 1 use SYSRESET 1 use CFG1 7 uses CFG2 102 uses CFG3 122 uses CFG4 227 uses Carry cells: ARI1 34 uses - used for arithmetic functions ARI1 5 uses - used for Wide-Mux implementation Total ARI1 39 uses Sequential Cells: SLE 392 uses DSP Blocks: 0 of 84 (0%) I/O ports: 37 I/O primitives: 19 BIBUF 1 use INBUF 3 uses INBUF_DIFF 1 use OUTBUF 13 uses TRIBUFF 1 use Global Clock Buffers: 12 RAM/ROM usage summary Total Block RAMs (RAM64x18) : 2 of 112 (1%) Total LUTs: 497 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 72; LUTs = 72; RAM1K18 Interface Logic : SLEs = 0; LUTs = 0; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 392 + 72 + 0 + 0 = 464; Total number of LUTs after P&R: 497 + 72 + 0 + 0 = 569; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 68MB peak: 185MB) Process took 0h:00m:07s realtime, 0h:00m:07s cputime # Mon Jun 7 21:12:38 2021 ###########################################################]