Project Settings Project Name top_syn Device Name synthesis: Microchip SmartFusion2 : M2S090TS Implementation Name synthesis Top Module top Retiming 0 Resource Sharing 1 Fanout Guide 10000 Disable I/O Insertion 0 Disable Sequential Optimizations 0 FSM Compiler 1 Run Status Job Name Status CPU Time Real Time Memory Date/Time (compiler) Complete 134 62 0 - 00m:09s - 6/7/2021 9:12:27 PM (premap) Complete 39 28 0 0m:01s 0m:01s 176MB 6/7/2021 9:12:31 PM (fpga_mapper) Complete 34 18 0 0m:07s 0m:07s 185MB 6/7/2021 9:12:38 PM Multi-srs Generator Complete 6/7/2021 9:12:28 PM Area Summary Carry Cells 39 Sequential Cells 392 DSP Blocks (dsp_used) 0 I/O Cells 19 Global Clock Buffers 12 RAM64x18 (v_ram) 2 LUTs (total_luts) 497 Timing Summary Clock Name Req Freq Est Freq Slack CLK0_PAD 50.0 MHz NA NA Demo_sb_0/CCC_0/GL0 100.0 MHz 117.9 MHz 1.517 Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB 25.0 MHz 106.7 MHz 15.313 Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 502.7 MHz 18.011 FCCC_0/GL0 62.5 MHz NA NA FCCC_0/GL1 62.5 MHz NA NA FCCC_1/GL0 125.0 MHz NA NA SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] 125.0 MHz NA NA SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1] 125.0 MHz NA NA top_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock 100.0 MHz NA NA System 100.0 MHz NA NA Optimizations Summary Combined Clock Conversion 3 / 4