@W: BN309 |One or more non-fatal issues found in constraints; Please run Constraint Check for analysis
@W: BN132 :"c:\igloo2_task_feb_2021\sf2\dg0636_sf2_tftp_update_recovery\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Removing sequential instance Demo_sb_0.CORERESETP_0.sdif3_spll_lock_q1 because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif0_spll_lock_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\igloo2_task_feb_2021\sf2\dg0636_sf2_tftp_update_recovery\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Removing sequential instance Demo_sb_0.CORERESETP_0.sdif3_spll_lock_q2 because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif0_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: FX107 :"c:\igloo2_task_feb_2021\sf2\dg0636_sf2_tftp_update_recovery\libero_project\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":101:0:101:5|RAM fifo_mem_q[8:0] (in view: CORESPI_LIB.spi_fifo_8s_32s_5_1(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"c:\igloo2_task_feb_2021\sf2\dg0636_sf2_tftp_update_recovery\libero_project\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":101:0:101:5|RAM fifo_mem_q[8:0] (in view: CORESPI_LIB.spi_fifo_8s_32s_5_0(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: MO160 :"c:\igloo2_task_feb_2021\sf2\dg0636_sf2_tftp_update_recovery\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":255:4:255:9|Register bit CORECONFIGP_0.paddr[16] (in view view:work.Demo_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: BN132 :"c:\igloo2_task_feb_2021\sf2\dg0636_sf2_tftp_update_recovery\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing instance Demo_sb_0.CORERESETP_0.SDIF_READY_int because it is equivalent to instance Demo_sb_0.CORERESETP_0.sm0_state[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\igloo2_task_feb_2021\sf2\dg0636_sf2_tftp_update_recovery\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":496:4:496:9|Removing instance Demo_sb_0.CORERESETP_0.POWER_ON_RESET_N_q1 because it is equivalent to instance CORESPI_0.USPI.UCC.ssel_rx_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\igloo2_task_feb_2021\sf2\dg0636_sf2_tftp_update_recovery\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":496:4:496:9|Removing instance Demo_sb_0.CORERESETP_0.POWER_ON_RESET_N_clk_base because it is equivalent to instance CORESPI_0.USPI.UCC.ssel_rx_q2. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BW156 :|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
@W: MT246 :"c:\igloo2_task_feb_2021\sf2\dg0636_sf2_tftp_update_recovery\libero_project\component\work\top\fccc_1\top_fccc_1_fccc.v":20:36:20:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock top_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock with period 10.00ns. Please declare a user-defined clock on net SERDES_IF2_0.REFCLK1_OUT.
@W: MT447 :"c:/igloo2_task_feb_2021/sf2/dg0636_sf2_tftp_update_recovery/libero_project/designer/top/synthesis.fdc":19:0:19:0|Timing constraint (from [get_cells { Demo_sb_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { Demo_sb_0.CORERESETP_0.sm0_areset_n_rcosc Demo_sb_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"c:/igloo2_task_feb_2021/sf2/dg0636_sf2_tftp_update_recovery/libero_project/designer/top/synthesis.fdc":20:0:20:0|Timing constraint (from [get_cells { Demo_sb_0.CORERESETP_0.MSS_HPMS_READY_int Demo_sb_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { Demo_sb_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"c:/igloo2_task_feb_2021/sf2/dg0636_sf2_tftp_update_recovery/libero_project/designer/top/synthesis.fdc":22:0:22:0|Timing constraint (through [get_pins { Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST.CONFIG_PRESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"c:/igloo2_task_feb_2021/sf2/dg0636_sf2_tftp_update_recovery/libero_project/designer/top/synthesis.fdc":23:0:23:0|Timing constraint (through [get_pins { Demo_sb_0.SYSRESET_POR.POWER_ON_RESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"c:/igloo2_task_feb_2021/sf2/dg0636_sf2_tftp_update_recovery/libero_project/designer/top/synthesis.fdc":24:0:24:0|Timing constraint (from [get_pins { Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST.GTX_CLKPF }] to [get_pins { SERDES_IF2_0.SERDESIF_INST.EPCS_TXDATA[*] }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT443 :"c:/igloo2_task_feb_2021/sf2/dg0636_sf2_tftp_update_recovery/libero_project/designer/top/synthesis.fdc":25:0:25:0|Timing constraint (through [get_nets { Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PSEL Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PENABLE }] to [get_cells { Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PREADY* Demo_sb_0.CORECONFIGP_0.state[0] }]) (max delay 0.000000) was not applied to the design because none of the paths specified by the constraint exist in the design 
