@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: MO111 :"c:\igloo2_task_feb_2021\sf2\dg0636_sf2_tftp_update_recovery\libero_project\component\work\demo_sb\fabosc_0\demo_sb_fabosc_0_osc.v":20:7:20:16|Tristate driver XTLOSC_O2F (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N: MO111 :"c:\igloo2_task_feb_2021\sf2\dg0636_sf2_tftp_update_recovery\libero_project\component\work\demo_sb\fabosc_0\demo_sb_fabosc_0_osc.v":19:7:19:16|Tristate driver XTLOSC_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N: MO111 :"c:\igloo2_task_feb_2021\sf2\dg0636_sf2_tftp_update_recovery\libero_project\component\work\demo_sb\fabosc_0\demo_sb_fabosc_0_osc.v":18:7:18:20|Tristate driver RCOSC_1MHZ_O2F (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N: MO111 :"c:\igloo2_task_feb_2021\sf2\dg0636_sf2_tftp_update_recovery\libero_project\component\work\demo_sb\fabosc_0\demo_sb_fabosc_0_osc.v":17:7:17:20|Tristate driver RCOSC_1MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N: MO111 :"c:\igloo2_task_feb_2021\sf2\dg0636_sf2_tftp_update_recovery\libero_project\component\work\demo_sb\fabosc_0\demo_sb_fabosc_0_osc.v":15:7:15:24|Tristate driver RCOSC_25_50MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net RCOSC_25_50MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N: MO231 :"c:\igloo2_task_feb_2021\sf2\dg0636_sf2_tftp_update_recovery\libero_project\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":823:0:823:5|Found counter in view:CORESPI_LIB.spi_chanctrl_Z1(verilog) instance stxs_bitcnt[4:0] 
@N: MO231 :"c:\igloo2_task_feb_2021\sf2\dg0636_sf2_tftp_update_recovery\libero_project\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":286:0:286:5|Found counter in view:CORESPI_LIB.spi_chanctrl_Z1(verilog) instance spi_clk_count[7:0] 
@N: MO225 :"c:\igloo2_task_feb_2021\sf2\dg0636_sf2_tftp_update_recovery\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1170:4:1170:9|There are no possible illegal states for state machine sdif0_state[3:0] (in view: work.CoreResetP_Z5(verilog)); safe FSM implementation is not required.
@N: MO231 :"c:\igloo2_task_feb_2021\sf2\dg0636_sf2_tftp_update_recovery\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1485:4:1485:9|Found counter in view:work.CoreResetP_Z5(verilog) instance count_sdif0[12:0] 
@N: BN362 :"c:\igloo2_task_feb_2021\sf2\dg0636_sf2_tftp_update_recovery\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Removing sequential instance Demo_sb_0.CORERESETP_0.SDIF0_CORE_RESET_N_0 (in view: work.top(verilog)) because it does not drive other instances.
@N: BN362 :"c:\igloo2_task_feb_2021\sf2\dg0636_sf2_tftp_update_recovery\libero_project\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":286:0:286:5|Removing sequential instance CORESPI_0.USPI.UCC.spi_clk_next (in view: work.top(verilog)) because it does not drive other instances.
@N: FP130 |Promoting Net POWER_ON_RESET_N_arst on CLKINT  I_253 
@N: FP130 |Promoting Net Demo_sb_0.FIC_2_APB_M_PRESET_N_arst on CLKINT  I_254 
@N: FP130 |Promoting Net Demo_sb_0_INIT_APB_S_PCLK on CLKINT  I_255 
@N: FP130 |Promoting Net CORESPI_0.USPI.UCC.un1_resetn_tx_i on CLKINT  I_256 
@N: FP130 |Promoting Net Demo_sb_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT  I_257 
@N: FP130 |Promoting Net Demo_sb_0.CORERESETP_0.sdif0_areset_n_rcosc on CLKINT  I_258 
@N: FP130 |Promoting Net Demo_sb_0.CORERESETP_0.sm0_areset_n_arst on CLKINT  I_259 
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT615 |Found clock CLK0_PAD with period 20.00ns 
@N: MT615 |Found clock Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB with period 40.00ns 
@N: MT615 |Found clock Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT with period 20.00ns 
@N: MT615 |Found clock SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] with period 8.00ns 
@N: MT615 |Found clock SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1] with period 8.00ns 
@N: MT615 |Found clock Demo_sb_0/CCC_0/GL0 with period 10.00ns 
@N: MT615 |Found clock FCCC_0/GL0 with period 16.00ns 
@N: MT615 |Found clock FCCC_0/GL1 with period 16.00ns 
@N: MT615 |Found clock FCCC_1/GL0 with period 8.00ns 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
