@W: CG1337 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":805:7:805:17|Net resetn_rx_s is not declared.
@W: CL208 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v":134:0:134:5|All reachable assignments to bit 3 of control2[7:0] assign 0, register removed by optimization.
@W: CG1340 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":416:0:416:5|Index into variable txfifo_dhold could be out of range ; a simulation mismatch is possible.
@W: CG133 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":195:12:195:22|Object resetn_rx_d is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":196:12:196:22|Removing wire resetn_rx_p, as there is no assignment to it.
@W: CG360 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":200:12:200:22|Removing wire resetn_rx_r, as there is no assignment to it.
@W: CG133 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":222:12:222:36|Object stxs_txready_at_ssel_temp is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":1130:0:1130:5|Pruning unused register msrxs_ssel. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":823:0:823:5|Pruning unused register stxs_oen. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":719:0:719:5|Pruning unused register spi_ssel_neg. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":416:0:416:5|Pruning unused register mtx_bitcnt[4:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":416:0:416:5|Pruning unused register mtx_ssel. Make sure that there are no unused intermediate registers.
@W: CL177 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":343:0:343:5|Sharing sequential element cfg_enable_P1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CG360 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":244:12:244:20|Removing wire IA_PRDATA, as there is no assignment to it.
@W: CL207 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v":461:4:461:9|All reachable assignments to SDIF1_PENABLE assign 0, register removed by optimization.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1517:4:1517:9|Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers.
@W: CL177 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL190 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers.
@W: CL318 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\work\Demo_sb\FABOSC_0\Demo_sb_FABOSC_0_OSC.v":15:7:15:24|*Output RCOSC_25_50MHZ_CCC has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\work\Demo_sb\FABOSC_0\Demo_sb_FABOSC_0_OSC.v":17:7:17:20|*Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\work\Demo_sb\FABOSC_0\Demo_sb_FABOSC_0_OSC.v":18:7:18:20|*Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\work\Demo_sb\FABOSC_0\Demo_sb_FABOSC_0_OSC.v":19:7:19:16|*Output XTLOSC_CCC has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\work\Demo_sb\FABOSC_0\Demo_sb_FABOSC_0_OSC.v":20:7:20:16|*Output XTLOSC_O2F has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CG296 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\hdl\MUX4_4.v":25:8:25:10|Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list.
@W: CG290 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\hdl\MUX4_4.v":30:7:30:17|Referenced variable MSS_SPI0_DO is not in sensitivity list.
@W: CG290 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\hdl\MUX4_4.v":31:8:31:19|Referenced variable MSS_SPI0_CLK is not in sensitivity list.
@W: CG290 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\hdl\MUX4_4.v":32:8:32:19|Referenced variable MSS_SPI0_SS0 is not in sensitivity list.
@W: CG290 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\hdl\MUX4_4.v":37:7:37:16|Referenced variable CoreSPI_D0 is not in sensitivity list.
@W: CG290 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\hdl\MUX4_4.v":38:8:38:18|Referenced variable CoreSPI_CLK is not in sensitivity list.
@W: CG290 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\hdl\MUX4_4.v":39:8:39:18|Referenced variable CoreSPI_SS0 is not in sensitivity list.
@W: CL177 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL246 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v":70:12:70:16|Input port bits 1 to 0 of PADDR[6:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL190 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":823:0:823:5|Optimizing register bit stxs_bitsel[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":823:0:823:5|Pruning register bit 4 of stxs_bitsel[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL190 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":823:0:823:5|Optimizing register bit stxs_bitsel[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":823:0:823:5|Pruning register bit 3 of stxs_bitsel[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL246 :"C:\igloo2_task_feb_2021\SF2\DG0636_SF2_TFTP_Update_Recovery\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v":42:45:42:50|Input port bits 31 to 8 of wrdata[31:0] are unused. Assign logic for all port bits or change the input port size.

