Power Report for design top with the following settings:

Vendor: Microsemi Corporation
Program: Microsemi Libero Software, Release v12.6 (Version 12.900.20.24)
Copyright (C) 1989-
Date: Sun Jun 6 15:15:00 2021
Version: 3.0

Design: top
Family: SmartFusion2
Die: M2S090TS
Package: 484 FBGA
Temperature Range: COM
Voltage Range: COM
Operating Conditions: Typical
Operating Mode: Active
Process: Typical
Data Source: Production

Power Summary

Power (mW) Percentage
Total Power 230.859 100.0%
Static Power 33.839 14.7%
Dynamic Power 197.020 85.3%

Breakdown by Rail

Power (mW) Voltage (V) Current (mA)
Rail VDD 130.665 1.200 108.888
Rail VDDI 2.5 25.652 2.500 10.261
Rail CCC_NW1_PLL_VDDA 9.000 3.300 2.727
Rail SERDES_0_L23_VDDAPLL 3.125 2.500 1.250
Rail SERDES_0_L23_VDDAIO 26.092 1.200 21.744
Rail CCC_SW0_PLL_VDDA 9.000 3.300 2.727
Rail CCC_SW1_PLL_VDDA 9.000 3.300 2.727
Rail MDDR_PLL_VDDA 5.000 3.300 1.515
Rail VPP 13.325 3.300 4.038

Breakdown by Clock

Power (mW) Percentage
FCCC_0/CCC_INST/INST_CCC_IP:GL1 (clocks) 0.259 0.2%
FCCC_0/CCC_INST/INST_CCC_IP:GL1 (register outputs) 0.000 0.0%
FCCC_0/CCC_INST/INST_CCC_IP:GL1 (primary inputs) 0.000 0.0%
FCCC_0/CCC_INST/INST_CCC_IP:GL1 (combinational outputs) 0.000 0.0%
FCCC_0/CCC_INST/INST_CCC_IP:GL1 (set/reset nets) 0.000 0.0%
FCCC_0/CCC_INST/INST_CCC_IP:GL0 (clocks) 0.259 0.2%
FCCC_0/CCC_INST/INST_CCC_IP:GL0 (register outputs) 0.000 0.0%
FCCC_0/CCC_INST/INST_CCC_IP:GL0 (primary inputs) 0.000 0.0%
FCCC_0/CCC_INST/INST_CCC_IP:GL0 (combinational outputs) 0.000 0.0%
FCCC_0/CCC_INST/INST_CCC_IP:GL0 (set/reset nets) 0.000 0.0%
FCCC_1/CCC_INST/INST_CCC_IP:GL0 (clocks) 0.517 0.5%
FCCC_1/CCC_INST/INST_CCC_IP:GL0 (register outputs) 1.794 1.7%
FCCC_1/CCC_INST/INST_CCC_IP:GL0 (primary inputs) 0.000 0.0%
FCCC_1/CCC_INST/INST_CCC_IP:GL0 (combinational outputs) 9.018 8.4%
FCCC_1/CCC_INST/INST_CCC_IP:GL0 (set/reset nets) 0.000 0.0%
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (clocks) 81.211 75.6%
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (register outputs) 0.982 0.9%
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (primary inputs) 0.000 0.0%
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (combinational outputs) 3.027 2.8%
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (set/reset nets) 0.000 0.0%
CLK0_PAD (clocks) 0.814 0.8%
CLK0_PAD (register outputs) 0.019 0.0%
CLK0_PAD (primary inputs) 0.000 0.0%
CLK0_PAD (combinational outputs) 0.000 0.0%
CLK0_PAD (set/reset nets) 0.000 0.0%
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB (clocks) 6.774 6.3%
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB (register outputs) 0.420 0.4%
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB (primary inputs) 0.000 0.0%
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB (combinational outputs) 0.352 0.3%
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB (set/reset nets) 0.000 0.0%
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (clocks) 0.360 0.3%
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (register outputs) 0.041 0.0%
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (primary inputs) 0.000 0.0%
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (combinational outputs) 0.037 0.0%
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (set/reset nets) 0.000 0.0%
REFCLK1_P (clocks) 0.000 0.0%
REFCLK1_P (register outputs) 0.000 0.0%
REFCLK1_P (primary inputs) 0.000 0.0%
REFCLK1_P (combinational outputs) 0.000 0.0%
REFCLK1_P (set/reset nets) 0.000 0.0%
SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1] (clocks) 0.138 0.1%
SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1] (register outputs) 0.015 0.0%
SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1] (primary inputs) 0.000 0.0%
SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1] (combinational outputs) 0.795 0.7%
SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1] (set/reset nets) 0.000 0.0%
SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] (clocks) 0.474 0.4%
SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] (register outputs) 0.012 0.0%
SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] (primary inputs) 0.000 0.0%
SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] (combinational outputs) 0.000 0.0%
SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] (set/reset nets) 0.000 0.0%
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_CLK_OUT (clocks) 0.000 0.0%
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_CLK_OUT (register outputs) 0.000 0.0%
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_CLK_OUT (primary inputs) 0.000 0.0%
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_CLK_OUT (combinational outputs) 0.000 0.0%
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_CLK_OUT (set/reset nets) 0.000 0.0%
Input to Output 0.056 0.1%

Breakdown by Type

Power (mW) Percentage
Type Net 7.161 3.1%
Type Gate 34.138 14.8%
Type I/O 19.525 8.5%
Type Memory 1.403 0.6%
Type Core Static 18.535 8.0%
Type Banks Static 6.265 2.7%
Type VPP Static 0.825 0.4%
Type Built-in Blocks 107.852 46.7%
Type SERDES 35.155 15.2%