Timing Multi Corner Report Max Delay Analysis

SmartTime Version 2021.1.0.17

Microsemi Corporation - Microsemi Libero Software Release v2021.1 (Version 2021.1.0.17)

Date: Mon Jun 7 21:16:29 2021

Design top
Family SmartFusion2
Die M2S090TS
Package 484 FBGA
Temperature Range 0 - 85 C
Voltage Range 1.14 - 1.26 V
Speed Grade -1
Design State Post-Layout
Data source Production
Multi Corner Report Operating Conditions BEST, TYPICAL, WORST
Scenario for Timing Analysis timing_analysis

Summary

Clock Domain Required Period (ns) Required Frequency (MHz) Worst Slack (ns) Operating Conditions
CLK0_PAD 20.000 50.000
Demo_sb_0/CCC_0/GL0 10.000 100.000 3.619 WORST
Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB 40.000 25.000 1.671 BEST
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDCF N/A N/A
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_CLK_OUT N/A N/A
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_CLK_OUT N/A N/A
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 20.000 50.000 8.399 WORST
FCCC_0/GL0 16.000 62.500 4.799 WORST
FCCC_0/GL1 16.000 62.500 4.560 WORST
FCCC_1/GL0 8.000 125.000
SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] 8.000 125.000
SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1] 8.000 125.000

Worst Slack (ns) Operating Conditions
Input to Output

Clock Domain CLK0_PAD

Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin Demo_sb_0/CCC_0/CLK0_PAD_INST/U_IOPAD:PAD

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain Demo_sb_0/CCC_0/GL0

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[2] 5.072 3.744 9.679 13.423 1.184 6.256 WORST
Path 2 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[5] 5.333 3.804 9.940 13.744 0.863 6.196 WORST
Path 3 CORESPI_0/USPI/URXF/rd_pointer_q[3]:CLK Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[0] 5.632 3.826 9.924 13.750 0.851 6.174 WORST
Path 4 CORESPI_0/USPI/URXF/rd_pointer_q[4]:CLK Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[0] 5.525 3.933 9.817 13.750 0.851 6.067 WORST
Path 5 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[4] 5.149 3.974 9.756 13.730 0.877 6.026 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE
To: Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[2]
data required time 13.423
data arrival time - 9.679
slack 3.744
Data arrival time calculation
Demo_sb_0/CCC_0/GL0 0.000 0.000
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 2.235 2.235
Demo_sb_0/CCC_0/GL0_INST:An net Demo_sb_0/CCC_0/GL0_net + 0.423 2.658 r
Demo_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 2.836 12 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1:An net Demo_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.623 3.459 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1:YR cell ADLIB:RGB + 0.316 3.775 1 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B net Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_YR + 0.407 4.182 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB cell ADLIB:IP_INTERFACE + 0.209 4.391 1 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE net Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net + 0.216 4.607 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_ADDR[4] cell ADLIB:MSS_075_IP + 1.429 6.036 33 r
CORESPI_0/USPI/URF/prdata_2_6_1[2]:D net Demo_sb_0_AMBA_SLAVE_0_PADDR[4] + 0.770 6.806 r
CORESPI_0/USPI/URF/prdata_2_6_1[2]:Y cell ADLIB:CFG4 + 0.158 6.964 1 r
CORESPI_0/USPI/URF/prdata_2_6_2[2]:B net CORESPI_0/USPI/URF/prdata_2_6_1_Z[2] + 0.225 7.189 r
CORESPI_0/USPI/URF/prdata_2_6_2[2]:Y cell ADLIB:CFG3 + 0.074 7.263 1 r
CORESPI_0/USPI/URF/prdata_2_RNO[2]:B net CORESPI_0/USPI/URF/prdata_2_6_2_Z[2] + 0.620 7.883 r
CORESPI_0/USPI/URF/prdata_2_RNO[2]:Y cell ADLIB:CFG3 + 0.168 8.051 1 r
CORESPI_0/USPI/URF/prdata_2[2]:C net CORESPI_0/USPI/URF/N_130 + 0.220 8.271 r
CORESPI_0/USPI/URF/prdata_2[2]:Y cell ADLIB:CFG4 + 0.072 8.343 1 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST_RNO_1:B net Demo_sb_0.AMBA_SLAVE_0_PRDATAS0_m_1[2] + 0.085 8.428 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST_RNO_1:Y cell ADLIB:CFG4 + 0.072 8.500 1 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_4:A net Demo_sb_0/Demo_sb_MSS_0/AMBA_SLAVE_0_PRDATAS0_m[2] + 0.756 9.256 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_4:IPA cell ADLIB:IP_INTERFACE + 0.194 9.450 1 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[2] net Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/F_HM0_RDATA_net[2] + 0.229 9.679 r
data arrival time 9.679
Data required time calculation
Demo_sb_0/CCC_0/GL0 Clock Constraint 10.000 10.000
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 10.000 r
Clock generation + 2.235 12.235
Demo_sb_0/CCC_0/GL0_INST:An net Demo_sb_0/CCC_0/GL0_net + 0.423 12.658 r
Demo_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 12.836 12 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1:An net Demo_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.623 13.459 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1:YR cell ADLIB:RGB + 0.316 13.775 1 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B net Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_YR + 0.407 14.182 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB cell ADLIB:IP_INTERFACE + 0.209 14.391 1 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE net Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net + 0.216 14.607 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[2] Library setup time ADLIB:MSS_075_IP - 1.184 13.423
data required time 13.423
Operating Conditions WORST

SET External Setup

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) External Setup (ns) Operating Conditions
Path 1 SPISDI CORESPI_0/USPI/UCC/msrxs_shiftreg[0]:D 5.338 5.338 0.174 1.349 WORST
Path 2 SPISDI CORESPI_0/USPI/UCC/msrxs_datain[0]:D 5.351 5.351 0.174 1.344 WORST
Path 3 SPISDI CORESPI_0/USPI/UCC/data_rx_q1:D 4.582 4.582 0.174 0.593 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SPISDI
To: CORESPI_0/USPI/UCC/msrxs_shiftreg[0]:D
data required time N/C
data arrival time - 5.338
slack N/C
Data arrival time calculation
SPISDI 0.000 0.000 f
SPISDI_ibuf/U0/U_IOPAD:PAD net SPISDI + 0.000 0.000 f
SPISDI_ibuf/U0/U_IOPAD:Y cell ADLIB:IOPAD_IN + 1.403 1.403 1 f
SPISDI_ibuf/U0/U_IOINFF:A net SPISDI_ibuf/U0/YIN1 + 0.224 1.627 f
SPISDI_ibuf/U0/U_IOINFF:Y cell ADLIB:IOINFF_BYPASS + 0.147 1.774 3 f
CORESPI_0/USPI/UCC/spi_di_mux:A net SPISDI_c + 2.732 4.506 f
CORESPI_0/USPI/UCC/spi_di_mux:Y cell ADLIB:CFG3 + 0.164 4.670 2 f
CORESPI_0/USPI/UCC/msrxs_shiftreg_5[0]:B net CORESPI_0/USPI/UCC/spi_di_mux_Z + 0.428 5.098 f
CORESPI_0/USPI/UCC/msrxs_shiftreg_5[0]:Y cell ADLIB:CFG2 + 0.164 5.262 1 f
CORESPI_0/USPI/UCC/msrxs_shiftreg[0]:D net CORESPI_0/USPI/UCC/msrxs_shiftreg_5_Z[0] + 0.076 5.338 f
data arrival time 5.338
Data required time calculation
Demo_sb_0/CCC_0/GL0 N/C N/C
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 N/C r
Clock generation + 2.168 N/C
Demo_sb_0/CCC_0/GL0_INST:An net Demo_sb_0/CCC_0/GL0_net + 0.410 N/C r
Demo_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.173 N/C 12 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An net Demo_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.592 N/C f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YR cell ADLIB:RGB + 0.307 N/C 41 r
CORESPI_0/USPI/UCC/msrxs_shiftreg[0]:CLK net Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbr_net_1 + 0.513 N/C r
CORESPI_0/USPI/UCC/msrxs_shiftreg[0]:D Library setup time ADLIB:SLE - 0.174 N/C
Operating Conditions WORST

SET Clock to Output

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Clock to Out (ns) Operating Conditions
Path 1 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE GPIO_5_M2F 10.628 15.235 15.235 WORST
Path 2 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE GPIO_9_M2F 10.472 15.079 15.079 WORST
Path 3 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE GPIO_0_M2F 10.440 15.047 15.047 WORST
Path 4 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE GPIO_8_M2F 10.390 14.997 14.997 WORST
Path 5 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE GPIO_1_M2F 10.288 14.895 14.895 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE
To: GPIO_5_M2F
data required time N/C
data arrival time - 15.235
slack N/C
Data arrival time calculation
Demo_sb_0/CCC_0/GL0 0.000 0.000
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 2.235 2.235
Demo_sb_0/CCC_0/GL0_INST:An net Demo_sb_0/CCC_0/GL0_net + 0.423 2.658 r
Demo_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 2.836 12 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1:An net Demo_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.623 3.459 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1:YR cell ADLIB:RGB + 0.316 3.775 1 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B net Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_YR + 0.407 4.182 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB cell ADLIB:IP_INTERFACE + 0.209 4.391 1 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE net Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net + 0.216 4.607 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_SDI_MGPIO5A_H2F_B cell ADLIB:MSS_075_IP + 1.461 6.068 1 f
GPIO_5_M2F_obuf/U0/U_IOOUTFF:A net GPIO_5_M2F_c + 6.052 12.120 f
GPIO_5_M2F_obuf/U0/U_IOOUTFF:Y cell ADLIB:IOOUTFF_BYPASS + 0.330 12.450 1 f
GPIO_5_M2F_obuf/U0/U_IOPAD:D net GPIO_5_M2F_obuf/U0/DOUT + 0.083 12.533 f
GPIO_5_M2F_obuf/U0/U_IOPAD:PAD cell ADLIB:IOPAD_TRI + 2.702 15.235 0 f
GPIO_5_M2F net GPIO_5_M2F + 0.000 15.235 f
data arrival time 15.235
Data required time calculation
Demo_sb_0/CCC_0/GL0 N/C N/C
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 N/C r
Clock generation + 2.235 N/C
GPIO_5_M2F N/C f
Operating Conditions WORST

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 CORESPI_0/USPI/UCC/ssel_rx_q2:CLK CORESPI_0/USPI/UCC/stxs_direct:ALn 5.989 3.619 10.280 13.899 0.353 6.381 0.039 WORST
Path 2 CORESPI_0/USPI/UCC/ssel_rx_q2:CLK CORESPI_0/USPI/UCC/stxs_bitsel[1]:ALn 5.989 3.619 10.280 13.899 0.353 6.381 0.039 WORST
Path 3 CORESPI_0/USPI/UCC/ssel_rx_q2:CLK CORESPI_0/USPI/UCC/stxs_strobetx:ALn 6.009 3.626 10.300 13.926 0.353 6.374 0.012 WORST
Path 4 CORESPI_0/USPI/UCC/ssel_rx_q2:CLK CORESPI_0/USPI/UCC/stxs_state:ALn 6.009 3.626 10.300 13.926 0.353 6.374 0.012 WORST
Path 5 CORESPI_0/USPI/UCC/ssel_rx_q2:CLK CORESPI_0/USPI/UCC/stxs_midbit:ALn 6.009 3.626 10.300 13.926 0.353 6.374 0.012 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORESPI_0/USPI/UCC/ssel_rx_q2:CLK
To: CORESPI_0/USPI/UCC/stxs_direct:ALn
data required time 13.899
data arrival time - 10.280
slack 3.619
Data arrival time calculation
Demo_sb_0/CCC_0/GL0 0.000 0.000
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 2.235 2.235
Demo_sb_0/CCC_0/GL0_INST:An net Demo_sb_0/CCC_0/GL0_net + 0.423 2.658 r
Demo_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 2.836 12 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An net Demo_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.610 3.446 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YR cell ADLIB:RGB + 0.316 3.762 75 r
CORESPI_0/USPI/UCC/ssel_rx_q2:CLK net Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbr_net_1 + 0.529 4.291 r
CORESPI_0/USPI/UCC/ssel_rx_q2:Q cell ADLIB:SLE + 0.108 4.399 5 f
CORESPI_0/USPI/UCC/un1_resetn_tx:B net Demo_sb_0.CORERESETP_0.POWER_ON_RESET_N_clk_base + 1.847 6.246 f
CORESPI_0/USPI/UCC/un1_resetn_tx:Y cell ADLIB:CFG3 + 0.099 6.345 1 r
CORESPI_0/USPI/UCC/un1_resetn_tx_RNIPA23:An net CORESPI_0/USPI/UCC/un1_resetn_tx_Z + 2.095 8.440 f
CORESPI_0/USPI/UCC/un1_resetn_tx_RNIPA23:YEn cell ADLIB:GBM + 0.374 8.814 4 f
CORESPI_0/USPI/UCC/un1_resetn_tx_RNIPA23/U0_RGB1:An net CORESPI_0/USPI/UCC/un1_resetn_tx_RNIPA23/U0_YWn_GEast + 0.615 9.429 f
CORESPI_0/USPI/UCC/un1_resetn_tx_RNIPA23/U0_RGB1:YR cell ADLIB:RGB + 0.316 9.745 5 r
CORESPI_0/USPI/UCC/stxs_direct:ALn net CORESPI_0/USPI/UCC/un1_resetn_tx_RNIPA23/U0_RGB1_YR + 0.535 10.280 r
data arrival time 10.280
Data required time calculation
Demo_sb_0/CCC_0/GL0 Clock Constraint 10.000 10.000
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 10.000 r
Clock generation + 2.235 12.235
Demo_sb_0/CCC_0/GL0_INST:An net Demo_sb_0/CCC_0/GL0_net + 0.423 12.658 r
Demo_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 12.836 12 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An net Demo_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.610 13.446 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YR cell ADLIB:RGB + 0.316 13.762 41 r
CORESPI_0/USPI/UCC/stxs_direct:CLK net Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbr_net_1 + 0.490 14.252 r
CORESPI_0/USPI/UCC/stxs_direct:ALn Library recovery time ADLIB:SLE - 0.353 13.899
data required time 13.899
Operating Conditions WORST

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB to Demo_sb_0/CCC_0/GL0

No Path

SET Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT to Demo_sb_0/CCC_0/GL0

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Operating Conditions
Path 1 Demo_sb_0/CORERESETP_0/release_sdif3_core:CLK Demo_sb_0/CORERESETP_0/release_sdif3_core_q1:D 0.787 5.871 8.163 14.034 0.254 WORST
Path 2 Demo_sb_0/CORERESETP_0/release_sdif1_core:CLK Demo_sb_0/CORERESETP_0/release_sdif1_core_q1:D 0.793 5.884 8.141 14.025 0.254 WORST
Path 3 Demo_sb_0/CORERESETP_0/release_sdif0_core:CLK Demo_sb_0/CORERESETP_0/release_sdif0_core_q1:D 0.614 6.058 7.989 14.047 0.254 WORST
Path 4 Demo_sb_0/CORERESETP_0/ddr_settled:CLK Demo_sb_0/CORERESETP_0/ddr_settled_q1:D 0.598 6.065 7.972 14.037 0.254 WORST
Path 5 Demo_sb_0/CORERESETP_0/release_sdif2_core:CLK Demo_sb_0/CORERESETP_0/release_sdif2_core_q1:D 0.617 6.076 7.958 14.034 0.254 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Demo_sb_0/CORERESETP_0/release_sdif3_core:CLK
To: Demo_sb_0/CORERESETP_0/release_sdif3_core_q1:D
data required time 14.034
data arrival time - 8.163
slack 5.871
Data arrival time calculation
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 0.000 0.000
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT + 1.797 1.797 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 1.949 1 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.583 5.532 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.374 5.906 2 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An net Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.631 6.537 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YL cell ADLIB:RGB + 0.317 6.854 13 r
Demo_sb_0/CORERESETP_0/release_sdif3_core:CLK net Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbl_net_1 + 0.522 7.376 r
Demo_sb_0/CORERESETP_0/release_sdif3_core:Q cell ADLIB:SLE + 0.087 7.463 1 r
Demo_sb_0/CORERESETP_0/release_sdif3_core_q1:D net Demo_sb_0/CORERESETP_0/release_sdif3_core_Z + 0.700 8.163 r
data arrival time 8.163
Data required time calculation
Demo_sb_0/CCC_0/GL0 Clock Constraint 10.000 10.000
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 10.000 r
Clock generation + 2.235 12.235
Demo_sb_0/CCC_0/GL0_INST:An net Demo_sb_0/CCC_0/GL0_net + 0.423 12.658 r
Demo_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 12.836 12 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB10:An net Demo_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.634 13.470 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB10:YL cell ADLIB:RGB + 0.317 13.787 19 r
Demo_sb_0/CORERESETP_0/release_sdif3_core_q1:CLK net Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB10_rgbl_net_1 + 0.501 14.288 r
Demo_sb_0/CORERESETP_0/release_sdif3_core_q1:D Library setup time ADLIB:SLE - 0.254 14.034
data required time 14.034
Operating Conditions WORST

Clock Domain Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN 1.820 1.671 1.820 3.491 0.245 -1.671 BEST
Path 2 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB Demo_sb_0/CORECONFIGP_0/state[0]:D 1.338 2.191 1.338 3.529 0.201 -2.191 BEST
Path 3 Demo_sb_0/CORECONFIGP_0/psel:CLK SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:APB_PSEL 7.633 9.858 13.184 23.042 2.663 20.284 WORST
Path 4 Demo_sb_0/CORECONFIGP_0/SDIF0_PENABLE:CLK SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:APB_PENABLE 6.876 12.554 12.436 24.990 0.715 14.892 WORST
Path 5 Demo_sb_0/CORECONFIGP_0/psel:CLK Demo_sb_0/CORECONFIGP_0/soft_reset_reg[7]:EN 4.757 14.817 10.308 25.125 0.308 10.366 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB
To: Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN
data required time 3.491
data arrival time - 1.820
slack 1.671
Data arrival time calculation
Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB 0.000 0.000
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB Clock source + 0.000 0.000 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PENABLE cell ADLIB:MSS_075_IP + 0.587 0.587 3 r
Demo_sb_0/CORECONFIGP_0/next_state5:A net Demo_sb_0/Demo_sb_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE + 0.511 1.098 r
Demo_sb_0/CORECONFIGP_0/next_state5:Y cell ADLIB:CFG2 + 0.098 1.196 1 f
Demo_sb_0/CORECONFIGP_0/state_ns_0_a3[0]:A net Demo_sb_0/CORECONFIGP_0/next_state5_Z + 0.064 1.260 f
Demo_sb_0/CORECONFIGP_0/state_ns_0_a3[0]:Y cell ADLIB:CFG3 + 0.060 1.320 2 f
Demo_sb_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0:A net Demo_sb_0/CORECONFIGP_0/state_ns[0] + 0.070 1.390 f
Demo_sb_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0:Y cell ADLIB:CFG3 + 0.060 1.450 1 f
Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN net Demo_sb_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_Z + 0.370 1.820 f
data arrival time 1.820
Data required time calculation
Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB Max Delay Constraint 0.000 0.000
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB Clock source + 0.000 0.000 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST_RNI9FDA:An net Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB + 2.491 2.491 f
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST_RNI9FDA:YEn cell ADLIB:GBM + 0.257 2.748 8 f
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST_RNI9FDA/U0_RGB1_RGB0:An net Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST_RNI9FDA/U0_YWn_GEast + 0.412 3.160 f
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST_RNI9FDA/U0_RGB1_RGB0:YR cell ADLIB:RGB + 0.218 3.378 18 r
Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:CLK net Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST_RNI9FDA/U0_RGB1_RGB0_rgbr_net_1 + 0.358 3.736 r
Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN Library setup time ADLIB:SLE - 0.245 3.491
data required time 3.491
Operating Conditions BEST

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET Demo_sb_0/CCC_0/GL0 to Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB

No Path

Clock Domain Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDCF

SET Register to Register

No Path

SET External Setup

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) External Setup (ns) Operating Conditions
Path 1 PHY_MDIO Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDIF 7.620 7.620 -1.682 5.938 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: PHY_MDIO
To: Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDIF
data required time N/C
data arrival time - 7.620
slack N/C
Data arrival time calculation
PHY_MDIO 0.000 0.000 f
BIBUF_0/U0/U_IOPAD:PAD net PHY_MDIO + 0.000 0.000 f
BIBUF_0/U0/U_IOPAD:Y cell ADLIB:IOPAD_BI + 1.403 1.403 1 f
BIBUF_0/U0/U_IOINFF:A net BIBUF_0/U0/YIN1 + -0.027 1.376 f
BIBUF_0/U0/U_IOINFF:Y cell ADLIB:IOINFF_BYPASS + 0.057 1.433 1 f
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_98:A net BIBUF_0_Y + 5.744 7.177 f
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_98:IPA cell ADLIB:IP_INTERFACE + 0.199 7.376 1 f
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDIF net Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/MDIF_net + 0.244 7.620 f
data arrival time 7.620
Data required time calculation
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDCF N/C N/C
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDCF Clock source + 0.000 N/C r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDIF Library setup time ADLIB:MSS_075_IP - -1.682 N/C
Operating Conditions WORST

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_CLK_OUT

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_CLK_OUT

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 Demo_sb_0/CORERESETP_0/count_sdif0[7]:CLK Demo_sb_0/CORERESETP_0/release_sdif0_core:EN 2.858 16.822 10.229 27.051 0.308 3.178 WORST
Path 2 Demo_sb_0/CORERESETP_0/count_sdif0[3]:CLK Demo_sb_0/CORERESETP_0/release_sdif0_core:EN 2.641 17.039 10.012 27.051 0.308 2.961 WORST
Path 3 Demo_sb_0/CORERESETP_0/count_sdif0[0]:CLK Demo_sb_0/CORERESETP_0/release_sdif0_core:EN 2.558 17.122 9.929 27.051 0.308 2.878 WORST
Path 4 Demo_sb_0/CORERESETP_0/count_sdif0[1]:CLK Demo_sb_0/CORERESETP_0/release_sdif0_core:EN 2.556 17.124 9.927 27.051 0.308 2.876 WORST
Path 5 Demo_sb_0/CORERESETP_0/count_sdif0[9]:CLK Demo_sb_0/CORERESETP_0/release_sdif0_core:EN 2.546 17.142 9.909 27.051 0.308 2.858 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Demo_sb_0/CORERESETP_0/count_sdif0[7]:CLK
To: Demo_sb_0/CORERESETP_0/release_sdif0_core:EN
data required time 27.051
data arrival time - 10.229
slack 16.822
Data arrival time calculation
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 0.000 0.000
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT + 1.797 1.797 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 1.949 1 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.583 5.532 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.374 5.906 2 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An net Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.625 6.531 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YL cell ADLIB:RGB + 0.317 6.848 17 r
Demo_sb_0/CORERESETP_0/count_sdif0[7]:CLK net Demo_sb_0/FABOSC_0_RCOSC_25_50MHZ_O2F + 0.523 7.371 r
Demo_sb_0/CORERESETP_0/count_sdif0[7]:Q cell ADLIB:SLE + 0.087 7.458 2 r
Demo_sb_0/CORERESETP_0/release_sdif0_core6_8:B net Demo_sb_0/CORERESETP_0/count_sdif0_Z[7] + 0.445 7.903 r
Demo_sb_0/CORERESETP_0/release_sdif0_core6_8:Y cell ADLIB:CFG4 + 0.326 8.229 1 f
Demo_sb_0/CORERESETP_0/release_sdif0_core6:D net Demo_sb_0/CORERESETP_0/release_sdif0_core6_8_Z + 0.661 8.890 f
Demo_sb_0/CORERESETP_0/release_sdif0_core6:Y cell ADLIB:CFG4 + 0.287 9.177 1 f
Demo_sb_0/CORERESETP_0/release_sdif0_core:EN net Demo_sb_0/CORERESETP_0/release_sdif0_core6_Z + 1.052 10.229 f
data arrival time 10.229
Data required time calculation
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Clock Constraint 20.000 20.000
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 20.000 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT + 1.797 21.797 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 21.949 1 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.583 25.532 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.374 25.906 2 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An net Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.625 26.531 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YL cell ADLIB:RGB + 0.317 26.848 17 r
Demo_sb_0/CORERESETP_0/release_sdif0_core:CLK net Demo_sb_0/FABOSC_0_RCOSC_25_50MHZ_O2F + 0.511 27.359 r
Demo_sb_0/CORERESETP_0/release_sdif0_core:EN Library setup time ADLIB:SLE - 0.308 27.051
data required time 27.051
Operating Conditions WORST

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK Demo_sb_0/CORERESETP_0/count_sdif0[7]:ALn 3.471 16.143 10.859 27.002 0.353 3.857 0.033 WORST
Path 2 Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK Demo_sb_0/CORERESETP_0/count_sdif0[5]:ALn 3.471 16.143 10.859 27.002 0.353 3.857 0.033 WORST
Path 3 Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK Demo_sb_0/CORERESETP_0/count_sdif0[3]:ALn 3.471 16.143 10.859 27.002 0.353 3.857 0.033 WORST
Path 4 Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK Demo_sb_0/CORERESETP_0/count_sdif0[1]:ALn 3.471 16.143 10.859 27.002 0.353 3.857 0.033 WORST
Path 5 Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK Demo_sb_0/CORERESETP_0/count_sdif0[0]:ALn 3.471 16.143 10.859 27.002 0.353 3.857 0.033 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK
To: Demo_sb_0/CORERESETP_0/count_sdif0[7]:ALn
data required time 27.002
data arrival time - 10.859
slack 16.143
Data arrival time calculation
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 0.000 0.000
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT + 1.797 1.797 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 1.949 1 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.583 5.532 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.374 5.906 2 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An net Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.631 6.537 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YL cell ADLIB:RGB + 0.317 6.854 13 r
Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK net Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbl_net_1 + 0.534 7.388 r
Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:Q cell ADLIB:SLE + 0.087 7.475 1 r
Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIEI67:An net Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_0 + 1.521 8.996 f
Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIEI67:YEn cell ADLIB:GBM + 0.374 9.370 1 f
Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIEI67/U0_RGB1:An net Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIEI67/U0_YWn_GEast + 0.623 9.993 f
Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIEI67/U0_RGB1:YL cell ADLIB:RGB + 0.317 10.310 14 r
Demo_sb_0/CORERESETP_0/count_sdif0[7]:ALn net Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_Z + 0.549 10.859 r
data arrival time 10.859
Data required time calculation
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Clock Constraint 20.000 20.000
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 20.000 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT + 1.797 21.797 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 21.949 1 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.583 25.532 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.374 25.906 2 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An net Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.625 26.531 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YL cell ADLIB:RGB + 0.317 26.848 17 r
Demo_sb_0/CORERESETP_0/count_sdif0[7]:CLK net Demo_sb_0/FABOSC_0_RCOSC_25_50MHZ_O2F + 0.507 27.355 r
Demo_sb_0/CORERESETP_0/count_sdif0[7]:ALn Library recovery time ADLIB:SLE - 0.353 27.002
data required time 27.002
Operating Conditions WORST

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET Demo_sb_0/CCC_0/GL0 to Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Operating Conditions
Path 1 Demo_sb_0/CORERESETP_0/count_sdif0_enable:CLK Demo_sb_0/CORERESETP_0/count_sdif0_enable_q1:D 4.469 8.399 8.776 17.175 0.174 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Demo_sb_0/CORERESETP_0/count_sdif0_enable:CLK
To: Demo_sb_0/CORERESETP_0/count_sdif0_enable_q1:D
data required time 17.175
data arrival time - 8.776
slack 8.399
Data arrival time calculation
Demo_sb_0/CCC_0/GL0 0.000 0.000
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 2.235 2.235
Demo_sb_0/CCC_0/GL0_INST:An net Demo_sb_0/CCC_0/GL0_net + 0.423 2.658 r
Demo_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 2.836 12 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB9:An net Demo_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.636 3.472 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB9:YL cell ADLIB:RGB + 0.317 3.789 10 r
Demo_sb_0/CORERESETP_0/count_sdif0_enable:CLK net Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB9_rgbl_net_1 + 0.518 4.307 r
Demo_sb_0/CORERESETP_0/count_sdif0_enable:Q cell ADLIB:SLE + 0.108 4.415 1 f
mdr_Demo_sb_0/CORERESETP_0/count_sdif0_enable_q1_CFG1D_TEST3:A net Demo_sb_0/CORERESETP_0/count_sdif0_enable_Z + 0.837 5.252 f
mdr_Demo_sb_0/CORERESETP_0/count_sdif0_enable_q1_CFG1D_TEST3:Y cell ADLIB:CFG1D_TEST + 0.372 5.624 1 f
mdr_Demo_sb_0/CORERESETP_0/count_sdif0_enable_q1_CFG1D_TEST2:A net mdr_Demo_sb_0/CORERESETP_0/count_sdif0_enable_q1_CFG1D_TEST_net3 + 0.300 5.924 f
mdr_Demo_sb_0/CORERESETP_0/count_sdif0_enable_q1_CFG1D_TEST2:Y cell ADLIB:CFG1D_TEST + 0.372 6.296 1 f
mdr_Demo_sb_0/CORERESETP_0/count_sdif0_enable_q1_CFG1D_TEST1:A net mdr_Demo_sb_0/CORERESETP_0/count_sdif0_enable_q1_CFG1D_TEST_net2 + 0.204 6.500 f
mdr_Demo_sb_0/CORERESETP_0/count_sdif0_enable_q1_CFG1D_TEST1:Y cell ADLIB:CFG1D_TEST + 0.372 6.872 1 f
mdr_Demo_sb_0/CORERESETP_0/count_sdif0_enable_q1_CFG1D_TEST0:A net mdr_Demo_sb_0/CORERESETP_0/count_sdif0_enable_q1_CFG1D_TEST_net1 + 0.301 7.173 f
mdr_Demo_sb_0/CORERESETP_0/count_sdif0_enable_q1_CFG1D_TEST0:Y cell ADLIB:CFG1D_TEST + 0.372 7.545 1 f
mdr_Demo_sb_0/CORERESETP_0/count_sdif0_enable_q1_CFG1D_TEST:A net mdr_Demo_sb_0/CORERESETP_0/count_sdif0_enable_q1_CFG1D_TEST_net0 + 0.205 7.750 f
mdr_Demo_sb_0/CORERESETP_0/count_sdif0_enable_q1_CFG1D_TEST:Y cell ADLIB:CFG1D_TEST + 0.372 8.122 1 f
Demo_sb_0/CORERESETP_0/count_sdif0_enable_q1:D net mdr_Demo_sb_0/CORERESETP_0/count_sdif0_enable_q1_CFG1D_TEST_net + 0.654 8.776 f
data arrival time 8.776
Data required time calculation
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Clock Constraint 10.000 10.000
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 10.000 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT + 1.797 11.797 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 11.949 1 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.583 15.532 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.374 15.906 2 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An net Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.625 16.531 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YL cell ADLIB:RGB + 0.317 16.848 17 r
Demo_sb_0/CORERESETP_0/count_sdif0_enable_q1:CLK net Demo_sb_0/FABOSC_0_RCOSC_25_50MHZ_O2F + 0.501 17.349 r
Demo_sb_0/CORERESETP_0/count_sdif0_enable_q1:D Library setup time ADLIB:SLE - 0.174 17.175
data required time 17.175
Operating Conditions WORST

Clock Domain FCCC_0/GL0

Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin FCCC_0/GL0_INST/U0_RGB1:An

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] to FCCC_0/GL0

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Operating Conditions
Path 1 SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[7] 10.954 4.799 10.954 15.753 -0.278 WORST
Path 2 SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[3] 10.897 4.829 10.897 15.726 -0.251 WORST
Path 3 SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[5] 10.844 4.951 10.844 15.795 -0.320 WORST
Path 4 SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[6] 10.693 5.112 10.693 15.805 -0.330 WORST
Path 5 SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[4] 10.609 5.123 10.609 15.732 -0.257 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]
To: Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[7]
data required time 15.753
data arrival time - 10.954
slack 4.799
Data arrival time calculation
SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] 0.000 0.000
SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Clock source + 0.000 0.000 r
SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXDATA[37] cell ADLIB:SERDESIF_075_IP + 0.160 0.160 1 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100_CFG1D_TEST2:A net SERDES_IF2_0_EPCS_3_RX_DATA[7] + 7.144 7.304 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100_CFG1D_TEST2:Y cell ADLIB:CFG1D_TEST + 0.372 7.676 1 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100_CFG1D_TEST1:A net mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100_CFG1D_TEST_net2 + 0.204 7.880 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100_CFG1D_TEST1:Y cell ADLIB:CFG1D_TEST + 0.372 8.252 1 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100_CFG1D_TEST0:A net mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100_CFG1D_TEST_net1 + 0.689 8.941 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100_CFG1D_TEST0:Y cell ADLIB:CFG1D_TEST + 0.372 9.313 1 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100_CFG1D_TEST:A net mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100_CFG1D_TEST_net0 + 0.205 9.518 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100_CFG1D_TEST:Y cell ADLIB:CFG1D_TEST + 0.372 9.890 1 f
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100:B net mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100_CFG1D_TEST_net + 0.588 10.478 f
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100:IPB cell ADLIB:IP_INTERFACE + 0.224 10.702 1 f
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[7] net Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/RCGF_net[7] + 0.252 10.954 f
data arrival time 10.954
Data required time calculation
FCCC_0/GL0 Clock Constraint 8.000 8.000
FCCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 8.000 r
Clock generation + 5.419 13.419
FCCC_0/GL0_INST:An net FCCC_0/GL0_net + 0.456 13.875 r
FCCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 14.053 1 f
FCCC_0/GL0_INST/U0_RGB1:An net FCCC_0/GL0_INST/U0_YWn_GEast + 0.600 14.653 f
FCCC_0/GL0_INST/U0_RGB1:YR cell ADLIB:RGB + 0.316 14.969 1 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_92:A net FCCC_0/GL0_INST/U0_RGB1_YR + 0.411 15.380 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_92:IPA cell ADLIB:IP_INTERFACE + 0.194 15.574 0 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RX_CLKPF net Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/RX_CLKPF_net + 0.221 15.795 r
clock-to-clock uncertainty - 0.320 15.475
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[7] Library setup time ADLIB:MSS_075_IP - -0.278 15.753
data required time 15.753
Operating Conditions WORST

Clock Domain FCCC_0/GL1

Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin FCCC_0/GL1_INST/U0_RGB1:An

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] to FCCC_0/GL1

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Operating Conditions
Path 1 SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[7] 10.954 4.560 10.954 15.514 -0.010 WORST
Path 2 SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[3] 10.897 4.592 10.897 15.489 0.015 WORST
Path 3 SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[5] 10.844 4.664 10.844 15.508 -0.004 WORST
Path 4 SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[4] 10.609 4.766 10.609 15.375 0.129 WORST
Path 5 SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[6] 10.693 4.774 10.693 15.467 0.037 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]
To: Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[7]
data required time 15.514
data arrival time - 10.954
slack 4.560
Data arrival time calculation
SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] 0.000 0.000
SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Clock source + 0.000 0.000 r
SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXDATA[37] cell ADLIB:SERDESIF_075_IP + 0.160 0.160 1 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100_CFG1D_TEST2:A net SERDES_IF2_0_EPCS_3_RX_DATA[7] + 7.144 7.304 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100_CFG1D_TEST2:Y cell ADLIB:CFG1D_TEST + 0.372 7.676 1 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100_CFG1D_TEST1:A net mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100_CFG1D_TEST_net2 + 0.204 7.880 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100_CFG1D_TEST1:Y cell ADLIB:CFG1D_TEST + 0.372 8.252 1 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100_CFG1D_TEST0:A net mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100_CFG1D_TEST_net1 + 0.689 8.941 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100_CFG1D_TEST0:Y cell ADLIB:CFG1D_TEST + 0.372 9.313 1 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100_CFG1D_TEST:A net mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100_CFG1D_TEST_net0 + 0.205 9.518 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100_CFG1D_TEST:Y cell ADLIB:CFG1D_TEST + 0.372 9.890 1 f
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100:B net mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100_CFG1D_TEST_net + 0.588 10.478 f
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100:IPB cell ADLIB:IP_INTERFACE + 0.224 10.702 1 f
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[7] net Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/RCGF_net[7] + 0.252 10.954 f
data arrival time 10.954
Data required time calculation
FCCC_0/GL1 Clock Constraint 8.000 8.000
FCCC_0/CCC_INST/INST_CCC_IP:GL1 Clock source + 0.000 8.000 r
Clock generation + 5.449 13.449
FCCC_0/GL1_INST:An net FCCC_0/GL1_net + 0.461 13.910 r
FCCC_0/GL1_INST:YEn cell ADLIB:GBM + 0.178 14.088 1 f
FCCC_0/GL1_INST/U0_RGB1:An net FCCC_0/GL1_INST/U0_YWn_GEast + 0.599 14.687 f
FCCC_0/GL1_INST/U0_RGB1:YR cell ADLIB:RGB + 0.316 15.003 1 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_91:A net FCCC_0/GL1_INST/U0_RGB1_YR + 0.405 15.408 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_91:IPA cell ADLIB:IP_INTERFACE + 0.194 15.602 0 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:TX_CLKPF net Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/TX_CLKPF_net + 0.222 15.824 r
clock-to-clock uncertainty - 0.320 15.504
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[7] Library setup time ADLIB:MSS_075_IP - -0.010 15.514
data required time 15.514
Operating Conditions WORST

Clock Domain FCCC_1/GL0

Info: The maximum frequency of this clock domain is limited by the period of pin Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:GTX_CLKPF

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1]

Info: The maximum frequency of this clock domain is limited by the period of pin SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]

Info: The maximum frequency of this clock domain is limited by the period of pin SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1]

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET FCCC_1/GL0 to SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]

No Path

Path Set Pin to Pin

SET Input to Output

No Path

Path Set User Sets