#Build: Synplify Pro (R) R-2020.09M-SP1-1, Build 100R, Feb 17 2021 #install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro #OS: Windows 8 6.2 #Hostname: HYD-LT-I62935 # Tue Jun 15 15:17:23 2021 #Implementation: synthesis Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys HDL Compiler, Version comp202009synp2, Build 102R, Built Feb 17 2021 10:19:36, @ @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Verilog Compiler, Version comp202009synp2, Build 147R, Built Mar 17 2021 10:14:42, @ @N: : | Running in 64-bit mode @I::"C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro\lib\generic\smartfusion2.v" (library work) @I::"C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb\CCC_0\Demo_sb_CCC_0_FCCC.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb\FABOSC_0\Demo_sb_FABOSC_0_OSC.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb\Demo_sb.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\hdl\Clock_check.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\SgCore\TAMPER2\2.1.300\tamper_comps.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\program_recovery_WA\TAMPER2_0\program_recovery_WA_TAMPER2_0_TAMPER2.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\program_recovery_WA\program_recovery_WA.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\top\FCCC_0\top_FCCC_0_FCCC.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\top\FCCC_1\top_FCCC_1_FCCC.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\top\SERDES_IF2_0\top_SERDES_IF2_0_SERDES_IF2_syn.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\top\SERDES_IF2_0\top_SERDES_IF2_0_SERDES_IF2.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\top\top.v" (library work) Verilog syntax check successful! Options changed - recompiling Selecting top level module top @N:CG364 : smartfusion2.v(126) | Synthesizing module AND2 in library work. Running optimization stage 1 on AND2 ....... Finished optimization stage 1 on AND2 (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB) @N:CG364 : smartfusion2.v(286) | Synthesizing module BIBUF in library work. Running optimization stage 1 on BIBUF ....... Finished optimization stage 1 on BIBUF (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB) @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC in library work. Running optimization stage 1 on VCC ....... Finished optimization stage 1 on VCC (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB) @N:CG364 : smartfusion2.v(372) | Synthesizing module GND in library work. Running optimization stage 1 on GND ....... Finished optimization stage 1 on GND (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB) @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT in library work. Running optimization stage 1 on CLKINT ....... Finished optimization stage 1 on CLKINT (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB) @N:CG364 : smartfusion2.v(729) | Synthesizing module CCC in library work. Running optimization stage 1 on CCC ....... Finished optimization stage 1 on CCC (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB) @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF in library work. Running optimization stage 1 on INBUF ....... Finished optimization stage 1 on INBUF (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB) @N:CG364 : Demo_sb_CCC_0_FCCC.v(5) | Synthesizing module Demo_sb_CCC_0_FCCC in library work. Running optimization stage 1 on Demo_sb_CCC_0_FCCC ....... Finished optimization stage 1 on Demo_sb_CCC_0_FCCC (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB) @N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP in library work. FAMILY=32'b00000000000000000000000000010011 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000001 VERSION_MAJOR=32'b00000000000000000000000000000111 VERSION_MINOR=32'b00000000000000000000000000000000 VERSION_MAJOR_VECTOR=16'b0000000000000111 VERSION_MINOR_VECTOR=16'b0000000000000000 S0=2'b00 S1=2'b01 S2=2'b10 Generated name = CoreConfigP_Z1 Running optimization stage 1 on CoreConfigP_Z1 ....... @W:CL207 : coreconfigp.v(461) | All reachable assignments to SDIF1_PENABLE assign 0, register removed by optimization. Finished optimization stage 1 on CoreConfigP_Z1 (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 95MB) @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP in library work. FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000001 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z2 Running optimization stage 1 on CoreResetP_Z2 ....... @W:CL169 : coreresetp.v(1613) | Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1581) | Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1549) | Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1517) | Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1365) | Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1300) | Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1235) | Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1089) | Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers. @W:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : coreresetp.v(1089) | Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers. Finished optimization stage 1 on CoreResetP_Z2 (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB) @N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF in library work. Running optimization stage 1 on TRIBUFF ....... Finished optimization stage 1 on TRIBUFF (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB) @N:CG364 : Demo_sb_MSS_syn.v(5) | Synthesizing module MSS_075 in library work. Running optimization stage 1 on MSS_075 ....... Finished optimization stage 1 on MSS_075 (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB) @N:CG364 : Demo_sb_MSS.v(9) | Synthesizing module Demo_sb_MSS in library work. Running optimization stage 1 on Demo_sb_MSS ....... Finished optimization stage 1 on Demo_sb_MSS (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB in library work. Running optimization stage 1 on RCOSC_25_50MHZ_FAB ....... Finished optimization stage 1 on RCOSC_25_50MHZ_FAB (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ in library work. Running optimization stage 1 on RCOSC_25_50MHZ ....... Finished optimization stage 1 on RCOSC_25_50MHZ (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : osc_comps.v(39) | Synthesizing module RCOSC_1MHZ_FAB in library work. Running optimization stage 1 on RCOSC_1MHZ_FAB ....... Finished optimization stage 1 on RCOSC_1MHZ_FAB (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : osc_comps.v(1) | Synthesizing module RCOSC_1MHZ in library work. Running optimization stage 1 on RCOSC_1MHZ ....... Finished optimization stage 1 on RCOSC_1MHZ (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : Demo_sb_FABOSC_0_OSC.v(5) | Synthesizing module Demo_sb_FABOSC_0_OSC in library work. Running optimization stage 1 on Demo_sb_FABOSC_0_OSC ....... @W:CL318 : Demo_sb_FABOSC_0_OSC.v(15) | *Output RCOSC_25_50MHZ_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. Finished optimization stage 1 on Demo_sb_FABOSC_0_OSC (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : smartfusion2.v(720) | Synthesizing module SYSRESET in library work. Running optimization stage 1 on SYSRESET ....... Finished optimization stage 1 on SYSRESET (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : Demo_sb.v(9) | Synthesizing module Demo_sb in library work. Running optimization stage 1 on Demo_sb ....... Finished optimization stage 1 on Demo_sb (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : top_FCCC_0_FCCC.v(5) | Synthesizing module top_FCCC_0_FCCC in library work. Running optimization stage 1 on top_FCCC_0_FCCC ....... Finished optimization stage 1 on top_FCCC_0_FCCC (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : top_FCCC_1_FCCC.v(5) | Synthesizing module top_FCCC_1_FCCC in library work. Running optimization stage 1 on top_FCCC_1_FCCC ....... Finished optimization stage 1 on top_FCCC_1_FCCC (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : Clock_check.v(19) | Synthesizing module Clock_check in library work. Running optimization stage 1 on Clock_check ....... @W:CL265 : Clock_check.v(25) | Removing unused bit 25 of count[25:0]. Either assign all bits or reduce the width of the signal. @A:CL291 : Clock_check.v(25) | Register pulse with asynchronous load is being synthesized in compatability mode. A synthesis/simulation mismatch is possible. Finished optimization stage 1 on Clock_check (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : tamper_comps.v(1) | Synthesizing module TAMPER in library work. Running optimization stage 1 on TAMPER ....... Finished optimization stage 1 on TAMPER (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : program_recovery_WA_TAMPER2_0_TAMPER2.v(5) | Synthesizing module program_recovery_WA_TAMPER2_0_TAMPER2 in library work. Running optimization stage 1 on program_recovery_WA_TAMPER2_0_TAMPER2 ....... Finished optimization stage 1 on program_recovery_WA_TAMPER2_0_TAMPER2 (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : program_recovery_WA.v(9) | Synthesizing module program_recovery_WA in library work. Running optimization stage 1 on program_recovery_WA ....... Finished optimization stage 1 on program_recovery_WA (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : smartfusion2.v(320) | Synthesizing module INBUF_DIFF in library work. Running optimization stage 1 on INBUF_DIFF ....... Finished optimization stage 1 on INBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : top_SERDES_IF2_0_SERDES_IF2_syn.v(5) | Synthesizing module SERDESIF_075 in library work. Running optimization stage 1 on SERDESIF_075 ....... Finished optimization stage 1 on SERDESIF_075 (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : top_SERDES_IF2_0_SERDES_IF2.v(5) | Synthesizing module top_SERDES_IF2_0_SERDES_IF2 in library work. Running optimization stage 1 on top_SERDES_IF2_0_SERDES_IF2 ....... Finished optimization stage 1 on top_SERDES_IF2_0_SERDES_IF2 (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) @N:CG364 : top.v(9) | Synthesizing module top in library work. Running optimization stage 1 on top ....... Finished optimization stage 1 on top (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) Running optimization stage 2 on top ....... Finished optimization stage 2 on top (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) Running optimization stage 2 on top_SERDES_IF2_0_SERDES_IF2 ....... Finished optimization stage 2 on top_SERDES_IF2_0_SERDES_IF2 (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) Running optimization stage 2 on SERDESIF_075 ....... Finished optimization stage 2 on SERDESIF_075 (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) Running optimization stage 2 on INBUF_DIFF ....... Finished optimization stage 2 on INBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) Running optimization stage 2 on program_recovery_WA ....... Finished optimization stage 2 on program_recovery_WA (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) Running optimization stage 2 on program_recovery_WA_TAMPER2_0_TAMPER2 ....... Finished optimization stage 2 on program_recovery_WA_TAMPER2_0_TAMPER2 (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) Running optimization stage 2 on TAMPER ....... Finished optimization stage 2 on TAMPER (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) Running optimization stage 2 on Clock_check ....... Finished optimization stage 2 on Clock_check (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) Running optimization stage 2 on top_FCCC_1_FCCC ....... Finished optimization stage 2 on top_FCCC_1_FCCC (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) Running optimization stage 2 on top_FCCC_0_FCCC ....... Finished optimization stage 2 on top_FCCC_0_FCCC (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) Running optimization stage 2 on Demo_sb ....... Finished optimization stage 2 on Demo_sb (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) Running optimization stage 2 on SYSRESET ....... Finished optimization stage 2 on SYSRESET (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) Running optimization stage 2 on Demo_sb_FABOSC_0_OSC ....... @N:CL159 : Demo_sb_FABOSC_0_OSC.v(14) | Input XTL is unused. Finished optimization stage 2 on Demo_sb_FABOSC_0_OSC (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) Running optimization stage 2 on RCOSC_1MHZ ....... Finished optimization stage 2 on RCOSC_1MHZ (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) Running optimization stage 2 on RCOSC_1MHZ_FAB ....... Finished optimization stage 2 on RCOSC_1MHZ_FAB (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) Running optimization stage 2 on RCOSC_25_50MHZ ....... Finished optimization stage 2 on RCOSC_25_50MHZ (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) Running optimization stage 2 on RCOSC_25_50MHZ_FAB ....... Finished optimization stage 2 on RCOSC_25_50MHZ_FAB (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) Running optimization stage 2 on Demo_sb_MSS ....... Finished optimization stage 2 on Demo_sb_MSS (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) Running optimization stage 2 on MSS_075 ....... Finished optimization stage 2 on MSS_075 (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) Running optimization stage 2 on TRIBUFF ....... Finished optimization stage 2 on TRIBUFF (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) Running optimization stage 2 on CoreResetP_Z2 ....... @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state. Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state. Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state. Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state. Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state. Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @N:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused. @N:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused. @N:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused. @N:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused. @N:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused. @N:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused. @N:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused. @N:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused. @N:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused. @N:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused. @N:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused. @N:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused. @N:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused. @N:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused. Finished optimization stage 2 on CoreResetP_Z2 (CPU Time 0h:00m:00s, Memory Used current: 97MB peak: 97MB) Running optimization stage 2 on CoreConfigP_Z1 ....... @N:CL201 : coreconfigp.v(447) | Trying to extract state machine for register state. Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL159 : coreconfigp.v(71) | Input SDIF1_PREADY is unused. @N:CL159 : coreconfigp.v(72) | Input SDIF1_PSLVERR is unused. Finished optimization stage 2 on CoreConfigP_Z1 (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 108MB) Running optimization stage 2 on Demo_sb_CCC_0_FCCC ....... Finished optimization stage 2 on Demo_sb_CCC_0_FCCC (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 108MB) Running optimization stage 2 on INBUF ....... Finished optimization stage 2 on INBUF (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 108MB) Running optimization stage 2 on CCC ....... Finished optimization stage 2 on CCC (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 108MB) Running optimization stage 2 on CLKINT ....... Finished optimization stage 2 on CLKINT (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 108MB) Running optimization stage 2 on GND ....... Finished optimization stage 2 on GND (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 108MB) Running optimization stage 2 on VCC ....... Finished optimization stage 2 on VCC (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 108MB) Running optimization stage 2 on BIBUF ....... Finished optimization stage 2 on BIBUF (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 108MB) Running optimization stage 2 on AND2 ....... Finished optimization stage 2 on AND2 (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 108MB) For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 98MB peak: 108MB) Process took 0h:00m:04s realtime, 0h:00m:04s cputime Process completed successfully. # Tue Jun 15 15:17:28 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202009synp2, Build 102R, Built Feb 17 2021 10:19:36, @ @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 95MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Jun 15 15:17:28 2021 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: top_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 23MB peak: 32MB) Process took 0h:00m:05s realtime, 0h:00m:05s cputime Process completed successfully. # Tue Jun 15 15:17:28 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202009synp2, Build 102R, Built Feb 17 2021 10:19:36, @ @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 96MB peak: 96MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Jun 15 15:17:30 2021 ###########################################################] Premap Report # Tue Jun 15 15:17:31 2021 Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Generic Technology Pre-mapping, Version map202009act, Build 069R, Built Mar 17 2021 10:25:05, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 123MB peak: 130MB) Reading constraint file: C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\designer\top\synthesis.fdc Linked File: top_scck.rpt See clock summary report "C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\synthesis\top_scck.rpt" @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 132MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB) @W:BN132 : coreresetp.v(1089) | Removing sequential instance Demo_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance Demo_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MO111 : demo_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_sb_fabosc_0_osc.v(15) | Tristate driver RCOSC_25_50MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net RCOSC_25_50MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @W:MO129 : coreresetp.v(676) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance Demo_sb_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance Demo_sb_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(1388) | Sequential instance Demo_sb_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation. @N:BN362 : coreconfigp.v(461) | Removing sequential instance MDDR_PENABLE (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF3_PENABLE (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:FX1184 : | Applying syn_allowed_resources blockrams=109 on top level netlist top Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ------------------------------------------------------------------------------------------------------------------------------------------------ 0 - System 100.0 MHz 10.000 system system_clkgroup 0 0 - Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 111 0 - Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_1 56 0 - Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 49 0 - top_FCCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_4 1 0 - top_FCCC_0_FCCC|GL1_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_3 1 0 - top_FCCC_1_FCCC|GL0_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_5 1 0 - top_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_6 1 ================================================================================================================================================ Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System 0 - - - - Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock 111 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST.CLK_CONFIG_APB(MSS_075) SERDES_IF2_0.SERDESIF_INST.APB_CLK - Demo_sb_0.CORECONFIGP_0.un1_FIC_2_APB_M_PCLK.I[0](inv) Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock 56 Demo_sb_0.FABOSC_0.I_RCOSC_25_50MHZ.CLKOUT(RCOSC_25_50MHZ) program_recovery_WA_0.Clock_check_0.count[24:0].C - Demo_sb_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB.A(RCOSC_25_50MHZ_FAB) Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock 49 Demo_sb_0.CCC_0.CCC_INST.GL0(CCC) Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST.CLK_BASE - Demo_sb_0.CCC_0.GL0_INST.I(BUFG) top_FCCC_0_FCCC|GL0_net_inferred_clock 1 FCCC_0.CCC_INST.GL0(CCC) Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST.RX_CLKPF - FCCC_0.GL0_INST.I(BUFG) top_FCCC_0_FCCC|GL1_net_inferred_clock 1 FCCC_0.CCC_INST.GL1(CCC) Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST.TX_CLKPF - FCCC_0.GL1_INST.I(BUFG) top_FCCC_1_FCCC|GL0_net_inferred_clock 1 FCCC_1.CCC_INST.GL0(CCC) Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST.GTX_CLKPF - FCCC_1.GL0_INST.I(BUFG) top_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock 1 SERDES_IF2_0.refclk1_inbuf_diff.Y(INBUF_DIFF) SERDES_IF2_0.SERDESIF_INST.REFCLK1 - - ================================================================================================================================================================================================================================================================================== @W:MT530 : coreconfigp.v(546) | Found inferred clock Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock which controls 111 sequential elements including Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[31:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coreresetp.v(1485) | Found inferred clock Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock which controls 56 sequential elements including Demo_sb_0.CORERESETP_0.count_sdif0[12:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coreresetp.v(1170) | Found inferred clock Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock which controls 49 sequential elements including Demo_sb_0.CORERESETP_0.count_sdif0_enable. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : demo_sb_mss.v(324) | Found inferred clock top_FCCC_0_FCCC|GL1_net_inferred_clock which controls 1 sequential elements including Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : demo_sb_mss.v(324) | Found inferred clock top_FCCC_0_FCCC|GL0_net_inferred_clock which controls 1 sequential elements including Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : demo_sb_mss.v(324) | Found inferred clock top_FCCC_1_FCCC|GL0_net_inferred_clock which controls 1 sequential elements including Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : top_serdes_if2_0_serdes_if2.v(103) | Found inferred clock top_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock which controls 1 sequential elements including SERDES_IF2_0.SERDESIF_INST. This clock has no specified timing constraint which may adversely impact design performance. @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\synthesis\top.sap. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 169MB peak: 169MB) Encoding state machine state[2:0] (in view: work.CoreConfigP_Z1(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z2(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sdif0_state[3:0] (in view: work.CoreResetP_Z2(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : coreresetp.v(1170) | There are no possible illegal states for state machine sdif0_state[3:0] (in view: work.CoreResetP_Z2(verilog)); safe FSM implementation is not required. Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB) Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 85MB peak: 172MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Jun 15 15:17:32 2021 ###########################################################] Map & Optimize Report # Tue Jun 15 15:17:32 2021 Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Generic Technology Mapper, Version map202009act, Build 069R, Built Mar 17 2021 10:25:05, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 130MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 130MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 130MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 130MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 164MB peak: 164MB) @N:MO111 : demo_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_sb_fabosc_0_osc.v(15) | Tristate driver RCOSC_25_50MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net RCOSC_25_50MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @W:BN132 : coreresetp.v(963) | Removing sequential instance Demo_sb_0.CORERESETP_0.sdif3_spll_lock_q1 because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif0_spll_lock_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(963) | Removing sequential instance Demo_sb_0.CORERESETP_0.sdif3_spll_lock_q2 because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif0_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance. #### START OF SSF LOG MESSAGES #### #### END OF SSF LOG MESSAGES #### Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 168MB peak: 168MB) Encoding state machine CORECONFIGP_0.state[2:0] (in view: work.Demo_sb(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @W:MO160 : coreconfigp.v(255) | Register bit CORECONFIGP_0.paddr[16] (in view view:work.Demo_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z2(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sdif0_state[3:0] (in view: work.CoreResetP_Z2(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : coreresetp.v(1170) | There are no possible illegal states for state machine sdif0_state[3:0] (in view: work.CoreResetP_Z2(verilog)); safe FSM implementation is not required. @N:MO231 : coreresetp.v(1485) | Found counter in view:work.CoreResetP_Z2(verilog) instance count_sdif0[12:0] @W:BN132 : coreresetp.v(1089) | Removing instance Demo_sb_0.CORERESETP_0.SDIF_READY_int because it is equivalent to instance Demo_sb_0.CORERESETP_0.sm0_state[6]. To keep the instance, apply constraint syn_preserve=1 on the instance. Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 169MB peak: 169MB) @N:BN362 : coreresetp.v(1170) | Removing sequential instance Demo_sb_0.CORERESETP_0.SDIF0_CORE_RESET_N_0 (in view: work.top(verilog)) because it does not drive other instances. Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 170MB peak: 170MB) Available hyper_sources - for debug and ip models None Found Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB) Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 171MB peak: 171MB) Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:01s -0.05ns 143 / 206 2 0h:00m:01s -0.05ns 140 / 206 @N:FX271 : coreconfigp.v(461) | Replicating instance Demo_sb_0.CORECONFIGP_0.psel (in view: work.top(verilog)) with 4 loads 1 time to improve timing. Timing driven replication report Added 1 Registers via timing driven replication Added 1 LUTs via timing driven replication 3 0h:00m:01s 0.44ns 141 / 207 @N:FP130 : | Promoting Net Demo_sb_0.FIC_2_APB_M_PRESET_N_arst on CLKINT I_95 @N:FP130 : | Promoting Net Demo_sb_0_INIT_APB_S_PCLK on CLKINT I_96 @N:FP130 : | Promoting Net Demo_sb_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT I_97 @N:FP130 : | Promoting Net Demo_sb_0.CORERESETP_0.sdif0_areset_n_rcosc on CLKINT I_98 @N:FP130 : | Promoting Net Demo_sb_0.CORERESETP_0.sm0_areset_n_arst on CLKINT I_99 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 173MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 1 non-gated/non-generated clock tree(s) driving 1 clock pin(s) of sequential element(s) 7 gated/generated clock tree(s) driving 214 clock pin(s) of sequential element(s) 0 instances converted, 214 sequential instances remain driven by gated/generated clocks ========================================= Non-Gated/Non-Generated Clocks ========================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ------------------------------------------------------------------------------------------------------------------ ClockId0008 SERDES_IF2_0.refclk1_inbuf_diff INBUF_DIFF 1 SERDES_IF2_0.SERDESIF_INST ================================================================================================================== ================================================================================================== Gated/Generated Clocks ================================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST MSS_075 110 Demo_sb_0.CORECONFIGP_0.soft_reset_reg[10] No gated clock conversion method for cell cell:ACG4.SLE ClockId0002 Demo_sb_0.FABOSC_0.I_RCOSC_25_50MHZ RCOSC_25_50MHZ 57 Demo_sb_0.CORERESETP_0.release_sdif0_core No gated clock conversion method for cell cell:ACG4.SLE ClockId0003 Demo_sb_0.CCC_0.CCC_INST CCC 43 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_075 ClockId0004 FCCC_0.CCC_INST CCC 1 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_075 ClockId0005 FCCC_0.CCC_INST CCC 1 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_075 ClockId0006 FCCC_1.CCC_INST CCC 1 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_075 ClockId0007 program_recovery_WA_0.Clock_check_0.un1_pulse10 CFG4 1 program_recovery_WA_0.Clock_check_0.un1_pulse10_1_rs No gated clock conversion method for cell cell:ACG4.SLE ============================================================================================================================================================================================================================ ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 142MB peak: 173MB) Writing Analyst data base C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\synthesis\synwork\top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 172MB peak: 173MB) Writing EDIF Netlist and constraint files @N:FX1056 : | Writing EDF file: C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\synthesis\top.edn @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Writing FDC file C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\synthesis\top_synplify.fdc Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 174MB) Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 175MB) Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 173MB peak: 175MB) @W:MT246 : program_recovery_wa_tamper2_0_tamper2.v(31) | Blackbox TAMPER is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : top_fccc_1_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on net Demo_sb_0.Demo_sb_MSS_0.FIC_2_APB_M_PCLK. @W:MT420 : | Found inferred clock Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock with period 10.00ns. Please declare a user-defined clock on net Demo_sb_0.FABOSC_0.N_RCOSC_25_50MHZ_CLKOUT. @W:MT420 : | Found inferred clock Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on net Demo_sb_0.CCC_0.GL0_net. @W:MT420 : | Found inferred clock top_FCCC_0_FCCC|GL1_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on net FCCC_0.GL1_net. @W:MT420 : | Found inferred clock top_FCCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on net FCCC_0.GL0_net. @W:MT420 : | Found inferred clock top_FCCC_1_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on net FCCC_1.GL0_net. @W:MT420 : | Found inferred clock top_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock with period 10.00ns. Please declare a user-defined clock on net SERDES_IF2_0.REFCLK1_OUT. ##### START OF TIMING REPORT #####[ # Timing report written on Tue Jun 15 15:17:35 2021 # Top view: top Requested Frequency: 100.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\designer\top\synthesis.fdc @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: 0.778 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------------------------------ Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 400.4 MHz 10.000 2.498 7.503 inferred Inferred_clkgroup_2 Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock 100.0 MHz 502.7 MHz 10.000 1.989 8.011 inferred Inferred_clkgroup_1 Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 118.4 MHz 10.000 8.443 0.778 inferred Inferred_clkgroup_0 top_FCCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_4 top_FCCC_0_FCCC|GL1_net_inferred_clock 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_3 top_FCCC_1_FCCC|GL0_net_inferred_clock 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_5 top_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_6 System 100.0 MHz 708.8 MHz 10.000 1.411 8.589 system system_clkgroup ================================================================================================================================================================== Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 10.000 8.589 | No paths - | No paths - | No paths - Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock | 10.000 3.462 | No paths - | 5.000 3.228 | 5.000 0.778 Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock | Diff grp - | No paths - | No paths - | No paths - Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock System | 10.000 8.524 | No paths - | No paths - | No paths - Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock | 10.000 8.011 | No paths - | No paths - | No paths - Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock | Diff grp - | No paths - | No paths - | No paths - Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock | Diff grp - | No paths - | No paths - | No paths - Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock | 10.000 7.503 | No paths - | No paths - | No paths - ================================================================================================================================================================================================================ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- Demo_sb_0.CORERESETP_0.release_sdif0_core_clk_base Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q release_sdif0_core_clk_base 0.094 7.503 Demo_sb_0.CORERESETP_0.ddr_settled_clk_base Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q ddr_settled_clk_base 0.094 7.570 Demo_sb_0.CORERESETP_0.sdif0_spll_lock_q2 Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q next_sm0_state18 0.094 7.682 Demo_sb_0.CORERESETP_0.CONFIG1_DONE_clk_base Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q CONFIG1_DONE_clk_base 0.094 7.724 Demo_sb_0.CORERESETP_0.release_sdif1_core_clk_base Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q release_sdif1_core_clk_base 0.094 8.145 Demo_sb_0.CORERESETP_0.release_sdif2_core_clk_base Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q release_sdif2_core_clk_base 0.094 8.185 Demo_sb_0.CORERESETP_0.release_sdif3_core_clk_base Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q release_sdif3_core_clk_base 0.094 8.252 Demo_sb_0.CORERESETP_0.sdif0_state[0] Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q sdif0_state[0] 0.094 8.504 Demo_sb_0.CORERESETP_0.sm0_state[4] Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q sm0_state[4] 0.094 8.600 Demo_sb_0.CORERESETP_0.sdif0_state[1] Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q sdif0_state[1] 0.094 8.607 ======================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- Demo_sb_0.CORERESETP_0.sm0_state[4] Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE D sm0_state_ns[4] 9.778 7.503 Demo_sb_0.CORERESETP_0.SDIF_RELEASED_int Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE EN next_sdif_released_0_sqmuxa 9.707 7.626 Demo_sb_0.CORERESETP_0.sm0_state[5] Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE D sm0_state_ns[5] 9.778 7.634 Demo_sb_0.CORERESETP_0.count_sdif0_enable Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE EN N_280_i 9.707 7.682 Demo_sb_0.CORERESETP_0.SDIF0_PHY_RESET_N_int Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE EN next_sdif0_phy_reset_n_0_sqmuxa 9.707 7.769 Demo_sb_0.CORERESETP_0.sdif0_state[0] Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE D N_5_mux_i 9.778 7.871 Demo_sb_0.CORERESETP_0.sm0_state[3] Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE D sm0_state_ns[3] 9.778 8.602 Demo_sb_0.CORERESETP_0.sdif0_state[1] Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE D N_4_i 9.778 8.634 Demo_sb_0.CORERESETP_0.count_sdif0_enable Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE D sdif0_state_i[0] 9.778 8.637 Demo_sb_0.CORERESETP_0.sm0_state[2] Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE D sm0_state_ns[2] 9.778 8.691 ====================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 2.276 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 7.503 Number of logic level(s): 3 Starting point: Demo_sb_0.CORERESETP_0.release_sdif0_core_clk_base / Q Ending point: Demo_sb_0.CORERESETP_0.sm0_state[4] / D The start point is clocked by Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK The end point is clocked by Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------- Demo_sb_0.CORERESETP_0.release_sdif0_core_clk_base SLE Q Out 0.094 0.094 f - release_sdif0_core_clk_base Net - - 0.216 - 1 Demo_sb_0.CORERESETP_0.next_sdif0_state19 CFG2 B In - 0.310 f - Demo_sb_0.CORERESETP_0.next_sdif0_state19 CFG2 Y Out 0.143 0.453 f - next_sdif0_state19 Net - - 0.432 - 2 Demo_sb_0.CORERESETP_0.next_sm0_state25 CFG4 D In - 0.885 f - Demo_sb_0.CORERESETP_0.next_sm0_state25 CFG4 Y Out 0.250 1.135 f - next_sm0_state25 Net - - 0.648 - 3 Demo_sb_0.CORERESETP_0.sm0_state_ns[4] CFG4 D In - 1.784 f - Demo_sb_0.CORERESETP_0.sm0_state_ns[4] CFG4 Y Out 0.276 2.059 r - sm0_state_ns[4] Net - - 0.216 - 1 Demo_sb_0.CORERESETP_0.sm0_state[4] SLE D In - 2.276 r - ================================================================================================================= Total path delay (propagation time + setup) of 2.497 is 0.985(39.4%) logic and 1.512(60.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------- Demo_sb_0.CORERESETP_0.count_sdif0[0] Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_sdif0[0] 0.076 8.011 Demo_sb_0.CORERESETP_0.count_sdif0[1] Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_sdif0[1] 0.076 8.295 Demo_sb_0.CORERESETP_0.count_sdif0[3] Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_sdif0[3] 0.076 8.314 Demo_sb_0.CORERESETP_0.count_sdif0[6] Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_sdif0[6] 0.094 8.350 Demo_sb_0.CORERESETP_0.count_sdif0[2] Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_sdif0[2] 0.094 8.378 Demo_sb_0.CORERESETP_0.count_sdif0[4] Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_sdif0[4] 0.076 8.386 Demo_sb_0.CORERESETP_0.count_sdif0[5] Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_sdif0[5] 0.094 8.418 Demo_sb_0.CORERESETP_0.count_sdif0[8] Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_sdif0[8] 0.094 8.418 Demo_sb_0.CORERESETP_0.count_sdif0[10] Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_sdif0[10] 0.076 8.423 Demo_sb_0.CORERESETP_0.count_sdif0[11] Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_sdif0[11] 0.094 8.457 ================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Demo_sb_0.CORERESETP_0.release_sdif0_core Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE EN release_sdif0_core6 9.707 8.011 Demo_sb_0.CORERESETP_0.count_sdif0[12] Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_sdif0_s[12] 9.778 8.425 Demo_sb_0.CORERESETP_0.count_sdif0[11] Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_sdif0_s[11] 9.778 8.440 Demo_sb_0.CORERESETP_0.count_sdif0[10] Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_sdif0_s[10] 9.778 8.454 Demo_sb_0.CORERESETP_0.count_sdif0[9] Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_sdif0_s[9] 9.778 8.468 Demo_sb_0.CORERESETP_0.count_sdif0[8] Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_sdif0_s[8] 9.778 8.482 Demo_sb_0.CORERESETP_0.count_sdif0[7] Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_sdif0_s[7] 9.778 8.496 Demo_sb_0.CORERESETP_0.count_sdif0[6] Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_sdif0_s[6] 9.778 8.511 program_recovery_WA_0.TAMPER2_0.TAMPER_INST Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock TAMPER RESET_N pulse_1_i 10.000 8.524 Demo_sb_0.CORERESETP_0.count_sdif0[5] Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_sdif0_s[5] 9.778 8.525 ================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.293 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.707 - Propagation time: 1.696 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 8.011 Number of logic level(s): 2 Starting point: Demo_sb_0.CORERESETP_0.count_sdif0[0] / Q Ending point: Demo_sb_0.CORERESETP_0.release_sdif0_core / EN The start point is clocked by Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK The end point is clocked by Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------- Demo_sb_0.CORERESETP_0.count_sdif0[0] SLE Q Out 0.076 0.076 r - count_sdif0[0] Net - - 0.648 - 3 Demo_sb_0.CORERESETP_0.release_sdif0_core6_8 CFG4 D In - 0.724 r - Demo_sb_0.CORERESETP_0.release_sdif0_core6_8 CFG4 Y Out 0.284 1.008 f - release_sdif0_core6_8 Net - - 0.216 - 1 Demo_sb_0.CORERESETP_0.release_sdif0_core6 CFG4 D In - 1.224 f - Demo_sb_0.CORERESETP_0.release_sdif0_core6 CFG4 Y Out 0.250 1.474 f - release_sdif0_core6 Net - - 0.221 - 1 Demo_sb_0.CORERESETP_0.release_sdif0_core SLE EN In - 1.696 f - =========================================================================================================== Total path delay (propagation time + setup) of 1.989 is 0.904(45.4%) logic and 1.085(54.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Demo_sb_0.CORECONFIGP_0.psel_fast Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q psel_fast 0.094 0.778 Demo_sb_0.CORECONFIGP_0.psel Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q psel 0.094 2.424 Demo_sb_0.CORECONFIGP_0.SDIF0_PENABLE Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q Demo_sb_0_SDIF0_INIT_APB_PENABLE 0.094 3.200 Demo_sb_0.CORECONFIGP_0.state[1] Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q state[1] 0.076 3.228 Demo_sb_0.CORECONFIGP_0.paddr[15] Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q Demo_sb_0_SDIF0_INIT_APB_PADDR[15] 0.076 3.287 SERDES_IF2_0.SERDESIF_INST Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SERDESIF_075 APB_PRDATA[8] Demo_sb_0_SDIF0_INIT_APB_PRDATA[8] 5.255 3.462 SERDES_IF2_0.SERDESIF_INST Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SERDESIF_075 APB_PRDATA[13] Demo_sb_0_SDIF0_INIT_APB_PRDATA[13] 5.196 3.521 SERDES_IF2_0.SERDESIF_INST Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SERDESIF_075 APB_PRDATA[9] Demo_sb_0_SDIF0_INIT_APB_PRDATA[9] 5.129 3.588 Demo_sb_0.CORECONFIGP_0.state[0] Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q state[0] 0.076 3.599 SERDES_IF2_0.SERDESIF_INST Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SERDESIF_075 APB_PRDATA[17] Demo_sb_0_SDIF0_INIT_APB_PRDATA[17] 5.201 3.626 ======================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SERDES_IF2_0.SERDESIF_INST Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SERDESIF_075 APB_PSEL Demo_sb_0_SDIF0_INIT_APB_PSELx 2.269 0.778 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PREADY Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0 4.707 2.322 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[2] Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[2] 4.778 2.335 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[3] Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[3] 4.778 2.335 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[4] Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[4] 4.778 2.335 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[5] Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[5] 4.778 2.335 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[6] Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[6] 4.778 2.335 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[7] Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[7] 4.778 2.335 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[8] Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[8] 4.778 2.335 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[9] Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[9] 4.778 2.335 ============================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.000 - Setup time: 2.731 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.269 - Propagation time: 1.491 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 0.778 Number of logic level(s): 1 Starting point: Demo_sb_0.CORECONFIGP_0.psel_fast / Q Ending point: SERDES_IF2_0.SERDESIF_INST / APB_PSEL The start point is clocked by Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock [falling] (rise=0.000 fall=5.000 period=10.000) on pin CLK The end point is clocked by Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin APB_CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------- Demo_sb_0.CORECONFIGP_0.psel_fast SLE Q Out 0.094 0.094 f - psel_fast Net - - 0.216 - 1 Demo_sb_0.CORECONFIGP_0.R_SDIF0_PSEL CFG2 A In - 0.310 f - Demo_sb_0.CORECONFIGP_0.R_SDIF0_PSEL CFG2 Y Out 0.076 0.386 f - Demo_sb_0_SDIF0_INIT_APB_PSELx Net - - 1.105 - 31 SERDES_IF2_0.SERDESIF_INST SERDESIF_075 APB_PSEL In - 1.491 f - =============================================================================================================== Total path delay (propagation time + setup) of 4.222 is 2.901(68.7%) logic and 1.321(31.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------ program_recovery_WA_0.Clock_check_0.un1_pulse10_1_rs System SLE Q un1_pulse10_1_rs 0.094 8.589 ============================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------- program_recovery_WA_0.TAMPER2_0.TAMPER_INST System TAMPER RESET_N pulse_1_i 10.000 8.589 ===================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 10.000 - Propagation time: 1.411 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 8.589 Number of logic level(s): 1 Starting point: program_recovery_WA_0.Clock_check_0.un1_pulse10_1_rs / Q Ending point: program_recovery_WA_0.TAMPER2_0.TAMPER_INST / RESET_N The start point is clocked by System [rising] on pin CLK The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------ program_recovery_WA_0.Clock_check_0.un1_pulse10_1_rs SLE Q Out 0.094 0.094 f - un1_pulse10_1_rs Net - - 0.216 - 1 program_recovery_WA_0.Clock_check_0.pulse_1_RNIIP8N CFG3 B In - 0.310 f - program_recovery_WA_0.Clock_check_0.pulse_1_RNIIP8N CFG3 Y Out 0.129 0.439 r - pulse_1_i Net - - 0.971 - 1 program_recovery_WA_0.TAMPER2_0.TAMPER_INST TAMPER RESET_N In - 1.411 r - ======================================================================================================================== Total path delay (propagation time + setup) of 1.411 is 0.223(15.8%) logic and 1.188(84.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 173MB peak: 175MB) Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 173MB peak: 175MB) --------------------------------------- Resource Usage Report for top Mapping to part: m2s090tsfbga484-1 Cell usage: AND2 1 use CCC 3 uses CLKINT 11 uses MSS_075 1 use RCOSC_1MHZ 1 use RCOSC_1MHZ_FAB 1 use RCOSC_25_50MHZ 1 use RCOSC_25_50MHZ_FAB 1 use SERDESIF_075 1 use SYSRESET 1 use TAMPER 1 use CFG1 6 uses CFG2 30 uses CFG3 19 uses CFG4 52 uses Carry cells: ARI1 13 uses - used for arithmetic functions Sequential Cells: SLE 209 uses DSP Blocks: 0 of 84 (0%) I/O ports: 37 I/O primitives: 19 BIBUF 3 uses INBUF 3 uses INBUF_DIFF 1 use OUTBUF 10 uses TRIBUFF 2 uses Global Clock Buffers: 11 Total LUTs: 120 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 0; LUTs = 0; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 209 + 0 + 0 + 0 = 209; Total number of LUTs after P&R: 120 + 0 + 0 + 0 = 120; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 63MB peak: 175MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime # Tue Jun 15 15:17:36 2021 ###########################################################]