Project Settings Project Name top_syn Device Name synthesis: Microchip SmartFusion2 : M2S090TS Implementation Name synthesis Top Module top Retiming 0 Resource Sharing 1 Fanout Guide 10000 Disable I/O Insertion 0 Disable Sequential Optimizations 0 FSM Compiler 1 Run Status Job Name Status CPU Time Real Time Memory Date/Time (compiler) Complete 59 35 0 - 00m:05s - 6/15/2021 3:17:28 PM (premap) Complete 32 23 0 0m:01s 0m:01s 172MB 6/15/2021 3:17:32 PM (fpga_mapper) Complete 21 13 0 0m:03s 0m:03s 175MB 6/15/2021 3:17:36 PM Multi-srs Generator Complete 00m:01s 6/15/2021 3:17:30 PM Area Summary Carry Cells 13 Sequential Cells 209 DSP Blocks (dsp_used) 0 I/O Cells 19 Global Clock Buffers 11 LUTs (total_luts) 120 Timing Summary Clock Name Req Freq Est Freq Slack Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 400.4 MHz 7.503 Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock 100.0 MHz 502.7 MHz 8.011 Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 118.4 MHz 0.778 top_FCCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz NA NA top_FCCC_0_FCCC|GL1_net_inferred_clock 100.0 MHz NA NA top_FCCC_1_FCCC|GL0_net_inferred_clock 100.0 MHz NA NA top_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock 100.0 MHz NA NA System 100.0 MHz 708.8 MHz 8.589 Optimizations Summary Combined Clock Conversion 1 / 7