#Build: Synplify Pro (R) N-2018.03M-SP1-1, Build 209R, Oct 23 2018 #install: C:\Microsemi\Libero_SoC_12.1\SynplifyPro #OS: Windows 8 6.2 #Hostname: HYD-LT-X61679 # Tue Jun 11 14:25:52 2019 #Implementation: synthesis Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: N-2018.03M-SP1-1 Install: C:\Microsemi\Libero_SoC_12.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-X61679 Implementation : synthesis Synopsys HDL Compiler, Version comp2018q2p1, Build 223R, Built Oct 23 2018 09:18:38 @N: : | Running in 64-bit mode Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: N-2018.03M-SP1-1 Install: C:\Microsemi\Libero_SoC_12.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-X61679 Implementation : synthesis Synopsys Verilog Compiler, Version comp2018q2p1, Build 223R, Built Oct 23 2018 09:18:38 @N: : | Running in 64-bit mode @I::"C:\Microsemi\Libero_SoC_12.1\SynplifyPro\lib\generic\smartfusion2.v" (library work) @I::"C:\Microsemi\Libero_SoC_12.1\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Microsemi\Libero_SoC_12.1\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_12.1\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_12.1\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo\FCCC_0\Demo_FCCC_0_FCCC.v" (library work) @I::"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo\FCCC_1\Demo_FCCC_1_FCCC.v" (library work) @I::"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo\SERDES_IF2_0\Demo_SERDES_IF2_0_SERDES_IF2_syn.v" (library work) @I::"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo\SERDES_IF2_0\Demo_SERDES_IF2_0_SERDES_IF2.v" (library work) @I::"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v" (library work) @I::"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v" (library work) @I::"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v" (library work) @I::"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb\CCC_0\Demo_sb_CCC_0_FCCC.v" (library work) @I::"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" (library work) @I::"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb\FABOSC_0\Demo_sb_FABOSC_0_OSC.v" (library work) @I::"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v" (library work) @I::"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS.v" (library work) @I::"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb\Demo_sb.v" (library work) @I::"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\hdl\Clock_check.v" (library work) @I::"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\SgCore\TAMPER2\2.1.300\tamper_comps.v" (library work) @I::"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\program_recovery_WA\TAMPER2_0\program_recovery_WA_TAMPER2_0_TAMPER2.v" (library work) @I::"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\program_recovery_WA\program_recovery_WA.v" (library work) @I::"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo\Demo.v" (library work) Verilog syntax check successful! Options changed - recompiling Selecting top level module Demo @N:CG364 : smartfusion2.v(126) | Synthesizing module AND2 in library work. Running optimization stage 1 on AND2 ....... @N:CG364 : smartfusion2.v(286) | Synthesizing module BIBUF in library work. Running optimization stage 1 on BIBUF ....... @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC in library work. Running optimization stage 1 on VCC ....... @N:CG364 : smartfusion2.v(372) | Synthesizing module GND in library work. Running optimization stage 1 on GND ....... @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT in library work. Running optimization stage 1 on CLKINT ....... @N:CG364 : smartfusion2.v(729) | Synthesizing module CCC in library work. Running optimization stage 1 on CCC ....... @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF in library work. Running optimization stage 1 on INBUF ....... @N:CG364 : Demo_sb_CCC_0_FCCC.v(5) | Synthesizing module Demo_sb_CCC_0_FCCC in library work. Running optimization stage 1 on Demo_sb_CCC_0_FCCC ....... @N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP in library work. FAMILY=32'b00000000000000000000000000010011 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000001 VERSION_MAJOR=32'b00000000000000000000000000000111 VERSION_MINOR=32'b00000000000000000000000000000000 VERSION_MAJOR_VECTOR=16'b0000000000000111 VERSION_MINOR_VECTOR=16'b0000000000000000 S0=2'b00 S1=2'b01 S2=2'b10 Generated name = CoreConfigP_Z1 Running optimization stage 1 on CoreConfigP_Z1 ....... @W:CL207 : coreconfigp.v(461) | All reachable assignments to SDIF1_PENABLE assign 0, register removed by optimization. @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP in library work. FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000001 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z2 Running optimization stage 1 on CoreResetP_Z2 ....... @W:CL169 : coreresetp.v(1613) | Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1581) | Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1549) | Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1517) | Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1365) | Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1300) | Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1235) | Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1089) | Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers. @W:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : coreresetp.v(1089) | Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers. @N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF in library work. Running optimization stage 1 on TRIBUFF ....... @N:CG364 : Demo_sb_MSS_syn.v(5) | Synthesizing module MSS_075 in library work. Running optimization stage 1 on MSS_075 ....... @W:CL318 : Demo_sb_MSS_syn.v(1098) | *Output CAN_RXBUS_MGPIO3A_H2F_A has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1099) | *Output CAN_RXBUS_MGPIO3A_H2F_B has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1100) | *Output CAN_TX_EBL_MGPIO4A_H2F_A has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1101) | *Output CAN_TX_EBL_MGPIO4A_H2F_B has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1102) | *Output CAN_TXBUS_MGPIO2A_H2F_A has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1103) | *Output CAN_TXBUS_MGPIO2A_H2F_B has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1104) | *Output CLK_CONFIG_APB has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1105) | *Output COMMS_INT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1106) | *Output CONFIG_PRESET_N has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1107) | *Output EDAC_ERROR has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1108) | *Output F_FM0_RDATA has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1109) | *Output F_FM0_READYOUT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1110) | *Output F_FM0_RESP has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1111) | *Output F_HM0_ADDR has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1112) | *Output F_HM0_ENABLE has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1113) | *Output F_HM0_SEL has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1114) | *Output F_HM0_SIZE has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1115) | *Output F_HM0_TRANS1 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1116) | *Output F_HM0_WDATA has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1117) | *Output F_HM0_WRITE has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1118) | *Output FAB_CHRGVBUS has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1119) | *Output FAB_DISCHRGVBUS has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1120) | *Output FAB_DMPULLDOWN has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1121) | *Output FAB_DPPULLDOWN has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1122) | *Output FAB_DRVVBUS has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1123) | *Output FAB_IDPULLUP has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1124) | *Output FAB_OPMODE has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1125) | *Output FAB_SUSPENDM has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1126) | *Output FAB_TERMSEL has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1127) | *Output FAB_TXVALID has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1128) | *Output FAB_VCONTROL has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1129) | *Output FAB_VCONTROLLOADM has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1130) | *Output FAB_XCVRSEL has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1131) | *Output FAB_XDATAOUT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1132) | *Output FACC_GLMUX_SEL has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1133) | *Output FIC32_0_MASTER has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1134) | *Output FIC32_1_MASTER has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1135) | *Output FPGA_RESET_N has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1136) | *Output GTX_CLK has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1137) | *Output H2F_INTERRUPT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1138) | *Output H2F_NMI has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1139) | *Output H2FCALIB has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1140) | *Output I2C0_SCL_MGPIO31B_H2F_A has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1141) | *Output I2C0_SCL_MGPIO31B_H2F_B has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1142) | *Output I2C0_SDA_MGPIO30B_H2F_A has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1143) | *Output I2C0_SDA_MGPIO30B_H2F_B has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1144) | *Output I2C1_SCL_MGPIO1A_H2F_A has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1145) | *Output I2C1_SCL_MGPIO1A_H2F_B has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1146) | *Output I2C1_SDA_MGPIO0A_H2F_A has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1147) | *Output I2C1_SDA_MGPIO0A_H2F_B has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1148) | *Output MDCF has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1149) | *Output MDOENF has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1150) | *Output MDOF has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1151) | *Output MMUART0_CTS_MGPIO19B_H2F_A has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1152) | *Output MMUART0_CTS_MGPIO19B_H2F_B has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1153) | *Output MMUART0_DCD_MGPIO22B_H2F_A has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1154) | *Output MMUART0_DCD_MGPIO22B_H2F_B has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1155) | *Output MMUART0_DSR_MGPIO20B_H2F_A has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1156) | *Output MMUART0_DSR_MGPIO20B_H2F_B has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1157) | *Output MMUART0_DTR_MGPIO18B_H2F_A has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1158) | *Output MMUART0_DTR_MGPIO18B_H2F_B has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1159) | *Output MMUART0_RI_MGPIO21B_H2F_A has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1160) | *Output MMUART0_RI_MGPIO21B_H2F_B has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1161) | *Output MMUART0_RTS_MGPIO17B_H2F_A has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1162) | *Output MMUART0_RTS_MGPIO17B_H2F_B has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1163) | *Output MMUART0_RXD_MGPIO28B_H2F_A has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1164) | *Output MMUART0_RXD_MGPIO28B_H2F_B has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1165) | *Output MMUART0_SCK_MGPIO29B_H2F_A has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1166) | *Output MMUART0_SCK_MGPIO29B_H2F_B has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1167) | *Output MMUART0_TXD_MGPIO27B_H2F_A has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1168) | *Output MMUART0_TXD_MGPIO27B_H2F_B has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1169) | *Output MMUART1_DTR_MGPIO12B_H2F_A has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1170) | *Output MMUART1_RTS_MGPIO11B_H2F_A has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1171) | *Output MMUART1_RTS_MGPIO11B_H2F_B has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1172) | *Output MMUART1_RXD_MGPIO26B_H2F_A has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1173) | *Output MMUART1_RXD_MGPIO26B_H2F_B has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1174) | *Output MMUART1_SCK_MGPIO25B_H2F_A has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1175) | *Output MMUART1_SCK_MGPIO25B_H2F_B has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1176) | *Output MMUART1_TXD_MGPIO24B_H2F_A has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1177) | *Output MMUART1_TXD_MGPIO24B_H2F_B has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1178) | *Output MPLL_LOCK has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1179) | *Output PER2_FABRIC_PADDR has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1180) | *Output PER2_FABRIC_PENABLE has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1181) | *Output PER2_FABRIC_PSEL has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1182) | *Output PER2_FABRIC_PWDATA has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1183) | *Output PER2_FABRIC_PWRITE has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1184) | *Output RTC_MATCH has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1185) | *Output SLEEPDEEP has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1186) | *Output SLEEPHOLDACK has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1187) | *Output SLEEPING has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1188) | *Output SMBALERT_NO0 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1189) | *Output SMBALERT_NO1 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1190) | *Output SMBSUS_NO0 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1191) | *Output SMBSUS_NO1 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1192) | *Output SPI0_CLK_OUT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1193) | *Output SPI0_SDI_MGPIO5A_H2F_A has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1194) | *Output SPI0_SDI_MGPIO5A_H2F_B has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1195) | *Output SPI0_SDO_MGPIO6A_H2F_A has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1196) | *Output SPI0_SDO_MGPIO6A_H2F_B has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Demo_sb_MSS_syn.v(1197) | *Output SPI0_SS0_MGPIO7A_H2F_A has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. Only the first 100 messages of id 'CL318' are reported. To see all messages use 'report_messages -log E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\synthesis\synlog\Demo_compiler.srr -id CL318' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL318} -count unlimited' in the Tcl shell. @N:CG364 : Demo_sb_MSS.v(9) | Synthesizing module Demo_sb_MSS in library work. Running optimization stage 1 on Demo_sb_MSS ....... @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB in library work. Running optimization stage 1 on RCOSC_25_50MHZ_FAB ....... @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ in library work. Running optimization stage 1 on RCOSC_25_50MHZ ....... @N:CG364 : osc_comps.v(39) | Synthesizing module RCOSC_1MHZ_FAB in library work. Running optimization stage 1 on RCOSC_1MHZ_FAB ....... @N:CG364 : osc_comps.v(1) | Synthesizing module RCOSC_1MHZ in library work. Running optimization stage 1 on RCOSC_1MHZ ....... @N:CG364 : Demo_sb_FABOSC_0_OSC.v(5) | Synthesizing module Demo_sb_FABOSC_0_OSC in library work. Running optimization stage 1 on Demo_sb_FABOSC_0_OSC ....... @N:CG364 : smartfusion2.v(720) | Synthesizing module SYSRESET in library work. Running optimization stage 1 on SYSRESET ....... @N:CG364 : Demo_sb.v(9) | Synthesizing module Demo_sb in library work. Running optimization stage 1 on Demo_sb ....... @N:CG364 : Demo_FCCC_0_FCCC.v(5) | Synthesizing module Demo_FCCC_0_FCCC in library work. Running optimization stage 1 on Demo_FCCC_0_FCCC ....... @N:CG364 : Demo_FCCC_1_FCCC.v(5) | Synthesizing module Demo_FCCC_1_FCCC in library work. Running optimization stage 1 on Demo_FCCC_1_FCCC ....... @N:CG364 : Clock_check.v(19) | Synthesizing module Clock_check in library work. Running optimization stage 1 on Clock_check ....... @W:CL265 : Clock_check.v(25) | Removing unused bit 25 of count[25:0]. Either assign all bits or reduce the width of the signal. @A:CL291 : Clock_check.v(25) | Register pulse with asynchronous load is being synthesized in compatability mode. A synthesis/simulation mismatch is possible. @N:CG364 : tamper_comps.v(1) | Synthesizing module TAMPER in library work. Running optimization stage 1 on TAMPER ....... @N:CG364 : program_recovery_WA_TAMPER2_0_TAMPER2.v(5) | Synthesizing module program_recovery_WA_TAMPER2_0_TAMPER2 in library work. Running optimization stage 1 on program_recovery_WA_TAMPER2_0_TAMPER2 ....... @N:CG364 : program_recovery_WA.v(9) | Synthesizing module program_recovery_WA in library work. Running optimization stage 1 on program_recovery_WA ....... @N:CG364 : smartfusion2.v(320) | Synthesizing module INBUF_DIFF in library work. Running optimization stage 1 on INBUF_DIFF ....... @N:CG364 : Demo_SERDES_IF2_0_SERDES_IF2_syn.v(5) | Synthesizing module SERDESIF_075 in library work. Running optimization stage 1 on SERDESIF_075 ....... @N:CG364 : Demo_SERDES_IF2_0_SERDES_IF2.v(5) | Synthesizing module Demo_SERDES_IF2_0_SERDES_IF2 in library work. Running optimization stage 1 on Demo_SERDES_IF2_0_SERDES_IF2 ....... @N:CG364 : Demo.v(9) | Synthesizing module Demo in library work. Running optimization stage 1 on Demo ....... Running optimization stage 2 on Demo ....... Running optimization stage 2 on Demo_SERDES_IF2_0_SERDES_IF2 ....... Running optimization stage 2 on SERDESIF_075 ....... Running optimization stage 2 on INBUF_DIFF ....... Running optimization stage 2 on program_recovery_WA ....... Running optimization stage 2 on program_recovery_WA_TAMPER2_0_TAMPER2 ....... Running optimization stage 2 on TAMPER ....... Running optimization stage 2 on Clock_check ....... Running optimization stage 2 on Demo_FCCC_1_FCCC ....... Running optimization stage 2 on Demo_FCCC_0_FCCC ....... Running optimization stage 2 on Demo_sb ....... Running optimization stage 2 on SYSRESET ....... Running optimization stage 2 on Demo_sb_FABOSC_0_OSC ....... @N:CL159 : Demo_sb_FABOSC_0_OSC.v(14) | Input XTL is unused. Running optimization stage 2 on RCOSC_1MHZ ....... Running optimization stage 2 on RCOSC_1MHZ_FAB ....... Running optimization stage 2 on RCOSC_25_50MHZ ....... Running optimization stage 2 on RCOSC_25_50MHZ_FAB ....... Running optimization stage 2 on Demo_sb_MSS ....... Running optimization stage 2 on MSS_075 ....... Running optimization stage 2 on TRIBUFF ....... Running optimization stage 2 on CoreResetP_Z2 ....... @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state. Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state. Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state. Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state. Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state. Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @N:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused. @N:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused. @N:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused. @N:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused. @N:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused. @N:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused. @N:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused. @N:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused. @N:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused. @N:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused. @N:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused. @N:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused. @N:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused. @N:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused. Running optimization stage 2 on CoreConfigP_Z1 ....... @N:CL201 : coreconfigp.v(447) | Trying to extract state machine for register state. Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL159 : coreconfigp.v(71) | Input SDIF1_PREADY is unused. @N:CL159 : coreconfigp.v(72) | Input SDIF1_PSLVERR is unused. Running optimization stage 2 on Demo_sb_CCC_0_FCCC ....... Running optimization stage 2 on INBUF ....... Running optimization stage 2 on CCC ....... Running optimization stage 2 on CLKINT ....... Running optimization stage 2 on GND ....... Running optimization stage 2 on VCC ....... Running optimization stage 2 on BIBUF ....... Running optimization stage 2 on AND2 ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 86MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Jun 11 14:25:53 2019 ###########################################################] Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: N-2018.03M-SP1-1 Install: C:\Microsemi\Libero_SoC_12.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-X61679 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 223R, Built Oct 23 2018 09:18:38 @N: : | Running in 64-bit mode File D:\cap\sympify_bug_fix\synplify_L201609M-2_W\bin64\syn_nfilter.exe changed - recompiling File C:\Users\athuldeep.n\Desktop\IAP\m2s_dg0636_liberov11p8_sp1_df\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\synthesis\synwork\layer0.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Jun 11 14:25:53 2019 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Jun 11 14:25:53 2019 ###########################################################] Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: N-2018.03M-SP1-1 Install: C:\Microsemi\Libero_SoC_12.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-X61679 Database state : E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\synthesis\synwork\|synthesis Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 223R, Built Oct 23 2018 09:18:38 @N: : | Running in 64-bit mode File D:\cap\sympify_bug_fix\synplify_L201609M-2_W\bin64\syn_nfilter.exe changed - recompiling File C:\Users\athuldeep.n\Desktop\IAP\m2s_dg0636_liberov11p8_sp1_df\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\synthesis\synwork\Demo_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Jun 11 14:25:54 2019 ###########################################################] Premap Report # Tue Jun 11 14:25:55 2019 Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: N-2018.03M-SP1-1 Install: C:\Microsemi\Libero_SoC_12.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-X61679 Implementation : synthesis Synopsys Generic Technology Pre-mapping, Version mapact, Build 2461R, Built Nov 29 2018 09:35:20 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Reading constraint file: E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\designer\Demo\synthesis.fdc @N:MF284 : | Setting synthesis effort to medium for the design Linked File: Demo_scck.rpt @W:MF499 : | Found issues with constraints. Please check report file E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\synthesis\Demo_scck.rpt. @W:BN309 : | One or more non-fatal issues found in constraints; Please run Constraint Check for analysis @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 107MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 107MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 107MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 109MB) @N:MF284 : | Setting synthesis effort to medium for the design @W:BN132 : coreresetp.v(1089) | Removing sequential instance Demo_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance Demo_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MH105 : | UMR3 is only supported for HAPS-80. @N:MH105 : | UMR3 is only supported for HAPS-80. @N:MO111 : demo_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_sb_fabosc_0_osc.v(15) | Tristate driver RCOSC_25_50MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net RCOSC_25_50MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @W:MO129 : coreresetp.v(676) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance Demo_sb_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance Demo_sb_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance Demo_sb_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(1388) | Sequential instance Demo_sb_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation. @N:BN362 : coreconfigp.v(461) | Removing sequential instance MDDR_PENABLE (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF3_PENABLE (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. syn_allowed_resources : blockrams=109 set on top level netlist Demo Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 0 - Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB 25.0 MHz 40.000 declared default_clkgroup 111 0 - Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 20.000 declared default_clkgroup 56 0 - CLK0_PAD 50.0 MHz 20.000 declared default_clkgroup 0 1 . Demo_sb_0/CCC_0/GL0 100.0 MHz 10.000 generated (from CLK0_PAD) default_clkgroup 49 0 - SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] 125.0 MHz 8.000 declared default_clkgroup 0 1 . FCCC_0/GL0 62.5 MHz 16.000 generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup 1 1 . FCCC_0/GL1 62.5 MHz 16.000 generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup 1 0 - SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1] 125.0 MHz 8.000 declared default_clkgroup 0 1 . FCCC_1/GL0 125.0 MHz 8.000 generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]) default_clkgroup 1 0 - Demo_sb_0/FABOSC_0/I_RCOSC_1MHZ/CLKOUT 1.0 MHz 1000.000 declared default_clkgroup 0 0 - System 100.0 MHz 10.000 system system_clkgroup 0 0 - Demo_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 1 ============================================================================================================================================================================================= Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB 111 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST.CLK_CONFIG_APB(MSS_075) SERDES_IF2_0.SERDESIF_INST.APB_CLK - Demo_sb_0.CORECONFIGP_0.un1_FIC_2_APB_M_PCLK.I[0](inv) Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 56 Demo_sb_0.FABOSC_0.I_RCOSC_25_50MHZ.CLKOUT(RCOSC_25_50MHZ) program_recovery_WA_0.Clock_check_0.count[24:0].C - Demo_sb_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB.A(RCOSC_25_50MHZ_FAB) CLK0_PAD 0 CLK0_PAD(port) - - Demo_sb_0.CCC_0.CLK0_PAD_INST.I(IBUF) Demo_sb_0/CCC_0/GL0 49 Demo_sb_0.CCC_0.CCC_INST.GL0(CCC) Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST.CLK_BASE - Demo_sb_0.CCC_0.GL0_INST.I(BUFG) SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] 0 SERDES_IF2_0.SERDESIF_INST.EPCS_RXCLK[1](SERDESIF_075) - - - FCCC_0/GL0 1 FCCC_0.CCC_INST.GL0(CCC) Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST.RX_CLKPF - FCCC_0.GL0_INST.I(BUFG) FCCC_0/GL1 1 FCCC_0.CCC_INST.GL1(CCC) Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST.TX_CLKPF - FCCC_0.GL1_INST.I(BUFG) SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1] 0 SERDES_IF2_0.SERDESIF_INST.EPCS_TXCLK[1](SERDESIF_075) - - - FCCC_1/GL0 1 FCCC_1.CCC_INST.GL0(CCC) Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST.GTX_CLKPF - FCCC_1.GL0_INST.I(BUFG) Demo_sb_0/FABOSC_0/I_RCOSC_1MHZ/CLKOUT 0 Demo_sb_0.FABOSC_0.I_RCOSC_1MHZ.CLKOUT(RCOSC_1MHZ) - - program_recovery_WA_0.Clock_check_0.pulse10[0].I[0](inv) System 0 - - - - Demo_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock 1 SERDES_IF2_0.refclk1_inbuf_diff.Y(INBUF_DIFF) SERDES_IF2_0.SERDESIF_INST.REFCLK1 - - ============================================================================================================================================================================================================================================================================== @W:MT530 : demo_serdes_if2_0_serdes_if2.v(103) | Found inferred clock Demo_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock which controls 1 sequential elements including SERDES_IF2_0.SERDESIF_INST. This clock has no specified timing constraint which may adversely impact design performance. @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\synthesis\Demo.sap. Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) Encoding state machine state[2:0] (in view: work.CoreConfigP_Z1(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z2(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sdif0_state[3:0] (in view: work.CoreResetP_Z2(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : coreresetp.v(1170) | There are no possible illegal states for state machine sdif0_state[3:0] (in view: work.CoreResetP_Z2(verilog)); safe FSM implementation is not required. Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) @W:MF511 : | Found issues with constraints. Please check constraint checker report "E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\synthesis\Demo_cck.rpt" . Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 140MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Jun 11 14:25:56 2019 ###########################################################] Map & Optimize Report # Tue Jun 11 14:25:56 2019 Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: N-2018.03M-SP1-1 Install: C:\Microsemi\Libero_SoC_12.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-X61679 Implementation : synthesis Synopsys Generic Technology Mapper, Version mapact, Build 2461R, Built Nov 29 2018 09:35:20 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF284 : | Setting synthesis effort to medium for the design @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB) @W:BN309 : | One or more non-fatal issues found in constraints; Please run Constraint Check for analysis @N:MF284 : | Setting synthesis effort to medium for the design Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 138MB) @N:MO111 : demo_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_sb_fabosc_0_osc.v(15) | Tristate driver RCOSC_25_50MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net RCOSC_25_50MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @W:BN132 : coreresetp.v(963) | Removing sequential instance Demo_sb_0.CORERESETP_0.sdif3_spll_lock_q1 because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif0_spll_lock_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(884) | Removing sequential instance Demo_sb_0.CORERESETP_0.sdif1_areset_n_rcosc_q1 because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(912) | Removing sequential instance Demo_sb_0.CORERESETP_0.sdif3_areset_n_rcosc_q1 because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(898) | Removing sequential instance Demo_sb_0.CORERESETP_0.sdif2_areset_n_rcosc_q1 because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(755) | Removing sequential instance Demo_sb_0.CORERESETP_0.sm0_areset_n_q1 because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif0_areset_n_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(963) | Removing sequential instance Demo_sb_0.CORERESETP_0.sdif3_spll_lock_q2 because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif0_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(912) | Removing sequential instance Demo_sb_0.CORERESETP_0.sdif3_areset_n_rcosc because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif2_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(898) | Removing sequential instance Demo_sb_0.CORERESETP_0.sdif2_areset_n_rcosc because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif1_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(884) | Removing sequential instance Demo_sb_0.CORERESETP_0.sdif1_areset_n_rcosc because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif0_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(797) | Removing sequential instance Demo_sb_0.CORERESETP_0.sdif0_areset_n_clk_base because it is equivalent to instance Demo_sb_0.CORERESETP_0.sm0_areset_n_clk_base. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(1581) | Removing sequential instance Demo_sb_0.CORERESETP_0.release_sdif3_core because it is equivalent to instance Demo_sb_0.CORERESETP_0.release_sdif2_core. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(1549) | Removing sequential instance Demo_sb_0.CORERESETP_0.release_sdif2_core because it is equivalent to instance Demo_sb_0.CORERESETP_0.release_sdif1_core. To keep the instance, apply constraint syn_preserve=1 on the instance. Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 138MB) Encoding state machine CORECONFIGP_0.state[2:0] (in view: work.Demo_sb(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @W:MO160 : coreconfigp.v(255) | Register bit CORECONFIGP_0.paddr[16] (in view view:work.Demo_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z2(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sdif0_state[3:0] (in view: work.CoreResetP_Z2(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : coreresetp.v(1170) | There are no possible illegal states for state machine sdif0_state[3:0] (in view: work.CoreResetP_Z2(verilog)); safe FSM implementation is not required. @N:MO231 : coreresetp.v(1485) | Found counter in view:work.CoreResetP_Z2(verilog) instance count_sdif0[12:0] @W:BN132 : coreresetp.v(1089) | Removing instance Demo_sb_0.CORERESETP_0.SDIF_READY_int because it is equivalent to instance Demo_sb_0.CORERESETP_0.sm0_state[6]. To keep the instance, apply constraint syn_preserve=1 on the instance. Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 138MB) @N:BN362 : coreresetp.v(1170) | Removing sequential instance Demo_sb_0.CORERESETP_0.SDIF0_CORE_RESET_N_0 (in view: work.Demo(verilog)) because it does not drive other instances. Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 139MB) Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 139MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 139MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 139MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 139MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 139MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 139MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s 6.56ns 128 / 196 @N:FP130 : | Promoting Net Demo_sb_0_INIT_APB_S_PRESET_N on CLKINT I_64 @N:FP130 : | Promoting Net Demo_sb_0_INIT_APB_S_PCLK on CLKINT I_65 @N:FP130 : | Promoting Net Demo_sb_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT I_66 @N:FP130 : | Promoting Net Demo_sb_0.CORERESETP_0.sdif0_areset_n_rcosc on CLKINT I_67 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 139MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 139MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 3 non-gated/non-generated clock tree(s) driving 159 clock pin(s) of sequential element(s) 5 gated/generated clock tree(s) driving 45 clock pin(s) of sequential element(s) 0 instances converted, 45 sequential instances remain driven by gated/generated clocks =========================================================== Non-Gated/Non-Generated Clocks ============================================================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0005 SERDES_IF2_0.refclk1_inbuf_diff INBUF_DIFF 1 SERDES_IF2_0.SERDESIF_INST ClockId0007 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST clock definition on MSS_075 109 Demo_sb_0.CORECONFIGP_0.SDIF_RELEASED_q2 ClockId0008 Demo_sb_0.FABOSC_0.I_RCOSC_25_50MHZ clock definition on RCOSC_25_50MHZ 49 Demo_sb_0.CORERESETP_0.count_sdif0[12] ======================================================================================================================================================= ============================================================================================================================== Gated/Generated Clocks =============================================================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 Demo_sb_0.CCC_0.CCC_INST CCC 41 Demo_sb_0.CORERESETP_0.FIC_2_APB_M_PRESET_N_q1 Illegal instance on clock path. See the Gated Clocks description in the user guide for conversion requirements ClockId0002 FCCC_0.CCC_INST CCC 1 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_075 ClockId0003 FCCC_0.CCC_INST CCC 1 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_075 ClockId0004 FCCC_1.CCC_INST CCC 1 Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_075 ClockId0006 program_recovery_WA_0.Clock_check_0.un1_pulse10 clock definition on CFG4 1 program_recovery_WA_0.Clock_check_0.un1_pulse10_1_rs Clock conversion disabled ===================================================================================================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 139MB) Writing Analyst data base E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\synthesis\synwork\Demo_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 136MB peak: 139MB) Writing EDIF Netlist and constraint files @N:FX1056 : | Writing EDF file: E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\synthesis\Demo.edn @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Writing FDC file E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\synthesis\Demo_synplify.fdc N-2018.03M-SP1-1 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 138MB peak: 140MB) Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 138MB peak: 140MB) @W:MT246 : program_recovery_wa_tamper2_0_tamper2.v(31) | Blackbox TAMPER is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : demo_fccc_1_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N:MT615 : | Found clock CLK0_PAD with period 20.00ns @N:MT615 : | Found clock Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB with period 40.00ns @N:MT615 : | Found clock Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT with period 20.00ns @N:MT615 : | Found clock Demo_sb_0/FABOSC_0/I_RCOSC_1MHZ/CLKOUT with period 1000.00ns @N:MT615 : | Found clock SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] with period 8.00ns @N:MT615 : | Found clock SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1] with period 8.00ns @N:MT615 : | Found clock Demo_sb_0/CCC_0/GL0 with period 10.00ns @N:MT615 : | Found clock FCCC_0/GL0 with period 16.00ns @N:MT615 : | Found clock FCCC_0/GL1 with period 16.00ns @N:MT615 : | Found clock FCCC_1/GL0 with period 8.00ns @W:MT420 : | Found inferred clock Demo_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock with period 10.00ns. Please declare a user-defined clock on net SERDES_IF2_0.REFCLK1_OUT. ##### START OF TIMING REPORT #####[ # Timing Report written on Tue Jun 11 14:25:58 2019 # Top view: Demo Requested Frequency: 1.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\designer\Demo\synthesis.fdc @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: 7.503 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CLK0_PAD 50.0 MHz NA 20.000 NA NA declared default_clkgroup Demo_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_0 Demo_sb_0/CCC_0/GL0 100.0 MHz 400.4 MHz 10.000 2.498 7.503 generated (from CLK0_PAD) default_clkgroup Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB 25.0 MHz 106.7 MHz 40.000 9.375 15.313 declared default_clkgroup Demo_sb_0/FABOSC_0/I_RCOSC_1MHZ/CLKOUT 1.0 MHz 708.8 MHz 1000.000 1.411 998.589 declared default_clkgroup Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 502.7 MHz 20.000 1.989 18.011 declared default_clkgroup FCCC_0/GL0 62.5 MHz NA 16.000 NA NA generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup FCCC_0/GL1 62.5 MHz NA 16.000 NA NA generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup FCCC_1/GL0 125.0 MHz NA 8.000 NA NA generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]) default_clkgroup SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] 125.0 MHz NA 8.000 NA NA declared default_clkgroup SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1] 125.0 MHz NA 8.000 NA NA declared default_clkgroup System 100.0 MHz NA 10.000 NA NA system system_clkgroup ================================================================================================================================================================================================================= Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB | 40.000 33.819 | No paths - | 20.000 18.228 | 20.000 15.313 Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB Demo_sb_0/CCC_0/GL0 | 10.000 False | No paths - | No paths - | No paths - Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT System | 20.000 18.524 | No paths - | No paths - | No paths - Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 20.000 18.011 | No paths - | No paths - | No paths - Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Demo_sb_0/CCC_0/GL0 | 10.000 False | No paths - | No paths - | No paths - Demo_sb_0/FABOSC_0/I_RCOSC_1MHZ/CLKOUT System | No paths - | No paths - | No paths - | 1000.000 998.589 Demo_sb_0/CCC_0/GL0 Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB | 10.000 False | No paths - | No paths - | No paths - Demo_sb_0/CCC_0/GL0 Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 10.000 False | No paths - | No paths - | No paths - Demo_sb_0/CCC_0/GL0 Demo_sb_0/CCC_0/GL0 | 10.000 7.503 | No paths - | No paths - | No paths - ================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: Demo_sb_0/CCC_0/GL0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------- Demo_sb_0.CORERESETP_0.release_sdif0_core_clk_base Demo_sb_0/CCC_0/GL0 SLE Q release_sdif0_core_clk_base 0.094 7.503 Demo_sb_0.CORERESETP_0.ddr_settled_clk_base Demo_sb_0/CCC_0/GL0 SLE Q ddr_settled_clk_base 0.094 7.570 Demo_sb_0.CORERESETP_0.sdif0_spll_lock_q2 Demo_sb_0/CCC_0/GL0 SLE Q next_sm0_state18 0.094 7.682 Demo_sb_0.CORERESETP_0.CONFIG1_DONE_clk_base Demo_sb_0/CCC_0/GL0 SLE Q CONFIG1_DONE_clk_base 0.094 7.724 Demo_sb_0.CORERESETP_0.release_sdif1_core_clk_base Demo_sb_0/CCC_0/GL0 SLE Q release_sdif1_core_clk_base 0.094 8.145 Demo_sb_0.CORERESETP_0.release_sdif2_core_clk_base Demo_sb_0/CCC_0/GL0 SLE Q release_sdif2_core_clk_base 0.094 8.185 Demo_sb_0.CORERESETP_0.release_sdif3_core_clk_base Demo_sb_0/CCC_0/GL0 SLE Q release_sdif3_core_clk_base 0.094 8.252 Demo_sb_0.CORERESETP_0.sdif0_state[0] Demo_sb_0/CCC_0/GL0 SLE Q sdif0_state[0] 0.094 8.504 Demo_sb_0.CORERESETP_0.sm0_state[4] Demo_sb_0/CCC_0/GL0 SLE Q sm0_state[4] 0.094 8.600 Demo_sb_0.CORERESETP_0.sdif0_state[1] Demo_sb_0/CCC_0/GL0 SLE Q sdif0_state[1] 0.094 8.607 ================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------ Demo_sb_0.CORERESETP_0.sm0_state[4] Demo_sb_0/CCC_0/GL0 SLE D sm0_state_ns[4] 9.778 7.503 Demo_sb_0.CORERESETP_0.SDIF_RELEASED_int Demo_sb_0/CCC_0/GL0 SLE EN next_sdif_released_0_sqmuxa 9.707 7.626 Demo_sb_0.CORERESETP_0.sm0_state[5] Demo_sb_0/CCC_0/GL0 SLE D sm0_state_ns[5] 9.778 7.634 Demo_sb_0.CORERESETP_0.count_sdif0_enable Demo_sb_0/CCC_0/GL0 SLE EN N_226_i 9.707 7.682 Demo_sb_0.CORERESETP_0.SDIF0_PHY_RESET_N_int Demo_sb_0/CCC_0/GL0 SLE EN next_sdif0_phy_reset_n_0_sqmuxa 9.707 7.769 Demo_sb_0.CORERESETP_0.sdif0_state[0] Demo_sb_0/CCC_0/GL0 SLE D N_5_mux_i 9.778 7.871 Demo_sb_0.CORERESETP_0.sm0_state[3] Demo_sb_0/CCC_0/GL0 SLE D sm0_state_ns[3] 9.778 8.602 Demo_sb_0.CORERESETP_0.sdif0_state[1] Demo_sb_0/CCC_0/GL0 SLE D N_4_i 9.778 8.634 Demo_sb_0.CORERESETP_0.count_sdif0_enable Demo_sb_0/CCC_0/GL0 SLE D sdif0_state_i[0] 9.778 8.637 Demo_sb_0.CORERESETP_0.sm0_state[2] Demo_sb_0/CCC_0/GL0 SLE D sm0_state_ns[2] 9.778 8.691 ================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 2.276 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 7.503 Number of logic level(s): 3 Starting point: Demo_sb_0.CORERESETP_0.release_sdif0_core_clk_base / Q Ending point: Demo_sb_0.CORERESETP_0.sm0_state[4] / D The start point is clocked by Demo_sb_0/CCC_0/GL0 [rising] on pin CLK The end point is clocked by Demo_sb_0/CCC_0/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------- Demo_sb_0.CORERESETP_0.release_sdif0_core_clk_base SLE Q Out 0.094 0.094 - release_sdif0_core_clk_base Net - - 0.216 - 1 Demo_sb_0.CORERESETP_0.next_sdif0_state15 CFG2 B In - 0.310 - Demo_sb_0.CORERESETP_0.next_sdif0_state15 CFG2 Y Out 0.143 0.453 - next_sdif0_state15 Net - - 0.432 - 2 Demo_sb_0.CORERESETP_0.next_sm0_state25 CFG4 D In - 0.885 - Demo_sb_0.CORERESETP_0.next_sm0_state25 CFG4 Y Out 0.250 1.135 - next_sm0_state25 Net - - 0.648 - 3 Demo_sb_0.CORERESETP_0.sm0_state_ns[4] CFG4 D In - 1.784 - Demo_sb_0.CORERESETP_0.sm0_state_ns[4] CFG4 Y Out 0.276 2.059 - sm0_state_ns[4] Net - - 0.216 - 1 Demo_sb_0.CORERESETP_0.sm0_state[4] SLE D In - 2.276 - ================================================================================================================= Total path delay (propagation time + setup) of 2.497 is 0.985(39.4%) logic and 1.512(60.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Demo_sb_0.CORECONFIGP_0.psel Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE Q psel 0.094 15.313 Demo_sb_0.CORECONFIGP_0.SDIF0_PENABLE Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE Q Demo_sb_0_SDIF0_INIT_APB_PENABLE 0.094 18.200 Demo_sb_0.CORECONFIGP_0.state[1] Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE Q state[1] 0.076 18.228 Demo_sb_0.CORECONFIGP_0.paddr[15] Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE Q Demo_sb_0_SDIF0_INIT_APB_PADDR[15] 0.076 18.695 Demo_sb_0.CORECONFIGP_0.state[0] Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE Q state[0] 0.076 18.695 SERDES_IF2_0.SERDESIF_INST Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PREADY Demo_sb_0_SDIF0_INIT_APB_PREADY 4.732 33.819 SERDES_IF2_0.SERDESIF_INST Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PRDATA[25] Demo_sb_0_SDIF0_INIT_APB_PRDATA[25] 5.348 33.855 SERDES_IF2_0.SERDESIF_INST Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PRDATA[29] Demo_sb_0_SDIF0_INIT_APB_PRDATA[29] 5.235 33.968 SERDES_IF2_0.SERDESIF_INST Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PRDATA[24] Demo_sb_0_SDIF0_INIT_APB_PRDATA[24] 5.230 33.973 SERDES_IF2_0.SERDESIF_INST Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PRDATA[28] Demo_sb_0_SDIF0_INIT_APB_PRDATA[28] 5.217 33.986 =================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SERDES_IF2_0.SERDESIF_INST Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PSEL Demo_sb_0_SDIF0_INIT_APB_PSELx 17.269 15.313 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[0] Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[0] 19.778 16.700 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[1] Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[1] 19.778 16.700 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[2] Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[2] 19.778 16.700 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[3] Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[3] 19.778 16.700 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[4] Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[4] 19.778 16.700 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[5] Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[5] 19.778 16.700 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[6] Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[6] 19.778 16.700 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[7] Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[7] 19.778 16.700 Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[8] Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[8] 19.778 16.700 ================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 2.731 + Clock delay at ending point: 0.000 (ideal) = Required time: 17.269 - Propagation time: 1.956 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 15.313 Number of logic level(s): 1 Starting point: Demo_sb_0.CORECONFIGP_0.psel / Q Ending point: SERDES_IF2_0.SERDESIF_INST / APB_PSEL The start point is clocked by Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB [falling] on pin CLK The end point is clocked by Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB [rising] on pin APB_CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------- Demo_sb_0.CORECONFIGP_0.psel SLE Q Out 0.094 0.094 - psel Net - - 0.648 - 3 Demo_sb_0.CORECONFIGP_0.int_sel_1_sqmuxa CFG2 A In - 0.742 - Demo_sb_0.CORECONFIGP_0.int_sel_1_sqmuxa CFG2 Y Out 0.076 0.818 - Demo_sb_0_SDIF0_INIT_APB_PSELx Net - - 1.138 - 35 SERDES_IF2_0.SERDESIF_INST SERDESIF_075 APB_PSEL In - 1.956 - =================================================================================================================== Total path delay (propagation time + setup) of 4.687 is 2.901(61.9%) logic and 1.787(38.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: Demo_sb_0/FABOSC_0/I_RCOSC_1MHZ/CLKOUT ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------- program_recovery_WA_0.Clock_check_0.un1_pulse10_1_rs Demo_sb_0/FABOSC_0/I_RCOSC_1MHZ/CLKOUT SLE Q un1_pulse10_1_rs 0.094 998.589 ============================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------- program_recovery_WA_0.TAMPER2_0.TAMPER_INST Demo_sb_0/FABOSC_0/I_RCOSC_1MHZ/CLKOUT TAMPER RESET_N pulse_1_i 1000.000 998.589 ==================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 1000.000 - Propagation time: 1.411 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 998.589 Number of logic level(s): 1 Starting point: program_recovery_WA_0.Clock_check_0.un1_pulse10_1_rs / Q Ending point: program_recovery_WA_0.TAMPER2_0.TAMPER_INST / RESET_N The start point is clocked by Demo_sb_0/FABOSC_0/I_RCOSC_1MHZ/CLKOUT [falling] on pin CLK The end point is clocked by System [falling] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------ program_recovery_WA_0.Clock_check_0.un1_pulse10_1_rs SLE Q Out 0.094 0.094 - un1_pulse10_1_rs Net - - 0.216 - 1 program_recovery_WA_0.Clock_check_0.pulse_1_RNIIP8N CFG3 B In - 0.310 - program_recovery_WA_0.Clock_check_0.pulse_1_RNIIP8N CFG3 Y Out 0.129 0.439 - pulse_1_i Net - - 0.971 - 1 program_recovery_WA_0.TAMPER2_0.TAMPER_INST TAMPER RESET_N In - 1.411 - ======================================================================================================================== Total path delay (propagation time + setup) of 1.411 is 0.223(15.8%) logic and 1.188(84.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------- Demo_sb_0.CORERESETP_0.count_sdif0[0] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[0] 0.076 18.011 Demo_sb_0.CORERESETP_0.count_sdif0[1] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[1] 0.076 18.295 Demo_sb_0.CORERESETP_0.count_sdif0[3] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[3] 0.076 18.314 Demo_sb_0.CORERESETP_0.count_sdif0[6] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[6] 0.094 18.350 Demo_sb_0.CORERESETP_0.count_sdif0[2] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[2] 0.094 18.378 Demo_sb_0.CORERESETP_0.count_sdif0[4] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[4] 0.076 18.386 Demo_sb_0.CORERESETP_0.count_sdif0[5] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[5] 0.094 18.418 Demo_sb_0.CORERESETP_0.count_sdif0[8] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[8] 0.094 18.418 Demo_sb_0.CORERESETP_0.count_sdif0[10] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[10] 0.076 18.423 Demo_sb_0.CORERESETP_0.count_sdif0[11] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[11] 0.094 18.457 ================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------- Demo_sb_0.CORERESETP_0.release_sdif0_core Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE EN release_sdif0_core4 19.706 18.011 Demo_sb_0.CORERESETP_0.count_sdif0[12] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[12] 19.778 18.425 Demo_sb_0.CORERESETP_0.count_sdif0[11] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[11] 19.778 18.440 Demo_sb_0.CORERESETP_0.count_sdif0[10] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[10] 19.778 18.454 Demo_sb_0.CORERESETP_0.count_sdif0[9] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[9] 19.778 18.468 Demo_sb_0.CORERESETP_0.count_sdif0[8] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[8] 19.778 18.482 Demo_sb_0.CORERESETP_0.count_sdif0[7] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[7] 19.778 18.497 Demo_sb_0.CORERESETP_0.count_sdif0[6] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[6] 19.778 18.511 program_recovery_WA_0.TAMPER2_0.TAMPER_INST Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT TAMPER RESET_N pulse_1_i 20.000 18.524 Demo_sb_0.CORERESETP_0.count_sdif0[5] Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[5] 19.778 18.525 ================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 0.294 + Clock delay at ending point: 0.000 (ideal) = Required time: 19.706 - Propagation time: 1.696 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 18.011 Number of logic level(s): 2 Starting point: Demo_sb_0.CORERESETP_0.count_sdif0[0] / Q Ending point: Demo_sb_0.CORERESETP_0.release_sdif0_core / EN The start point is clocked by Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] on pin CLK The end point is clocked by Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------- Demo_sb_0.CORERESETP_0.count_sdif0[0] SLE Q Out 0.076 0.076 - count_sdif0[0] Net - - 0.648 - 3 Demo_sb_0.CORERESETP_0.release_sdif0_core4_8 CFG4 D In - 0.724 - Demo_sb_0.CORERESETP_0.release_sdif0_core4_8 CFG4 Y Out 0.284 1.008 - release_sdif0_core4_8 Net - - 0.216 - 1 Demo_sb_0.CORERESETP_0.release_sdif0_core4 CFG4 D In - 1.224 - Demo_sb_0.CORERESETP_0.release_sdif0_core4 CFG4 Y Out 0.250 1.474 - release_sdif0_core4 Net - - 0.221 - 1 Demo_sb_0.CORERESETP_0.release_sdif0_core SLE EN In - 1.696 - =========================================================================================================== Total path delay (propagation time + setup) of 1.989 is 0.904(45.4%) logic and 1.085(54.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied @W:MT447 : synthesis.fdc(21) | Timing constraint (from [get_cells { Demo_sb_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { Demo_sb_0.CORERESETP_0.sm0_areset_n_rcosc Demo_sb_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(22) | Timing constraint (from [get_cells { Demo_sb_0.CORERESETP_0.MSS_HPMS_READY_int Demo_sb_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { Demo_sb_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(24) | Timing constraint (through [get_pins { Demo_sb_0.SYSRESET_POR.POWER_ON_RESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT443 : synthesis.fdc(25) | Timing constraint (through [get_nets { Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PSEL Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PENABLE }] to [get_cells { Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PREADY* Demo_sb_0.CORECONFIGP_0.state[0] }]) (max delay 0.000000) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT446 : synthesis.fdc(27) | Timing constraint (from [get_pins { Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST.GTX_CLKPF }] to [get_pins { SERDES_IF2_0.SERDESIF_INST.EPCS_TXDATA[*] }]) (multi path 3) was not applied to the design because none of the paths specified by the constraint exist in the design Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 138MB peak: 140MB) Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 138MB peak: 140MB) --------------------------------------- Resource Usage Report for Demo Mapping to part: m2s090tsfbga484-1 Cell usage: AND2 1 use CCC 3 uses CLKINT 10 uses MSS_075 1 use RCOSC_1MHZ 1 use RCOSC_1MHZ_FAB 1 use RCOSC_25_50MHZ 1 use RCOSC_25_50MHZ_FAB 1 use SERDESIF_075 1 use SYSRESET 1 use TAMPER 1 use CFG1 8 uses CFG2 30 uses CFG3 12 uses CFG4 52 uses Carry cells: ARI1 13 uses - used for arithmetic functions Sequential Cells: SLE 198 uses DSP Blocks: 0 of 84 (0%) I/O ports: 37 I/O primitives: 19 BIBUF 3 uses INBUF 3 uses INBUF_DIFF 1 use OUTBUF 10 uses TRIBUFF 2 uses Global Clock Buffers: 10 Total LUTs: 115 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 0; LUTs = 0; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 198 + 0 + 0 + 0 = 198; Total number of LUTs after P&R: 115 + 0 + 0 + 0 = 115; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 30MB peak: 140MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Jun 11 14:25:58 2019 ###########################################################]