@W: BN132 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance Demo_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance Demo_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":676:4:676:9|Sequential instance Demo_sb_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance Demo_sb_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance Demo_sb_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance Demo_sb_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance Demo_sb_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":676:4:676:9|Sequential instance Demo_sb_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance Demo_sb_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance Demo_sb_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance Demo_sb_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance Demo_sb_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":676:4:676:9|Sequential instance Demo_sb_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance Demo_sb_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance Demo_sb_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance Demo_sb_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sequential instance Demo_sb_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation.
@W: MT530 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Found inferred clock Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock which controls 111 sequential elements including Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[31:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1485:4:1485:9|Found inferred clock Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock which controls 56 sequential elements including Demo_sb_0.CORERESETP_0.count_sdif0[12:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Found inferred clock Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock which controls 49 sequential elements including Demo_sb_0.CORERESETP_0.count_sdif0_enable. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\work\demo_sb_mss\demo_sb_mss.v":324:0:324:13|Found inferred clock top_FCCC_0_FCCC|GL1_net_inferred_clock which controls 1 sequential elements including Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\work\demo_sb_mss\demo_sb_mss.v":324:0:324:13|Found inferred clock top_FCCC_0_FCCC|GL0_net_inferred_clock which controls 1 sequential elements including Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\work\demo_sb_mss\demo_sb_mss.v":324:0:324:13|Found inferred clock top_FCCC_1_FCCC|GL0_net_inferred_clock which controls 1 sequential elements including Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\work\top\serdes_if2_0\top_serdes_if2_0_serdes_if2.v":103:52:103:64|Found inferred clock top_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock which controls 1 sequential elements including SERDES_IF2_0.SERDESIF_INST. This clock has no specified timing constraint which may adversely impact design performance. 
