@W: BN132 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Removing sequential instance Demo_sb_0.CORERESETP_0.sdif3_spll_lock_q1 because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif0_spll_lock_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Removing sequential instance Demo_sb_0.CORERESETP_0.sdif3_spll_lock_q2 because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif0_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MO160 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":255:4:255:9|Register bit CORECONFIGP_0.paddr[16] (in view view:work.Demo_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: BN132 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing instance Demo_sb_0.CORERESETP_0.SDIF_READY_int because it is equivalent to instance Demo_sb_0.CORERESETP_0.sm0_state[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MT246 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\work\program_recovery_wa\tamper2_0\program_recovery_wa_tamper2_0_tamper2.v":31:11:31:21|Blackbox TAMPER is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\work\top\fccc_1\top_fccc_1_fccc.v":20:36:20:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock Demo_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on net Demo_sb_0.Demo_sb_MSS_0.FIC_2_APB_M_PCLK.
@W: MT420 |Found inferred clock Demo_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock with period 10.00ns. Please declare a user-defined clock on net Demo_sb_0.FABOSC_0.N_RCOSC_25_50MHZ_CLKOUT.
@W: MT420 |Found inferred clock Demo_sb_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on net Demo_sb_0.CCC_0.GL0_net.
@W: MT420 |Found inferred clock top_FCCC_0_FCCC|GL1_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on net FCCC_0.GL1_net.
@W: MT420 |Found inferred clock top_FCCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on net FCCC_0.GL0_net.
@W: MT420 |Found inferred clock top_FCCC_1_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on net FCCC_1.GL0_net.
@W: MT420 |Found inferred clock top_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock with period 10.00ns. Please declare a user-defined clock on net SERDES_IF2_0.REFCLK1_OUT.
