@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: MO111 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\work\demo_sb\fabosc_0\demo_sb_fabosc_0_osc.v":20:7:20:16|Tristate driver XTLOSC_O2F (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N: MO111 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\work\demo_sb\fabosc_0\demo_sb_fabosc_0_osc.v":19:7:19:16|Tristate driver XTLOSC_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N: MO111 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\work\demo_sb\fabosc_0\demo_sb_fabosc_0_osc.v":17:7:17:20|Tristate driver RCOSC_1MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N: MO111 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\work\demo_sb\fabosc_0\demo_sb_fabosc_0_osc.v":15:7:15:24|Tristate driver RCOSC_25_50MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) on net RCOSC_25_50MHZ_CCC (in view: work.Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N: MO225 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1170:4:1170:9|There are no possible illegal states for state machine sdif0_state[3:0] (in view: work.CoreResetP_Z2(verilog)); safe FSM implementation is not required.
@N: MO231 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1485:4:1485:9|Found counter in view:work.CoreResetP_Z2(verilog) instance count_sdif0[12:0] 
@N: BN362 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Removing sequential instance Demo_sb_0.CORERESETP_0.SDIF0_CORE_RESET_N_0 (in view: work.top(verilog)) because it does not drive other instances.
@N: FX271 :"c:\igloo2_task_feb_2021\sf2\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":461:4:461:9|Replicating instance Demo_sb_0.CORECONFIGP_0.psel (in view: work.top(verilog)) with 4 loads 1 time to improve timing.
@N: FP130 |Promoting Net Demo_sb_0.FIC_2_APB_M_PRESET_N_arst on CLKINT  I_95 
@N: FP130 |Promoting Net Demo_sb_0_INIT_APB_S_PCLK on CLKINT  I_96 
@N: FP130 |Promoting Net Demo_sb_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT  I_97 
@N: FP130 |Promoting Net Demo_sb_0.CORERESETP_0.sdif0_areset_n_rcosc on CLKINT  I_98 
@N: FP130 |Promoting Net Demo_sb_0.CORERESETP_0.sm0_areset_n_arst on CLKINT  I_99 
@N: FX1056 |Writing EDF file: C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\synthesis\top.edn
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
