@W: CL207 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v":461:4:461:9|All reachable assignments to SDIF1_PENABLE assign 0, register removed by optimization.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1517:4:1517:9|Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers.
@W: CL177 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL190 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers.
@W: CL318 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb\FABOSC_0\Demo_sb_FABOSC_0_OSC.v":15:7:15:24|*Output RCOSC_25_50MHZ_CCC has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb\FABOSC_0\Demo_sb_FABOSC_0_OSC.v":17:7:17:20|*Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb\FABOSC_0\Demo_sb_FABOSC_0_OSC.v":19:7:19:16|*Output XTLOSC_CCC has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb\FABOSC_0\Demo_sb_FABOSC_0_OSC.v":20:7:20:16|*Output XTLOSC_O2F has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL265 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\hdl\Clock_check.v":25:0:25:5|Removing unused bit 25 of count[25:0]. Either assign all bits or reduce the width of the signal.
@W: CL177 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\igloo2_task_feb_2021\SF2\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.

