@W: BN309 |One or more non-fatal issues found in constraints; Please run Constraint Check for analysis
@W: BN132 :"e:\12.1_designs\dg0636\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Removing sequential instance Demo_sb_0.CORERESETP_0.sdif3_spll_lock_q1 because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif0_spll_lock_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\12.1_designs\dg0636\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":884:4:884:9|Removing sequential instance Demo_sb_0.CORERESETP_0.sdif1_areset_n_rcosc_q1 because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\12.1_designs\dg0636\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":912:4:912:9|Removing sequential instance Demo_sb_0.CORERESETP_0.sdif3_areset_n_rcosc_q1 because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\12.1_designs\dg0636\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":898:4:898:9|Removing sequential instance Demo_sb_0.CORERESETP_0.sdif2_areset_n_rcosc_q1 because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\12.1_designs\dg0636\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":755:4:755:9|Removing sequential instance Demo_sb_0.CORERESETP_0.sm0_areset_n_q1 because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif0_areset_n_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\12.1_designs\dg0636\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Removing sequential instance Demo_sb_0.CORERESETP_0.sdif3_spll_lock_q2 because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif0_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\12.1_designs\dg0636\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":912:4:912:9|Removing sequential instance Demo_sb_0.CORERESETP_0.sdif3_areset_n_rcosc because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif2_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\12.1_designs\dg0636\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":898:4:898:9|Removing sequential instance Demo_sb_0.CORERESETP_0.sdif2_areset_n_rcosc because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif1_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\12.1_designs\dg0636\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":884:4:884:9|Removing sequential instance Demo_sb_0.CORERESETP_0.sdif1_areset_n_rcosc because it is equivalent to instance Demo_sb_0.CORERESETP_0.sdif0_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\12.1_designs\dg0636\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":797:4:797:9|Removing sequential instance Demo_sb_0.CORERESETP_0.sdif0_areset_n_clk_base because it is equivalent to instance Demo_sb_0.CORERESETP_0.sm0_areset_n_clk_base. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\12.1_designs\dg0636\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Removing sequential instance Demo_sb_0.CORERESETP_0.release_sdif3_core because it is equivalent to instance Demo_sb_0.CORERESETP_0.release_sdif2_core. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\12.1_designs\dg0636\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Removing sequential instance Demo_sb_0.CORERESETP_0.release_sdif2_core because it is equivalent to instance Demo_sb_0.CORERESETP_0.release_sdif1_core. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MO160 :"e:\12.1_designs\dg0636\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":255:4:255:9|Register bit CORECONFIGP_0.paddr[16] (in view view:work.Demo_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: BN132 :"e:\12.1_designs\dg0636\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing instance Demo_sb_0.CORERESETP_0.SDIF_READY_int because it is equivalent to instance Demo_sb_0.CORERESETP_0.sm0_state[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MT246 :"e:\12.1_designs\dg0636\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\work\program_recovery_wa\tamper2_0\program_recovery_wa_tamper2_0_tamper2.v":31:11:31:21|Blackbox TAMPER is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"e:\12.1_designs\dg0636\sf2_tftp_update_recovery_demo_df\sample_files\recovery_wa\demo\component\work\demo\fccc_1\demo_fccc_1_fccc.v":20:36:20:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock Demo_SERDES_IF2_0_SERDES_IF2|REFCLK1_OUT_inferred_clock with period 10.00ns. Please declare a user-defined clock on net SERDES_IF2_0.REFCLK1_OUT.
@W: MT447 :"e:/12.1_designs/dg0636/sf2_tftp_update_recovery_demo_df/sample_files/recovery_wa/demo/designer/demo/synthesis.fdc":21:0:21:0|Timing constraint (from [get_cells { Demo_sb_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { Demo_sb_0.CORERESETP_0.sm0_areset_n_rcosc Demo_sb_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"e:/12.1_designs/dg0636/sf2_tftp_update_recovery_demo_df/sample_files/recovery_wa/demo/designer/demo/synthesis.fdc":22:0:22:0|Timing constraint (from [get_cells { Demo_sb_0.CORERESETP_0.MSS_HPMS_READY_int Demo_sb_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { Demo_sb_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"e:/12.1_designs/dg0636/sf2_tftp_update_recovery_demo_df/sample_files/recovery_wa/demo/designer/demo/synthesis.fdc":24:0:24:0|Timing constraint (through [get_pins { Demo_sb_0.SYSRESET_POR.POWER_ON_RESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT443 :"e:/12.1_designs/dg0636/sf2_tftp_update_recovery_demo_df/sample_files/recovery_wa/demo/designer/demo/synthesis.fdc":25:0:25:0|Timing constraint (through [get_nets { Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PSEL Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PENABLE }] to [get_cells { Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PREADY* Demo_sb_0.CORECONFIGP_0.state[0] }]) (max delay 0.000000) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT446 :"e:/12.1_designs/dg0636/sf2_tftp_update_recovery_demo_df/sample_files/recovery_wa/demo/designer/demo/synthesis.fdc":27:0:27:0|Timing constraint (from [get_pins { Demo_sb_0.Demo_sb_MSS_0.MSS_ADLIB_INST.GTX_CLKPF }] to [get_pins { SERDES_IF2_0.SERDESIF_INST.EPCS_TXDATA[*] }]) (multi path 3) was not applied to the design because none of the paths specified by the constraint exist in the design 
