@W: CL207 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v":461:4:461:9|All reachable assignments to SDIF1_PENABLE assign 0, register removed by optimization.
@W: CL169 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1517:4:1517:9|Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers.
@W: CL177 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL190 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1098:7:1098:29|*Output CAN_RXBUS_MGPIO3A_H2F_A has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1099:7:1099:29|*Output CAN_RXBUS_MGPIO3A_H2F_B has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1100:7:1100:30|*Output CAN_TX_EBL_MGPIO4A_H2F_A has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1101:7:1101:30|*Output CAN_TX_EBL_MGPIO4A_H2F_B has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1102:7:1102:29|*Output CAN_TXBUS_MGPIO2A_H2F_A has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1103:7:1103:29|*Output CAN_TXBUS_MGPIO2A_H2F_B has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1104:7:1104:20|*Output CLK_CONFIG_APB has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1105:7:1105:15|*Output COMMS_INT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1106:7:1106:21|*Output CONFIG_PRESET_N has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1107:13:1107:22|*Output EDAC_ERROR has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1108:14:1108:24|*Output F_FM0_RDATA has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1109:7:1109:20|*Output F_FM0_READYOUT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1110:7:1110:16|*Output F_FM0_RESP has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1111:14:1111:23|*Output F_HM0_ADDR has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1112:7:1112:18|*Output F_HM0_ENABLE has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1113:7:1113:15|*Output F_HM0_SEL has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1114:13:1114:22|*Output F_HM0_SIZE has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1115:7:1115:18|*Output F_HM0_TRANS1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1116:14:1116:24|*Output F_HM0_WDATA has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1117:7:1117:17|*Output F_HM0_WRITE has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1118:7:1118:18|*Output FAB_CHRGVBUS has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1119:7:1119:21|*Output FAB_DISCHRGVBUS has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1120:7:1120:20|*Output FAB_DMPULLDOWN has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1121:7:1121:20|*Output FAB_DPPULLDOWN has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1122:7:1122:17|*Output FAB_DRVVBUS has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1123:7:1123:18|*Output FAB_IDPULLUP has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1124:13:1124:22|*Output FAB_OPMODE has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1125:7:1125:18|*Output FAB_SUSPENDM has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1126:7:1126:17|*Output FAB_TERMSEL has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1127:7:1127:17|*Output FAB_TXVALID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1128:13:1128:24|*Output FAB_VCONTROL has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1129:7:1129:23|*Output FAB_VCONTROLLOADM has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1130:13:1130:23|*Output FAB_XCVRSEL has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1131:13:1131:24|*Output FAB_XDATAOUT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1132:7:1132:20|*Output FACC_GLMUX_SEL has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1133:13:1133:26|*Output FIC32_0_MASTER has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1134:13:1134:26|*Output FIC32_1_MASTER has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1135:7:1135:18|*Output FPGA_RESET_N has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1136:7:1136:13|*Output GTX_CLK has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1137:14:1137:26|*Output H2F_INTERRUPT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1138:7:1138:13|*Output H2F_NMI has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1139:7:1139:14|*Output H2FCALIB has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1140:7:1140:29|*Output I2C0_SCL_MGPIO31B_H2F_A has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1141:7:1141:29|*Output I2C0_SCL_MGPIO31B_H2F_B has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1142:7:1142:29|*Output I2C0_SDA_MGPIO30B_H2F_A has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1143:7:1143:29|*Output I2C0_SDA_MGPIO30B_H2F_B has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1144:7:1144:28|*Output I2C1_SCL_MGPIO1A_H2F_A has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1145:7:1145:28|*Output I2C1_SCL_MGPIO1A_H2F_B has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1146:7:1146:28|*Output I2C1_SDA_MGPIO0A_H2F_A has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1147:7:1147:28|*Output I2C1_SDA_MGPIO0A_H2F_B has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1148:7:1148:10|*Output MDCF has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1149:7:1149:12|*Output MDOENF has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1150:7:1150:10|*Output MDOF has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1151:7:1151:32|*Output MMUART0_CTS_MGPIO19B_H2F_A has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1152:7:1152:32|*Output MMUART0_CTS_MGPIO19B_H2F_B has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1153:7:1153:32|*Output MMUART0_DCD_MGPIO22B_H2F_A has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1154:7:1154:32|*Output MMUART0_DCD_MGPIO22B_H2F_B has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1155:7:1155:32|*Output MMUART0_DSR_MGPIO20B_H2F_A has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1156:7:1156:32|*Output MMUART0_DSR_MGPIO20B_H2F_B has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1157:7:1157:32|*Output MMUART0_DTR_MGPIO18B_H2F_A has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1158:7:1158:32|*Output MMUART0_DTR_MGPIO18B_H2F_B has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1159:7:1159:31|*Output MMUART0_RI_MGPIO21B_H2F_A has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1160:7:1160:31|*Output MMUART0_RI_MGPIO21B_H2F_B has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1161:7:1161:32|*Output MMUART0_RTS_MGPIO17B_H2F_A has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1162:7:1162:32|*Output MMUART0_RTS_MGPIO17B_H2F_B has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1163:7:1163:32|*Output MMUART0_RXD_MGPIO28B_H2F_A has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1164:7:1164:32|*Output MMUART0_RXD_MGPIO28B_H2F_B has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1165:7:1165:32|*Output MMUART0_SCK_MGPIO29B_H2F_A has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1166:7:1166:32|*Output MMUART0_SCK_MGPIO29B_H2F_B has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1167:7:1167:32|*Output MMUART0_TXD_MGPIO27B_H2F_A has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1168:7:1168:32|*Output MMUART0_TXD_MGPIO27B_H2F_B has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1169:7:1169:32|*Output MMUART1_DTR_MGPIO12B_H2F_A has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1170:7:1170:32|*Output MMUART1_RTS_MGPIO11B_H2F_A has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1171:7:1171:32|*Output MMUART1_RTS_MGPIO11B_H2F_B has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1172:7:1172:32|*Output MMUART1_RXD_MGPIO26B_H2F_A has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1173:7:1173:32|*Output MMUART1_RXD_MGPIO26B_H2F_B has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1174:7:1174:32|*Output MMUART1_SCK_MGPIO25B_H2F_A has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1175:7:1175:32|*Output MMUART1_SCK_MGPIO25B_H2F_B has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1176:7:1176:32|*Output MMUART1_TXD_MGPIO24B_H2F_A has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1177:7:1177:32|*Output MMUART1_TXD_MGPIO24B_H2F_B has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1178:7:1178:15|*Output MPLL_LOCK has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1179:14:1179:30|*Output PER2_FABRIC_PADDR has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1180:7:1180:25|*Output PER2_FABRIC_PENABLE has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1181:7:1181:22|*Output PER2_FABRIC_PSEL has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1182:14:1182:31|*Output PER2_FABRIC_PWDATA has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1183:7:1183:24|*Output PER2_FABRIC_PWRITE has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1184:7:1184:15|*Output RTC_MATCH has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1185:7:1185:15|*Output SLEEPDEEP has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1186:7:1186:18|*Output SLEEPHOLDACK has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1187:7:1187:14|*Output SLEEPING has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1188:7:1188:18|*Output SMBALERT_NO0 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1189:7:1189:18|*Output SMBALERT_NO1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1190:7:1190:16|*Output SMBSUS_NO0 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1191:7:1191:16|*Output SMBSUS_NO1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1192:7:1192:18|*Output SPI0_CLK_OUT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1193:7:1193:28|*Output SPI0_SDI_MGPIO5A_H2F_A has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1194:7:1194:28|*Output SPI0_SDI_MGPIO5A_H2F_B has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1195:7:1195:28|*Output SPI0_SDO_MGPIO6A_H2F_A has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1196:7:1196:28|*Output SPI0_SDO_MGPIO6A_H2F_B has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\work\Demo_sb_MSS\Demo_sb_MSS_syn.v":1197:7:1197:28|*Output SPI0_SS0_MGPIO7A_H2F_A has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL265 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\hdl\Clock_check.v":25:0:25:5|Removing unused bit 25 of count[25:0]. Either assign all bits or reduce the width of the signal.
@W: CL177 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"E:\12.1_Designs\DG0636\SF2_TFTP_Update_Recovery_Demo_DF\Sample_files\Recovery_WA\Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.

