Timing Multi Corner Report Max Delay Analysis

SmartTime Version 2021.1.0.17

Microsemi Corporation - Microsemi Libero Software Release v2021.1 (Version 2021.1.0.17)

Date: Tue Jun 15 15:19:15 2021

Design top
Family SmartFusion2
Die M2S090TS
Package 484 FBGA
Temperature Range 0 - 85 C
Voltage Range 1.14 - 1.26 V
Speed Grade -1
Design State Post-Layout
Data source Production
Multi Corner Report Operating Conditions BEST, TYPICAL, WORST
Scenario for Timing Analysis timing_analysis

Summary

Clock Domain Required Period (ns) Required Frequency (MHz) Worst Slack (ns) Operating Conditions
CLK0_PAD N/A N/A
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 N/A N/A
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB N/A N/A
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDCF N/A N/A
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT N/A N/A
FCCC_0/CCC_INST/INST_CCC_IP:GL0 N/A N/A
FCCC_0/CCC_INST/INST_CCC_IP:GL1 N/A N/A
FCCC_1/CCC_INST/INST_CCC_IP:GL0 N/A N/A
SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] N/A N/A
SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1] N/A N/A

Worst Slack (ns) Operating Conditions
Input to Output

Clock Domain CLK0_PAD

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 Demo_sb_0/CORERESETP_0/CONFIG1_DONE_clk_base:CLK Demo_sb_0/CORERESETP_0/count_sdif0_enable:EN 2.794 4.859 0.308 3.146 WORST
Path 2 Demo_sb_0/CORERESETP_0/sdif0_spll_lock_q2:CLK Demo_sb_0/CORERESETP_0/count_sdif0_enable:EN 2.754 4.820 0.308 3.107 WORST
Path 3 Demo_sb_0/CORERESETP_0/CONFIG1_DONE_clk_base:CLK Demo_sb_0/CORERESETP_0/SDIF0_PHY_RESET_N_int:EN 2.502 4.567 0.308 2.863 WORST
Path 4 Demo_sb_0/CORERESETP_0/sdif0_spll_lock_q2:CLK Demo_sb_0/CORERESETP_0/SDIF0_PHY_RESET_N_int:EN 2.462 4.528 0.308 2.824 WORST
Path 5 Demo_sb_0/CORERESETP_0/ddr_settled_clk_base:CLK Demo_sb_0/CORERESETP_0/count_sdif0_enable:EN 2.298 4.334 0.308 2.621 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Demo_sb_0/CORERESETP_0/CONFIG1_DONE_clk_base:CLK
To: Demo_sb_0/CORERESETP_0/count_sdif0_enable:EN
data required time N/C
data arrival time - 4.859
slack N/C
Data arrival time calculation
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 0.000 0.000
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Demo_sb_0/CCC_0/GL0_INST:An net Demo_sb_0/CCC_0/GL0_net + 0.459 0.459 r
Demo_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 0.637 5 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An net Demo_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.574 1.211 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YL cell ADLIB:RGB + 0.317 1.528 11 r
Demo_sb_0/CORERESETP_0/CONFIG1_DONE_clk_base:CLK net Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbl_net_1 + 0.537 2.065 r
Demo_sb_0/CORERESETP_0/CONFIG1_DONE_clk_base:Q cell ADLIB:SLE + 0.108 2.173 3 f
Demo_sb_0/CORERESETP_0/next_sdif0_state12_i:A net Demo_sb_0/CORERESETP_0/CONFIG1_DONE_clk_base + 0.313 2.486 f
Demo_sb_0/CORERESETP_0/next_sdif0_state12_i:Y cell ADLIB:CFG2 + 0.147 2.633 3 r
Demo_sb_0/CORERESETP_0/count_sdif0_enable_RNO_0:D net Demo_sb_0/CORERESETP_0/N_242_i + 0.771 3.404 r
Demo_sb_0/CORERESETP_0/count_sdif0_enable_RNO_0:Y cell ADLIB:CFG4 + 0.332 3.736 1 f
Demo_sb_0/CORERESETP_0/count_sdif0_enable:EN net Demo_sb_0/CORERESETP_0/N_280_i + 1.123 4.859 f
data arrival time 4.859
Data required time calculation
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 N/C N/C
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 N/C r
Demo_sb_0/CCC_0/GL0_INST:An net Demo_sb_0/CCC_0/GL0_net + 0.459 N/C r
Demo_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 N/C 5 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB3:An net Demo_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.572 N/C f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB3:YL cell ADLIB:RGB + 0.317 N/C 8 r
Demo_sb_0/CORERESETP_0/count_sdif0_enable:CLK net Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB3_rgbl_net_1 + 0.495 N/C r
Demo_sb_0/CORERESETP_0/count_sdif0_enable:EN Library setup time ADLIB:SLE - 0.308 N/C
Operating Conditions WORST

SET External Setup

No Path

SET Clock to Output

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Clock to Out (ns) Operating Conditions
Path 1 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE SPI_0_DO 7.893 10.290 10.290 WORST
Path 2 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE GPIO_0_M2F 6.983 9.380 9.380 WORST
Path 3 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE GPIO_5_M2F 6.970 9.367 9.367 WORST
Path 4 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE GPIO_7_M2F 6.754 9.151 9.151 WORST
Path 5 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE GPIO_2_M2F 6.655 9.052 9.052 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE
To: SPI_0_DO
data required time N/C
data arrival time - 10.290
slack N/C
Data arrival time calculation
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 0.000 0.000
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Demo_sb_0/CCC_0/GL0_INST:An net Demo_sb_0/CCC_0/GL0_net + 0.459 0.459 r
Demo_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 0.637 5 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1:An net Demo_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.612 1.249 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1:YR cell ADLIB:RGB + 0.316 1.565 1 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B net Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_YR + 0.407 1.972 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB cell ADLIB:IP_INTERFACE + 0.209 2.181 1 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE net Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net + 0.216 2.397 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_SDO_USBA_STP_MGPIO6A_OUT cell ADLIB:MSS_075_IP + 3.872 6.269 1 f
Demo_sb_0/Demo_sb_MSS_0/SPI_0_DO_PAD/U_IOPAD:D net Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST_SPI0_SDO_USBA_STP_MGPIO6A_OUT + 1.319 7.588 f
Demo_sb_0/Demo_sb_MSS_0/SPI_0_DO_PAD/U_IOPAD:PAD cell ADLIB:IOPAD_TRI + 2.702 10.290 0 f
SPI_0_DO net SPI_0_DO + 0.000 10.290 f
data arrival time 10.290
Data required time calculation
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 N/C N/C
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 N/C r
SPI_0_DO N/C f
Operating Conditions WORST

SET Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB to Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

No Path

SET Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT to Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

No Path

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 Demo_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK Demo_sb_0/CORERESETP_0/sdif0_areset_n_q1:ALn 4.108 6.130 0.353 4.446 -0.015 WORST
Path 2 Demo_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base:ALn 4.108 6.130 0.353 4.443 -0.018 WORST
Path 3 Demo_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK Demo_sb_0/CORERESETP_0/sm0_areset_n_q1:ALn 4.108 6.130 0.353 4.433 -0.028 WORST
Path 4 Demo_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK Demo_sb_0/CORERESETP_0/sdif0_areset_n_clk_base:ALn 4.108 6.130 0.353 4.433 -0.028 WORST
Path 5 Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base:CLK Demo_sb_0/CORERESETP_0/release_sdif2_core_clk_base:ALn 3.254 5.310 0.353 3.635 0.028 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Demo_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK
To: Demo_sb_0/CORERESETP_0/sdif0_areset_n_q1:ALn
data required time N/C
data arrival time - 6.130
slack N/C
Data arrival time calculation
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 0.000 0.000
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Demo_sb_0/CCC_0/GL0_INST:An net Demo_sb_0/CCC_0/GL0_net + 0.459 0.459 r
Demo_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 0.637 5 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB0:An net Demo_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.574 1.211 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB0:YR cell ADLIB:RGB + 0.316 1.527 5 r
Demo_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK net Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB0_rgbr_net_1 + 0.495 2.022 r
Demo_sb_0/CORERESETP_0/MSS_HPMS_READY_int:Q cell ADLIB:SLE + 0.087 2.109 1 r
Demo_sb_0/CORERESETP_0/sdif0_areset_n:B net Demo_sb_0/CORERESETP_0/MSS_HPMS_READY_int + 0.316 2.425 r
Demo_sb_0/CORERESETP_0/sdif0_areset_n:Y cell ADLIB:CFG2 + 0.158 2.583 1 r
Demo_sb_0/CORERESETP_0/sdif0_areset_n_RNIL3AD:An net Demo_sb_0/CORERESETP_0/sm0_areset_n + 1.764 4.347 f
Demo_sb_0/CORERESETP_0/sdif0_areset_n_RNIL3AD:YEn cell ADLIB:GBM + 0.374 4.721 2 f
Demo_sb_0/CORERESETP_0/sdif0_areset_n_RNIL3AD/U0_RGB1_RGB0:An net Demo_sb_0/CORERESETP_0/sdif0_areset_n_RNIL3AD/U0_YWn_GEast + 0.566 5.287 f
Demo_sb_0/CORERESETP_0/sdif0_areset_n_RNIL3AD/U0_RGB1_RGB0:YL cell ADLIB:RGB + 0.317 5.604 4 r
Demo_sb_0/CORERESETP_0/sdif0_areset_n_q1:ALn net Demo_sb_0/CORERESETP_0/sdif0_areset_n_RNIL3AD/U0_RGB1_RGB0_rgbl_net_1 + 0.526 6.130 r
data arrival time 6.130
Data required time calculation
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 N/C N/C
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 N/C r
Demo_sb_0/CCC_0/GL0_INST:An net Demo_sb_0/CCC_0/GL0_net + 0.459 N/C r
Demo_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 N/C 5 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An net Demo_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.574 N/C f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YL cell ADLIB:RGB + 0.317 N/C 11 r
Demo_sb_0/CORERESETP_0/sdif0_areset_n_q1:CLK net Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbl_net_1 + 0.509 N/C r
Demo_sb_0/CORERESETP_0/sdif0_areset_n_q1:ALn Library recovery time ADLIB:SLE - 0.353 N/C
Operating Conditions WORST

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:APB_CLK Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[8]:D 8.479 14.048 0.254 9.069 WORST
Path 2 SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:APB_CLK Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[17]:D 8.240 13.809 0.254 8.832 WORST
Path 3 SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:APB_CLK Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[14]:D 8.252 13.821 0.254 8.830 WORST
Path 4 SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:APB_CLK Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN 8.178 13.747 0.308 8.814 WORST
Path 5 SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:APB_CLK Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[1]:D 8.210 13.779 0.174 8.733 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:APB_CLK
To: Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[8]:D
data required time N/C
data arrival time - 14.048
slack N/C
Data arrival time calculation
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB 0.000 0.000
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB Clock source + 0.000 0.000 r
Demo_sb_0/Demo_sb_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI1SM8:An net Demo_sb_0/Demo_sb_MSS_0/FIC_2_APB_M_PCLK + 3.459 3.459 f
Demo_sb_0/Demo_sb_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI1SM8:YWn cell ADLIB:GBM + 0.374 3.833 2 f
Demo_sb_0/Demo_sb_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI1SM8/U0_RGB1_RGB6:An net Demo_sb_0/Demo_sb_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI1SM8/U0_YWn + 0.581 4.414 f
Demo_sb_0/Demo_sb_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI1SM8/U0_RGB1_RGB6:YL cell ADLIB:RGB + 0.317 4.731 1 r
SERDES_IF2_0/SERDESIF_INST/IP_INTERFACE_161:B net Demo_sb_0/Demo_sb_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI1SM8/U0_RGB1_RGB6_rgbl_net_1 + 0.401 5.132 r
SERDES_IF2_0/SERDESIF_INST/IP_INTERFACE_161:IPB cell ADLIB:IP_INTERFACE + 0.209 5.341 1 r
SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:APB_CLK net SERDES_IF2_0/SERDESIF_INST/APB_CLK_net + 0.228 5.569 r
SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:APB_PRDATA[8] cell ADLIB:SERDESIF_075_IP + 3.500 9.069 1 r
Demo_sb_0/CORECONFIGP_0/un1_SDIF0_PRDATA[8]:C net Demo_sb_0_SDIF0_INIT_APB_PRDATA[8] + 4.103 13.172 r
Demo_sb_0/CORECONFIGP_0/un1_SDIF0_PRDATA[8]:Y cell ADLIB:CFG4 + 0.158 13.330 1 r
Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO[8]:D net Demo_sb_0/CORECONFIGP_0/N_272 + 0.306 13.636 r
Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_RNO[8]:Y cell ADLIB:CFG4 + 0.337 13.973 1 r
Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[8]:D net Demo_sb_0/CORECONFIGP_0/prdata[8] + 0.075 14.048 r
data arrival time 14.048
Data required time calculation
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB N/C N/C
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB Clock source + 0.000 N/C r
Demo_sb_0/Demo_sb_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI1SM8:An net Demo_sb_0/Demo_sb_MSS_0/FIC_2_APB_M_PCLK + 3.459 N/C f
Demo_sb_0/Demo_sb_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI1SM8:YEn cell ADLIB:GBM + 0.374 N/C 6 f
Demo_sb_0/Demo_sb_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI1SM8/U0_RGB1_RGB1:An net Demo_sb_0/Demo_sb_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI1SM8/U0_YWn_GEast + 0.577 N/C f
Demo_sb_0/Demo_sb_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI1SM8/U0_RGB1_RGB1:YL cell ADLIB:RGB + 0.317 N/C 28 r
Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[8]:CLK net Demo_sb_0/Demo_sb_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI1SM8/U0_RGB1_RGB1_rgbl_net_1 + 0.506 N/C r
Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[8]:D Library setup time ADLIB:SLE - 0.254 N/C
Operating Conditions WORST

SET External Setup

No Path

SET Clock to Output

No Path

SET Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDCF

SET Register to Register

No Path

SET External Setup

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) External Setup (ns) Operating Conditions
Path 1 PHY_MDIO Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDIF 2.832 2.832 -1.536 1.296 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: PHY_MDIO
To: Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDIF
data required time N/C
data arrival time - 2.832
slack N/C
Data arrival time calculation
PHY_MDIO 0.000 0.000 r
BIBUF_0/U0/U_IOPAD:PAD net PHY_MDIO + 0.000 0.000 r
BIBUF_0/U0/U_IOPAD:Y cell ADLIB:IOPAD_BI + 0.729 0.729 1 r
BIBUF_0/U0/U_IOINFF:A net BIBUF_0/U0/YIN1 + 0.165 0.894 r
BIBUF_0/U0/U_IOINFF:Y cell ADLIB:IOINFF_BYPASS + 0.112 1.006 1 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_98:A net BIBUF_0_Y + 1.396 2.402 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_98:IPA cell ADLIB:IP_INTERFACE + 0.194 2.596 1 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDIF net Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/MDIF_net + 0.236 2.832 r
data arrival time 2.832
Data required time calculation
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDCF N/C N/C
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDCF Clock source + 0.000 N/C r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDIF Library setup time ADLIB:MSS_075_IP - -1.536 N/C
Operating Conditions WORST

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 Demo_sb_0/CORERESETP_0/count_sdif0[11]:CLK Demo_sb_0/CORERESETP_0/release_sdif0_core:EN 2.989 10.277 0.308 3.325 WORST
Path 2 Demo_sb_0/CORERESETP_0/count_sdif0[6]:CLK Demo_sb_0/CORERESETP_0/release_sdif0_core:EN 2.945 10.255 0.308 3.303 WORST
Path 3 Demo_sb_0/CORERESETP_0/count_sdif0[12]:CLK Demo_sb_0/CORERESETP_0/release_sdif0_core:EN 2.764 10.043 0.308 3.091 WORST
Path 4 Demo_sb_0/CORERESETP_0/count_sdif0[8]:CLK Demo_sb_0/CORERESETP_0/release_sdif0_core:EN 2.725 10.032 0.308 3.080 WORST
Path 5 Demo_sb_0/CORERESETP_0/count_sdif0[5]:CLK Demo_sb_0/CORERESETP_0/release_sdif0_core:EN 2.656 9.975 0.308 3.023 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Demo_sb_0/CORERESETP_0/count_sdif0[11]:CLK
To: Demo_sb_0/CORERESETP_0/release_sdif0_core:EN
data required time N/C
data arrival time - 10.277
slack N/C
Data arrival time calculation
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT 0.000 0.000
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT + 1.797 1.797 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 1.949 1 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.578 5.527 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.374 5.901 4 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB2:An net Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.561 6.462 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB2:YL cell ADLIB:RGB + 0.317 6.779 17 r
Demo_sb_0/CORERESETP_0/count_sdif0[11]:CLK net Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB2_rgbl_net_1 + 0.509 7.288 r
Demo_sb_0/CORERESETP_0/count_sdif0[11]:Q cell ADLIB:SLE + 0.108 7.396 2 f
Demo_sb_0/CORERESETP_0/release_sdif0_core6_7:B net Demo_sb_0/CORERESETP_0/count_sdif0[11] + 0.419 7.815 f
Demo_sb_0/CORERESETP_0/release_sdif0_core6_7:Y cell ADLIB:CFG4 + 0.287 8.102 1 f
Demo_sb_0/CORERESETP_0/release_sdif0_core6:B net Demo_sb_0/CORERESETP_0/release_sdif0_core6_7 + 0.666 8.768 f
Demo_sb_0/CORERESETP_0/release_sdif0_core6:Y cell ADLIB:CFG4 + 0.287 9.055 1 f
Demo_sb_0/CORERESETP_0/release_sdif0_core:EN net Demo_sb_0/CORERESETP_0/release_sdif0_core6 + 1.222 10.277 f
data arrival time 10.277
Data required time calculation
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT N/C N/C
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 N/C r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT + 1.797 N/C r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 N/C 1 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.578 N/C f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.374 N/C 4 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB2:An net Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.561 N/C f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB2:YL cell ADLIB:RGB + 0.317 N/C 17 r
Demo_sb_0/CORERESETP_0/release_sdif0_core:CLK net Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB2_rgbl_net_1 + 0.481 N/C r
Demo_sb_0/CORERESETP_0/release_sdif0_core:EN Library setup time ADLIB:SLE - 0.308 N/C
Operating Conditions WORST

SET External Setup

No Path

SET Clock to Output

No Path

SET Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT

No Path

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK Demo_sb_0/CORERESETP_0/count_sdif0[10]:ALn 3.308 10.632 0.353 3.721 0.060 WORST
Path 2 Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK Demo_sb_0/CORERESETP_0/count_sdif0[12]:ALn 3.307 10.631 0.353 3.720 0.060 WORST
Path 3 Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK Demo_sb_0/CORERESETP_0/count_sdif0[8]:ALn 3.329 10.653 0.353 3.715 0.033 WORST
Path 4 Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK Demo_sb_0/CORERESETP_0/count_sdif0[4]:ALn 3.329 10.653 0.353 3.715 0.033 WORST
Path 5 Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK Demo_sb_0/CORERESETP_0/count_sdif0[2]:ALn 3.329 10.653 0.353 3.715 0.033 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK
To: Demo_sb_0/CORERESETP_0/count_sdif0[10]:ALn
data required time N/C
data arrival time - 10.632
slack N/C
Data arrival time calculation
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT 0.000 0.000
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT + 1.797 1.797 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 1.949 1 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.578 5.527 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.374 5.901 4 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An net Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.562 6.463 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YL cell ADLIB:RGB + 0.317 6.780 13 r
Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK net Demo_sb_0_RCOSC_25_50MHZ_O2F + 0.544 7.324 r
Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:Q cell ADLIB:SLE + 0.087 7.411 1 r
Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIEI67:An net Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_0 + 1.439 8.850 f
Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIEI67:YEn cell ADLIB:GBM + 0.374 9.224 1 f
Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIEI67/U0_RGB1:An net Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIEI67/U0_YWn_GEast + 0.569 9.793 f
Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIEI67/U0_RGB1:YL cell ADLIB:RGB + 0.317 10.110 14 r
Demo_sb_0/CORERESETP_0/count_sdif0[10]:ALn net Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc + 0.522 10.632 r
data arrival time 10.632
Data required time calculation
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT N/C N/C
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 N/C r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT + 1.797 N/C r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 N/C 1 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.578 N/C f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.374 N/C 4 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB2:An net Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.561 N/C f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB2:YL cell ADLIB:RGB + 0.317 N/C 17 r
Demo_sb_0/CORERESETP_0/count_sdif0[10]:CLK net Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB2_rgbl_net_1 + 0.485 N/C r
Demo_sb_0/CORERESETP_0/count_sdif0[10]:ALn Library recovery time ADLIB:SLE - 0.353 N/C
Operating Conditions WORST

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain FCCC_0/CCC_INST/INST_CCC_IP:GL0

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] to FCCC_0/CCC_INST/INST_CCC_IP:GL0

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain FCCC_0/CCC_INST/INST_CCC_IP:GL1

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] to FCCC_0/CCC_INST/INST_CCC_IP:GL1

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain FCCC_1/CCC_INST/INST_CCC_IP:GL0

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1]

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET FCCC_1/CCC_INST/INST_CCC_IP:GL0 to SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1]

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Path Set Pin to Pin

SET Input to Output

No Path

Path Set User Sets