"CLK0_PAD",,"CLK0_PAD","CLK0_PAD"
"Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0",,"Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0","Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0"
"Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB",,"Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB","Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB"
"Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDCF",,"Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDCF","Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDCF"
"Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT",,"Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT","Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT"
"FCCC_0/CCC_INST/INST_CCC_IP:GL0",,"FCCC_0/CCC_INST/INST_CCC_IP:GL0","FCCC_0/CCC_INST/INST_CCC_IP:GL0"
"FCCC_0/CCC_INST/INST_CCC_IP:GL1",,"FCCC_0/CCC_INST/INST_CCC_IP:GL1","FCCC_0/CCC_INST/INST_CCC_IP:GL1"
"FCCC_1/CCC_INST/INST_CCC_IP:GL0",,"FCCC_1/CCC_INST/INST_CCC_IP:GL0","FCCC_1/CCC_INST/INST_CCC_IP:GL0"
"SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]",,"SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]","SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]"
"SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1]",,"SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1]","SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1]"
