Timing Report Max Delay Analysis

SmartTime Version 12.600.0.14

Microsemi Corporation - Microsemi Libero Software Release v12.1 (Version 12.600.0.14)

Date: Tue Jun 11 14:28:46 2019

Design Demo
Family SmartFusion2
Die M2S090TS
Package 484 FBGA
Temperature Range 0 - 85 C
Voltage Range 1.14 - 1.26 V
Speed Grade -1
Design State Post-Layout
Data source Production
Min Operating Conditions BEST - 1.26 V - 0 C
Max Operating Conditions WORST - 1.14 V - 85 C
Operating Conditions WORST - 1.14 V - 85 C
Scenario for Timing Analysis timing_analysis

Summary

Clock Domain Period (ns) Frequency (MHz) Required Period (ns) Required Frequency (MHz) External Setup (ns) Max Clock-To-Out (ns)
CLK0_PAD 1.600 625.000 20.000 50.000 N/A N/A
Demo_sb_0/CCC_0/GL0 4.684 213.493 10.000 100.000 N/A 15.315
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 3.900 256.410 20.000 50.000 N/A N/A
FCCC_0/GL0 1.186 843.170 16.000 62.500 N/A N/A
FCCC_0/GL1 1.040 961.538 16.000 62.500 N/A N/A
FCCC_1/GL0 2.210 452.489 8.000 125.000 N/A N/A
Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB 19.720 50.710 40.000 25.000 N/A N/A
Demo_sb_0/FABOSC_0/I_RCOSC_1MHZ/CLKOUT 0.284 3521.127 1000.000 1.000 N/A N/A
SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] 1.818 550.055 8.000 125.000 N/A N/A
SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1] 1.142 875.657 8.000 125.000 N/A N/A

Min Delay (ns) Max Delay (ns)
Input to Output N/A

Clock Domain CLK0_PAD

Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin Demo_sb_0/CCC_0/CLK0_PAD_INST/U_IOPAD:PAD

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain Demo_sb_0/CCC_0/GL0

Info: The maximum frequency of this clock domain is limited by the period of pin Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns)
Path 1 Demo_sb_0/CORERESETP_0/release_sdif0_core_clk_base:CLK Demo_sb_0/CORERESETP_0/SDIF_RELEASED_int:EN 2.528 7.135 6.828 13.963 0.308 2.865
Path 2 Demo_sb_0/CORERESETP_0/ddr_settled_clk_base:CLK Demo_sb_0/CORERESETP_0/SDIF_RELEASED_int:EN 2.451 7.212 6.751 13.963 0.308 2.788
Path 3 Demo_sb_0/CORERESETP_0/CONFIG1_DONE_clk_base:CLK Demo_sb_0/CORERESETP_0/SDIF0_PHY_RESET_N_int:EN 2.373 7.302 6.661 13.963 0.308 2.698
Path 4 Demo_sb_0/CORERESETP_0/sdif0_spll_lock_q2:CLK Demo_sb_0/CORERESETP_0/SDIF0_PHY_RESET_N_int:EN 2.321 7.354 6.609 13.963 0.308 2.646
Path 5 Demo_sb_0/CORERESETP_0/CONFIG1_DONE_clk_base:CLK Demo_sb_0/CORERESETP_0/count_sdif0_enable:EN 2.160 7.494 6.448 13.942 0.308 2.506

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Demo_sb_0/CORERESETP_0/release_sdif0_core_clk_base:CLK
To: Demo_sb_0/CORERESETP_0/SDIF_RELEASED_int:EN
data required time 13.963
data arrival time - 6.828
slack 7.135
Data arrival time calculation
Demo_sb_0/CCC_0/GL0 0.000 0.000
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 2.235 2.235
Demo_sb_0/CCC_0/GL0_INST:An net Demo_sb_0/CCC_0/GL0_net + 0.423 2.658 r
Demo_sb_0/CCC_0/GL0_INST:YWn cell ADLIB:GBM + 0.177 2.835 4 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB4:An net Demo_sb_0/CCC_0/GL0_INST/U0_YWn + 0.602 3.437 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB4:YR cell ADLIB:RGB + 0.316 3.753 31 r
Demo_sb_0/CORERESETP_0/release_sdif0_core_clk_base:CLK net Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB4_rgbr_net_1 + 0.547 4.300 r
Demo_sb_0/CORERESETP_0/release_sdif0_core_clk_base:Q cell ADLIB:SLE + 0.108 4.408 1 f
Demo_sb_0/CORERESETP_0/next_sdif0_state15:B net Demo_sb_0/CORERESETP_0/release_sdif0_core_clk_base + 0.314 4.722 f
Demo_sb_0/CORERESETP_0/next_sdif0_state15:Y cell ADLIB:CFG2 + 0.164 4.886 2 f
Demo_sb_0/CORERESETP_0/next_sm0_state25:D net Demo_sb_0/CORERESETP_0/next_sdif0_state15 + 0.450 5.336 f
Demo_sb_0/CORERESETP_0/next_sm0_state25:Y cell ADLIB:CFG4 + 0.087 5.423 3 f
Demo_sb_0/CORERESETP_0/next_sdif_released_0_sqmuxa_0_a3:A net Demo_sb_0/CORERESETP_0/next_sm0_state25 + 0.611 6.034 f
Demo_sb_0/CORERESETP_0/next_sdif_released_0_sqmuxa_0_a3:Y cell ADLIB:CFG2 + 0.087 6.121 1 f
Demo_sb_0/CORERESETP_0/SDIF_RELEASED_int:EN net Demo_sb_0/CORERESETP_0/next_sdif_released_0_sqmuxa + 0.707 6.828 f
data arrival time 6.828
Data required time calculation
Demo_sb_0/CCC_0/GL0 Clock Constraint 10.000 10.000
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 10.000 r
Clock generation + 2.235 12.235
Demo_sb_0/CCC_0/GL0_INST:An net Demo_sb_0/CCC_0/GL0_net + 0.423 12.658 r
Demo_sb_0/CCC_0/GL0_INST:YWn cell ADLIB:GBM + 0.177 12.835 4 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB4:An net Demo_sb_0/CCC_0/GL0_INST/U0_YWn + 0.602 13.437 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB4:YR cell ADLIB:RGB + 0.316 13.753 31 r
Demo_sb_0/CORERESETP_0/SDIF_RELEASED_int:CLK net Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB4_rgbr_net_1 + 0.518 14.271 r
Demo_sb_0/CORERESETP_0/SDIF_RELEASED_int:EN Library setup time ADLIB:SLE - 0.308 13.963
data required time 13.963

SET External Setup

No Path

SET Clock to Output

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Clock to Out (ns)
Path 1 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE GPIO_5_M2F 10.719 15.315 15.315
Path 2 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE GPIO_7_M2F 10.543 15.139 15.139
Path 3 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE GPIO_0_M2F 10.440 15.036 15.036
Path 4 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE GPIO_6_M2F 10.362 14.958 14.958
Path 5 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE GPIO_1_M2F 10.285 14.881 14.881

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE
To: GPIO_5_M2F
data required time N/C
data arrival time - 15.315
slack N/C
Data arrival time calculation
Demo_sb_0/CCC_0/GL0 0.000 0.000
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 2.235 2.235
Demo_sb_0/CCC_0/GL0_INST:An net Demo_sb_0/CCC_0/GL0_net + 0.423 2.658 r
Demo_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 2.836 2 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1:An net Demo_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.612 3.448 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1:YR cell ADLIB:RGB + 0.316 3.764 1 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B net Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_YR + 0.407 4.171 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB cell ADLIB:IP_INTERFACE + 0.209 4.380 1 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE net Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net + 0.216 4.596 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_SDI_MGPIO5A_H2F_B cell ADLIB:MSS_075_IP + 1.461 6.057 1 f
GPIO_5_M2F_obuf/U0/U_IOOUTFF:A net GPIO_5_M2F_c + 6.143 12.200 f
GPIO_5_M2F_obuf/U0/U_IOOUTFF:Y cell ADLIB:IOOUTFF_BYPASS + 0.330 12.530 1 f
GPIO_5_M2F_obuf/U0/U_IOPAD:D net GPIO_5_M2F_obuf/U0/DOUT + 0.083 12.613 f
GPIO_5_M2F_obuf/U0/U_IOPAD:PAD cell ADLIB:IOPAD_TRI + 2.702 15.315 0 f
GPIO_5_M2F net GPIO_5_M2F + 0.000 15.315 f
data arrival time 15.315
Data required time calculation
Demo_sb_0/CCC_0/GL0 N/C N/C
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 N/C r
Clock generation + 2.235 N/C
GPIO_5_M2F N/C f

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns)
Path 1 Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base:CLK Demo_sb_0/CORERESETP_0/CONFIG1_DONE_clk_base:ALn 3.718 5.901 8.018 13.919 0.353 4.099 0.028
Path 2 Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base:CLK Demo_sb_0/CORERESETP_0/CONFIG2_DONE_clk_base:ALn 3.718 5.901 8.018 13.919 0.353 4.099 0.028
Path 3 Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base:CLK Demo_sb_0/CORERESETP_0/sdif0_spll_lock_q1:ALn 3.718 5.901 8.018 13.919 0.353 4.099 0.028
Path 4 Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base:CLK Demo_sb_0/CORERESETP_0/sdif0_spll_lock_q2:ALn 3.718 5.901 8.018 13.919 0.353 4.099 0.028
Path 5 Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base:CLK Demo_sb_0/CORERESETP_0/sm0_state[3]:ALn 3.718 5.901 8.018 13.919 0.353 4.099 0.028

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base:CLK
To: Demo_sb_0/CORERESETP_0/CONFIG1_DONE_clk_base:ALn
data required time 13.919
data arrival time - 8.018
slack 5.901
Data arrival time calculation
Demo_sb_0/CCC_0/GL0 0.000 0.000
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 2.235 2.235
Demo_sb_0/CCC_0/GL0_INST:An net Demo_sb_0/CCC_0/GL0_net + 0.423 2.658 r
Demo_sb_0/CCC_0/GL0_INST:YWn cell ADLIB:GBM + 0.177 2.835 4 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB4:An net Demo_sb_0/CCC_0/GL0_INST/U0_YWn + 0.602 3.437 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB4:YR cell ADLIB:RGB + 0.316 3.753 31 r
Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base:CLK net Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB4_rgbr_net_1 + 0.547 4.300 r
Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base:Q cell ADLIB:SLE + 0.087 4.387 1 r
Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base_RNI2J49:An net Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base_0 + 1.760 6.147 f
Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base_RNI2J49:YWn cell ADLIB:GBM + 0.374 6.521 1 f
Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base_RNI2J49/U0_RGB1:An net Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base_RNI2J49/U0_YWn + 0.609 7.130 f
Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base_RNI2J49/U0_RGB1:YR cell ADLIB:RGB + 0.316 7.446 29 r
Demo_sb_0/CORERESETP_0/CONFIG1_DONE_clk_base:ALn net Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base_RNI2J49/U0_RGB1_YR + 0.572 8.018 r
data arrival time 8.018
Data required time calculation
Demo_sb_0/CCC_0/GL0 Clock Constraint 10.000 10.000
Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 10.000 r
Clock generation + 2.235 12.235
Demo_sb_0/CCC_0/GL0_INST:An net Demo_sb_0/CCC_0/GL0_net + 0.423 12.658 r
Demo_sb_0/CCC_0/GL0_INST:YWn cell ADLIB:GBM + 0.177 12.835 4 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB4:An net Demo_sb_0/CCC_0/GL0_INST/U0_YWn + 0.602 13.437 f
Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB4:YR cell ADLIB:RGB + 0.316 13.753 31 r
Demo_sb_0/CORERESETP_0/CONFIG1_DONE_clk_base:CLK net Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB4_rgbr_net_1 + 0.519 14.272 r
Demo_sb_0/CORERESETP_0/CONFIG1_DONE_clk_base:ALn Library recovery time ADLIB:SLE - 0.353 13.919
data required time 13.919

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT to Demo_sb_0/CCC_0/GL0

No Path

SET Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB to Demo_sb_0/CCC_0/GL0

No Path

Clock Domain Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns)
Path 1 Demo_sb_0/CORERESETP_0/count_sdif0[5]:CLK Demo_sb_0/CORERESETP_0/release_sdif0_core:EN 2.607 17.042 9.990 27.032 0.308 2.958
Path 2 Demo_sb_0/CORERESETP_0/count_sdif0[1]:CLK Demo_sb_0/CORERESETP_0/release_sdif0_core:EN 2.460 17.189 9.843 27.032 0.308 2.811
Path 3 Demo_sb_0/CORERESETP_0/count_sdif0[4]:CLK Demo_sb_0/CORERESETP_0/release_sdif0_core:EN 2.431 17.231 9.801 27.032 0.308 2.769
Path 4 Demo_sb_0/CORERESETP_0/count_sdif0[10]:CLK Demo_sb_0/CORERESETP_0/release_sdif0_core:EN 2.411 17.251 9.781 27.032 0.308 2.749
Path 5 Demo_sb_0/CORERESETP_0/count_sdif0[7]:CLK Demo_sb_0/CORERESETP_0/release_sdif0_core:EN 2.372 17.277 9.755 27.032 0.308 2.723

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Demo_sb_0/CORERESETP_0/count_sdif0[5]:CLK
To: Demo_sb_0/CORERESETP_0/release_sdif0_core:EN
data required time 27.032
data arrival time - 9.990
slack 17.042
Data arrival time calculation
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 0.000 0.000
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT + 1.797 1.797 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 1.949 1 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.595 5.544 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YWn cell ADLIB:GBM + 0.374 5.918 3 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:An net Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn + 0.598 6.516 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:YR cell ADLIB:RGB + 0.316 6.832 18 r
Demo_sb_0/CORERESETP_0/count_sdif0[5]:CLK net Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1_rgbr_net_1 + 0.551 7.383 r
Demo_sb_0/CORERESETP_0/count_sdif0[5]:Q cell ADLIB:SLE + 0.108 7.491 2 f
Demo_sb_0/CORERESETP_0/release_sdif0_core4_1:B net Demo_sb_0/CORERESETP_0/count_sdif0[5] + 0.673 8.164 f
Demo_sb_0/CORERESETP_0/release_sdif0_core4_1:Y cell ADLIB:CFG4 + 0.287 8.451 1 f
Demo_sb_0/CORERESETP_0/release_sdif0_core4:C net Demo_sb_0/CORERESETP_0/release_sdif0_core4_1 + 0.204 8.655 f
Demo_sb_0/CORERESETP_0/release_sdif0_core4:Y cell ADLIB:CFG4 + 0.287 8.942 1 f
Demo_sb_0/CORERESETP_0/release_sdif0_core:EN net Demo_sb_0/CORERESETP_0/release_sdif0_core4 + 1.048 9.990 f
data arrival time 9.990
Data required time calculation
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Clock Constraint 20.000 20.000
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 20.000 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT + 1.797 21.797 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 21.949 1 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.595 25.544 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YWn cell ADLIB:GBM + 0.374 25.918 3 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:An net Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn + 0.598 26.516 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:YR cell ADLIB:RGB + 0.316 26.832 18 r
Demo_sb_0/CORERESETP_0/release_sdif0_core:CLK net Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1_rgbr_net_1 + 0.508 27.340 r
Demo_sb_0/CORERESETP_0/release_sdif0_core:EN Library setup time ADLIB:SLE - 0.308 27.032
data required time 27.032

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns)
Path 1 Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK Demo_sb_0/CORERESETP_0/count_sdif0[10]:ALn 3.559 16.100 10.901 27.001 0.353 3.900 -0.012
Path 2 Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK Demo_sb_0/CORERESETP_0/count_sdif0[2]:ALn 3.559 16.100 10.901 27.001 0.353 3.900 -0.012
Path 3 Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK Demo_sb_0/CORERESETP_0/count_sdif0[4]:ALn 3.559 16.100 10.901 27.001 0.353 3.900 -0.012
Path 4 Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK Demo_sb_0/CORERESETP_0/count_sdif0[6]:ALn 3.559 16.100 10.901 27.001 0.353 3.900 -0.012
Path 5 Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK Demo_sb_0/CORERESETP_0/release_sdif1_core:ALn 3.559 16.100 10.901 27.001 0.353 3.900 -0.012

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK
To: Demo_sb_0/CORERESETP_0/count_sdif0[10]:ALn
data required time 27.001
data arrival time - 10.901
slack 16.100
Data arrival time calculation
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 0.000 0.000
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT + 1.797 1.797 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 1.949 1 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.595 5.544 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YWn cell ADLIB:GBM + 0.374 5.918 3 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB2:An net Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn + 0.594 6.512 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB2:YR cell ADLIB:RGB + 0.316 6.828 13 r
Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK net Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB2_rgbr_net_1 + 0.514 7.342 r
Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:Q cell ADLIB:SLE + 0.087 7.429 1 r
Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIEI67:An net Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_0 + 1.619 9.048 f
Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIEI67:YWn cell ADLIB:GBM + 0.374 9.422 1 f
Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIEI67/U0_RGB1:An net Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIEI67/U0_YWn + 0.592 10.014 f
Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIEI67/U0_RGB1:YR cell ADLIB:RGB + 0.316 10.330 15 r
Demo_sb_0/CORERESETP_0/count_sdif0[10]:ALn net Demo_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIEI67/U0_RGB1_YR + 0.571 10.901 r
data arrival time 10.901
Data required time calculation
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Clock Constraint 20.000 20.000
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 20.000 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT + 1.797 21.797 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 21.949 1 r
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.595 25.544 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YWn cell ADLIB:GBM + 0.374 25.918 3 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:An net Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn + 0.598 26.516 f
Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:YR cell ADLIB:RGB + 0.316 26.832 18 r
Demo_sb_0/CORERESETP_0/count_sdif0[10]:CLK net Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1_rgbr_net_1 + 0.522 27.354 r
Demo_sb_0/CORERESETP_0/count_sdif0[10]:ALn Library recovery time ADLIB:SLE - 0.353 27.001
data required time 27.001

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET Demo_sb_0/CCC_0/GL0 to Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

No Path

Clock Domain FCCC_0/GL0

Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin FCCC_0/GL0_INST/U0_RGB1:An

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] to FCCC_0/GL0

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns)
Path 1 SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[8] 9.742 5.816 9.742 15.558 -0.109
Path 2 SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[4] 9.640 6.066 9.640 15.706 -0.257
Path 3 SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[1] 9.516 6.069 9.516 15.585 -0.136
Path 4 SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[9] 9.723 6.114 9.723 15.837 -0.388
Path 5 SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[7] 9.605 6.122 9.605 15.727 -0.278

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]
To: Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[8]
data required time 15.558
data arrival time - 9.742
slack 5.816
Data arrival time calculation
SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] 0.000 0.000
SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Clock source + 0.000 0.000 r
SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXDATA[38] cell ADLIB:SERDESIF_075_IP + 0.131 0.131 1 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101_CFG1A_TEST:A net SERDES_IF2_0_EPCS_3_RX_DATA[8] + 6.654 6.785 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101_CFG1A_TEST:Y cell ADLIB:CFG1A_TEST + 0.087 6.872 1 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101_CFG1D_TEST1:A net mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101_CFG1A_TEST_net + 0.204 7.076 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101_CFG1D_TEST1:Y cell ADLIB:CFG1D_TEST + 0.372 7.448 1 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101_CFG1D_TEST0:A net mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101_CFG1D_TEST_net1 + 0.300 7.748 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101_CFG1D_TEST0:Y cell ADLIB:CFG1D_TEST + 0.372 8.120 1 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101_CFG1D_TEST:A net mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101_CFG1D_TEST_net0 + 0.204 8.324 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101_CFG1D_TEST:Y cell ADLIB:CFG1D_TEST + 0.372 8.696 1 f
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101:B net mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101_CFG1D_TEST_net + 0.568 9.264 f
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101:IPB cell ADLIB:IP_INTERFACE + 0.224 9.488 1 f
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[8] net Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/RCGF_net[8] + 0.254 9.742 f
data arrival time 9.742
Data required time calculation
FCCC_0/GL0 Clock Constraint 8.000 8.000
FCCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 8.000 r
Clock generation + 5.395 13.395
FCCC_0/GL0_INST:An net FCCC_0/GL0_net + 0.461 13.856 r
FCCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 14.034 1 f
FCCC_0/GL0_INST/U0_RGB1:An net FCCC_0/GL0_INST/U0_YWn_GEast + 0.598 14.632 f
FCCC_0/GL0_INST/U0_RGB1:YR cell ADLIB:RGB + 0.316 14.948 1 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_92:A net FCCC_0/GL0_INST/U0_RGB1_YR + 0.406 15.354 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_92:IPA cell ADLIB:IP_INTERFACE + 0.194 15.548 0 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RX_CLKPF net Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/RX_CLKPF_net + 0.221 15.769 r
clock-to-clock uncertainty - 0.320 15.449
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[8] Library setup time ADLIB:MSS_075_IP - -0.109 15.558
data required time 15.558

Clock Domain FCCC_0/GL1

Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin FCCC_0/GL1_INST/U0_RGB1:An

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] to FCCC_0/GL1

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns)
Path 1 SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[8] 9.742 5.512 9.742 15.254 0.230
Path 2 SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[4] 9.640 5.715 9.640 15.355 0.129
Path 3 SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[9] 9.723 5.744 9.723 15.467 0.017
Path 4 SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[1] 9.516 5.766 9.516 15.282 0.202
Path 5 SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[7] 9.605 5.889 9.605 15.494 -0.010

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]
To: Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[8]
data required time 15.254
data arrival time - 9.742
slack 5.512
Data arrival time calculation
SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] 0.000 0.000
SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Clock source + 0.000 0.000 r
SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXDATA[38] cell ADLIB:SERDESIF_075_IP + 0.131 0.131 1 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101_CFG1A_TEST:A net SERDES_IF2_0_EPCS_3_RX_DATA[8] + 6.654 6.785 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101_CFG1A_TEST:Y cell ADLIB:CFG1A_TEST + 0.087 6.872 1 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101_CFG1D_TEST1:A net mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101_CFG1A_TEST_net + 0.204 7.076 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101_CFG1D_TEST1:Y cell ADLIB:CFG1D_TEST + 0.372 7.448 1 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101_CFG1D_TEST0:A net mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101_CFG1D_TEST_net1 + 0.300 7.748 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101_CFG1D_TEST0:Y cell ADLIB:CFG1D_TEST + 0.372 8.120 1 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101_CFG1D_TEST:A net mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101_CFG1D_TEST_net0 + 0.204 8.324 f
mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101_CFG1D_TEST:Y cell ADLIB:CFG1D_TEST + 0.372 8.696 1 f
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101:B net mdr_Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101_CFG1D_TEST_net + 0.568 9.264 f
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101:IPB cell ADLIB:IP_INTERFACE + 0.224 9.488 1 f
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[8] net Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/RCGF_net[8] + 0.254 9.742 f
data arrival time 9.742
Data required time calculation
FCCC_0/GL1 Clock Constraint 8.000 8.000
FCCC_0/CCC_INST/INST_CCC_IP:GL1 Clock source + 0.000 8.000 r
Clock generation + 5.419 13.419
FCCC_0/GL1_INST:An net FCCC_0/GL1_net + 0.459 13.878 r
FCCC_0/GL1_INST:YEn cell ADLIB:GBM + 0.178 14.056 1 f
FCCC_0/GL1_INST/U0_RGB1:An net FCCC_0/GL1_INST/U0_YWn_GEast + 0.608 14.664 f
FCCC_0/GL1_INST/U0_RGB1:YR cell ADLIB:RGB + 0.316 14.980 1 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_91:A net FCCC_0/GL1_INST/U0_RGB1_YR + 0.408 15.388 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_91:IPA cell ADLIB:IP_INTERFACE + 0.194 15.582 0 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:TX_CLKPF net Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/TX_CLKPF_net + 0.222 15.804 r
clock-to-clock uncertainty - 0.320 15.484
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[8] Library setup time ADLIB:MSS_075_IP - 0.230 15.254
data required time 15.254

Clock Domain FCCC_1/GL0

Info: The maximum frequency of this clock domain is limited by the period of pin Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:GTX_CLKPF

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns)
Path 1 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN 2.435 2.749 2.435 5.184 0.308 -2.749
Path 2 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB Demo_sb_0/CORECONFIGP_0/state[0]:D 2.140 3.098 2.140 5.238 0.254 -3.098
Path 3 Demo_sb_0/CORECONFIGP_0/psel:CLK SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:APB_PSEL 7.332 10.140 12.981 23.121 2.663 19.720
Path 4 Demo_sb_0/CORECONFIGP_0/SDIF0_PENABLE:CLK SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:APB_PENABLE 6.915 12.506 12.563 25.069 0.715 14.988
Path 5 Demo_sb_0/CORECONFIGP_0/psel:CLK Demo_sb_0/CORECONFIGP_0/soft_reset_reg[11]:EN 2.709 16.819 8.358 25.177 0.308 6.362

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB
To: Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN
data required time 5.184
data arrival time - 2.435
slack 2.749
Data arrival time calculation
Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB 0.000 0.000
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB Clock source + 0.000 0.000 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PSEL cell ADLIB:MSS_075_IP + 0.852 0.852 1 f
Demo_sb_0/CORECONFIGP_0/next_state4:B net Demo_sb_0/Demo_sb_MSS_TMP_0_FIC_2_APB_MASTER_PSELx + 0.697 1.549 f
Demo_sb_0/CORECONFIGP_0/next_state4:Y cell ADLIB:CFG2 + 0.164 1.713 2 f
Demo_sb_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0:C net Demo_sb_0/CORECONFIGP_0/next_state4 + 0.099 1.812 f
Demo_sb_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0:Y cell ADLIB:CFG4 + 0.087 1.899 1 f
Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN net Demo_sb_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0 + 0.536 2.435 f
data arrival time 2.435
Data required time calculation
Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB Max Delay Constraint 0.000 0.000
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB Clock source + 0.000 0.000 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST_RNI9FDA:An net Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB + 3.682 3.682 f
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST_RNI9FDA:YEn cell ADLIB:GBM + 0.374 4.056 3 f
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST_RNI9FDA/U0_RGB1_RGB1:An net Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST_RNI9FDA/U0_YWn_GEast + 0.595 4.651 f
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST_RNI9FDA/U0_RGB1_RGB1:YR cell ADLIB:RGB + 0.316 4.967 23 r
Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:CLK net Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST_RNI9FDA/U0_RGB1_RGB1_rgbr_net_1 + 0.525 5.492 r
Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN Library setup time ADLIB:SLE - 0.308 5.184
data required time 5.184

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET Demo_sb_0/CCC_0/GL0 to Demo_sb_0/Demo_sb_MSS_0/CLK_CONFIG_APB

No Path

Clock Domain Demo_sb_0/FABOSC_0/I_RCOSC_1MHZ/CLKOUT

Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin program_recovery_WA_0/Clock_check_0/un1_pulse10_1_rs:CLK

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1]

Info: The maximum frequency of this clock domain is limited by the period of pin SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]

Info: The maximum frequency of this clock domain is limited by the period of pin SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1]

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET FCCC_1/GL0 to SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns)
Path 1 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:GTX_CLKPF SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[28] 9.281 7.607 14.273 21.880 2.120
Path 2 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:GTX_CLKPF SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[23] 9.120 7.742 14.112 21.854 2.146
Path 3 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:GTX_CLKPF SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[24] 9.077 7.797 14.069 21.866 2.134
Path 4 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:GTX_CLKPF SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[25] 9.089 7.877 14.081 21.958 2.042
Path 5 Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:GTX_CLKPF SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[22] 8.977 7.927 13.969 21.896 2.104

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:GTX_CLKPF
To: SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[28]
data required time 21.880
data arrival time - 14.273
slack 7.607
Data arrival time calculation
FCCC_1/GL0 0.000 0.000
FCCC_1/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 2.598 2.598
FCCC_1/GL0_INST:An net FCCC_1/GL0_net + 0.478 3.076 r
FCCC_1/GL0_INST:YEn cell ADLIB:GBM + 0.178 3.254 1 f
FCCC_1/GL0_INST/U0_RGB1:An net FCCC_1/GL0_INST/U0_YWn_GEast + 0.604 3.858 f
FCCC_1/GL0_INST/U0_RGB1:YR cell ADLIB:RGB + 0.316 4.174 1 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_99:A net FCCC_1/GL0_INST/U0_RGB1_YR + 0.405 4.579 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_99:IPA cell ADLIB:IP_INTERFACE + 0.194 4.773 1 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:GTX_CLKPF net Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/GTX_CLKPF_net + 0.219 4.992 r
Demo_sb_0/Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:TCGF[8] cell ADLIB:MSS_075_IP + 2.194 7.186 1 f
SERDES_IF2_0/SERDESIF_INST/IP_INTERFACE_208:A net Demo_sb_0_MAC_TBI_TCGF[8] + 6.695 13.881 f
SERDES_IF2_0/SERDESIF_INST/IP_INTERFACE_208:IPA cell ADLIB:IP_INTERFACE + 0.199 14.080 1 f
SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[28] net SERDES_IF2_0/SERDESIF_INST/EPCS_TXDATA_net[28] + 0.193 14.273 f
data arrival time 14.273
Data required time calculation
SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1] Multicyle Constraint 24.000 24.000
SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1] Clock source + 0.000 24.000 r
SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[28] Library setup time ADLIB:SERDESIF_075_IP - 2.120 21.880
data required time 21.880

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