Data Sheet: top

Project Settings
FAM: SmartFusion2
Die: M2S090TS
Package: 484 FBGA
Speed Grade: -1
Voltage: 1.2
HDL: Verilog
Project Description: SPI4.2
Location: C:/igloo2_task_feb_2021/SF2/SF2_TFTP_Update_Recovery_Demo_DF/Sample_files/Recovery_WA/Demo/component/work/top
State (Time): GENERATED ( Tue Jun 15 16:06:24 2021 )

Table of Contents
Generated Files
IO's
Hardware Instances
Firmware
Memory Map

Generated Files

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IO's

No IO's

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Cores

No Instances

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Firmware


No Firmware Generated. Design may not contain any processor subsystems, or firmware have not been downloaded to your vault

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Memory Map
The SmartDesign top contains the following Masters under its hierarchy
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CM3

Peripheral Offset Address Range High Address DRC
DDR_0_SPACE_3 0xD000_0000 256MB 0xDFFF_FFFF
DDR_0_SPACE_2 0xC000_0000 256MB 0xCFFF_FFFF
DDR_0_SPACE_1 0xB000_0000 256MB 0xBFFF_FFFF
DDR_0_SPACE_0 0xA000_0000 256MB 0xAFFF_FFFF
AHB2ENVM1_REGISTERS 0x600C_0000 256KB 0x600F_FFFF
AHB2ENVM0_REGISTERS 0x6008_0000 256KB 0x600B_FFFF
ENTIRE_ENVM 0x6000_0000 512KB 0x6007_FFFF
ENVM-eNVM 0x6000_0000 88KB 0x6001_62FF
CACHE_BACKDOOR 0x4040_0000 64KB 0x4040_FFFF
MAC 0x4004_1000 4KB 0x4004_1FFF
SYSREG 0x4003_8000 4KB 0x4003_8FFF
SERDES_IF2_0:APB_SLAVE 0x4002_8000 9KB 0x4002_A3FF
RTC 0x4001_7000 4KB 0x4001_7FFF
COMBLK 0x4001_6000 4KB 0x4001_6FFF
HDMA 0x4001_4000 4KB 0x4001_4FFF
GPIO 0x4001_3000 4KB 0x4001_3FFF
MMUART_1 0x4001_0000 4KB 0x4001_0FFF
H2FINTERRUPT 0x4000_6000 4KB 0x4000_6FFF
TIMER 0x4000_4000 4KB 0x4000_4FFF
SPI_0 0x4000_1000 4KB 0x4000_1FFF
RECYCLED_ESRAM1 0x2001_2000 8KB 0x2001_3FFF
RECYCLED_ESRAM0 0x2001_0000 8KB 0x2001_1FFF
ESRAM1 0x2000_8000 32KB 0x2000_FFFF
ESRAM0 0x2000_0000 32KB 0x2000_7FFF
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