@W: BN231 |Constraints on tristate nets currently not supported
@W: MO111 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\tsmac_top.v":285:0:285:13|Tristate driver CORETSE_AHBI00 on net CORETSE_AHBI00 has its enable tied to GND (module tsmac_top_Z9) 
@W: MO111 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\tsmac_top.v":283:0:283:13|Tristate driver CORETSE_AHBO00 on net CORETSE_AHBO00 has its enable tied to GND (module tsmac_top_Z9) 
@W: MO111 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\tsmac_top.v":281:0:281:13|Tristate driver CORETSE_AHBil0 on net CORETSE_AHBil0 has its enable tied to GND (module tsmac_top_Z9) 
@W: MO111 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\tsmac_top.v":279:0:279:13|Tristate driver CORETSE_AHBol0 on net CORETSE_AHBol0 has its enable tied to GND (module tsmac_top_Z9) 
@W: MO111 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\tsmac_top.v":277:0:277:13|Tristate driver CORETSE_AHBll0 on net CORETSE_AHBll0 has its enable tied to GND (module tsmac_top_Z9) 
@W: MO111 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\coretse_top.v":234:0:234:11|Tristate driver TSMAC_TXER_O on net TSMAC_TXER_O has its enable tied to GND (module CoreTSE_top_19s_1s_11s_12s_1s_1s_1s_18s) 
@W: MO111 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\coretse_top.v":231:0:231:11|Tristate driver TSMAC_TXEN_O on net TSMAC_TXEN_O has its enable tied to GND (module CoreTSE_top_19s_1s_11s_12s_1s_1s_1s_18s) 
@W: MO111 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\coretse_top.v":228:0:228:10|Tristate driver TSMAC_TXD_O_1 on net TSMAC_TXD_O_1 has its enable tied to GND (module CoreTSE_top_19s_1s_11s_12s_1s_1s_1s_18s) 
@W: MO111 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\coretse_top.v":228:0:228:10|Tristate driver TSMAC_TXD_O_2 on net TSMAC_TXD_O_2 has its enable tied to GND (module CoreTSE_top_19s_1s_11s_12s_1s_1s_1s_18s) 
@W: MO111 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\coretse_top.v":228:0:228:10|Tristate driver TSMAC_TXD_O_3 on net TSMAC_TXD_O_3 has its enable tied to GND (module CoreTSE_top_19s_1s_11s_12s_1s_1s_1s_18s) 
@W: MO111 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\coretse_top.v":228:0:228:10|Tristate driver TSMAC_TXD_O_4 on net TSMAC_TXD_O_4 has its enable tied to GND (module CoreTSE_top_19s_1s_11s_12s_1s_1s_1s_18s) 
@W: MO111 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\coretse_top.v":228:0:228:10|Tristate driver TSMAC_TXD_O_5 on net TSMAC_TXD_O_5 has its enable tied to GND (module CoreTSE_top_19s_1s_11s_12s_1s_1s_1s_18s) 
@W: MO111 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\coretse_top.v":228:0:228:10|Tristate driver TSMAC_TXD_O_6 on net TSMAC_TXD_O_6 has its enable tied to GND (module CoreTSE_top_19s_1s_11s_12s_1s_1s_1s_18s) 
@W: MO111 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\coretse_top.v":228:0:228:10|Tristate driver TSMAC_TXD_O_7 on net TSMAC_TXD_O_7 has its enable tied to GND (module CoreTSE_top_19s_1s_11s_12s_1s_1s_1s_18s) 
@W: MO111 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\coretse_top.v":228:0:228:10|Tristate driver TSMAC_TXD_O_8 on net TSMAC_TXD_O_8 has its enable tied to GND (module CoreTSE_top_19s_1s_11s_12s_1s_1s_1s_18s) 
@W: MO111 :"d:\cases\coretse\coretse_webserver\component\work\coretse_webserver\coretse_ahb_0\rtl\vlog\core_obfuscated\coretse_ahb.v":415:0:415:6|Tristate driver RXHLOCK on net RXHLOCK has its enable tied to GND (module CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s) 
@W: MO111 :"d:\cases\coretse\coretse_webserver\component\work\coretse_webserver\coretse_ahb_0\rtl\vlog\core_obfuscated\coretse_ahb.v":344:0:344:6|Tristate driver TXHLOCK on net TXHLOCK has its enable tied to GND (module CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s) 
@W: MO111 :|Tristate driver TXD_t[0] on net TXD[0] has its enable tied to GND (module CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s) 
@W: MO111 :|Tristate driver TXD_t[1] on net TXD[1] has its enable tied to GND (module CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s) 
@W: MO111 :|Tristate driver TXD_t[2] on net TXD[2] has its enable tied to GND (module CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s) 
@W: MO111 :|Tristate driver TXD_t[3] on net TXD[3] has its enable tied to GND (module CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s) 
@W: MO111 :|Tristate driver TXD_t[4] on net TXD[4] has its enable tied to GND (module CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s) 
@W: MO111 :|Tristate driver TXD_t[5] on net TXD[5] has its enable tied to GND (module CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s) 
@W: MO111 :|Tristate driver TXD_t[6] on net TXD[6] has its enable tied to GND (module CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s) 
@W: MO111 :|Tristate driver TXD_t[7] on net TXD[7] has its enable tied to GND (module CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s) 
@W: MO111 :|Tristate driver TXEN_t on net TXEN has its enable tied to GND (module CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s) 
@W: MO111 :|Tristate driver TXER_t on net TXER has its enable tied to GND (module CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s) 
@W: MO111 :"d:\cases\coretse\coretse_webserver\component\work\coretse_webserver\osc_0\coretse_webserver_osc_0_osc.v":20:7:20:16|Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module CoreTSE_Webserver_OSC_0_OSC) 
@W: MO111 :"d:\cases\coretse\coretse_webserver\component\work\coretse_webserver\osc_0\coretse_webserver_osc_0_osc.v":19:7:19:16|Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module CoreTSE_Webserver_OSC_0_OSC) 
@W: MO111 :"d:\cases\coretse\coretse_webserver\component\work\coretse_webserver\osc_0\coretse_webserver_osc_0_osc.v":18:7:18:20|Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module CoreTSE_Webserver_OSC_0_OSC) 
@W: MO111 :"d:\cases\coretse\coretse_webserver\component\work\coretse_webserver\osc_0\coretse_webserver_osc_0_osc.v":17:7:17:20|Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module CoreTSE_Webserver_OSC_0_OSC) 
@W: MO111 :"d:\cases\coretse\coretse_webserver\component\work\coretse_webserver\osc_0\coretse_webserver_osc_0_osc.v":15:7:15:24|Tristate driver RCOSC_25_50MHZ_CCC on net RCOSC_25_50MHZ_CCC has its enable tied to GND (module CoreTSE_Webserver_OSC_0_OSC) 
@W: MO111 :|Tristate driver CORETSE_AHB_0_AHBMTX_HLOCK_t on net CORETSE_AHB_0_AHBMTX_HLOCK has its enable tied to GND (module CoreTSE_Webserver) 
@W: MO111 :|Tristate driver CORETSE_AHB_0_AHBMRX_HLOCK_t on net CORETSE_AHB_0_AHBMRX_HLOCK has its enable tied to GND (module CoreTSE_Webserver) 
@W: MO171 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance CoreResetP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance CoreResetP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sequential instance CoreResetP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\msgmii_clkrst.v":354:0:354:5|Sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0.CORETSE_AHBOi0.CORETSE_AHBo1i0.CORETSE_AHBoO1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\msgmii_clkrst.v":328:0:328:5|Sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0.CORETSE_AHBOi0.CORETSE_AHBo1i0.CORETSE_AHBl010 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\msgmii_clkrst.v":315:0:315:5|Sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0.CORETSE_AHBOi0.CORETSE_AHBo1i0.CORETSE_AHBI010 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\pemstat_cntrl.v":406:0:406:5|Sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBlO0i reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\pecar.v":872:0:872:5|Sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBlOIo.CORETSE_AHBO10o reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\pecar.v":886:0:886:5|Sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBlOIo.CORETSE_AHBI10o reduced to a combinational gate by constant propagation 
@W: BN132 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Removing sequential instance CoreResetP_0.sdif3_spll_lock_q1,  because it is equivalent to instance CoreResetP_0.sdif0_spll_lock_q1
@W: BN132 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Removing sequential instance CoreResetP_0.sdif3_spll_lock_q2,  because it is equivalent to instance CoreResetP_0.sdif0_spll_lock_q2
@W: MT462 :"d:\cases\coretse\coretse_webserver\component\work\coretse_webserver\serdes_if2_0\coretse_webserver_serdes_if2_0_serdes_if2.v":98:15:98:32|Net SERDES_IF2_0.REFCLK1_OUT appears to be an unidentified clock source. Assuming default frequency. 
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_2.regHADDR[1] is always 0, optimizing ...
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_2.regHADDR[0] is always 0, optimizing ...
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[16] is always 0, optimizing ...
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_1.SDATASELInt[16] is always 0, optimizing ...
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_1.regHSIZE[0] is always 0, optimizing ...
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_1.regHADDR[1] is always 0, optimizing ...
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_1.regHADDR[0] is always 0, optimizing ...
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_2.SDATASELInt[16] is always 0, optimizing ...
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_2.regHSIZE[0] is always 0, optimizing ...
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_1.regHMASTLOCK is always 0, optimizing ...
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_2.regHMASTLOCK is always 0, optimizing ...
@W: BN132 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing instance CoreAHBLite_0.matrix4x16.masterstage_1.regHSIZE[1],  because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_1.regHTRANS
@W: BN132 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing instance CoreAHBLite_0.matrix4x16.masterstage_2.regHSIZE[1],  because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_2.regHTRANS
@W: BN132 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing instance CoreAHBLite_0.matrix4x16.masterstage_2.regHADDR[31],  because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_2.regHADDR[30]
@W: BN132 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing instance CoreAHBLite_0.matrix4x16.masterstage_2.regHADDR[30],  because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_2.regHADDR[28]
@W: BN132 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[31],  because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[30]
@W: BN132 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing instance CoreAHBLite_0.matrix4x16.masterstage_1.regHADDR[31],  because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_1.regHADDR[30]
@W: BN132 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing instance CoreAHBLite_0.matrix4x16.masterstage_1.regHADDR[30],  because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_1.regHADDR[28]
@W: BN132 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[29],  because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28]
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[15] is always 0, optimizing ...
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[12] is always 0, optimizing ...
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[3] is always 0, optimizing ...
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[0] is always 0, optimizing ...
@W: MO197 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|FSM register arbRegSMCurrentState[14] removed due to constant propagation
@W: MO197 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|FSM register arbRegSMCurrentState[2] removed due to constant propagation
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[1] is always 0, optimizing ...
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[12] is always 0, optimizing ...
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[8] is always 0, optimizing ...
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[4] is always 0, optimizing ...
@W: FX107 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\rx4096x36.v":131:0:131:5|No read/write conflict check. Possible simulation mismatch!
@W: FX107 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\tx2048x40.v":131:0:131:5|No read/write conflict check. Possible simulation mismatch!
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\pemstat_eim.v":1931:0:1931:5|Register bit CORETSE_AHBo1li.CORETSE_AHBl00i[30] is always 0, optimizing ...
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\pemstat_eim.v":1931:0:1931:5|Register bit CORETSE_AHBo1li.CORETSE_AHBl00i[29] is always 0, optimizing ...
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\pemstat_eim.v":1931:0:1931:5|Register bit CORETSE_AHBo1li.CORETSE_AHBl00i[28] is always 0, optimizing ...
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\pemstat_eim.v":1931:0:1931:5|Register bit CORETSE_AHBo1li.CORETSE_AHBl00i[27] is always 0, optimizing ...
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\pemstat_eim.v":1931:0:1931:5|Register bit CORETSE_AHBo1li.CORETSE_AHBl00i[26] is always 0, optimizing ...
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\pemstat_eim.v":1931:0:1931:5|Register bit CORETSE_AHBo1li.CORETSE_AHBl00i[25] is always 0, optimizing ...
@W: MO160 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\pemstat_eim.v":1931:0:1931:5|Register bit CORETSE_AHBo1li.CORETSE_AHBl00i[24] is always 0, optimizing ...
@W: MO129 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\pemstat_cntrl.v":2167:0:2167:5|Sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBIIIi[36] reduced to a combinational gate by constant propagation
@W: MO129 :"d:\cases\coretse\coretse_webserver\component\actel\directcore\coretse_ahb\2.1.105\rtl\vlog\core_obfuscated\pemstat_cntrl.v":2167:0:2167:5|Sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBIIIi[37] reduced to a combinational gate by constant propagation
@W: MT462 :"d:\cases\coretse\coretse_webserver\component\work\coretse_webserver\serdes_if2_0\coretse_webserver_serdes_if2_0_serdes_if2.v":98:15:98:32|Net SERDES_IF2_0.REFCLK1_OUT appears to be an unidentified clock source. Assuming default frequency. 
@W: MT462 :"d:\cases\coretse\coretse_webserver\component\work\coretse_webserver\serdes_if2_0\coretse_webserver_serdes_if2_0_serdes_if2.v":98:15:98:32|Net SERDES_IF2_0.REFCLK1_OUT appears to be an unidentified clock source. Assuming default frequency. 
@W: MT246 :"d:\cases\coretse\coretse_webserver\component\work\coretse_webserver\fccc_3\coretse_webserver_fccc_3_fccc.v":37:36:37:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock pemgt|CORETSE_AHBi01_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBooOo.CORETSE_AHBi01"
@W: MT447 :"d:/cases/coretse/coretse_webserver/designer/coretse_webserver/synthesis.fdc":20:0:20:0|Timing constraint (from [get_cells { CoreResetP_0.MSS_HPMS_READY_int }] to [get_cells { CoreResetP_0.sm0_areset_n_rcosc CoreResetP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"d:/cases/coretse/coretse_webserver/designer/coretse_webserver/synthesis.fdc":21:0:21:0|Timing constraint (from [get_cells { CoreResetP_0.MSS_HPMS_READY_int CoreResetP_0.SDIF*_PERST_N_re }] to [get_cells { CoreResetP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT443 :"d:/cases/coretse/coretse_webserver/designer/coretse_webserver/synthesis.fdc":23:0:23:0|Timing constraint (through [get_nets { CoreConfigP_0.FIC_2_APB_M_PSEL CoreConfigP_0.FIC_2_APB_M_PENABLE }] to [get_cells { CoreConfigP_0.FIC_2_APB_M_PREADY* CoreConfigP_0.state[0] }]) (max delay 0.000000) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"d:/cases/coretse/coretse_webserver/designer/coretse_webserver/synthesis.fdc":20:0:20:0|Timing constraint (from [get_cells { CoreResetP_0.MSS_HPMS_READY_int }] to [get_cells { CoreResetP_0.sm0_areset_n_rcosc CoreResetP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"d:/cases/coretse/coretse_webserver/designer/coretse_webserver/synthesis.fdc":21:0:21:0|Timing constraint (from [get_cells { CoreResetP_0.MSS_HPMS_READY_int CoreResetP_0.SDIF*_PERST_N_re }] to [get_cells { CoreResetP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT445 :"d:/cases/coretse/coretse_webserver/designer/coretse_webserver/synthesis.fdc":24:0:24:0|Timing constraint (through [get_nets { CoreConfigP_0.FIC_2_APB_M_PWRITE CoreConfigP_0.FIC_2_APB_M_PADDR[*] CoreConfigP_0.FIC_2_APB_M_PWDATA[*] CoreConfigP_0.FIC_2_APB_M_PSEL CoreConfigP_0.FIC_2_APB_M_PENABLE }]) (min delay -24.000000) was not applied to the design because none of the paths specified by the constraint exist in the design 
