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<doc>
<title>Timing Report Min Delay Analysis
</title>
<text>SmartTime Version 11.7.2.2</text>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.7 SP2 (Version 11.7.2.2)</text>
<text>Date: Thu Nov 17 15:36:41 2016
</text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>CoreTSE_Webserver</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2S090TS</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>484 FBGA</cell>
</row>
<row>
 <cell>Temperature Range</cell>
 <cell>0 - 85 C</cell>
</row>
<row>
 <cell>Voltage Range</cell>
 <cell>1.14 - 1.26 V</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Design State</cell>
 <cell>Post-Layout</cell>
</row>
<row>
 <cell>Data source</cell>
 <cell>Production</cell>
</row>
<row>
 <cell>Min Operating Conditions</cell>
 <cell>BEST - 1.26 V - 0 C</cell>
</row>
<row>
 <cell>Max Operating Conditions</cell>
 <cell>WORST - 1.14 V - 85 C</cell>
</row>
<row>
 <cell>Scenario for Timing Analysis</cell>
 <cell>timing_analysis</cell>
</row>
</table>
<text></text>
<section>
<name>Summary</name>
<table>
<header>
 <cell>Clock Domain</cell>
 <cell>Period (ns)</cell>
 <cell>Frequency (MHz)</cell>
 <cell>Required Period (ns)</cell>
 <cell>Required Frequency (MHz)</cell>
 <cell>External Setup (ns)</cell>
 <cell>External Hold (ns)</cell>
 <cell>Min Clock-To-Out (ns)</cell>
 <cell>Max Clock-To-Out (ns)</cell>
</header>
<row>
 <cell>CLK1_PAD</cell>
 <cell>1.600</cell>
 <cell>625.000</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBi01:Q</cell>
 <cell>6.554</cell>
 <cell>152.579</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>FCCC_0/GL0</cell>
 <cell>11.896</cell>
 <cell>84.062</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>3.835</cell>
 <cell>-1.646</cell>
 <cell>5.719</cell>
 <cell>15.545</cell>
</row>
<row>
 <cell>FCCC_1/GL0</cell>
 <cell>7.178</cell>
 <cell>139.315</cell>
 <cell>16.000</cell>
 <cell>62.500</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>FCCC_1/GL1</cell>
 <cell>2.262</cell>
 <cell>442.087</cell>
 <cell>16.000</cell>
 <cell>62.500</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>FCCC_2/GL0</cell>
 <cell>4.525</cell>
 <cell>220.994</cell>
 <cell>8.000</cell>
 <cell>125.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>FCCC_3/GL0</cell>
 <cell>2.516</cell>
 <cell>397.456</cell>
 <cell>8.000</cell>
 <cell>125.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ/CLKOUT</cell>
 <cell>2.869</cell>
 <cell>348.554</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB</cell>
 <cell>18.064</cell>
 <cell>55.359</cell>
 <cell>80.000</cell>
 <cell>12.500</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1]</cell>
 <cell>1.818</cell>
 <cell>550.055</cell>
 <cell>8.000</cell>
 <cell>125.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]</cell>
 <cell>1.142</cell>
 <cell>875.657</cell>
 <cell>8.000</cell>
 <cell>125.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>FCCC_3/GL1</cell>
 <cell>2.516</cell>
 <cell>397.456</cell>
 <cell>8.000</cell>
 <cell>125.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
<text></text>
<table>
<header>
 <cell></cell>
 <cell>Min Delay (ns)</cell>
 <cell>Max Delay (ns)</cell>
</header>
<row>
 <cell>Input to Output</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
</section>
<section>
<name>Clock Domain CLK1_PAD</name>
<text>Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin FCCC_0/CLK1_PAD_INST/U_IOPAD:PAD</text>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBi01:Q</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBI011/CORETSE_AHBiiOII:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBI011/CORETSE_AHBIo01:D</cell>
 <cell>0.280</cell>
 <cell></cell>
 <cell>2.830</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBI011/CORETSE_AHBliOII:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBI011/CORETSE_AHBoiOII:D</cell>
 <cell>0.313</cell>
 <cell></cell>
 <cell>2.863</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBI011/CORETSE_AHBi1OII[0]:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBI011/CORETSE_AHBi1OII[1]:D</cell>
 <cell>0.322</cell>
 <cell></cell>
 <cell>2.861</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBI011/CORETSE_AHBIiOII[2]:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBI011/CORETSE_AHBIlO1[2]:D</cell>
 <cell>0.323</cell>
 <cell></cell>
 <cell>2.862</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBI011/CORETSE_AHBIiOII[4]:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBI011/CORETSE_AHBIlO1[4]:D</cell>
 <cell>0.325</cell>
 <cell></cell>
 <cell>2.864</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBI011/CORETSE_AHBiiOII:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBI011/CORETSE_AHBIo01:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.830</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBi01:Q</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBi01:Q</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBi01_inferred_clock_RNIGRJ9:An</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI_inst_1/CORETSE_AHBooOo/CORETSE_AHBi01</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.423</cell>
 <cell>1.423</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBi01_inferred_clock_RNIGRJ9:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.223</cell>
 <cell>1.646</cell>
 <cell>7</cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI_inst_1/CORETSE_AHBooOo/CORETSE_AHBi01_inferred_clock_RNIGRJ9/U0_RGB1_RGB3:An</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI_inst_1/CORETSE_AHBooOo/CORETSE_AHBi01_inferred_clock_RNIGRJ9/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.386</cell>
 <cell>2.032</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI_inst_1/CORETSE_AHBooOo/CORETSE_AHBi01_inferred_clock_RNIGRJ9/U0_RGB1_RGB3:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>2.222</cell>
 <cell>28</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBI011/CORETSE_AHBiiOII:CLK</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI_inst_1/CORETSE_AHBooOo/CORETSE_AHBi01_inferred_clock_RNIGRJ9/U0_RGB1_RGB3_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.328</cell>
 <cell>2.550</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBI011/CORETSE_AHBiiOII:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.052</cell>
 <cell>2.602</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBI011/CORETSE_AHBIo01:D</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBI011/CORETSE_AHBiiOII</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.228</cell>
 <cell>2.830</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.830</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBi01:Q</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBi01:Q</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBi01_inferred_clock_RNIGRJ9:An</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI_inst_1/CORETSE_AHBooOo/CORETSE_AHBi01</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.423</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBi01_inferred_clock_RNIGRJ9:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.223</cell>
 <cell>N/C</cell>
 <cell>7</cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI_inst_1/CORETSE_AHBooOo/CORETSE_AHBi01_inferred_clock_RNIGRJ9/U0_RGB1_RGB3:An</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI_inst_1/CORETSE_AHBooOo/CORETSE_AHBi01_inferred_clock_RNIGRJ9/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.386</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI_inst_1/CORETSE_AHBooOo/CORETSE_AHBi01_inferred_clock_RNIGRJ9/U0_RGB1_RGB3:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>N/C</cell>
 <cell>28</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBI011/CORETSE_AHBIo01:CLK</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI_inst_1/CORETSE_AHBooOo/CORETSE_AHBi01_inferred_clock_RNIGRJ9/U0_RGB1_RGB3_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.377</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBI011/CORETSE_AHBIo01:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain FCCC_0/GL0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBilOi:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBI0Oi:D</cell>
 <cell>0.278</cell>
 <cell>0.231</cell>
 <cell>3.235</cell>
 <cell>3.004</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CoreResetP_0/SDIF3_PERST_N_q1:CLK</cell>
 <cell>CoreResetP_0/SDIF3_PERST_N_q2:D</cell>
 <cell>0.280</cell>
 <cell>0.231</cell>
 <cell>3.264</cell>
 <cell>3.033</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBIOooI/CORETSE_AHBOil0/CORETSE_AHBOl0oI[0]:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBIOooI/CORETSE_AHBOil0/CORETSE_AHBOl0oI[1]:D</cell>
 <cell>0.274</cell>
 <cell>0.231</cell>
 <cell>3.250</cell>
 <cell>3.019</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBoOooI/CORETSE_AHBI1II/CORETSE_AHBl10I:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBoOooI/CORETSE_AHBI1II/CORETSE_AHBI10I:D</cell>
 <cell>0.286</cell>
 <cell>0.233</cell>
 <cell>3.238</cell>
 <cell>3.005</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBoOooI/CORETSE_AHBi0II/CORETSE_AHBI1oI:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBoOooI/CORETSE_AHBi0II/CORETSE_AHBl1oI:D</cell>
 <cell>0.287</cell>
 <cell>0.234</cell>
 <cell>3.242</cell>
 <cell>3.008</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBilOi:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBI0Oi:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.235</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.004</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.231</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.867</cell>
 <cell>1.867</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>1.987</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>2.093</cell>
 <cell>31</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB15:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.364</cell>
 <cell>2.457</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB15:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>2.648</cell>
 <cell>23</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBilOi:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB15_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.309</cell>
 <cell>2.957</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBilOi:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.052</cell>
 <cell>3.009</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBI0Oi:D</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI_inst_1/CORETSE_AHBooOo/CORETSE_AHBilOi</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.226</cell>
 <cell>3.235</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.235</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.867</cell>
 <cell>1.867</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>1.987</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>2.093</cell>
 <cell>31</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB15:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.364</cell>
 <cell>2.457</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB15:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>2.648</cell>
 <cell>23</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBI0Oi:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB15_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.356</cell>
 <cell>3.004</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBI0Oi:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.004</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.004</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
 <cell>External Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>PHY_MDIO</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBIIOi[0]:D</cell>
 <cell>4.755</cell>
 <cell></cell>
 <cell>4.755</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>-1.646</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: PHY_MDIO</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBIIOi[0]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.755</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PHY_MDIO</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>BIBUF_0/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>PHY_MDIO</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>BIBUF_0/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_BI</cell>
 <cell>+</cell>
 <cell>1.415</cell>
 <cell>1.415</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>BIBUF_0/U0/U_IOINFF:A</cell>
 <cell>net</cell>
 <cell>BIBUF_0/U0/YIN1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>1.415</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>BIBUF_0/U0/U_IOINFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOINFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.050</cell>
 <cell>1.465</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBOIOi_0_a2[0]:C</cell>
 <cell>net</cell>
 <cell>BIBUF_0_Y</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.797</cell>
 <cell>3.262</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBOIOi_0_a2[0]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.101</cell>
 <cell>3.363</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBOIOi_0[0]:D</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI_inst_1/CORETSE_AHBooOo/N_808</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.226</cell>
 <cell>4.589</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBOIOi_0[0]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.121</cell>
 <cell>4.710</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBIIOi[0]:D</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI_inst_1/CORETSE_AHBooOo/CORETSE_AHBOIOi[0]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.045</cell>
 <cell>4.755</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.755</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.867</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.137</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.122</cell>
 <cell>N/C</cell>
 <cell>31</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB13:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.419</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB13:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.219</cell>
 <cell>N/C</cell>
 <cell>45</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBIIOi[0]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB13_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.345</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBIIOi[0]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Clock to Output</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Clock to Out (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CoreTSE_Webserver_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>MMUART_1_TXD</cell>
 <cell>2.641</cell>
 <cell></cell>
 <cell>5.719</cell>
 <cell></cell>
 <cell>5.719</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CoreTSE_Webserver_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>SPI_0_DO</cell>
 <cell>3.162</cell>
 <cell></cell>
 <cell>6.240</cell>
 <cell></cell>
 <cell>6.240</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CoreTSE_Webserver_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>SPI_1_DO</cell>
 <cell>3.647</cell>
 <cell></cell>
 <cell>6.725</cell>
 <cell></cell>
 <cell>6.725</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBi01:CLK</cell>
 <cell>PHY_MDC</cell>
 <cell>4.359</cell>
 <cell></cell>
 <cell>7.308</cell>
 <cell></cell>
 <cell>7.308</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBooOo/CORETSE_AHBO11:CLK</cell>
 <cell>PHY_MDIO</cell>
 <cell>4.647</cell>
 <cell></cell>
 <cell>7.594</cell>
 <cell></cell>
 <cell>7.594</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CoreTSE_Webserver_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MMUART_1_TXD</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.719</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.867</cell>
 <cell>1.867</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>1.987</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>2.093</cell>
 <cell>31</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.370</cell>
 <cell>2.463</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>2.653</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreTSE_Webserver_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.245</cell>
 <cell>2.898</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreTSE_Webserver_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.126</cell>
 <cell>3.024</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreTSE_Webserver_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>CoreTSE_Webserver_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.054</cell>
 <cell>3.078</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreTSE_Webserver_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MSS_075_IP</cell>
 <cell>+</cell>
 <cell>1.207</cell>
 <cell>4.285</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreTSE_Webserver_MSS_0/MMUART_1_TXD_PAD/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>CoreTSE_Webserver_MSS_0/MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>4.285</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreTSE_Webserver_MSS_0/MMUART_1_TXD_PAD/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>1.434</cell>
 <cell>5.719</cell>
 <cell>0</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MMUART_1_TXD</cell>
 <cell>net</cell>
 <cell>MMUART_1_TXD</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>5.719</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.719</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.867</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MMUART_1_TXD</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CoreResetP_0/sdif0_areset_n_clk_base:CLK</cell>
 <cell>CoreResetP_0/count_sdif0_enable:ALn</cell>
 <cell>0.482</cell>
 <cell>0.406</cell>
 <cell>3.438</cell>
 <cell>3.032</cell>
 <cell>0.000</cell>
 <cell>-0.076</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CoreResetP_0/sdif0_areset_n_clk_base:CLK</cell>
 <cell>CoreResetP_0/sdif0_state[0]:ALn</cell>
 <cell>0.482</cell>
 <cell>0.406</cell>
 <cell>3.438</cell>
 <cell>3.032</cell>
 <cell>0.000</cell>
 <cell>-0.076</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CoreResetP_0/sdif0_areset_n_clk_base:CLK</cell>
 <cell>CoreResetP_0/SDIF0_PHY_RESET_N_int:ALn</cell>
 <cell>0.482</cell>
 <cell>0.414</cell>
 <cell>3.438</cell>
 <cell>3.024</cell>
 <cell>0.000</cell>
 <cell>-0.068</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CoreResetP_0/sdif0_areset_n_clk_base:CLK</cell>
 <cell>CoreResetP_0/sdif0_state[1]:ALn</cell>
 <cell>0.482</cell>
 <cell>0.415</cell>
 <cell>3.438</cell>
 <cell>3.023</cell>
 <cell>0.000</cell>
 <cell>-0.067</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CoreResetP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>CoreResetP_0/mss_ready_state:ALn</cell>
 <cell>0.552</cell>
 <cell>0.485</cell>
 <cell>3.495</cell>
 <cell>3.010</cell>
 <cell>0.000</cell>
 <cell>-0.067</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CoreResetP_0/sdif0_areset_n_clk_base:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CoreResetP_0/count_sdif0_enable:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.438</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.032</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.406</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.867</cell>
 <cell>1.867</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>1.987</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>2.093</cell>
 <cell>31</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB26:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.372</cell>
 <cell>2.465</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB26:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>2.656</cell>
 <cell>16</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/sdif0_areset_n_clk_base:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB26_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.300</cell>
 <cell>2.956</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/sdif0_areset_n_clk_base:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.052</cell>
 <cell>3.008</cell>
 <cell>4</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/count_sdif0_enable:ALn</cell>
 <cell>net</cell>
 <cell>CoreResetP_0/sdif0_areset_n_clk_base</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.430</cell>
 <cell>3.438</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.438</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.867</cell>
 <cell>1.867</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>1.987</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>2.093</cell>
 <cell>31</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB27:An</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.372</cell>
 <cell>2.465</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB27:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>2.656</cell>
 <cell>29</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/count_sdif0_enable:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_0/GL0_INST/U0_RGB1_RGB27_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.376</cell>
 <cell>3.032</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/count_sdif0_enable:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.032</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.032</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET OSC_0/I_RCOSC_25_50MHZ/CLKOUT to FCCC_0/GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB to FCCC_0/GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_3/GL0 to FCCC_0/GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_3/GL1 to FCCC_0/GL0</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain FCCC_1/GL0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBIOlII:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBlOlII:D</cell>
 <cell>0.274</cell>
 <cell>0.229</cell>
 <cell>2.807</cell>
 <cell>2.578</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI[14]:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBoOlOI[14]:D</cell>
 <cell>0.287</cell>
 <cell>0.232</cell>
 <cell>2.830</cell>
 <cell>2.598</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI[10]:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBoOlOI[10]:D</cell>
 <cell>0.280</cell>
 <cell>0.233</cell>
 <cell>2.830</cell>
 <cell>2.597</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI[11]:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBoOlOI[11]:D</cell>
 <cell>0.290</cell>
 <cell>0.234</cell>
 <cell>2.832</cell>
 <cell>2.598</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI[9]:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBoOlOI[9]:D</cell>
 <cell>0.290</cell>
 <cell>0.237</cell>
 <cell>2.834</cell>
 <cell>2.597</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBIOlII:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBlOlII:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.807</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>2.578</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.229</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.443</cell>
 <cell>1.443</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>1.563</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>1.669</cell>
 <cell>20</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB14:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.369</cell>
 <cell>2.038</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB14:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>2.228</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBIOlII:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB14_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.305</cell>
 <cell>2.533</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBIOlII:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.055</cell>
 <cell>2.588</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBlOlII:D</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011_inst_1/CORETSE_AHBIOlII</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.219</cell>
 <cell>2.807</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.807</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.443</cell>
 <cell>1.443</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>1.563</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>1.669</cell>
 <cell>20</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB14:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.369</cell>
 <cell>2.038</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB14:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>2.228</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBlOlII:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB14_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.350</cell>
 <cell>2.578</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBlOlII:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.578</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.578</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBlOlII:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBolo0[8]:ALn</cell>
 <cell>2.223</cell>
 <cell>2.145</cell>
 <cell>4.756</cell>
 <cell>2.611</cell>
 <cell>0.000</cell>
 <cell>-0.078</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBlOlII:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBOi10[9]:ALn</cell>
 <cell>2.227</cell>
 <cell>2.145</cell>
 <cell>4.760</cell>
 <cell>2.615</cell>
 <cell>0.000</cell>
 <cell>-0.082</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBlOlII:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBolo0[6]:ALn</cell>
 <cell>2.223</cell>
 <cell>2.145</cell>
 <cell>4.756</cell>
 <cell>2.611</cell>
 <cell>0.000</cell>
 <cell>-0.078</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBlOlII:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBOIo0[6]:ALn</cell>
 <cell>2.223</cell>
 <cell>2.145</cell>
 <cell>4.756</cell>
 <cell>2.611</cell>
 <cell>0.000</cell>
 <cell>-0.078</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBlOlII:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBolo0[2]:ALn</cell>
 <cell>2.227</cell>
 <cell>2.145</cell>
 <cell>4.760</cell>
 <cell>2.615</cell>
 <cell>0.000</cell>
 <cell>-0.082</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBlOlII:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBolo0[8]:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.756</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>2.611</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.145</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.443</cell>
 <cell>1.443</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>1.563</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>1.669</cell>
 <cell>20</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB14:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.369</cell>
 <cell>2.038</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB14:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>2.228</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBlOlII:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB14_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.305</cell>
 <cell>2.533</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBlOlII:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.065</cell>
 <cell>2.598</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBoOlII:C</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011_inst_1/CORETSE_AHBlOlII</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.030</cell>
 <cell>2.628</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBoOlII:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.186</cell>
 <cell>2.814</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBoOlII_RNIPHQF:An</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011_inst_1/CORETSE_AHBoOlII</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.824</cell>
 <cell>3.638</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBoOlII_RNIPHQF:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.223</cell>
 <cell>3.861</cell>
 <cell>19</cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011_inst_1/CORETSE_AHBoOlII_RNIPHQF/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011_inst_1/CORETSE_AHBoOlII_RNIPHQF/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.366</cell>
 <cell>4.227</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011_inst_1/CORETSE_AHBoOlII_RNIPHQF/U0_RGB1_RGB2:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>4.417</cell>
 <cell>48</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBolo0[8]:ALn</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011_inst_1/CORETSE_AHBoOlII_RNIPHQF/U0_RGB1_RGB2_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.339</cell>
 <cell>4.756</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.756</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.443</cell>
 <cell>1.443</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>1.563</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>1.669</cell>
 <cell>20</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.371</cell>
 <cell>2.040</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB2:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>2.230</cell>
 <cell>48</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBolo0[8]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB2_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.381</cell>
 <cell>2.611</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBolo0[8]:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.611</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.611</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_0/GL0 to FCCC_1/GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] to FCCC_1/GL0</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI[19]:D</cell>
 <cell>2.725</cell>
 <cell>0.128</cell>
 <cell>2.725</cell>
 <cell>2.597</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI[15]:D</cell>
 <cell>2.753</cell>
 <cell>0.162</cell>
 <cell>2.753</cell>
 <cell>2.591</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI[14]:D</cell>
 <cell>2.758</cell>
 <cell>0.168</cell>
 <cell>2.758</cell>
 <cell>2.590</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI[18]:D</cell>
 <cell>2.763</cell>
 <cell>0.172</cell>
 <cell>2.763</cell>
 <cell>2.591</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI[11]:D</cell>
 <cell>2.820</cell>
 <cell>0.231</cell>
 <cell>2.820</cell>
 <cell>2.589</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI[19]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.725</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>2.597</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.128</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXDATA[39]</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SERDESIF_075_IP</cell>
 <cell>+</cell>
 <cell>-0.148</cell>
 <cell>-0.148</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI_5[19]_CFG1C_TEST0:A</cell>
 <cell>net</cell>
 <cell>SERDES_IF2_0_EPCS_3_RX_DATA[9]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.333</cell>
 <cell>2.185</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI_5[19]_CFG1C_TEST0:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1C_TEST</cell>
 <cell>+</cell>
 <cell>0.125</cell>
 <cell>2.310</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI_5[19]_CFG1C_TEST:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI_5[19]_CFG1C_TEST_net0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.135</cell>
 <cell>2.445</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI_5[19]_CFG1C_TEST:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1C_TEST</cell>
 <cell>+</cell>
 <cell>0.125</cell>
 <cell>2.570</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI_5[19]:B</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI_5[19]_CFG1C_TEST_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.057</cell>
 <cell>2.627</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI_5[19]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.052</cell>
 <cell>2.679</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI[19]:D</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI_5[19]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.046</cell>
 <cell>2.725</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.725</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.443</cell>
 <cell>1.443</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>1.563</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>1.669</cell>
 <cell>20</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB19:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.371</cell>
 <cell>2.040</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB19:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>2.230</cell>
 <cell>28</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI[19]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB19_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.367</cell>
 <cell>2.597</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI[19]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.597</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.597</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET FCCC_1/GL1 to FCCC_1/GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_2/GL0 to FCCC_1/GL0</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBO011/CORETSE_AHBioO1[0]:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBil11/CORETSE_AHBoIoi[0]:D</cell>
 <cell>0.479</cell>
 <cell>2.351</cell>
 <cell>4.956</cell>
 <cell>2.605</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBO011/CORETSE_AHBioO1[1]:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBil11/CORETSE_AHBoIoi[1]:D</cell>
 <cell>0.485</cell>
 <cell>2.378</cell>
 <cell>4.962</cell>
 <cell>2.584</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBiI11/CORETSE_AHBlI1II[8]:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI[18]:D</cell>
 <cell>0.822</cell>
 <cell>2.703</cell>
 <cell>5.294</cell>
 <cell>2.591</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBiI11/CORETSE_AHBlI1II[6]:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI[16]:D</cell>
 <cell>0.830</cell>
 <cell>2.718</cell>
 <cell>5.309</cell>
 <cell>2.591</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBiI11/CORETSE_AHBlI1II[4]:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI[14]:D</cell>
 <cell>0.936</cell>
 <cell>2.820</cell>
 <cell>5.410</cell>
 <cell>2.590</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBO011/CORETSE_AHBioO1[0]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBil11/CORETSE_AHBoIoi[0]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.956</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>2.605</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.351</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.378</cell>
 <cell>3.378</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>3.498</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>3.604</cell>
 <cell>16</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.375</cell>
 <cell>3.979</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB2:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>4.169</cell>
 <cell>7</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBO011/CORETSE_AHBioO1[0]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB2_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.308</cell>
 <cell>4.477</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBO011/CORETSE_AHBioO1[0]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.064</cell>
 <cell>4.541</cell>
 <cell>14</cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBil11/CORETSE_AHBoIoi[0]:D</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBioO1[0]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.415</cell>
 <cell>4.956</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.956</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.443</cell>
 <cell>1.443</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>1.563</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>1.669</cell>
 <cell>20</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB8:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.368</cell>
 <cell>2.037</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB8:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>2.227</cell>
 <cell>24</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBil11/CORETSE_AHBoIoi[0]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL0_INST/U0_RGB1_RGB8_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.378</cell>
 <cell>2.605</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBil11/CORETSE_AHBoIoi[0]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.605</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.605</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Clock Domain FCCC_1/GL1</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBoiIII:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBiiIII:D</cell>
 <cell>0.290</cell>
 <cell>0.245</cell>
 <cell>2.827</cell>
 <cell>2.582</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBoiIII:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBiiIII:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.827</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>2.582</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.245</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL1</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/CCC_INST/INST_CCC_IP:GL1</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.459</cell>
 <cell>1.459</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL1_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL1_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>1.579</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_1/GL1_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>1.685</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL1_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL1_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.356</cell>
 <cell>2.041</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL1_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>2.231</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBoiIII:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL1_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.306</cell>
 <cell>2.537</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBoiIII:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.052</cell>
 <cell>2.589</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBiiIII:D</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011_inst_1/CORETSE_AHBoiIII</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.238</cell>
 <cell>2.827</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.827</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL1</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/CCC_INST/INST_CCC_IP:GL1</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.459</cell>
 <cell>1.459</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL1_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL1_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>1.579</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_1/GL1_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>1.685</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL1_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL1_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.356</cell>
 <cell>2.041</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL1_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>2.231</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBiiIII:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL1_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.351</cell>
 <cell>2.582</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBiiIII:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.582</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.582</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBiiIII:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[8]:ALn</cell>
 <cell>0.786</cell>
 <cell>0.735</cell>
 <cell>3.323</cell>
 <cell>2.588</cell>
 <cell>0.000</cell>
 <cell>-0.051</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBiiIII:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[9]:ALn</cell>
 <cell>0.787</cell>
 <cell>0.736</cell>
 <cell>3.324</cell>
 <cell>2.588</cell>
 <cell>0.000</cell>
 <cell>-0.051</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBiiIII:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[6]:ALn</cell>
 <cell>0.786</cell>
 <cell>0.741</cell>
 <cell>3.323</cell>
 <cell>2.582</cell>
 <cell>0.000</cell>
 <cell>-0.045</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBiiIII:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[1]:ALn</cell>
 <cell>0.842</cell>
 <cell>0.790</cell>
 <cell>3.379</cell>
 <cell>2.589</cell>
 <cell>0.000</cell>
 <cell>-0.052</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBiiIII:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[7]:ALn</cell>
 <cell>0.842</cell>
 <cell>0.790</cell>
 <cell>3.379</cell>
 <cell>2.589</cell>
 <cell>0.000</cell>
 <cell>-0.052</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBiiIII:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[8]:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.323</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>2.588</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.735</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL1</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/CCC_INST/INST_CCC_IP:GL1</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.459</cell>
 <cell>1.459</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL1_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL1_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>1.579</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_1/GL1_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>1.685</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL1_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL1_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.356</cell>
 <cell>2.041</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL1_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>2.231</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBiiIII:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL1_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.306</cell>
 <cell>2.537</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBiiIII:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.064</cell>
 <cell>2.601</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBOOlII:C</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011_inst_1/CORETSE_AHBiiIII</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.031</cell>
 <cell>2.632</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBi011/CORETSE_AHBOOlII:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.189</cell>
 <cell>2.821</cell>
 <cell>10</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[8]:ALn</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBOOlII_i</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.502</cell>
 <cell>3.323</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.323</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL1</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/CCC_INST/INST_CCC_IP:GL1</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.459</cell>
 <cell>1.459</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL1_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL1_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>1.579</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_1/GL1_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>1.685</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL1_INST/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL1_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.362</cell>
 <cell>2.047</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL1_INST/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>2.237</cell>
 <cell>6</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[8]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL1_INST/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.351</cell>
 <cell>2.588</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[8]:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.588</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.588</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_0/GL0 to FCCC_1/GL1</name>
<text>No Path</text>
</section>
<section>
<name>SET SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] to FCCC_1/GL1</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[8]:D</cell>
 <cell>2.838</cell>
 <cell>0.250</cell>
 <cell>2.838</cell>
 <cell>2.588</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[9]:D</cell>
 <cell>2.857</cell>
 <cell>0.269</cell>
 <cell>2.857</cell>
 <cell>2.588</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[3]:D</cell>
 <cell>2.887</cell>
 <cell>0.296</cell>
 <cell>2.887</cell>
 <cell>2.591</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[4]:D</cell>
 <cell>2.889</cell>
 <cell>0.298</cell>
 <cell>2.889</cell>
 <cell>2.591</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[5]:D</cell>
 <cell>2.885</cell>
 <cell>0.299</cell>
 <cell>2.885</cell>
 <cell>2.586</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[8]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.838</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>2.588</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.250</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXDATA[38]</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SERDESIF_075_IP</cell>
 <cell>+</cell>
 <cell>-0.109</cell>
 <cell>-0.109</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI_5[18]_CFG1D_TEST:A</cell>
 <cell>net</cell>
 <cell>SERDES_IF2_0_EPCS_3_RX_DATA[8]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.248</cell>
 <cell>2.139</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI_5[18]_CFG1D_TEST:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.222</cell>
 <cell>2.361</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI_5[18]:B</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI_5[18]_CFG1D_TEST_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.256</cell>
 <cell>2.617</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI_5[18]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.098</cell>
 <cell>2.715</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[8]:D</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI_5[18]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.123</cell>
 <cell>2.838</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.838</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL1</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/CCC_INST/INST_CCC_IP:GL1</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.459</cell>
 <cell>1.459</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL1_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL1_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>1.579</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_1/GL1_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>1.685</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL1_INST/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL1_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.362</cell>
 <cell>2.047</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL1_INST/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>2.237</cell>
 <cell>6</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[8]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL1_INST/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.351</cell>
 <cell>2.588</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[8]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.588</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.588</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET FCCC_2/GL0 to FCCC_1/GL1</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBiI11/CORETSE_AHBlI1II[8]:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[8]:D</cell>
 <cell>0.893</cell>
 <cell>2.777</cell>
 <cell>5.365</cell>
 <cell>2.588</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBiI11/CORETSE_AHBlI1II[0]:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[0]:D</cell>
 <cell>0.945</cell>
 <cell>2.837</cell>
 <cell>5.422</cell>
 <cell>2.585</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBiI11/CORETSE_AHBlI1II[6]:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[6]:D</cell>
 <cell>0.966</cell>
 <cell>2.863</cell>
 <cell>5.445</cell>
 <cell>2.582</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBOoi0/CORETSE_AHBI0i0[7]:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[7]:D</cell>
 <cell>0.988</cell>
 <cell>2.876</cell>
 <cell>5.465</cell>
 <cell>2.589</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBiI11/CORETSE_AHBlI1II[7]:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[7]:D</cell>
 <cell>0.985</cell>
 <cell>2.879</cell>
 <cell>5.468</cell>
 <cell>2.589</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBiI11/CORETSE_AHBlI1II[8]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[8]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.365</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>2.588</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.777</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.378</cell>
 <cell>3.378</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>3.498</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>3.604</cell>
 <cell>16</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB15:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.372</cell>
 <cell>3.976</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB15:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>4.166</cell>
 <cell>23</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBiI11/CORETSE_AHBlI1II[8]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB15_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.306</cell>
 <cell>4.472</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBiI11/CORETSE_AHBlI1II[8]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.052</cell>
 <cell>4.524</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBiI11/CORETSE_AHBol1[8]:A</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBiI11/CORETSE_AHBlI1II[8]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>4.715</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBiI11/CORETSE_AHBol1[8]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.095</cell>
 <cell>4.810</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI_5[18]:A</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0_TCG[8]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.390</cell>
 <cell>5.200</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI_5[18]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.045</cell>
 <cell>5.245</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[8]:D</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBioIOI_5[18]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>5.365</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.365</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL1</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/CCC_INST/INST_CCC_IP:GL1</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.459</cell>
 <cell>1.459</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_1/GL1_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL1_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>1.579</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_1/GL1_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>1.685</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL1_INST/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL1_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.362</cell>
 <cell>2.047</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_1/GL1_INST/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>2.237</cell>
 <cell>6</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[8]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_1/GL1_INST/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.351</cell>
 <cell>2.588</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBol11/CORETSE_AHBooIOI[8]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.588</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.588</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Clock Domain FCCC_2/GL0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[3]:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[4]:D</cell>
 <cell>0.279</cell>
 <cell>0.231</cell>
 <cell>4.745</cell>
 <cell>4.514</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBiI11/CORETSE_AHBollII[3]:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBiI11/CORETSE_AHBOI1II[3]:D</cell>
 <cell>0.289</cell>
 <cell>0.231</cell>
 <cell>4.779</cell>
 <cell>4.548</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[2]:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[3]:D</cell>
 <cell>0.286</cell>
 <cell>0.233</cell>
 <cell>4.747</cell>
 <cell>4.514</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBO011/CORETSE_AHBi101/CORETSE_AHBIIlo:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBO011/CORETSE_AHBi101/CORETSE_AHBl0I1:D</cell>
 <cell>0.280</cell>
 <cell>0.234</cell>
 <cell>4.759</cell>
 <cell>4.525</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBO011/CORETSE_AHBi101/CORETSE_AHBl0lo:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBO011/CORETSE_AHBi101/CORETSE_AHBloI1:D</cell>
 <cell>0.286</cell>
 <cell>0.234</cell>
 <cell>4.758</cell>
 <cell>4.524</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[3]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[4]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.745</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>4.514</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.231</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.378</cell>
 <cell>3.378</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>3.498</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>3.604</cell>
 <cell>16</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB19:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.356</cell>
 <cell>3.960</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB19:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>4.151</cell>
 <cell>9</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[3]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB19_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.315</cell>
 <cell>4.466</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[3]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.052</cell>
 <cell>4.518</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[4]:D</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[3]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.227</cell>
 <cell>4.745</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.745</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.378</cell>
 <cell>3.378</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>3.498</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>3.604</cell>
 <cell>16</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB19:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.356</cell>
 <cell>3.960</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB19:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>4.151</cell>
 <cell>9</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[4]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB19_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.363</cell>
 <cell>4.514</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[4]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>4.514</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.514</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBo1i0/CORETSE_AHBlI10:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBOoi0/CORETSE_AHBO0i0[0]:ALn</cell>
 <cell>0.654</cell>
 <cell>0.600</cell>
 <cell>5.133</cell>
 <cell>4.533</cell>
 <cell>0.000</cell>
 <cell>-0.054</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBo1i0/CORETSE_AHBlI10:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBOoi0/CORETSE_AHBO0i0[1]:ALn</cell>
 <cell>0.654</cell>
 <cell>0.600</cell>
 <cell>5.133</cell>
 <cell>4.533</cell>
 <cell>0.000</cell>
 <cell>-0.054</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBo1i0/CORETSE_AHBlI10:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBOoi0/CORETSE_AHBO0i0[2]:ALn</cell>
 <cell>0.654</cell>
 <cell>0.600</cell>
 <cell>5.133</cell>
 <cell>4.533</cell>
 <cell>0.000</cell>
 <cell>-0.054</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBo1i0/CORETSE_AHBlI10:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBOoi0/CORETSE_AHBii10[5]:ALn</cell>
 <cell>0.654</cell>
 <cell>0.600</cell>
 <cell>5.133</cell>
 <cell>4.533</cell>
 <cell>0.000</cell>
 <cell>-0.054</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBo1i0/CORETSE_AHBlI10:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBOoi0/CORETSE_AHBii10[4]:ALn</cell>
 <cell>0.654</cell>
 <cell>0.606</cell>
 <cell>5.133</cell>
 <cell>4.527</cell>
 <cell>0.000</cell>
 <cell>-0.048</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBo1i0/CORETSE_AHBlI10:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBOoi0/CORETSE_AHBO0i0[0]:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.133</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>4.533</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.600</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.378</cell>
 <cell>3.378</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>3.498</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>3.604</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB18:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.365</cell>
 <cell>3.969</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB18:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>4.160</cell>
 <cell>9</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBo1i0/CORETSE_AHBlI10:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB18_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.319</cell>
 <cell>4.479</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBo1i0/CORETSE_AHBlI10:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.064</cell>
 <cell>4.543</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBo1i0/un1_CORETSE_AHBoO10:A</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBo1i0/CORETSE_AHBlI10</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>4.733</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBo1i0/un1_CORETSE_AHBoO10:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2</cell>
 <cell>+</cell>
 <cell>0.060</cell>
 <cell>4.793</cell>
 <cell>24</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBOoi0/CORETSE_AHBO0i0[0]:ALn</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBo1i0/un1_CORETSE_AHBoO10</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.340</cell>
 <cell>5.133</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.133</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.378</cell>
 <cell>3.378</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>3.498</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>3.604</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB18:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.365</cell>
 <cell>3.969</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB18:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>4.160</cell>
 <cell>9</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBOoi0/CORETSE_AHBO0i0[0]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB18_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.373</cell>
 <cell>4.533</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBOoi0/CORETSE_AHBO0i0[0]:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>4.533</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.533</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_0/GL0 to FCCC_2/GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_1/GL0 to FCCC_2/GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1] to FCCC_2/GL0</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1]</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]:D</cell>
 <cell>4.795</cell>
 <cell>0.281</cell>
 <cell>4.795</cell>
 <cell>4.514</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.795</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>4.514</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.281</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1]</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_READY[1]</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SERDESIF_075_IP</cell>
 <cell>+</cell>
 <cell>0.365</cell>
 <cell>0.365</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1C_TEST:A</cell>
 <cell>net</cell>
 <cell>SERDES_IF2_0_EPCS_3_READY</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.420</cell>
 <cell>0.785</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1C_TEST:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1C_TEST</cell>
 <cell>+</cell>
 <cell>0.121</cell>
 <cell>0.906</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST8:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1C_TEST_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.182</cell>
 <cell>1.088</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST8:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.207</cell>
 <cell>1.295</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST7:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST_net8</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.117</cell>
 <cell>1.412</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST7:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.207</cell>
 <cell>1.619</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST6:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST_net7</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.183</cell>
 <cell>1.802</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST6:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.207</cell>
 <cell>2.009</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST5:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST_net6</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.117</cell>
 <cell>2.126</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST5:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.207</cell>
 <cell>2.333</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST4:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST_net5</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.184</cell>
 <cell>2.517</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST4:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.207</cell>
 <cell>2.724</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST3:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST_net4</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.117</cell>
 <cell>2.841</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST3:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.207</cell>
 <cell>3.048</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST2:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST_net3</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.183</cell>
 <cell>3.231</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST2:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.207</cell>
 <cell>3.438</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST1:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST_net2</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.117</cell>
 <cell>3.555</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST1:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.207</cell>
 <cell>3.762</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST0:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST_net1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.185</cell>
 <cell>3.947</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST0:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.207</cell>
 <cell>4.154</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST_net0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.117</cell>
 <cell>4.271</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.207</cell>
 <cell>4.478</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]:D</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]_CFG1D_TEST_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.317</cell>
 <cell>4.795</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.795</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.378</cell>
 <cell>3.378</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>3.498</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>3.604</cell>
 <cell>16</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB19:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.356</cell>
 <cell>3.960</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB19:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>4.151</cell>
 <cell>9</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB19_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.363</cell>
 <cell>4.514</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[0]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>4.514</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.514</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET FCCC_3/GL0 to FCCC_2/GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_3/GL1 to FCCC_2/GL0</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain FCCC_3/GL0</name>
<text>Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBoo0/CORETSE_AHBooOoI_CORETSE_AHBooOoI_0_5/INST_RAM1K18_IP:B_CLK</text>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_0/GL0 to FCCC_3/GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_1/GL0 to FCCC_3/GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_2/GL0 to FCCC_3/GL0</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBOoi0/CORETSE_AHBo110:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBl1Oo/CORETSE_AHBIOlo/CORETSE_AHBoi1II:D</cell>
 <cell>2.726</cell>
 <cell>0.154</cell>
 <cell>7.213</cell>
 <cell>7.059</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBOoi0/CORETSE_AHBo110:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBl1Oo/CORETSE_AHBIOlo/CORETSE_AHBoi1II:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.213</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>7.059</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.154</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.378</cell>
 <cell>3.378</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>3.498</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>3.604</cell>
 <cell>16</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB15:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.372</cell>
 <cell>3.976</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB15:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>4.166</cell>
 <cell>23</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBOoi0/CORETSE_AHBo110:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB15_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.321</cell>
 <cell>4.487</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBOoi0/CORETSE_AHBo110:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.052</cell>
 <cell>4.539</cell>
 <cell>3</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1A_TEST:A</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBo110</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.529</cell>
 <cell>5.068</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1A_TEST:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1A_TEST</cell>
 <cell>+</cell>
 <cell>0.045</cell>
 <cell>5.113</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1D_TEST2:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1A_TEST_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.184</cell>
 <cell>5.297</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1D_TEST2:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.207</cell>
 <cell>5.504</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1D_TEST1:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1D_TEST_net2</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.117</cell>
 <cell>5.621</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1D_TEST1:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.207</cell>
 <cell>5.828</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1D_TEST0:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1D_TEST_net1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.183</cell>
 <cell>6.011</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1D_TEST0:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.207</cell>
 <cell>6.218</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1D_TEST:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1D_TEST_net0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.117</cell>
 <cell>6.335</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1D_TEST:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.207</cell>
 <cell>6.542</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1D_TEST_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.054</cell>
 <cell>6.596</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.045</cell>
 <cell>6.641</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBl1Oo/CORETSE_AHBIOlo/CORETSE_AHBoi1II:D</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBll</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.572</cell>
 <cell>7.213</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.213</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_3/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_3/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>4.045</cell>
 <cell>4.045</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_3/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_3/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>4.165</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_3/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>4.271</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_3/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>FCCC_3/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.366</cell>
 <cell>4.637</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_3/GL0_INST/U0_RGB1:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>4.828</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_3/CCC_INST/IP_INTERFACE_1:A</cell>
 <cell>net</cell>
 <cell>FCCC_3/FCCC_3_GL0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.245</cell>
 <cell>5.073</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_3/CCC_INST/IP_INTERFACE_1:IPA</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.117</cell>
 <cell>5.190</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_3/CCC_INST/INST_CCC_IP:CLK1</cell>
 <cell>net</cell>
 <cell>FCCC_3/CCC_INST/CLK1_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>5.190</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_3/CCC_INST/INST_CCC_IP:GL1</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CCC_IP</cell>
 <cell>+</cell>
 <cell>0.738</cell>
 <cell>5.928</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_3/GL1_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_3/GL1_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>6.048</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_3/GL1_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>6.154</cell>
 <cell>26</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_3/GL1_INST/U0_RGB1_RGB18:An</cell>
 <cell>net</cell>
 <cell>FCCC_3/GL1_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.367</cell>
 <cell>6.521</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_3/GL1_INST/U0_RGB1_RGB18:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>6.712</cell>
 <cell>37</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBl1Oo/CORETSE_AHBIOlo/CORETSE_AHBoi1II:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_3/GL1_INST/U0_RGB1_RGB18_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.347</cell>
 <cell>7.059</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBl1Oo/CORETSE_AHBIOlo/CORETSE_AHBoi1II:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>7.059</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.059</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET FCCC_3/GL1 to FCCC_3/GL0</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain OSC_0/I_RCOSC_25_50MHZ/CLKOUT</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CoreResetP_0/sm0_areset_n_rcosc_q1:CLK</cell>
 <cell>CoreResetP_0/sm0_areset_n_rcosc:D</cell>
 <cell>0.283</cell>
 <cell>0.238</cell>
 <cell>3.623</cell>
 <cell>3.385</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CoreResetP_0/sdif3_areset_n_rcosc_q1:CLK</cell>
 <cell>CoreResetP_0/sdif3_areset_n_rcosc:D</cell>
 <cell>0.284</cell>
 <cell>0.240</cell>
 <cell>3.627</cell>
 <cell>3.387</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CoreResetP_0/sdif2_areset_n_rcosc_q1:CLK</cell>
 <cell>CoreResetP_0/sdif2_areset_n_rcosc:D</cell>
 <cell>0.286</cell>
 <cell>0.240</cell>
 <cell>3.614</cell>
 <cell>3.374</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CoreResetP_0/sdif1_areset_n_rcosc_q1:CLK</cell>
 <cell>CoreResetP_0/sdif1_areset_n_rcosc:D</cell>
 <cell>0.286</cell>
 <cell>0.241</cell>
 <cell>3.626</cell>
 <cell>3.385</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CoreResetP_0/sdif0_areset_n_rcosc_q1:CLK</cell>
 <cell>CoreResetP_0/sdif0_areset_n_rcosc:D</cell>
 <cell>0.288</cell>
 <cell>0.243</cell>
 <cell>3.634</cell>
 <cell>3.391</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CoreResetP_0/sm0_areset_n_rcosc_q1:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CoreResetP_0/sm0_areset_n_rcosc:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.623</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.385</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.238</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ/CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>OSC_0/N_RCOSC_25_50MHZ_CLKOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.092</cell>
 <cell>0.092</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>OSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.155</cell>
 <cell>2.247</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.224</cell>
 <cell>2.471</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.378</cell>
 <cell>2.849</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>3.040</cell>
 <cell>6</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/sm0_areset_n_rcosc_q1:CLK</cell>
 <cell>net</cell>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.300</cell>
 <cell>3.340</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/sm0_areset_n_rcosc_q1:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.052</cell>
 <cell>3.392</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/sm0_areset_n_rcosc:D</cell>
 <cell>net</cell>
 <cell>CoreResetP_0/sm0_areset_n_rcosc_q1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.231</cell>
 <cell>3.623</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.623</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ/CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>OSC_0/N_RCOSC_25_50MHZ_CLKOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.092</cell>
 <cell>0.092</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>OSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.155</cell>
 <cell>2.247</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.224</cell>
 <cell>2.471</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.378</cell>
 <cell>2.849</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>3.040</cell>
 <cell>6</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>net</cell>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.345</cell>
 <cell>3.385</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/sm0_areset_n_rcosc:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.385</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.385</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CoreResetP_0/sdif1_areset_n_rcosc:CLK</cell>
 <cell>CoreResetP_0/release_sdif1_core:ALn</cell>
 <cell>0.472</cell>
 <cell>0.431</cell>
 <cell>3.812</cell>
 <cell>3.381</cell>
 <cell>0.000</cell>
 <cell>-0.041</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CoreResetP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>CoreResetP_0/count_sdif0_enable_rcosc:ALn</cell>
 <cell>0.504</cell>
 <cell>0.458</cell>
 <cell>3.844</cell>
 <cell>3.386</cell>
 <cell>0.000</cell>
 <cell>-0.046</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CoreResetP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>CoreResetP_0/count_sdif0_enable_q1:ALn</cell>
 <cell>0.504</cell>
 <cell>0.458</cell>
 <cell>3.844</cell>
 <cell>3.386</cell>
 <cell>0.000</cell>
 <cell>-0.046</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CoreResetP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>CoreResetP_0/ddr_settled:ALn</cell>
 <cell>0.504</cell>
 <cell>0.464</cell>
 <cell>3.844</cell>
 <cell>3.380</cell>
 <cell>0.000</cell>
 <cell>-0.040</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CoreResetP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>CoreResetP_0/count_sdif0[12]:ALn</cell>
 <cell>0.594</cell>
 <cell>0.549</cell>
 <cell>3.940</cell>
 <cell>3.391</cell>
 <cell>0.000</cell>
 <cell>-0.045</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CoreResetP_0/sdif1_areset_n_rcosc:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CoreResetP_0/release_sdif1_core:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.812</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.381</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.431</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ/CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>OSC_0/N_RCOSC_25_50MHZ_CLKOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.092</cell>
 <cell>0.092</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>OSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.155</cell>
 <cell>2.247</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.224</cell>
 <cell>2.471</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.375</cell>
 <cell>2.846</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>3.037</cell>
 <cell>19</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/sdif1_areset_n_rcosc:CLK</cell>
 <cell>net</cell>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.303</cell>
 <cell>3.340</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/sdif1_areset_n_rcosc:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.052</cell>
 <cell>3.392</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/release_sdif1_core:ALn</cell>
 <cell>net</cell>
 <cell>CoreResetP_0/sdif1_areset_n_rcosc</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.420</cell>
 <cell>3.812</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.812</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ/CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>OSC_0/N_RCOSC_25_50MHZ_CLKOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.092</cell>
 <cell>0.092</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>OSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.155</cell>
 <cell>2.247</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.224</cell>
 <cell>2.471</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.378</cell>
 <cell>2.849</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB2:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>3.040</cell>
 <cell>3</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/release_sdif1_core:CLK</cell>
 <cell>net</cell>
 <cell>OSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB2_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.341</cell>
 <cell>3.381</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreResetP_0/release_sdif1_core:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.381</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.381</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_0/GL0 to OSC_0/I_RCOSC_25_50MHZ/CLKOUT</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CoreConfigP_0/INIT_DONE_q1:CLK</cell>
 <cell>CoreConfigP_0/INIT_DONE_q2:D</cell>
 <cell>0.287</cell>
 <cell>0.235</cell>
 <cell>3.390</cell>
 <cell>3.155</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CoreConfigP_0/state[1]:CLK</cell>
 <cell>CoreConfigP_0/state[1]:D</cell>
 <cell>0.303</cell>
 <cell>0.303</cell>
 <cell>3.415</cell>
 <cell>3.112</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CoreConfigP_0/state[0]:CLK</cell>
 <cell>CoreConfigP_0/state[1]:D</cell>
 <cell>0.362</cell>
 <cell>0.308</cell>
 <cell>3.468</cell>
 <cell>3.160</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CoreConfigP_0/SDIF_RELEASED_q1:CLK</cell>
 <cell>CoreConfigP_0/SDIF_RELEASED_q2:D</cell>
 <cell>0.357</cell>
 <cell>0.311</cell>
 <cell>3.460</cell>
 <cell>3.149</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CoreConfigP_0/state[1]:CLK</cell>
 <cell>CoreConfigP_0/FIC_2_APB_M_PREADY:D</cell>
 <cell>0.407</cell>
 <cell>0.366</cell>
 <cell>3.519</cell>
 <cell>3.153</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CoreConfigP_0/INIT_DONE_q1:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CoreConfigP_0/INIT_DONE_q2:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.390</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.155</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.235</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>CoreTSE_Webserver_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreTSE_Webserver_MSS_0/MSS_ADLIB_INST_RNI3KN8:An</cell>
 <cell>net</cell>
 <cell>CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.015</cell>
 <cell>2.015</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CoreTSE_Webserver_MSS_0/MSS_ADLIB_INST_RNI3KN8:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.224</cell>
 <cell>2.239</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>CoreTSE_Webserver_MSS_0/MSS_ADLIB_INST_RNI3KN8/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>CoreTSE_Webserver_MSS_0/MSS_ADLIB_INST_RNI3KN8/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.362</cell>
 <cell>2.601</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CoreTSE_Webserver_MSS_0/MSS_ADLIB_INST_RNI3KN8/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>2.791</cell>
 <cell>44</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreConfigP_0/INIT_DONE_q1:CLK</cell>
 <cell>net</cell>
 <cell>CoreTSE_Webserver_MSS_0/MSS_ADLIB_INST_RNI3KN8/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.312</cell>
 <cell>3.103</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreConfigP_0/INIT_DONE_q1:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.052</cell>
 <cell>3.155</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreConfigP_0/INIT_DONE_q2:D</cell>
 <cell>net</cell>
 <cell>CoreConfigP_0/INIT_DONE_q1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.235</cell>
 <cell>3.390</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.390</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>CoreTSE_Webserver_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreTSE_Webserver_MSS_0/MSS_ADLIB_INST_RNI3KN8:An</cell>
 <cell>net</cell>
 <cell>CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.015</cell>
 <cell>2.015</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CoreTSE_Webserver_MSS_0/MSS_ADLIB_INST_RNI3KN8:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.224</cell>
 <cell>2.239</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>CoreTSE_Webserver_MSS_0/MSS_ADLIB_INST_RNI3KN8/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>CoreTSE_Webserver_MSS_0/MSS_ADLIB_INST_RNI3KN8/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.362</cell>
 <cell>2.601</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>CoreTSE_Webserver_MSS_0/MSS_ADLIB_INST_RNI3KN8/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>2.791</cell>
 <cell>44</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreConfigP_0/INIT_DONE_q2:CLK</cell>
 <cell>net</cell>
 <cell>CoreTSE_Webserver_MSS_0/MSS_ADLIB_INST_RNI3KN8/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.364</cell>
 <cell>3.155</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CoreConfigP_0/INIT_DONE_q2:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.155</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.155</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_0/GL0 to CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1]</name>
<text>Info: The maximum frequency of this clock domain is limited by the period of pin SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]</text>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]</name>
<text>Info: The maximum frequency of this clock domain is limited by the period of pin SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1]</text>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_2/GL0 to SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[8]:CLK</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXVAL[1]</cell>
 <cell>0.560</cell>
 <cell>6.241</cell>
 <cell>5.021</cell>
 <cell>-1.220</cell>
 <cell>-1.220</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBiI11/CORETSE_AHBlI1II[4]:CLK</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[24]</cell>
 <cell>2.746</cell>
 <cell>8.585</cell>
 <cell>7.220</cell>
 <cell>-1.365</cell>
 <cell>-1.365</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBiI11/CORETSE_AHBlI1II[6]:CLK</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[26]</cell>
 <cell>2.861</cell>
 <cell>8.621</cell>
 <cell>7.340</cell>
 <cell>-1.281</cell>
 <cell>-1.281</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBiI11/CORETSE_AHBlI1II[5]:CLK</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[25]</cell>
 <cell>2.841</cell>
 <cell>8.626</cell>
 <cell>7.319</cell>
 <cell>-1.307</cell>
 <cell>-1.307</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBIoi0/CORETSE_AHBiI11/CORETSE_AHBlI1II[1]:CLK</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[21]</cell>
 <cell>2.796</cell>
 <cell>8.628</cell>
 <cell>7.274</cell>
 <cell>-1.354</cell>
 <cell>-1.354</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[8]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXVAL[1]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.021</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>-1.220</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.241</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.378</cell>
 <cell>3.378</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>3.498</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>3.604</cell>
 <cell>16</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB19:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.356</cell>
 <cell>3.960</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB19:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>4.151</cell>
 <cell>9</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[8]:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB19_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.310</cell>
 <cell>4.461</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBIOI[8]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.052</cell>
 <cell>4.513</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/IP_INTERFACE_199:B</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0_TBI_TXVAL</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.355</cell>
 <cell>4.868</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/IP_INTERFACE_199:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.126</cell>
 <cell>4.994</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXVAL[1]</cell>
 <cell>net</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/EPCS_TXVAL_net[1]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.027</cell>
 <cell>5.021</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.021</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1]</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXVAL[1]</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SERDESIF_075_IP</cell>
 <cell>+</cell>
 <cell>-1.220</cell>
 <cell>-1.220</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-1.220</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Clock Domain FCCC_3/GL1</name>
<text>Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBoo0/CORETSE_AHBooOoI_CORETSE_AHBooOoI_0_5/INST_RAM1K18_IP:B_CLK</text>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_0/GL0 to FCCC_3/GL1</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_1/GL0 to FCCC_3/GL1</name>
<text>No Path</text>
</section>
<section>
<name>SET FCCC_2/GL0 to FCCC_3/GL1</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBOoi0/CORETSE_AHBo110:CLK</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBl1Oo/CORETSE_AHBIOlo/CORETSE_AHBoi1II:D</cell>
 <cell>2.726</cell>
 <cell>0.154</cell>
 <cell>7.213</cell>
 <cell>7.059</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBOoi0/CORETSE_AHBo110:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBl1Oo/CORETSE_AHBIOlo/CORETSE_AHBoi1II:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.213</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>7.059</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.154</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.378</cell>
 <cell>3.378</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>3.498</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>3.604</cell>
 <cell>16</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB15:An</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.372</cell>
 <cell>3.976</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB15:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>4.166</cell>
 <cell>23</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBOoi0/CORETSE_AHBo110:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_2/GL0_INST/U0_RGB1_RGB15_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.321</cell>
 <cell>4.487</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBOoi0/CORETSE_AHBo110:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.052</cell>
 <cell>4.539</cell>
 <cell>3</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1A_TEST:A</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBo110</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.529</cell>
 <cell>5.068</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1A_TEST:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1A_TEST</cell>
 <cell>+</cell>
 <cell>0.045</cell>
 <cell>5.113</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1D_TEST2:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1A_TEST_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.184</cell>
 <cell>5.297</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1D_TEST2:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.207</cell>
 <cell>5.504</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1D_TEST1:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1D_TEST_net2</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.117</cell>
 <cell>5.621</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1D_TEST1:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.207</cell>
 <cell>5.828</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1D_TEST0:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1D_TEST_net1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.183</cell>
 <cell>6.011</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1D_TEST0:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.207</cell>
 <cell>6.218</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1D_TEST:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1D_TEST_net0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.117</cell>
 <cell>6.335</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1D_TEST:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1D_TEST</cell>
 <cell>+</cell>
 <cell>0.207</cell>
 <cell>6.542</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01:A</cell>
 <cell>net</cell>
 <cell>mdr_CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0_CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01_CFG1D_TEST_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.054</cell>
 <cell>6.596</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBio0.CORETSE_AHBOi0/CORETSE_AHBlOO1/CORETSE_AHBO01:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.045</cell>
 <cell>6.641</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBl1Oo/CORETSE_AHBIOlo/CORETSE_AHBoi1II:D</cell>
 <cell>net</cell>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBll</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.572</cell>
 <cell>7.213</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.213</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_3/GL1</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_3/CCC_INST/INST_CCC_IP:GL1</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>5.928</cell>
 <cell>5.928</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FCCC_3/GL1_INST:An</cell>
 <cell>net</cell>
 <cell>FCCC_3/GL1_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>6.048</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>FCCC_3/GL1_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>6.154</cell>
 <cell>26</cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_3/GL1_INST/U0_RGB1_RGB18:An</cell>
 <cell>net</cell>
 <cell>FCCC_3/GL1_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.367</cell>
 <cell>6.521</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>FCCC_3/GL1_INST/U0_RGB1_RGB18:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>6.712</cell>
 <cell>37</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBl1Oo/CORETSE_AHBIOlo/CORETSE_AHBoi1II:CLK</cell>
 <cell>net</cell>
 <cell>FCCC_3/GL1_INST/U0_RGB1_RGB18_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.347</cell>
 <cell>7.059</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CORETSE_AHB_0/CoreTSE_top_inst/CORETSE_AHBilI/CORETSE_AHBiOooI/CORETSE_AHBl1Oo/CORETSE_AHBIOlo/CORETSE_AHBoi1II:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>7.059</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.059</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET FCCC_3/GL0 to FCCC_3/GL1</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set Pin to Pin</name>
<section>
<name>SET Input to Output</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set User Sets</name>
</section>
</doc>
