Project Settings
Project Name | CoreTSE_Webserver_syn | Implementation Name | synthesis
Top Module | CoreTSE_Webserver | Retiming | 0
Resource Sharing | 1 | Fanout Guide | 10000
Disable I/O Insertion | 0 | FSM Compiler | 1

Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
(compiler) | Complete | 173 | 407 | 0 | - | 0m:10s | - | 11/17/2016 3:26:44 PM
(premap) | Complete | 62 | 16 | 0 | 0m:02s | 0m:02s | 190MB | 11/17/2016 3:26:49 PM
(fpga_mapper) | Complete | 205 | 97 | 0 | 01m:04s | 01m:04s | 327MB | 11/17/2016 3:27:54 PM
Multi-srs Generator | Complete |  |  |  | 0m:02s |  |  | 11/17/2016 3:26:46 PM

Area Summary
Carry Cells | 1456 | Sequential Cells | 5172
DSP Blocks (MACC) (dsp_used) | 0 | I/O Cells | 23
Global Clock Buffers | 27 | Block Rams (RAM1K18) (v_ram) | 14
LUTs (total_luts) | 9782 |  |

Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
CLK1_PAD | 50.0 MHz | NA | NA
CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB | 12.5 MHz | 107.9 MHz | 35.365
FCCC_0/GL0 | 50.0 MHz | 35.8 MHz | -1.275
FCCC_1/GL0 | 62.5 MHz | 65.8 MHz | 2.685
FCCC_1/GL1 | 62.5 MHz | 80.2 MHz | 7.106
FCCC_2/GL0 | 125.0 MHz | 160.4 MHz | 2.738
FCCC_3/GL0 | 125.0 MHz | NA | NA
FCCC_3/GL1 | 125.0 MHz | 89.5 MHz | -1.587
OSC_0/I_RCOSC_25_50MHZ/CLKOUT | 50.0 MHz | 431.2 MHz | 17.681
SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] | 125.0 MHz | NA | NA
SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1] | 125.0 MHz | NA | NA
pemgt|CORETSE_AHBi01_inferred_clock | 100.0 MHz | 152.0 MHz | 3.420
System | 100.0 MHz | 477.6 MHz | 7.906

Optimizations Summary
Combined Clock Conversion | 8 / 1 |  |