| Project Settings |
|---|
| Project Name | EDAC_top_syn | Implementation Name | synthesis |
| Top Module | EDAC_top | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 10000 |
| Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
48 |
35 |
0 |
- |
00m:01s |
- |
14-Mar-17
2:32:50 PM |
| (premap) | Complete |
52 |
19 |
0 |
0m:00s |
0m:00s |
138MB |
14-Mar-17
2:32:52 PM |
| (fpga_mapper) | Complete |
35 |
27 |
0 |
0m:01s |
0m:01s |
138MB |
14-Mar-17
2:32:54 PM |
| Multi-srs Generator |
Complete | | | | | | | 14-Mar-17
2:32:51 PM |
| Area Summary |
|---|
| |
| Carry Cells | 14 |
Sequential Cells | 125 |
| DSP Blocks (MACC)
(dsp_used) | 0 |
I/O Cells | 89 |
| Global Clock Buffers | 6 |
LUTs
(total_luts) | 81 |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| EDAC_CCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | 499.9 MHz | 8.000 |
| EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | 100.0 MHz | 428.6 MHz | 7.667 |
| EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock | 100.0 MHz | 107.9 MHz | 0.734 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 0 / 3 |
| |
|