EDAC_top_syn (synthesis)
Synthesis -
Compiler Report
Compiler Constraint Applicator
Pre-mapping Report
Clock Summary
Mapper Report
Clock Conversion
Timing Report
Performance Summary
Clock Relationships
Interface Information
Detailed Report for Clocks
Clock: EDAC_CCC_0_FCCC|GL0_net_inferred_clock
Starting Points with Worst Slack
Ending Points with Worst Slack
Worst Path Information
Clock: EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock
Starting Points with Worst Slack
Ending Points with Worst Slack
Worst Path Information
Clock: EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock
Starting Points with Worst Slack
Ending Points with Worst Slack
Worst Path Information
Resource Utilization
Constraint Checker Report (14:32 14-Mar)
Hierarchical Area Report(EDAC_top) (14:32 14-Mar)