#Build: Synplify Pro L-2016.09M-2, Build 065R, Nov 16 2016 #install: D:\microsemi\Libero_v11.8\SynplifyPro #OS: Windows 7 6.1 #Hostname: W764-KOTIPALLID # Tue Mar 14 14:32:49 2017 #Implementation: synthesis Synopsys HDL Compiler, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Synopsys Verilog Compiler, version comp2016q3p1, Build 127R, built Nov 24 2016 @N: : | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. @I::"D:\microsemi\Libero_v11.8\SynplifyPro\lib\generic\smartfusion2.v" (library work) @I::"D:\microsemi\Libero_v11.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\microsemi\Libero_v11.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\microsemi\Libero_v11.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\microsemi\Libero_v11.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"F:\11.8\SF2_EDAC_DDR_DF\DDR_EDAC\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v" (library work) @I::"F:\11.8\SF2_EDAC_DDR_DF\DDR_EDAC\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v" (library work) @I::"F:\11.8\SF2_EDAC_DDR_DF\DDR_EDAC\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v" (library work) @I::"F:\11.8\SF2_EDAC_DDR_DF\DDR_EDAC\component\work\EDAC\CCC_0\EDAC_CCC_0_FCCC.v" (library work) @I::"F:\11.8\SF2_EDAC_DDR_DF\DDR_EDAC\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" (library work) @I::"F:\11.8\SF2_EDAC_DDR_DF\DDR_EDAC\component\work\EDAC\FABOSC_0\EDAC_FABOSC_0_OSC.v" (library work) @I::"F:\11.8\SF2_EDAC_DDR_DF\DDR_EDAC\component\work\EDAC_MSS\EDAC_MSS_syn.v" (library work) @I::"F:\11.8\SF2_EDAC_DDR_DF\DDR_EDAC\component\work\EDAC_MSS\EDAC_MSS.v" (library work) @I::"F:\11.8\SF2_EDAC_DDR_DF\DDR_EDAC\component\work\EDAC\EDAC.v" (library work) @I::"F:\11.8\SF2_EDAC_DDR_DF\DDR_EDAC\component\work\EDAC_top\EDAC_top.v" (library work) Verilog syntax check successful! File F:\11.8\SF2_EDAC_DDR_DF\DDR_EDAC\component\work\EDAC_top\EDAC_top.v changed - recompiling Selecting top level module EDAC_top @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC in library work. @N:CG364 : smartfusion2.v(372) | Synthesizing module GND in library work. @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT in library work. @N:CG364 : smartfusion2.v(727) | Synthesizing module CCC in library work. @N:CG364 : EDAC_CCC_0_FCCC.v(5) | Synthesizing module EDAC_CCC_0_FCCC in library work. @N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP in library work. FAMILY=32'b00000000000000000000000000010011 MDDR_IN_USE=32'b00000000000000000000000000000001 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000000 VERSION_MAJOR=32'b00000000000000000000000000000111 VERSION_MINOR=32'b00000000000000000000000000000000 VERSION_MAJOR_VECTOR=16'b0000000000000111 VERSION_MINOR_VECTOR=16'b0000000000000000 S0=2'b00 S1=2'b01 S2=2'b10 Generated name = CoreConfigP_Z1 @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP in library work. FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000001 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000000 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z2 @W:CL169 : coreresetp.v(1581) | Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1549) | Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1517) | Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1485) | Pruning unused register count_sdif0[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1365) | Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1300) | Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1235) | Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1170) | Pruning unused register count_sdif0_enable. Make sure that there are no unused intermediate registers. @W:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : coreresetp.v(1089) | Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers. @N:CG364 : smartfusion2.v(274) | Synthesizing module OUTBUF in library work. @N:CG364 : smartfusion2.v(326) | Synthesizing module OUTBUF_DIFF in library work. @N:CG364 : smartfusion2.v(286) | Synthesizing module BIBUF in library work. @N:CG364 : smartfusion2.v(338) | Synthesizing module BIBUF_DIFF in library work. @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF in library work. @N:CG364 : EDAC_MSS_syn.v(5) | Synthesizing module MSS_120 in library work. @N:CG364 : EDAC_MSS.v(9) | Synthesizing module EDAC_MSS in library work. @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB in library work. @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ in library work. @N:CG364 : EDAC_FABOSC_0_OSC.v(5) | Synthesizing module EDAC_FABOSC_0_OSC in library work. @N:CG364 : smartfusion2.v(718) | Synthesizing module SYSRESET in library work. @N:CG364 : EDAC.v(9) | Synthesizing module EDAC in library work. @N:CG364 : EDAC_top.v(9) | Synthesizing module EDAC_top in library work. @W:CL157 : EDAC_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : EDAC_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : EDAC_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : EDAC_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @N:CL159 : EDAC_FABOSC_0_OSC.v(14) | Input XTL is unused. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state. Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state. Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state. Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state. Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state. Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @N:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused. @N:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused. @N:CL159 : coreresetp.v(59) | Input SDIF0_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused. @N:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused. @N:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused. @N:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused. @N:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused. @N:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused. @N:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused. @N:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused. @N:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused. @N:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused. @N:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused. @N:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused. @N:CL201 : coreconfigp.v(447) | Trying to extract state machine for register state. Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 77MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Mar 14 14:32:49 2017 ###########################################################] Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Mar 14 14:32:50 2017 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Mar 14 14:32:50 2017 ###########################################################] Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode File F:\11.8\SF2_EDAC_DDR_DF\DDR_EDAC\synthesis\synwork\EDAC_top_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Mar 14 14:32:51 2017 ###########################################################] Pre-mapping Report # Tue Mar 14 14:32:51 2017 Synopsys Generic Technology Pre-mapping, Version map201609actrcp1, Build 005R, Built Jan 25 2017 01:01:33 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.09M-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @A:MF827 : | No constraint file specified. Linked File: EDAC_top_scck.rpt Printing clock summary report in "F:\11.8\SF2_EDAC_DDR_DF\DDR_EDAC\synthesis\EDAC_top_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 109MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 109MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB) @W:BN132 : coreresetp.v(1089) | Removing sequential instance EDAC_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance EDAC_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MO111 : edac_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.EDAC_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.EDAC_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : edac_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.EDAC_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.EDAC_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : edac_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.EDAC_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.EDAC_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : edac_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.EDAC_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.EDAC_FABOSC_0_OSC(verilog)) has its enable tied to GND. @W:MO129 : coreresetp.v(676) | Sequential instance EDAC_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance EDAC_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance EDAC_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance EDAC_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance EDAC_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance EDAC_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance EDAC_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance EDAC_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance EDAC_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance EDAC_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance EDAC_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance EDAC_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance EDAC_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance EDAC_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(1388) | Sequential instance EDAC_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation. @N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF0_PENABLE (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF1_PENABLE (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF3_PENABLE (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_RELEASED_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_PHY_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance sdif0_state[3:0] (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_clk_base (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_q1 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. syn_allowed_resources : blockrams=236 set on top level netlist EDAC_top Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 138MB) Clock Summary ***************** Start Requested Requested Clock Clock Clock Clock Frequency Period Type Group Load ------------------------------------------------------------------------------------------------------------------------------ EDAC_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_1 38 EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 31 EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 109 ============================================================================================================================== @W:MT530 : coreconfigp.v(447) | Found inferred clock EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock which controls 109 sequential elements including EDAC_0.CORECONFIGP_0.FIC_2_APB_M_PREADY. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coreresetp.v(1089) | Found inferred clock EDAC_CCC_0_FCCC|GL0_net_inferred_clock which controls 38 sequential elements including EDAC_0.CORERESETP_0.count_ddr_enable. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coreresetp.v(1613) | Found inferred clock EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 31 sequential elements including EDAC_0.CORERESETP_0.count_ddr[13:0]. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file F:\11.8\SF2_EDAC_DDR_DF\DDR_EDAC\synthesis\EDAC_top.sap. Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 138MB) Encoding state machine state[2:0] (in view: work.CoreConfigP_Z1(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z2(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[16] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[17] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[18] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[19] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[20] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[21] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[22] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[23] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[24] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[25] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[26] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[27] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[28] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[29] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[30] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[31] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance paddr[11] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. None None Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 138MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 138MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Mar 14 14:32:52 2017 ###########################################################] Map & Optimize Report # Tue Mar 14 14:32:52 2017 Synopsys Generic Technology Mapper, Version map201609actrcp1, Build 005R, Built Jan 25 2017 01:01:33 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.09M-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB) @N:MO111 : edac_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.EDAC_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.EDAC_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : edac_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.EDAC_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.EDAC_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : edac_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.EDAC_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.EDAC_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : edac_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.EDAC_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.EDAC_FABOSC_0_OSC(verilog)) has its enable tied to GND. @W:BN132 : coreresetp.v(884) | Removing sequential instance EDAC_0.CORERESETP_0.sdif1_areset_n_rcosc_q1 because it is equivalent to instance EDAC_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(912) | Removing sequential instance EDAC_0.CORERESETP_0.sdif3_areset_n_rcosc_q1 because it is equivalent to instance EDAC_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(898) | Removing sequential instance EDAC_0.CORERESETP_0.sdif2_areset_n_rcosc_q1 because it is equivalent to instance EDAC_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(856) | Removing sequential instance EDAC_0.CORERESETP_0.sm0_areset_n_rcosc_q1 because it is equivalent to instance EDAC_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(898) | Removing sequential instance EDAC_0.CORERESETP_0.sdif2_areset_n_rcosc because it is equivalent to instance EDAC_0.CORERESETP_0.sm0_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(912) | Removing sequential instance EDAC_0.CORERESETP_0.sdif3_areset_n_rcosc because it is equivalent to instance EDAC_0.CORERESETP_0.sm0_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(884) | Removing sequential instance EDAC_0.CORERESETP_0.sdif1_areset_n_rcosc because it is equivalent to instance EDAC_0.CORERESETP_0.sm0_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(870) | Removing sequential instance EDAC_0.CORERESETP_0.sdif0_areset_n_rcosc because it is equivalent to instance EDAC_0.CORERESETP_0.sm0_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(1581) | Removing sequential instance EDAC_0.CORERESETP_0.release_sdif3_core because it is equivalent to instance EDAC_0.CORERESETP_0.release_sdif2_core. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(1549) | Removing sequential instance EDAC_0.CORERESETP_0.release_sdif2_core because it is equivalent to instance EDAC_0.CORERESETP_0.release_sdif1_core. To keep the instance, apply constraint syn_preserve=1 on the instance. Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB) Encoding state machine state[2:0] (in view: work.CoreConfigP_Z1(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[16] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[17] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[18] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[19] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[20] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[21] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[22] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[23] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[24] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[25] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[26] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[27] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[28] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[29] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[30] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[31] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance paddr[11] (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[31] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[30] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[29] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[28] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[27] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[26] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[25] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[24] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[23] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[22] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[21] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[20] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[19] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z2(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 @N:MO231 : coreresetp.v(1613) | Found counter in view:work.CoreResetP_Z2(verilog) instance count_ddr[13:0] Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 137MB) @N:BN362 : coreresetp.v(1089) | Removing sequential instance EDAC_0.CORERESETP_0.DDR_READY_int (in view: work.EDAC_top(verilog)) because it does not drive other instances. Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 137MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 137MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 137MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 137MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 137MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 137MB) @N:BN362 : coreconfigp.v(255) | Removing sequential instance EDAC_0.CORECONFIGP_0.paddr[14] (in view: work.EDAC_top(verilog)) because it does not drive other instances. Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 137MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 138MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s 0.29ns 127 / 125 2 0h:00m:00s 0.29ns 127 / 125 @N:FP130 : | Promoting Net EDAC_0.CORECONFIGP_0_APB_S_PRESET_N on CLKINT I_33 @N:FP130 : | Promoting Net EDAC_0.CORECONFIGP_0_APB_S_PCLK on CLKINT I_34 @N:FP130 : | Promoting Net EDAC_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT I_35 @N:FP130 : | Promoting Net EDAC_0.CORERESETP_0.sm0_areset_n_rcosc on CLKINT I_36 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 138MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 138MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 3 gated/generated clock tree(s) driving 127 clock pin(s) of sequential element(s) 0 instances converted, 127 sequential instances remain driven by gated/generated clocks ================================================================================= Gated/Generated Clocks ================================================================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ClockId0001 EDAC_0.EDAC_MSS_0.MSS_ADLIB_INST MSS_120 76 EDAC_0.EDAC_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_120 ClockId0002 EDAC_0.CCC_0.CCC_INST CCC 31 EDAC_0.EDAC_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_120 ClockId0003 EDAC_0.FABOSC_0.I_RCOSC_25_50MHZ RCOSC_25_50MHZ 20 EDAC_0.CORERESETP_0.count_ddr[13] No gated clock conversion method for cell cell:ACG4.SLE ========================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 138MB) Writing Analyst data base F:\11.8\SF2_EDAC_DDR_DF\DDR_EDAC\synthesis\synwork\EDAC_top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 134MB peak: 138MB) Writing EDIF Netlist and constraint files @N:FX1056 : | Writing EDF file: F:\11.8\SF2_EDAC_DDR_DF\DDR_EDAC\synthesis\EDAC_top.edn @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF L-2016.09M-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 135MB peak: 138MB) Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 136MB peak: 138MB) @W:MT246 : edac_ccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:EDAC_0.FABOSC_0.RCOSC_25_50MHZ_CCC" @W:MT420 : | Found inferred clock EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:EDAC_0.EDAC_MSS_0.FIC_2_APB_M_PCLK" @W:MT420 : | Found inferred clock EDAC_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:EDAC_0.CCC_0.GL0_net" ##### START OF TIMING REPORT #####[ # Timing Report written on Tue Mar 14 14:32:54 2017 # Top view: EDAC_top Requested Frequency: 100.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: 0.734 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------------------------------------------------- EDAC_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 499.9 MHz 10.000 2.000 8.000 inferred Inferred_clkgroup_1 EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock 100.0 MHz 428.6 MHz 10.000 2.333 7.667 inferred Inferred_clkgroup_2 EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 107.9 MHz 10.000 9.266 0.734 inferred Inferred_clkgroup_0 ========================================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock | 10.000 0.734 | No paths - | 5.000 2.990 | 5.000 1.864 EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock EDAC_CCC_0_FCCC|GL0_net_inferred_clock | Diff grp - | No paths - | No paths - | No paths - EDAC_CCC_0_FCCC|GL0_net_inferred_clock EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - EDAC_CCC_0_FCCC|GL0_net_inferred_clock EDAC_CCC_0_FCCC|GL0_net_inferred_clock | 10.000 8.000 | No paths - | No paths - | No paths - EDAC_CCC_0_FCCC|GL0_net_inferred_clock EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | Diff grp - | No paths - | No paths - | No paths - EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock EDAC_CCC_0_FCCC|GL0_net_inferred_clock | Diff grp - | No paths - | No paths - | No paths - EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | 10.000 7.667 | No paths - | No paths - | No paths - ================================================================================================================================================================================================ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: EDAC_CCC_0_FCCC|GL0_net_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------- EDAC_0.CORERESETP_0.sm0_state[3] EDAC_CCC_0_FCCC|GL0_net_inferred_clock SLE Q sm0_state[3] 0.076 8.000 EDAC_0.CORERESETP_0.sdif3_spll_lock_q2 EDAC_CCC_0_FCCC|GL0_net_inferred_clock SLE Q sdif3_spll_lock_q2 0.076 8.075 EDAC_0.CORERESETP_0.release_sdif0_core_clk_base EDAC_CCC_0_FCCC|GL0_net_inferred_clock SLE Q release_sdif0_core_clk_base 0.076 8.208 EDAC_0.CORERESETP_0.ddr_settled_clk_base EDAC_CCC_0_FCCC|GL0_net_inferred_clock SLE Q ddr_settled_clk_base 0.076 8.233 EDAC_0.CORERESETP_0.sm0_state[4] EDAC_CCC_0_FCCC|GL0_net_inferred_clock SLE Q sm0_state[4] 0.094 8.587 EDAC_0.CORERESETP_0.CONFIG2_DONE_clk_base EDAC_CCC_0_FCCC|GL0_net_inferred_clock SLE Q CONFIG2_DONE_clk_base 0.094 8.684 EDAC_0.CORERESETP_0.sm0_state[5] EDAC_CCC_0_FCCC|GL0_net_inferred_clock SLE Q sm0_state[5] 0.094 8.745 EDAC_0.CORERESETP_0.FIC_2_APB_M_PRESET_N_clk_base EDAC_CCC_0_FCCC|GL0_net_inferred_clock SLE Q FIC_2_APB_M_PRESET_N_clk_base 0.076 8.801 EDAC_0.CORERESETP_0.RESET_N_M2F_clk_base EDAC_CCC_0_FCCC|GL0_net_inferred_clock SLE Q RESET_N_M2F_clk_base 0.076 8.811 EDAC_0.CORERESETP_0.mss_ready_state EDAC_CCC_0_FCCC|GL0_net_inferred_clock SLE Q mss_ready_state 0.094 8.823 ===================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------ EDAC_0.CORERESETP_0.sm0_state[4] EDAC_CCC_0_FCCC|GL0_net_inferred_clock SLE D sm0_state_ns[4] 9.778 8.000 EDAC_0.CORERESETP_0.sm0_state[5] EDAC_CCC_0_FCCC|GL0_net_inferred_clock SLE D sm0_state_ns[5] 9.778 8.208 EDAC_0.CORERESETP_0.count_ddr_enable EDAC_CCC_0_FCCC|GL0_net_inferred_clock SLE D next_count_ddr_enable_0_sqmuxa 9.778 8.373 EDAC_0.CORERESETP_0.count_ddr_enable EDAC_CCC_0_FCCC|GL0_net_inferred_clock SLE EN un1_next_ddr_ready_0_sqmuxa 9.707 8.587 EDAC_0.CORERESETP_0.sm0_state[3] EDAC_CCC_0_FCCC|GL0_net_inferred_clock SLE D sm0_state_ns[3] 9.778 8.633 EDAC_0.CORERESETP_0.sm0_state[6] EDAC_CCC_0_FCCC|GL0_net_inferred_clock SLE EN sm0_state_ns_a3[6] 9.707 8.745 EDAC_0.CORERESETP_0.MSS_HPMS_READY_int EDAC_CCC_0_FCCC|GL0_net_inferred_clock SLE D MSS_HPMS_READY_int_4 9.778 8.801 EDAC_0.CORERESETP_0.mss_ready_select EDAC_CCC_0_FCCC|GL0_net_inferred_clock SLE EN mss_ready_select4 9.707 8.812 EDAC_0.CORERESETP_0.sm0_state[2] EDAC_CCC_0_FCCC|GL0_net_inferred_clock SLE D sm0_state_ns[2] 9.778 8.830 EDAC_0.CORERESETP_0.mss_ready_state EDAC_CCC_0_FCCC|GL0_net_inferred_clock SLE EN RESET_N_M2F_clk_base 9.707 8.926 ============================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 1.778 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 8.000 Number of logic level(s): 2 Starting point: EDAC_0.CORERESETP_0.sm0_state[3] / Q Ending point: EDAC_0.CORERESETP_0.sm0_state[4] / D The start point is clocked by EDAC_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK The end point is clocked by EDAC_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------- EDAC_0.CORERESETP_0.sm0_state[3] SLE Q Out 0.076 0.076 - sm0_state[3] Net - - 0.637 - 3 EDAC_0.CORERESETP_0.next_count_ddr_enable_0_sqmuxa_0_a3 CFG2 B In - 0.714 - EDAC_0.CORERESETP_0.next_count_ddr_enable_0_sqmuxa_0_a3 CFG2 Y Out 0.143 0.857 - next_count_ddr_enable_0_sqmuxa Net - - 0.548 - 2 EDAC_0.CORERESETP_0.sm0_state_ns[4] CFG4 D In - 1.405 - EDAC_0.CORERESETP_0.sm0_state_ns[4] CFG4 Y Out 0.236 1.641 - sm0_state_ns[4] Net - - 0.138 - 1 EDAC_0.CORERESETP_0.sm0_state[4] SLE D In - 1.778 - ====================================================================================================================== Total path delay (propagation time + setup) of 2.000 is 0.677(33.9%) logic and 1.323(66.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------ EDAC_0.CORERESETP_0.count_ddr[0] EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_ddr[0] 0.094 7.667 EDAC_0.CORERESETP_0.count_ddr[1] EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_ddr[1] 0.094 7.732 EDAC_0.CORERESETP_0.count_ddr[2] EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_ddr[2] 0.094 7.746 EDAC_0.CORERESETP_0.count_ddr[3] EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_ddr[3] 0.094 7.760 EDAC_0.CORERESETP_0.count_ddr[4] EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_ddr[4] 0.094 7.774 EDAC_0.CORERESETP_0.count_ddr[5] EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_ddr[5] 0.094 7.789 EDAC_0.CORERESETP_0.count_ddr[6] EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_ddr[6] 0.094 7.803 EDAC_0.CORERESETP_0.count_ddr[7] EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_ddr[7] 0.094 7.817 EDAC_0.CORERESETP_0.count_ddr[8] EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_ddr[8] 0.094 7.831 EDAC_0.CORERESETP_0.count_ddr[9] EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_ddr[9] 0.094 7.845 ================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------- EDAC_0.CORERESETP_0.count_ddr[13] EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_ddr_s[13] 9.778 7.667 EDAC_0.CORERESETP_0.count_ddr[12] EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_ddr_s[12] 9.778 7.681 EDAC_0.CORERESETP_0.count_ddr[11] EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_ddr_s[11] 9.778 7.695 EDAC_0.CORERESETP_0.count_ddr[10] EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_ddr_s[10] 9.778 7.709 EDAC_0.CORERESETP_0.count_ddr[9] EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_ddr_s[9] 9.778 7.723 EDAC_0.CORERESETP_0.count_ddr[8] EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_ddr_s[8] 9.778 7.738 EDAC_0.CORERESETP_0.count_ddr[7] EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_ddr_s[7] 9.778 7.752 EDAC_0.CORERESETP_0.count_ddr[6] EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_ddr_s[6] 9.778 7.766 EDAC_0.CORERESETP_0.count_ddr[5] EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_ddr_s[5] 9.778 7.780 EDAC_0.CORERESETP_0.count_ddr[4] EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_ddr_s[4] 9.778 7.795 ===================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 2.111 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 7.667 Number of logic level(s): 14 Starting point: EDAC_0.CORERESETP_0.count_ddr[0] / Q Ending point: EDAC_0.CORERESETP_0.count_ddr[13] / D The start point is clocked by EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock [rising] on pin CLK The end point is clocked by EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------- EDAC_0.CORERESETP_0.count_ddr[0] SLE Q Out 0.094 0.094 - count_ddr[0] Net - - 0.637 - 3 EDAC_0.CORERESETP_0.count_ddr_s_32 ARI1 B In - 0.732 - EDAC_0.CORERESETP_0.count_ddr_s_32 ARI1 FCO Out 0.174 0.906 - count_ddr_s_32_FCO Net - - 0.000 - 1 EDAC_0.CORERESETP_0.count_ddr_cry[1] ARI1 FCI In - 0.906 - EDAC_0.CORERESETP_0.count_ddr_cry[1] ARI1 FCO Out 0.014 0.920 - count_ddr_cry[1] Net - - 0.000 - 1 EDAC_0.CORERESETP_0.count_ddr_cry[2] ARI1 FCI In - 0.920 - EDAC_0.CORERESETP_0.count_ddr_cry[2] ARI1 FCO Out 0.014 0.935 - count_ddr_cry[2] Net - - 0.000 - 1 EDAC_0.CORERESETP_0.count_ddr_cry[3] ARI1 FCI In - 0.935 - EDAC_0.CORERESETP_0.count_ddr_cry[3] ARI1 FCO Out 0.014 0.949 - count_ddr_cry[3] Net - - 0.000 - 1 EDAC_0.CORERESETP_0.count_ddr_cry[4] ARI1 FCI In - 0.949 - EDAC_0.CORERESETP_0.count_ddr_cry[4] ARI1 FCO Out 0.014 0.963 - count_ddr_cry[4] Net - - 0.000 - 1 EDAC_0.CORERESETP_0.count_ddr_cry[5] ARI1 FCI In - 0.963 - EDAC_0.CORERESETP_0.count_ddr_cry[5] ARI1 FCO Out 0.014 0.977 - count_ddr_cry[5] Net - - 0.000 - 1 EDAC_0.CORERESETP_0.count_ddr_cry[6] ARI1 FCI In - 0.977 - EDAC_0.CORERESETP_0.count_ddr_cry[6] ARI1 FCO Out 0.014 0.991 - count_ddr_cry[6] Net - - 0.000 - 1 EDAC_0.CORERESETP_0.count_ddr_cry[7] ARI1 FCI In - 0.991 - EDAC_0.CORERESETP_0.count_ddr_cry[7] ARI1 FCO Out 0.014 1.006 - count_ddr_cry[7] Net - - 0.000 - 1 EDAC_0.CORERESETP_0.count_ddr_cry[8] ARI1 FCI In - 1.006 - EDAC_0.CORERESETP_0.count_ddr_cry[8] ARI1 FCO Out 0.014 1.020 - count_ddr_cry[8] Net - - 0.000 - 1 EDAC_0.CORERESETP_0.count_ddr_cry[9] ARI1 FCI In - 1.020 - EDAC_0.CORERESETP_0.count_ddr_cry[9] ARI1 FCO Out 0.014 1.034 - count_ddr_cry[9] Net - - 0.000 - 1 EDAC_0.CORERESETP_0.count_ddr_cry[10] ARI1 FCI In - 1.034 - EDAC_0.CORERESETP_0.count_ddr_cry[10] ARI1 FCO Out 0.014 1.048 - count_ddr_cry[10] Net - - 0.000 - 1 EDAC_0.CORERESETP_0.count_ddr_cry[11] ARI1 FCI In - 1.048 - EDAC_0.CORERESETP_0.count_ddr_cry[11] ARI1 FCO Out 0.014 1.062 - count_ddr_cry[11] Net - - 0.000 - 1 EDAC_0.CORERESETP_0.count_ddr_cry[12] ARI1 FCI In - 1.062 - EDAC_0.CORERESETP_0.count_ddr_cry[12] ARI1 FCO Out 0.014 1.077 - count_ddr_cry[12] Net - - 0.000 - 1 EDAC_0.CORERESETP_0.count_ddr_s[13] ARI1 FCI In - 1.077 - EDAC_0.CORERESETP_0.count_ddr_s[13] ARI1 S Out 0.063 1.140 - count_ddr_s[13] Net - - 0.971 - 1 EDAC_0.CORERESETP_0.count_ddr[13] SLE D In - 2.111 - ==================================================================================================== Total path delay (propagation time + setup) of 2.333 is 0.724(31.1%) logic and 1.609(68.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ EDAC_0.EDAC_MSS_0.MSS_ADLIB_INST EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_120 MDDR_FABRIC_PRDATA[3] CORECONFIGP_0_MDDR_APBmslave_PRDATA[3] 7.699 0.734 EDAC_0.EDAC_MSS_0.MSS_ADLIB_INST EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_120 MDDR_FABRIC_PRDATA[0] CORECONFIGP_0_MDDR_APBmslave_PRDATA[0] 7.510 0.982 EDAC_0.EDAC_MSS_0.MSS_ADLIB_INST EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_120 MDDR_FABRIC_PRDATA[1] CORECONFIGP_0_MDDR_APBmslave_PRDATA[1] 7.441 1.051 EDAC_0.EDAC_MSS_0.MSS_ADLIB_INST EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_120 MDDR_FABRIC_PRDATA[2] CORECONFIGP_0_MDDR_APBmslave_PRDATA[2] 7.189 1.303 EDAC_0.CORECONFIGP_0.psel EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q psel 0.076 1.864 EDAC_0.CORECONFIGP_0.state[1] EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q state[1] 0.076 2.990 EDAC_0.CORECONFIGP_0.paddr[16] EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q paddr[16] 0.094 3.013 EDAC_0.CORECONFIGP_0.paddr[15] EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q paddr[15] 0.094 3.055 EDAC_0.EDAC_MSS_0.MSS_ADLIB_INST EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_120 MDDR_FABRIC_PREADY CORECONFIGP_0_MDDR_APBmslave_PREADY 4.422 3.369 EDAC_0.EDAC_MSS_0.MSS_ADLIB_INST EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_120 MDDR_FABRIC_PRDATA[5] CORECONFIGP_0_MDDR_APBmslave_PRDATA[5] 4.329 3.613 ==================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------- EDAC_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[3] EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[3] 9.778 0.734 EDAC_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[0] EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[0] 9.778 0.982 EDAC_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[1] EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[1] 9.778 1.051 EDAC_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[2] EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[2] 9.778 1.303 EDAC_0.CORECONFIGP_0.FIC_2_APB_M_PREADY EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN FIC_2_APB_M_PREADY_RNO 4.707 1.864 EDAC_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[4] EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[4] 4.778 1.968 EDAC_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[5] EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[5] 4.778 1.968 EDAC_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[6] EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[6] 4.778 1.968 EDAC_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[7] EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[7] 4.778 1.968 EDAC_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[8] EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[8] 4.778 1.968 ========================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 9.044 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 0.734 Number of logic level(s): 1 Starting point: EDAC_0.EDAC_MSS_0.MSS_ADLIB_INST / MDDR_FABRIC_PRDATA[3] Ending point: EDAC_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[3] / D The start point is clocked by EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock [rising] on pin CLK_MDDR_APB The end point is clocked by EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------- EDAC_0.EDAC_MSS_0.MSS_ADLIB_INST MSS_120 MDDR_FABRIC_PRDATA[3] Out 7.699 7.699 - CORECONFIGP_0_MDDR_APBmslave_PRDATA[3] Net - - 0.971 - 1 EDAC_0.CORECONFIGP_0.prdata_0_iv[3] CFG4 D In - 8.670 - EDAC_0.CORECONFIGP_0.prdata_0_iv[3] CFG4 Y Out 0.236 8.906 - prdata[3] Net - - 0.138 - 1 EDAC_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[3] SLE D In - 9.044 - ============================================================================================================================= Total path delay (propagation time + setup) of 9.266 is 8.157(88.0%) logic and 1.109(12.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied None Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 136MB peak: 138MB) Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 136MB peak: 138MB) --------------------------------------- Resource Usage Report for EDAC_top Mapping to part: m2s150tsfc1152-1 Cell usage: CCC 1 use CLKINT 6 uses MSS_120 1 use RCOSC_25_50MHZ 1 use RCOSC_25_50MHZ_FAB 1 use SYSRESET 1 use CFG1 4 uses CFG2 15 uses CFG3 14 uses CFG4 34 uses Carry cells: ARI1 14 uses - used for arithmetic functions Sequential Cells: SLE 125 uses DSP Blocks: 0 of 240 (0%) I/O ports: 96 I/O primitives: 89 BIBUF 41 uses BIBUF_DIFF 5 uses INBUF 4 uses OUTBUF 38 uses OUTBUF_DIFF 1 use Global Clock Buffers: 6 of 8 (75%) Total LUTs: 81 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 0; LUTs = 0; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 125 + 0 + 0 + 0 = 125; Total number of LUTs after P&R: 81 + 0 + 0 + 0 = 81; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 28MB peak: 138MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Mar 14 14:32:54 2017 ###########################################################]