@W: BN132 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance EDAC_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance EDAC_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MO129 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":676:4:676:9|Sequential instance EDAC_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance EDAC_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance EDAC_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance EDAC_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance EDAC_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":676:4:676:9|Sequential instance EDAC_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance EDAC_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance EDAC_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance EDAC_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance EDAC_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":676:4:676:9|Sequential instance EDAC_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance EDAC_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance EDAC_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance EDAC_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sequential instance EDAC_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation.
@W: MT530 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":447:4:447:9|Found inferred clock EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock which controls 109 sequential elements including EDAC_0.CORECONFIGP_0.FIC_2_APB_M_PREADY. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Found inferred clock EDAC_CCC_0_FCCC|GL0_net_inferred_clock which controls 38 sequential elements including EDAC_0.CORERESETP_0.count_ddr_enable. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Found inferred clock EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 31 sequential elements including EDAC_0.CORERESETP_0.count_ddr[13:0]. This clock has no specified timing constraint which may adversely impact design performance. 
