@W: BN132 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":884:4:884:9|Removing sequential instance EDAC_0.CORERESETP_0.sdif1_areset_n_rcosc_q1 because it is equivalent to instance EDAC_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":912:4:912:9|Removing sequential instance EDAC_0.CORERESETP_0.sdif3_areset_n_rcosc_q1 because it is equivalent to instance EDAC_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":898:4:898:9|Removing sequential instance EDAC_0.CORERESETP_0.sdif2_areset_n_rcosc_q1 because it is equivalent to instance EDAC_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":856:4:856:9|Removing sequential instance EDAC_0.CORERESETP_0.sm0_areset_n_rcosc_q1 because it is equivalent to instance EDAC_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":898:4:898:9|Removing sequential instance EDAC_0.CORERESETP_0.sdif2_areset_n_rcosc because it is equivalent to instance EDAC_0.CORERESETP_0.sm0_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":912:4:912:9|Removing sequential instance EDAC_0.CORERESETP_0.sdif3_areset_n_rcosc because it is equivalent to instance EDAC_0.CORERESETP_0.sm0_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":884:4:884:9|Removing sequential instance EDAC_0.CORERESETP_0.sdif1_areset_n_rcosc because it is equivalent to instance EDAC_0.CORERESETP_0.sm0_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":870:4:870:9|Removing sequential instance EDAC_0.CORERESETP_0.sdif0_areset_n_rcosc because it is equivalent to instance EDAC_0.CORERESETP_0.sm0_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Removing sequential instance EDAC_0.CORERESETP_0.release_sdif3_core because it is equivalent to instance EDAC_0.CORERESETP_0.release_sdif2_core. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Removing sequential instance EDAC_0.CORERESETP_0.release_sdif2_core because it is equivalent to instance EDAC_0.CORERESETP_0.release_sdif1_core. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MO160 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[31] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[30] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[29] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[28] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[27] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[26] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[25] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[24] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[23] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[22] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[21] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[20] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[19] (in view view:work.CoreConfigP_Z1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MT246 :"f:\11.8\sf2_edac_ddr_df\ddr_edac\component\work\edac\ccc_0\edac_ccc_0_fccc.v":20:36:20:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock EDAC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:EDAC_0.FABOSC_0.RCOSC_25_50MHZ_CCC"
@W: MT420 |Found inferred clock EDAC_MSS|FIC_2_APB_M_PCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:EDAC_0.EDAC_MSS_0.FIC_2_APB_M_PCLK"
@W: MT420 |Found inferred clock EDAC_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:EDAC_0.CCC_0.GL0_net"
