//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Tue Mar 14 14:32:42 2017
// Version: v11.8 11.8.0.26
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

// EDAC_top
module EDAC_top(
    // Inputs
    DEVRST_N,
    MDDR_DQS_TMATCH_0_IN,
    MDDR_DQS_TMATCH_1_IN,
    MDDR_DQS_TMATCH_ECC_IN,
    MMUART_0_RXD_F2M,
    // Outputs
    EDAC_ERROR,
    MDDR_ADDR,
    MDDR_BA,
    MDDR_CAS_N,
    MDDR_CKE,
    MDDR_CLK,
    MDDR_CLK_N,
    MDDR_CS_N,
    MDDR_DQS_TMATCH_0_OUT,
    MDDR_DQS_TMATCH_1_OUT,
    MDDR_DQS_TMATCH_ECC_OUT,
    MDDR_ODT,
    MDDR_RAS_N,
    MDDR_RESET_N,
    MDDR_WE_N,
    MMUART_0_TXD_M2F,
    // Inouts
    MDDR_DM_RDQS,
    MDDR_DM_RDQS_ECC,
    MDDR_DQ,
    MDDR_DQS,
    MDDR_DQS_ECC,
    MDDR_DQS_ECC_N,
    MDDR_DQS_N,
    MDDR_DQ_ECC
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input         DEVRST_N;
input         MDDR_DQS_TMATCH_0_IN;
input         MDDR_DQS_TMATCH_1_IN;
input         MDDR_DQS_TMATCH_ECC_IN;
input         MMUART_0_RXD_F2M;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output [7:0]  EDAC_ERROR;
output [15:0] MDDR_ADDR;
output [2:0]  MDDR_BA;
output        MDDR_CAS_N;
output        MDDR_CKE;
output        MDDR_CLK;
output        MDDR_CLK_N;
output        MDDR_CS_N;
output        MDDR_DQS_TMATCH_0_OUT;
output        MDDR_DQS_TMATCH_1_OUT;
output        MDDR_DQS_TMATCH_ECC_OUT;
output        MDDR_ODT;
output        MDDR_RAS_N;
output        MDDR_RESET_N;
output        MDDR_WE_N;
output        MMUART_0_TXD_M2F;
//--------------------------------------------------------------------
// Inout
//--------------------------------------------------------------------
inout  [3:0]  MDDR_DM_RDQS;
inout         MDDR_DM_RDQS_ECC;
inout  [31:0] MDDR_DQ;
inout  [3:0]  MDDR_DQS;
inout         MDDR_DQS_ECC;
inout         MDDR_DQS_ECC_N;
inout  [3:0]  MDDR_DQS_N;
inout  [3:0]  MDDR_DQ_ECC;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire          DEVRST_N;
wire   [7:0]  EDAC_ERROR_net_0;
wire   [15:0] MDDR_ADDR_net_0;
wire   [2:0]  MDDR_BA_net_0;
wire          MDDR_CAS_N_net_0;
wire          MDDR_CKE_net_0;
wire          MDDR_CLK_net_0;
wire          MDDR_CLK_N_net_0;
wire          MDDR_CS_N_net_0;
wire   [3:0]  MDDR_DM_RDQS;
wire          MDDR_DM_RDQS_ECC;
wire   [31:0] MDDR_DQ;
wire   [3:0]  MDDR_DQ_ECC;
wire   [3:0]  MDDR_DQS;
wire          MDDR_DQS_ECC;
wire          MDDR_DQS_ECC_N;
wire   [3:0]  MDDR_DQS_N;
wire          MDDR_DQS_TMATCH_0_IN;
wire          MDDR_DQS_TMATCH_0_OUT_net_0;
wire          MDDR_DQS_TMATCH_1_IN;
wire          MDDR_DQS_TMATCH_1_OUT_2;
wire          MDDR_DQS_TMATCH_ECC_IN;
wire          MDDR_DQS_TMATCH_ECC_OUT_net_0;
wire          MDDR_ODT_net_0;
wire          MDDR_RAS_N_net_0;
wire          MDDR_RESET_N_net_0;
wire          MDDR_WE_N_net_0;
wire          MMUART_0_RXD_F2M;
wire          MMUART_0_TXD_M2F_net_0;
wire          MMUART_0_TXD_M2F_net_1;
wire          MDDR_DQS_TMATCH_0_OUT_net_1;
wire          MDDR_CAS_N_net_1;
wire          MDDR_CLK_net_1;
wire          MDDR_CLK_N_net_1;
wire          MDDR_CKE_net_1;
wire          MDDR_CS_N_net_1;
wire          MDDR_ODT_net_1;
wire          MDDR_RAS_N_net_1;
wire          MDDR_RESET_N_net_1;
wire          MDDR_WE_N_net_1;
wire          MDDR_DQS_TMATCH_ECC_OUT_net_1;
wire          MDDR_DQS_TMATCH_1_OUT_2_net_0;
wire   [7:0]  EDAC_ERROR_net_1;
wire   [15:0] MDDR_ADDR_net_1;
wire   [2:0]  MDDR_BA_net_1;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire          VCC_net;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign VCC_net = 1'b1;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign MMUART_0_TXD_M2F_net_1        = MMUART_0_TXD_M2F_net_0;
assign MMUART_0_TXD_M2F              = MMUART_0_TXD_M2F_net_1;
assign MDDR_DQS_TMATCH_0_OUT_net_1   = MDDR_DQS_TMATCH_0_OUT_net_0;
assign MDDR_DQS_TMATCH_0_OUT         = MDDR_DQS_TMATCH_0_OUT_net_1;
assign MDDR_CAS_N_net_1              = MDDR_CAS_N_net_0;
assign MDDR_CAS_N                    = MDDR_CAS_N_net_1;
assign MDDR_CLK_net_1                = MDDR_CLK_net_0;
assign MDDR_CLK                      = MDDR_CLK_net_1;
assign MDDR_CLK_N_net_1              = MDDR_CLK_N_net_0;
assign MDDR_CLK_N                    = MDDR_CLK_N_net_1;
assign MDDR_CKE_net_1                = MDDR_CKE_net_0;
assign MDDR_CKE                      = MDDR_CKE_net_1;
assign MDDR_CS_N_net_1               = MDDR_CS_N_net_0;
assign MDDR_CS_N                     = MDDR_CS_N_net_1;
assign MDDR_ODT_net_1                = MDDR_ODT_net_0;
assign MDDR_ODT                      = MDDR_ODT_net_1;
assign MDDR_RAS_N_net_1              = MDDR_RAS_N_net_0;
assign MDDR_RAS_N                    = MDDR_RAS_N_net_1;
assign MDDR_RESET_N_net_1            = MDDR_RESET_N_net_0;
assign MDDR_RESET_N                  = MDDR_RESET_N_net_1;
assign MDDR_WE_N_net_1               = MDDR_WE_N_net_0;
assign MDDR_WE_N                     = MDDR_WE_N_net_1;
assign MDDR_DQS_TMATCH_ECC_OUT_net_1 = MDDR_DQS_TMATCH_ECC_OUT_net_0;
assign MDDR_DQS_TMATCH_ECC_OUT       = MDDR_DQS_TMATCH_ECC_OUT_net_1;
assign MDDR_DQS_TMATCH_1_OUT_2_net_0 = MDDR_DQS_TMATCH_1_OUT_2;
assign MDDR_DQS_TMATCH_1_OUT         = MDDR_DQS_TMATCH_1_OUT_2_net_0;
assign EDAC_ERROR_net_1              = EDAC_ERROR_net_0;
assign EDAC_ERROR[7:0]               = EDAC_ERROR_net_1;
assign MDDR_ADDR_net_1               = MDDR_ADDR_net_0;
assign MDDR_ADDR[15:0]               = MDDR_ADDR_net_1;
assign MDDR_BA_net_1                 = MDDR_BA_net_0;
assign MDDR_BA[2:0]                  = MDDR_BA_net_1;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------EDAC
EDAC EDAC_0(
        // Inputs
        .MDDR_DQS_TMATCH_1_IN    ( MDDR_DQS_TMATCH_1_IN ),
        .MDDR_DQS_TMATCH_0_IN    ( MDDR_DQS_TMATCH_0_IN ),
        .FAB_RESET_N             ( VCC_net ),
        .MDDR_DQS_TMATCH_ECC_IN  ( MDDR_DQS_TMATCH_ECC_IN ),
        .DEVRST_N                ( DEVRST_N ),
        .MMUART_0_RXD_F2M        ( MMUART_0_RXD_F2M ),
        // Outputs
        .MDDR_DQS_TMATCH_0_OUT   ( MDDR_DQS_TMATCH_0_OUT_net_0 ),
        .MDDR_CAS_N              ( MDDR_CAS_N_net_0 ),
        .MDDR_CLK                ( MDDR_CLK_net_0 ),
        .MDDR_CLK_N              ( MDDR_CLK_N_net_0 ),
        .MDDR_CKE                ( MDDR_CKE_net_0 ),
        .MDDR_CS_N               ( MDDR_CS_N_net_0 ),
        .MDDR_ODT                ( MDDR_ODT_net_0 ),
        .MDDR_RAS_N              ( MDDR_RAS_N_net_0 ),
        .MDDR_RESET_N            ( MDDR_RESET_N_net_0 ),
        .MDDR_WE_N               ( MDDR_WE_N_net_0 ),
        .MDDR_DQS_TMATCH_1_OUT   ( MDDR_DQS_TMATCH_1_OUT_2 ),
        .POWER_ON_RESET_N        (  ),
        .INIT_DONE               (  ),
        .MDDR_DQS_TMATCH_ECC_OUT ( MDDR_DQS_TMATCH_ECC_OUT_net_0 ),
        .DDR_READY               (  ),
        .FAB_CCC_GL0             (  ),
        .FAB_CCC_LOCK            (  ),
        .MSS_READY               (  ),
        .MMUART_0_TXD_M2F        ( MMUART_0_TXD_M2F_net_0 ),
        .MDDR_ADDR               ( MDDR_ADDR_net_0 ),
        .MDDR_BA                 ( MDDR_BA_net_0 ),
        .EDAC_ERROR              ( EDAC_ERROR_net_0 ),
        // Inouts
        .MDDR_DM_RDQS_ECC        ( MDDR_DM_RDQS_ECC ),
        .MDDR_DQS_ECC            ( MDDR_DQS_ECC ),
        .MDDR_DQS_ECC_N          ( MDDR_DQS_ECC_N ),
        .MDDR_DM_RDQS            ( MDDR_DM_RDQS ),
        .MDDR_DQ                 ( MDDR_DQ ),
        .MDDR_DQS                ( MDDR_DQS ),
        .MDDR_DQS_N              ( MDDR_DQS_N ),
        .MDDR_DQ_ECC             ( MDDR_DQ_ECC ) 
        );


endmodule
