Microsemi Corporation - Microsemi Libero Software Release v11.8 (Version 11.8.0.26)

Date      :  Tue Mar 14 12:54:15 2017
Project   :  F:\11.8\SF2_EDAC_DDR_DF\DDR_EDAC
Component :  EDAC
Family    :  SmartFusion2


HDL source files for all Synthesis and Simulation tools:
    F:/11.8/SF2_EDAC_DDR_DF/DDR_EDAC/component/Actel/DirectCore/CoreConfigP/7.1.100/rtl/vlog/core/coreconfigp.v
    F:/11.8/SF2_EDAC_DDR_DF/DDR_EDAC/component/Actel/DirectCore/CoreResetP/7.1.100/rtl/vlog/core/coreresetp.v
    F:/11.8/SF2_EDAC_DDR_DF/DDR_EDAC/component/Actel/DirectCore/CoreResetP/7.1.100/rtl/vlog/core/coreresetp_pcie_hotreset.v
    F:/11.8/SF2_EDAC_DDR_DF/DDR_EDAC/component/work/EDAC/CCC_0/EDAC_CCC_0_FCCC.v
    F:/11.8/SF2_EDAC_DDR_DF/DDR_EDAC/component/work/EDAC/EDAC.v
    F:/11.8/SF2_EDAC_DDR_DF/DDR_EDAC/component/work/EDAC/FABOSC_0/EDAC_FABOSC_0_OSC.v
    F:/11.8/SF2_EDAC_DDR_DF/DDR_EDAC/component/work/EDAC_MSS/EDAC_MSS.v

HDL source files for Synopsys SynplifyPro Synthesis tool:
    F:/11.8/SF2_EDAC_DDR_DF/DDR_EDAC/component/Actel/SgCore/OSC/2.0.101/osc_comps.v
    F:/11.8/SF2_EDAC_DDR_DF/DDR_EDAC/component/work/EDAC_MSS/EDAC_MSS_syn.v

HDL source files for Mentor Precision Synthesis tool:
    F:/11.8/SF2_EDAC_DDR_DF/DDR_EDAC/component/Actel/SgCore/OSC/2.0.101/osc_comps_pre.v
    F:/11.8/SF2_EDAC_DDR_DF/DDR_EDAC/component/work/EDAC_MSS/EDAC_MSS_pre.v

Stimulus files for all Simulation tools:
    F:/11.8/SF2_EDAC_DDR_DF/DDR_EDAC/component/Actel/SmartFusion2MSS/MSS/1.1.500/peripheral_init.bfm
    F:/11.8/SF2_EDAC_DDR_DF/DDR_EDAC/component/work/EDAC_MSS/CM3_compile_bfm.tcl
    F:/11.8/SF2_EDAC_DDR_DF/DDR_EDAC/component/work/EDAC_MSS/test.bfm
    F:/11.8/SF2_EDAC_DDR_DF/DDR_EDAC/component/work/EDAC_MSS/user.bfm

Firmware files for all Software IDE tools:
    F:/11.8/SF2_EDAC_DDR_DF/DDR_EDAC/component/work/EDAC_MSS/sys_config_mddr_define.h
    F:/11.8/SF2_EDAC_DDR_DF/DDR_EDAC/component/work/EDAC_MSS/sys_config_mss_clocks.h

Configuration files to be used for Programming:
    F:/11.8/SF2_EDAC_DDR_DF/DDR_EDAC/component/work/EDAC_MSS/ENVM.cfg

Configuration files to be used for all Simulation tools:
    F:/11.8/SF2_EDAC_DDR_DF/DDR_EDAC/component/work/EDAC_MSS/ENVM.cfg
    F:/11.8/SF2_EDAC_DDR_DF/DDR_EDAC/component/work/EDAC_MSS/MDDR_init.bfm

Configuration files to be used for Power Analysis:
    F:/11.8/SF2_EDAC_DDR_DF/DDR_EDAC/component/work/EDAC_MSS/MDDR_init.reg

