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<doc>
<title>Compile Report</title>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.8 (Version 11.8.0.26)</text>
<text>Date: Tue Mar 14 14:33:04 2017
</text>
<section><name>Device Selection</name></section>
<table>
<header>
</header>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Device</cell>
 <cell>M2S150TS</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>1152 FC</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Temp</cell>
 <cell>-40:25:100</cell>
</row>
<row>
 <cell>Voltage</cell>
 <cell>1.26:1.20:1.14</cell>
</row>
<row>
 <cell>Core Voltage</cell>
 <cell>1.2V</cell>
</row>
<row>
 <cell>Ramp Rate</cell>
 <cell>100ms Minimum</cell>
</row>
<row>
 <cell>System Controller Suspend Mode</cell>
 <cell>No</cell>
</row>
<row>
 <cell>PLL Supply Voltage</cell>
 <cell>2.5V</cell>
</row>
<row>
 <cell>Default I/O technology</cell>
 <cell>LVCMOS 2.5V</cell>
</row>
<row>
 <cell>Restrict Probe Pins</cell>
 <cell>Yes</cell>
</row>
<row>
 <cell>Restrict SPI Pins</cell>
 <cell>No</cell>
</row>
</table>
<section><name>Source Files</name></section>
<table>
<header>
</header>
<row>
 <cell>Topcell</cell>
 <cell>EDAC_top</cell>
</row>
<row>
 <cell>Format</cell>
 <cell>EDIF</cell>
</row>
<row>
 <cell>Source</cell>
 <cell>F:\11.8\SF2_EDAC_DDR_DF\DDR_EDAC\synthesis\EDAC_top.edn</cell>
</row>
<row>
 <cell>Source</cell>
 <cell>F:\11.8\SF2_EDAC_DDR_DF\DDR_EDAC\constraint\tim_con.sdc</cell>
</row>
<row>
 <cell>Source</cell>
 <cell>F:\11.8\SF2_EDAC_DDR_DF\DDR_EDAC\constraint\io\EDAC_top.io.pdc</cell>
</row>
</table>
<section><name>Options</name></section>
<table>
<header>
</header>
<row>
 <cell>Merge User SDC file(s) with Existing Timing Constraints</cell>
 <cell>true</cell>
</row>
<row>
 <cell>Abort Compile if errors are found in PDC file(s)</cell>
 <cell>true</cell>
</row>
<row>
 <cell>Enable Single Event Transient mitigation</cell>
 <cell>false</cell>
</row>
<row>
 <cell>Enable Design Separation Methodology</cell>
 <cell>false</cell>
</row>
<row>
 <cell>Limit the number of high fanout nets to display to</cell>
 <cell>10</cell>
</row>
</table>
<section><name>Resource Usage</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Used</cell>
 <cell>Total</cell>
 <cell>Percentage</cell>
</header>
<row>
 <cell>4LUT</cell>
 <cell>81</cell>
 <cell>146124</cell>
 <cell>0.06</cell>
</row>
<row>
 <cell>DFF</cell>
 <cell>125</cell>
 <cell>146124</cell>
 <cell>0.09</cell>
</row>
<row>
 <cell>I/O Register</cell>
 <cell>0</cell>
 <cell>1716</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>User I/O</cell>
 <cell>95</cell>
 <cell>572</cell>
 <cell>16.61</cell>
</row>
<row>
 <cell>-- Single-ended I/O</cell>
 <cell>83</cell>
 <cell>572</cell>
 <cell>14.51</cell>
</row>
<row>
 <cell>-- Differential I/O Pairs</cell>
 <cell>6</cell>
 <cell>286</cell>
 <cell>2.10</cell>
</row>
<row>
 <cell>RAM64x18</cell>
 <cell>0</cell>
 <cell>240</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>RAM1K18</cell>
 <cell>0</cell>
 <cell>236</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>MACC</cell>
 <cell>0</cell>
 <cell>240</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>Chip Globals</cell>
 <cell>6</cell>
 <cell>16</cell>
 <cell>37.50</cell>
</row>
<row>
 <cell>CCC</cell>
 <cell>1</cell>
 <cell>8</cell>
 <cell>12.50</cell>
</row>
<row>
 <cell>RCOSC_25_50MHZ</cell>
 <cell>1</cell>
 <cell>1</cell>
 <cell>100.00</cell>
</row>
<row>
 <cell>RCOSC_1MHZ</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>XTLOSC</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>SERDESIF Blocks</cell>
 <cell>0</cell>
 <cell>4</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>-- SERDESIF Lanes</cell>
 <cell>0</cell>
 <cell>16</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>FDDR</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>MSS</cell>
 <cell>1</cell>
 <cell>1</cell>
 <cell>100.00</cell>
</row>
</table>
<section><name>Detailed Logic Resource Usage</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>4LUT</cell>
 <cell>DFF</cell>
</header>
<row>
 <cell>Fabric Logic</cell>
 <cell>81</cell>
 <cell>125</cell>
</row>
<row>
 <cell>RAM64x18 Interface Logic</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>RAM1K18 Interface Logic</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>MACC Interface Logic</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Total Used</cell>
 <cell>81</cell>
 <cell>125</cell>
</row>
</table>
<section><name>MSS Resource Usage</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Used</cell>
 <cell>Total</cell>
</header>
<row>
 <cell>Cortex-M3*</cell>
 <cell>1</cell>
 <cell>1</cell>
</row>
<row>
 <cell>eNVM (512KB)*</cell>
 <cell>1</cell>
 <cell>1</cell>
</row>
<row>
 <cell>eSRAM*</cell>
 <cell>2</cell>
 <cell>2</cell>
</row>
<row>
 <cell>TIMER*</cell>
 <cell>2</cell>
 <cell>2</cell>
</row>
<row>
 <cell>CAN</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>SPI</cell>
 <cell>0</cell>
 <cell>2</cell>
</row>
<row>
 <cell>I2C</cell>
 <cell>0</cell>
 <cell>2</cell>
</row>
<row>
 <cell>UART</cell>
 <cell>1</cell>
 <cell>2</cell>
</row>
<row>
 <cell>USB</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>MAC</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>MDDR</cell>
 <cell>1</cell>
 <cell>1</cell>
</row>
<row>
 <cell>HPDMA</cell>
 <cell>1</cell>
 <cell>1</cell>
</row>
<row>
 <cell>PDMA</cell>
 <cell>1</cell>
 <cell>1</cell>
</row>
</table>
<text>* These resources are always marked as used when you are using the MSS</text>
<text></text>
<section><name>Detailed Carry Chains Resource Usage</name></section>
<table>
<header>
</header>
<row>
 <cell>Length</cell>
 <cell>Used</cell>
</row>
<row>
 <cell>14</cell>
 <cell>1</cell>
</row>
<row>
 <cell>Total</cell>
 <cell>1</cell>
</row>
</table>
<section><name>I/O Function</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>w/o register</cell>
 <cell>w/ register</cell>
 <cell>w/ DDR register</cell>
</header>
<row>
 <cell>Input I/O</cell>
 <cell>4</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Output I/O</cell>
 <cell>38</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Bidirectional I/O</cell>
 <cell>41</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Differential Input I/O Pairs</cell>
 <cell>0</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Differential Output I/O Pairs</cell>
 <cell>1</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Differential Bidirectional I/O Pairs</cell>
 <cell>5</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
</table>
<section><name>I/O Technology</name></section>
<table>
<header>
 <cell>I/O Standard</cell>
 <cell>Vddi</cell>
 <cell>Vref</cell>
 <cell>Input</cell>
 <cell>Output</cell>
 <cell>Bidirectional</cell>
</header>
<row>
 <cell>LVCMOS25</cell>
 <cell> 2.50v</cell>
 <cell> N/A</cell>
 <cell> 1</cell>
 <cell> 9</cell>
 <cell> 0</cell>
</row>
<row>
 <cell>SSTL15I (Input/Bidirectional)</cell>
 <cell> 1.50v</cell>
 <cell> 0.75v</cell>
 <cell> 3</cell>
 <cell> 0</cell>
 <cell> 51</cell>
</row>
<row>
 <cell>SSTL15I (Output)</cell>
 <cell> 1.50v</cell>
 <cell> N/A</cell>
 <cell> 0</cell>
 <cell> 31</cell>
 <cell> 0</cell>
</row>
</table>
<section><name>I/O Placement</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Count</cell>
 <cell>Percentage</cell>
</header>
<row>
 <cell>Locked</cell>
 <cell> 95</cell>
 <cell>100.00%</cell>
</row>
<row>
 <cell>Placed</cell>
 <cell> 0</cell>
 <cell>0.00%</cell>
</row>
<row>
 <cell>UnPlaced</cell>
 <cell> 0</cell>
 <cell>0.00%</cell>
</row>
</table>
<section><name>Nets assigned to chip global resources</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>78</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/CORECONFIGP_0_APB_S_PRESET_N</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>76</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/CORECONFIGP_0_APB_S_PCLK</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>31</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/GL0_INST</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/CCC_0/GL0_INST/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>20</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/FABOSC_0_RCOSC_25_50MHZ_O2F</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>19</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/CORERESETP_0/sm0_areset_n_clk_base</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/CORERESETP_0/sm0_areset_n_clk_base_RNIMUV2/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>18</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/CORERESETP_0/sm0_areset_n_rcosc</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
</table>
<section><name>Nets assigned to row global resources</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
</table>
<section><name>High fanout nets</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>32</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/CORECONFIGP_0/state_455_d</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/CORECONFIGP_0/state_s0_0_a2</cell>
</row>
<row>
 <cell>25</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/CORECONFIGP_0/state[1]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/CORECONFIGP_0/state[1]</cell>
</row>
<row>
 <cell>19</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/CORECONFIGP_0_MDDR_APBmslave_PSELx</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/CORECONFIGP_0/psel_RNI26NO1</cell>
</row>
<row>
 <cell>17</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/CORECONFIGP_0/soft_reset_reg6</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/CORECONFIGP_0/soft_reset_reg6</cell>
</row>
<row>
 <cell>15</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/CORECONFIGP_0/int_prdata_4_sqmuxa</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/CORECONFIGP_0/int_prdata_4_sqmuxa</cell>
</row>
<row>
 <cell>14</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/CORERESETP_0/count_ddr_enable_rcosc</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/CORERESETP_0/count_ddr_enable_rcosc</cell>
</row>
<row>
 <cell>7</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/EDAC_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[2]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST</cell>
</row>
<row>
 <cell>7</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/EDAC_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[3]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST</cell>
</row>
<row>
 <cell>7</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/EDAC_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[4]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST</cell>
</row>
<row>
 <cell>5</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/CORECONFIGP_0/paddr[13]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/CORECONFIGP_0/paddr[13]</cell>
</row>
</table>
<section><name>High fanout nets (through buffer trees)</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>32</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/CORECONFIGP_0/state_455_d</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/CORECONFIGP_0/state_s0_0_a2</cell>
</row>
<row>
 <cell>25</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/CORECONFIGP_0/state[1]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/CORECONFIGP_0/state[1]</cell>
</row>
<row>
 <cell>19</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/CORECONFIGP_0_MDDR_APBmslave_PSELx</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/CORECONFIGP_0/psel_RNI26NO1</cell>
</row>
<row>
 <cell>17</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/CORECONFIGP_0/soft_reset_reg6</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/CORECONFIGP_0/soft_reset_reg6</cell>
</row>
<row>
 <cell>15</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/CORECONFIGP_0/int_prdata_4_sqmuxa</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/CORECONFIGP_0/int_prdata_4_sqmuxa</cell>
</row>
<row>
 <cell>14</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/CORERESETP_0/count_ddr_enable_rcosc</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/CORERESETP_0/count_ddr_enable_rcosc</cell>
</row>
<row>
 <cell>7</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/EDAC_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[2]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST</cell>
</row>
<row>
 <cell>7</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/EDAC_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[3]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST</cell>
</row>
<row>
 <cell>7</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/EDAC_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[4]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST</cell>
</row>
<row>
 <cell>5</cell>
 <cell>INT_NET</cell>
 <cell>Net   : EDAC_0/CORECONFIGP_0/paddr[13]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: EDAC_0/CORECONFIGP_0/paddr[13]</cell>
</row>
</table>
</doc>
