<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
<doc>
<title>Timing Report Max Delay Analysis
</title>
<text>SmartTime Version 11.8.0.26</text>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.8 (Version 11.8.0.26)</text>
<text>Date: Tue Mar 14 14:51:34 2017
</text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>EDAC_top</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2S150TS</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>1152 FC</cell>
</row>
<row>
 <cell>Temperature Range</cell>
 <cell>-40 - 100 C</cell>
</row>
<row>
 <cell>Voltage Range</cell>
 <cell>1.14 - 1.26 V</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Design State</cell>
 <cell>Post-Layout</cell>
</row>
<row>
 <cell>Data source</cell>
 <cell>Production</cell>
</row>
<row>
 <cell>Min Operating Conditions</cell>
 <cell>BEST - 1.26 V - -40 C</cell>
</row>
<row>
 <cell>Max Operating Conditions</cell>
 <cell>WORST - 1.14 V - 100 C</cell>
</row>
<row>
 <cell>Scenario for Timing Analysis</cell>
 <cell>Primary</cell>
</row>
</table>
<text></text>
<section>
<name>Summary</name>
<table>
<header>
 <cell>Clock Domain</cell>
 <cell>Period (ns)</cell>
 <cell>Frequency (MHz)</cell>
 <cell>Required Period (ns)</cell>
 <cell>Required Frequency (MHz)</cell>
 <cell>External Setup (ns)</cell>
 <cell>External Hold (ns)</cell>
 <cell>Min Clock-To-Out (ns)</cell>
 <cell>Max Clock-To-Out (ns)</cell>
</header>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>4.857</cell>
 <cell>205.888</cell>
 <cell>10.000</cell>
 <cell>100.000</cell>
 <cell>1.670</cell>
 <cell>-0.743</cell>
 <cell>6.748</cell>
 <cell>11.318</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>3.463</cell>
 <cell>288.767</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell>8.511</cell>
 <cell>117.495</cell>
 <cell>40.000</cell>
 <cell>25.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
<text></text>
<table>
<header>
 <cell></cell>
 <cell>Min Delay (ns)</cell>
 <cell>Max Delay (ns)</cell>
</header>
<row>
 <cell>Input to Output</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
</section>
<section>
<name>Clock Domain EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<text>Info: The maximum frequency of this clock domain is limited by the period of pin EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</text>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_state[3]:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr_enable:EN</cell>
 <cell>1.261</cell>
 <cell>8.367</cell>
 <cell>5.390</cell>
 <cell>13.757</cell>
 <cell>0.338</cell>
 <cell>1.633</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>EDAC_0/CORERESETP_0/ddr_settled_clk_base:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr_enable:EN</cell>
 <cell>1.222</cell>
 <cell>8.414</cell>
 <cell>5.343</cell>
 <cell>13.757</cell>
 <cell>0.338</cell>
 <cell>1.586</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>EDAC_0/CORERESETP_0/mss_ready_state:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/mss_ready_select:EN</cell>
 <cell>1.130</cell>
 <cell>8.516</cell>
 <cell>5.221</cell>
 <cell>13.737</cell>
 <cell>0.338</cell>
 <cell>1.484</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>EDAC_0/CORERESETP_0/CONFIG2_DONE_clk_base:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_state[6]:EN</cell>
 <cell>1.133</cell>
 <cell>8.527</cell>
 <cell>5.245</cell>
 <cell>13.772</cell>
 <cell>0.338</cell>
 <cell>1.473</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>EDAC_0/CORERESETP_0/sdif3_spll_lock_q2:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr_enable:EN</cell>
 <cell>1.095</cell>
 <cell>8.533</cell>
 <cell>5.224</cell>
 <cell>13.757</cell>
 <cell>0.338</cell>
 <cell>1.467</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORERESETP_0/sm0_state[3]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/CORERESETP_0/count_ddr_enable:EN</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>13.757</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>5.390</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>8.367</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.173</cell>
 <cell>2.173</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.288</cell>
 <cell>2.461</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.144</cell>
 <cell>2.605</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.616</cell>
 <cell>3.221</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.320</cell>
 <cell>3.541</cell>
 <cell>12</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_state[3]:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.588</cell>
 <cell>4.129</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_state[3]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.109</cell>
 <cell>4.238</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/un1_next_ddr_ready_0_sqmuxa:B</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_state[3]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.439</cell>
 <cell>4.677</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/un1_next_ddr_ready_0_sqmuxa:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.166</cell>
 <cell>4.843</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/count_ddr_enable:EN</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/un1_next_ddr_ready_0_sqmuxa</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.547</cell>
 <cell>5.390</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.390</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.173</cell>
 <cell>12.173</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.288</cell>
 <cell>12.461</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.144</cell>
 <cell>12.605</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.613</cell>
 <cell>13.218</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.320</cell>
 <cell>13.538</cell>
 <cell>9</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/count_ddr_enable:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.557</cell>
 <cell>14.095</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/count_ddr_enable:EN</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.338</cell>
 <cell>13.757</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>13.757</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>External Setup (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MMUART_0_RXD_F2M</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_RXD_F2H_SCP</cell>
 <cell>5.098</cell>
 <cell></cell>
 <cell>5.098</cell>
 <cell></cell>
 <cell>0.767</cell>
 <cell>1.670</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MMUART_0_RXD_F2M</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_RXD_F2H_SCP</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>5.098</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MMUART_0_RXD_F2M</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_RXD_F2M_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>MMUART_0_RXD_F2M</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_RXD_F2M_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>2.539</cell>
 <cell>2.539</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_RXD_F2M_ibuf/U0/U_IOINFF:A</cell>
 <cell>net</cell>
 <cell>MMUART_0_RXD_F2M_ibuf/U0/YIN1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.392</cell>
 <cell>2.931</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_RXD_F2M_ibuf/U0/U_IOINFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOINFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.091</cell>
 <cell>3.022</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_241:A</cell>
 <cell>net</cell>
 <cell>MMUART_0_RXD_F2M_c</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.822</cell>
 <cell>4.844</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_241:IPA</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.201</cell>
 <cell>5.045</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_RXD_F2H_SCP</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/MMUART0_RXD_F2H_SCP_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.053</cell>
 <cell>5.098</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.098</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.108</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.279</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.140</cell>
 <cell>N/C</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.592</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.309</cell>
 <cell>N/C</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.438</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.205</cell>
 <cell>N/C</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.124</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_RXD_F2H_SCP</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:MSS_120_IP</cell>
 <cell>-</cell>
 <cell>0.767</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Clock to Output</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Clock to Out (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell>MMUART_0_TXD_M2F</cell>
 <cell>6.993</cell>
 <cell></cell>
 <cell>11.318</cell>
 <cell></cell>
 <cell>11.318</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MMUART_0_TXD_M2F</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>11.318</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.173</cell>
 <cell>2.173</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.288</cell>
 <cell>2.461</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.144</cell>
 <cell>2.605</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.610</cell>
 <cell>3.215</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.319</cell>
 <cell>3.534</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.452</cell>
 <cell>3.986</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.211</cell>
 <cell>4.197</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.128</cell>
 <cell>4.325</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_TXD_MGPIO27B_H2F_A</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MSS_120_IP</cell>
 <cell>+</cell>
 <cell>1.539</cell>
 <cell>5.864</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_TXD_M2F_obuf/U0/U_IOOUTFF:A</cell>
 <cell>net</cell>
 <cell>MMUART_0_TXD_M2F_c</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.791</cell>
 <cell>7.655</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_TXD_M2F_obuf/U0/U_IOOUTFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOOUTFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.347</cell>
 <cell>8.002</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_TXD_M2F_obuf/U0/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>MMUART_0_TXD_M2F_obuf/U0/DOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.562</cell>
 <cell>8.564</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_TXD_M2F_obuf/U0/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>2.754</cell>
 <cell>11.318</cell>
 <cell>0</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_TXD_M2F</cell>
 <cell>net</cell>
 <cell>MMUART_0_TXD_M2F</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>11.318</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>11.318</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.173</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MMUART_0_TXD_M2F</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Recovery (ns)</cell>
 <cell>Minimum Period (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_state[1]:ALn</cell>
 <cell>3.062</cell>
 <cell>6.579</cell>
 <cell>7.164</cell>
 <cell>13.743</cell>
 <cell>0.356</cell>
 <cell>3.421</cell>
 <cell>0.003</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/CONFIG1_DONE_q1:ALn</cell>
 <cell>3.062</cell>
 <cell>6.579</cell>
 <cell>7.164</cell>
 <cell>13.743</cell>
 <cell>0.356</cell>
 <cell>3.421</cell>
 <cell>0.003</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_state[0]:ALn</cell>
 <cell>3.062</cell>
 <cell>6.579</cell>
 <cell>7.164</cell>
 <cell>13.743</cell>
 <cell>0.356</cell>
 <cell>3.421</cell>
 <cell>0.003</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/CONFIG1_DONE_clk_base:ALn</cell>
 <cell>3.062</cell>
 <cell>6.579</cell>
 <cell>7.164</cell>
 <cell>13.743</cell>
 <cell>0.356</cell>
 <cell>3.421</cell>
 <cell>0.003</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/INIT_DONE_int:ALn</cell>
 <cell>3.062</cell>
 <cell>6.579</cell>
 <cell>7.164</cell>
 <cell>13.743</cell>
 <cell>0.356</cell>
 <cell>3.421</cell>
 <cell>0.003</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/CORERESETP_0/sm0_state[1]:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>13.743</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>7.164</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.579</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.173</cell>
 <cell>2.173</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.288</cell>
 <cell>2.461</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.144</cell>
 <cell>2.605</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.617</cell>
 <cell>3.222</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.319</cell>
 <cell>3.541</cell>
 <cell>7</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.561</cell>
 <cell>4.102</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.088</cell>
 <cell>4.190</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base_RNIMUV2:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base_0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.082</cell>
 <cell>5.272</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base_RNIMUV2:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.361</cell>
 <cell>5.633</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base_RNIMUV2/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base_RNIMUV2/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.615</cell>
 <cell>6.248</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base_RNIMUV2/U0_RGB1_RGB0:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.320</cell>
 <cell>6.568</cell>
 <cell>10</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_state[1]:ALn</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base_RNIMUV2/U0_RGB1_RGB0_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.596</cell>
 <cell>7.164</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.164</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.173</cell>
 <cell>12.173</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.288</cell>
 <cell>12.461</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.144</cell>
 <cell>12.605</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.616</cell>
 <cell>13.221</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.320</cell>
 <cell>13.541</cell>
 <cell>12</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_state[1]:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.558</cell>
 <cell>14.099</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_state[1]:ALn</cell>
 <cell>Library recovery time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.356</cell>
 <cell>13.743</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>13.743</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT to EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET FIC2_CLK to EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORECONFIGP_0/control_reg_1[1]:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/CONFIG2_DONE_q1:D</cell>
 <cell>5.012</cell>
 <cell>2.292</cell>
 <cell>11.637</cell>
 <cell>13.929</cell>
 <cell>0.175</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>EDAC_0/CORECONFIGP_0/control_reg_1[0]:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/CONFIG1_DONE_q1:D</cell>
 <cell>4.883</cell>
 <cell>2.441</cell>
 <cell>11.483</cell>
 <cell>13.924</cell>
 <cell>0.175</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>EDAC_0/CORECONFIGP_0/soft_reset_reg[1]:CLK</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:USER_MSS_RESET_N</cell>
 <cell>2.258</cell>
 <cell>5.315</cell>
 <cell>8.874</cell>
 <cell>14.189</cell>
 <cell></cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORECONFIGP_0/control_reg_1[1]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/CORERESETP_0/CONFIG2_DONE_q1:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>13.929</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>11.637</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.292</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>4.766</cell>
 <cell>4.766</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.361</cell>
 <cell>5.127</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.603</cell>
 <cell>5.730</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.319</cell>
 <cell>6.049</cell>
 <cell>53</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/control_reg_1[1]:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.576</cell>
 <cell>6.625</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/control_reg_1[1]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.109</cell>
 <cell>6.734</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/CONFIG2_DONE_q1:D</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORECONFIGP_0_CONFIG2_DONE</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>4.903</cell>
 <cell>11.637</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>11.637</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.173</cell>
 <cell>12.173</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.288</cell>
 <cell>12.461</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.144</cell>
 <cell>12.605</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.613</cell>
 <cell>13.218</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.320</cell>
 <cell>13.538</cell>
 <cell>9</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/CONFIG2_DONE_q1:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.566</cell>
 <cell>14.104</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/CONFIG2_DONE_q1:D</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.175</cell>
 <cell>13.929</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>13.929</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Clock Domain EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[8]:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>2.119</cell>
 <cell>17.482</cell>
 <cell>10.599</cell>
 <cell>28.081</cell>
 <cell>0.338</cell>
 <cell>2.518</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[9]:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>2.058</cell>
 <cell>17.531</cell>
 <cell>10.550</cell>
 <cell>28.081</cell>
 <cell>0.338</cell>
 <cell>2.469</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[4]:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>1.878</cell>
 <cell>17.723</cell>
 <cell>10.358</cell>
 <cell>28.081</cell>
 <cell>0.338</cell>
 <cell>2.277</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[10]:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>1.868</cell>
 <cell>17.733</cell>
 <cell>10.348</cell>
 <cell>28.081</cell>
 <cell>0.338</cell>
 <cell>2.267</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[12]:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>1.886</cell>
 <cell>17.742</cell>
 <cell>10.339</cell>
 <cell>28.081</cell>
 <cell>0.338</cell>
 <cell>2.258</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORERESETP_0/count_ddr[8]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>28.081</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>10.599</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>17.482</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.406</cell>
 <cell>1.406</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.154</cell>
 <cell>1.560</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>5.048</cell>
 <cell>6.608</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.361</cell>
 <cell>6.969</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.621</cell>
 <cell>7.590</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.319</cell>
 <cell>7.909</cell>
 <cell>15</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/count_ddr[8]:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.571</cell>
 <cell>8.480</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/count_ddr[8]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.109</cell>
 <cell>8.589</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/ddr_settled4_7:C</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[8]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.652</cell>
 <cell>9.241</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/ddr_settled4_7:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.211</cell>
 <cell>9.452</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/ddr_settled4:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/ddr_settled4_7</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.306</cell>
 <cell>9.758</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/ddr_settled4:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.290</cell>
 <cell>10.048</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/ddr_settled4</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.551</cell>
 <cell>10.599</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.599</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>20.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.406</cell>
 <cell>21.406</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.154</cell>
 <cell>21.560</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>5.048</cell>
 <cell>26.608</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.361</cell>
 <cell>26.969</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.606</cell>
 <cell>27.575</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.320</cell>
 <cell>27.895</cell>
 <cell>3</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/ddr_settled:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.524</cell>
 <cell>28.419</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.338</cell>
 <cell>28.081</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>28.081</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Recovery (ns)</cell>
 <cell>Minimum Period (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[4]:ALn</cell>
 <cell>3.115</cell>
 <cell>16.537</cell>
 <cell>11.570</cell>
 <cell>28.107</cell>
 <cell>0.356</cell>
 <cell>3.463</cell>
 <cell>-0.008</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[8]:ALn</cell>
 <cell>3.115</cell>
 <cell>16.537</cell>
 <cell>11.570</cell>
 <cell>28.107</cell>
 <cell>0.356</cell>
 <cell>3.463</cell>
 <cell>-0.008</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[10]:ALn</cell>
 <cell>3.115</cell>
 <cell>16.537</cell>
 <cell>11.570</cell>
 <cell>28.107</cell>
 <cell>0.356</cell>
 <cell>3.463</cell>
 <cell>-0.008</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[6]:ALn</cell>
 <cell>3.115</cell>
 <cell>16.537</cell>
 <cell>11.570</cell>
 <cell>28.107</cell>
 <cell>0.356</cell>
 <cell>3.463</cell>
 <cell>-0.008</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[2]:ALn</cell>
 <cell>3.115</cell>
 <cell>16.537</cell>
 <cell>11.570</cell>
 <cell>28.107</cell>
 <cell>0.356</cell>
 <cell>3.463</cell>
 <cell>-0.008</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/CORERESETP_0/count_ddr[4]:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>28.107</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>11.570</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>16.537</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.406</cell>
 <cell>1.406</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.154</cell>
 <cell>1.560</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>5.048</cell>
 <cell>6.608</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.361</cell>
 <cell>6.969</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.621</cell>
 <cell>7.590</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.319</cell>
 <cell>7.909</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.546</cell>
 <cell>8.455</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.088</cell>
 <cell>8.543</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.128</cell>
 <cell>9.671</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.361</cell>
 <cell>10.032</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.617</cell>
 <cell>10.649</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.319</cell>
 <cell>10.968</cell>
 <cell>15</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/count_ddr[4]:ALn</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.602</cell>
 <cell>11.570</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>11.570</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>20.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.406</cell>
 <cell>21.406</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.154</cell>
 <cell>21.560</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>5.048</cell>
 <cell>26.608</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.361</cell>
 <cell>26.969</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.621</cell>
 <cell>27.590</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.319</cell>
 <cell>27.909</cell>
 <cell>15</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/count_ddr[4]:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.554</cell>
 <cell>28.463</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/count_ddr[4]:ALn</cell>
 <cell>Library recovery time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.356</cell>
 <cell>28.107</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>28.107</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain FIC2_CLK</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN</cell>
 <cell>2.956</cell>
 <cell>3.322</cell>
 <cell>2.956</cell>
 <cell>6.278</cell>
 <cell>0.338</cell>
 <cell>-3.322</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell>EDAC_0/CORECONFIGP_0/state[0]:D</cell>
 <cell>2.402</cell>
 <cell>3.949</cell>
 <cell>2.402</cell>
 <cell>6.351</cell>
 <cell>0.256</cell>
 <cell>-3.949</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>EDAC_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[4]:D</cell>
 <cell>2.817</cell>
 <cell>16.528</cell>
 <cell>9.823</cell>
 <cell>26.351</cell>
 <cell>0.256</cell>
 <cell>6.944</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>EDAC_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[15]:D</cell>
 <cell>2.816</cell>
 <cell>16.529</cell>
 <cell>9.822</cell>
 <cell>26.351</cell>
 <cell>0.256</cell>
 <cell>6.942</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>EDAC_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[7]:D</cell>
 <cell>2.816</cell>
 <cell>16.540</cell>
 <cell>9.822</cell>
 <cell>26.362</cell>
 <cell>0.256</cell>
 <cell>6.920</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.278</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>2.956</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.322</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PENABLE</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MSS_120_IP</cell>
 <cell>+</cell>
 <cell>0.313</cell>
 <cell>0.313</cell>
 <cell>3</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/next_state4:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.758</cell>
 <cell>2.071</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/next_state4:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2</cell>
 <cell>+</cell>
 <cell>0.145</cell>
 <cell>2.216</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PREADY_RNO:B</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORECONFIGP_0/next_state4</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.101</cell>
 <cell>2.317</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PREADY_RNO:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.088</cell>
 <cell>2.405</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PREADY_RNO</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.551</cell>
 <cell>2.956</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.956</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell>Max Delay Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>4.766</cell>
 <cell>4.766</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.361</cell>
 <cell>5.127</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.603</cell>
 <cell>5.730</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.319</cell>
 <cell>6.049</cell>
 <cell>53</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.567</cell>
 <cell>6.616</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.338</cell>
 <cell>6.278</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.278</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to FIC2_CLK</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORERESETP_0/INIT_DONE_int:CLK</cell>
 <cell>EDAC_0/CORECONFIGP_0/INIT_DONE_q1:D</cell>
 <cell>4.931</cell>
 <cell>7.372</cell>
 <cell>9.047</cell>
 <cell>16.419</cell>
 <cell>0.175</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORERESETP_0/INIT_DONE_int:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/CORECONFIGP_0/INIT_DONE_q1:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>16.419</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>9.047</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.372</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.173</cell>
 <cell>2.173</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.288</cell>
 <cell>2.461</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.144</cell>
 <cell>2.605</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.616</cell>
 <cell>3.221</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.320</cell>
 <cell>3.541</cell>
 <cell>12</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/INIT_DONE_int:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.575</cell>
 <cell>4.116</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/INIT_DONE_int:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.109</cell>
 <cell>4.225</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/INIT_DONE_q1:D</cell>
 <cell>net</cell>
 <cell>EDAC_0/INIT_DONE_int</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>4.822</cell>
 <cell>9.047</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>9.047</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>4.766</cell>
 <cell>14.766</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.361</cell>
 <cell>15.127</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.603</cell>
 <cell>15.730</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.319</cell>
 <cell>16.049</cell>
 <cell>53</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/INIT_DONE_q1:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.545</cell>
 <cell>16.594</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/INIT_DONE_q1:D</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.175</cell>
 <cell>16.419</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>16.419</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Path Set Pin to Pin</name>
<section>
<name>SET Input to Output</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set User Sets</name>
</section>
</doc>
