<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
<doc>
<title>Timing Report Max Delay Analysis
</title>
<text>SmartTime Version 11.6.0.34</text>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.6 (Version 11.6.0.34)</text>
<text>Date: Thu Oct 15 11:57:46 2015
</text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>EDAC_top</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2S150TS</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>1152 FC</cell>
</row>
<row>
 <cell>Temperature Range</cell>
 <cell>-40 - 100 C</cell>
</row>
<row>
 <cell>Voltage Range</cell>
 <cell>1.14 - 1.26 V</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Design State</cell>
 <cell>Post-Layout</cell>
</row>
<row>
 <cell>Data source</cell>
 <cell>Production</cell>
</row>
<row>
 <cell>Min Operating Conditions</cell>
 <cell>BEST - 1.26 V - -40 C</cell>
</row>
<row>
 <cell>Max Operating Conditions</cell>
 <cell>WORST - 1.14 V - 100 C</cell>
</row>
<row>
 <cell>Scenario for Timing Analysis</cell>
 <cell>Primary</cell>
</row>
</table>
<text></text>
<section>
<name>Summary</name>
<table>
<header>
 <cell>Clock Domain</cell>
 <cell>Period (ns)</cell>
 <cell>Frequency (MHz)</cell>
 <cell>Required Period (ns)</cell>
 <cell>Required Frequency (MHz)</cell>
 <cell>External Setup (ns)</cell>
 <cell>External Hold (ns)</cell>
 <cell>Min Clock-To-Out (ns)</cell>
 <cell>Max Clock-To-Out (ns)</cell>
</header>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>4.857</cell>
 <cell>205.888</cell>
 <cell>10.000</cell>
 <cell>100.000</cell>
 <cell>1.416</cell>
 <cell>-0.476</cell>
 <cell>5.922</cell>
 <cell>10.752</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>4.051</cell>
 <cell>246.853</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell>8.740</cell>
 <cell>114.416</cell>
 <cell>40.000</cell>
 <cell>25.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
<text></text>
<table>
<header>
 <cell></cell>
 <cell>Min Delay (ns)</cell>
 <cell>Max Delay (ns)</cell>
</header>
<row>
 <cell>Input to Output</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
</section>
<section>
<name>Clock Domain EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<text>Info: The maximum frequency of this clock domain is limited by the period of pin EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</text>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORERESETP_0/RESET_N_M2F_clk_base:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:D</cell>
 <cell>2.649</cell>
 <cell>7.083</cell>
 <cell>6.693</cell>
 <cell>13.776</cell>
 <cell>0.256</cell>
 <cell>2.917</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>EDAC_0/CORERESETP_0/RESET_N_M2F_clk_base:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/mss_ready_state:EN</cell>
 <cell>2.171</cell>
 <cell>7.471</cell>
 <cell>6.215</cell>
 <cell>13.686</cell>
 <cell>0.338</cell>
 <cell>2.529</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>EDAC_0/CORERESETP_0/ddr_settled_clk_base:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr_enable:EN</cell>
 <cell>1.768</cell>
 <cell>7.810</cell>
 <cell>5.869</cell>
 <cell>13.679</cell>
 <cell>0.338</cell>
 <cell>2.190</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_state[4]:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr_enable:EN</cell>
 <cell>1.565</cell>
 <cell>8.025</cell>
 <cell>5.654</cell>
 <cell>13.679</cell>
 <cell>0.338</cell>
 <cell>1.975</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_state[3]:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr_enable:EN</cell>
 <cell>1.499</cell>
 <cell>8.079</cell>
 <cell>5.600</cell>
 <cell>13.679</cell>
 <cell>0.338</cell>
 <cell>1.921</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORERESETP_0/RESET_N_M2F_clk_base:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>13.776</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>6.693</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.083</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.173</cell>
 <cell>2.173</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.288</cell>
 <cell>2.461</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.144</cell>
 <cell>2.605</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.587</cell>
 <cell>3.192</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.320</cell>
 <cell>3.512</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/RESET_N_M2F_clk_base:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.532</cell>
 <cell>4.044</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/RESET_N_M2F_clk_base:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.088</cell>
 <cell>4.132</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/MSS_HPMS_READY_int_4:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/RESET_N_M2F_clk_base</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.093</cell>
 <cell>6.225</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/MSS_HPMS_READY_int_4:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.160</cell>
 <cell>6.385</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:D</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/MSS_HPMS_READY_int_4</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.308</cell>
 <cell>6.693</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.693</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.173</cell>
 <cell>12.173</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.288</cell>
 <cell>12.461</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.144</cell>
 <cell>12.605</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.609</cell>
 <cell>13.214</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.319</cell>
 <cell>13.533</cell>
 <cell>7</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.499</cell>
 <cell>14.032</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:D</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.256</cell>
 <cell>13.776</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>13.776</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>External Setup (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MMUART_0_RXD_F2M</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_RXD_F2H_SCP</cell>
 <cell>4.760</cell>
 <cell></cell>
 <cell>4.760</cell>
 <cell></cell>
 <cell>0.767</cell>
 <cell>1.416</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MMUART_0_RXD_F2M</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_RXD_F2H_SCP</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>4.760</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MMUART_0_RXD_F2M</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_RXD_F2M_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>MMUART_0_RXD_F2M</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_RXD_F2M_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>2.593</cell>
 <cell>2.593</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_RXD_F2M_ibuf/U0/U_IOINFF:A</cell>
 <cell>net</cell>
 <cell>MMUART_0_RXD_F2M_ibuf/U0/YIN1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.593</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_RXD_F2M_ibuf/U0/U_IOINFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOINFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.091</cell>
 <cell>2.684</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_241:A</cell>
 <cell>net</cell>
 <cell>MMUART_0_RXD_F2M_c</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.822</cell>
 <cell>4.506</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_241:IPA</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.201</cell>
 <cell>4.707</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_RXD_F2H_SCP</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/MMUART0_RXD_F2H_SCP_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.053</cell>
 <cell>4.760</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.760</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.173</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.259</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.130</cell>
 <cell>N/C</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.550</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.287</cell>
 <cell>N/C</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.407</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>N/C</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.115</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_RXD_F2H_SCP</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:MSS_120_IP</cell>
 <cell>-</cell>
 <cell>0.767</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Clock to Output</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Clock to Out (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell>MMUART_0_TXD_M2F</cell>
 <cell>6.426</cell>
 <cell></cell>
 <cell>10.752</cell>
 <cell></cell>
 <cell>10.752</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MMUART_0_TXD_M2F</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>10.752</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.173</cell>
 <cell>2.173</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.288</cell>
 <cell>2.461</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.144</cell>
 <cell>2.605</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.611</cell>
 <cell>3.216</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.319</cell>
 <cell>3.535</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.452</cell>
 <cell>3.987</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.211</cell>
 <cell>4.198</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.128</cell>
 <cell>4.326</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_TXD_MGPIO27B_H2F_A</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MSS_120_IP</cell>
 <cell>+</cell>
 <cell>1.539</cell>
 <cell>5.865</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_TXD_M2F_obuf/U0/U_IOOUTFF:A</cell>
 <cell>net</cell>
 <cell>MMUART_0_TXD_M2F_c</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.786</cell>
 <cell>7.651</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_TXD_M2F_obuf/U0/U_IOOUTFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOOUTFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.347</cell>
 <cell>7.998</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_TXD_M2F_obuf/U0/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>MMUART_0_TXD_M2F_obuf/U0/DOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>7.998</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_TXD_M2F_obuf/U0/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>2.754</cell>
 <cell>10.752</cell>
 <cell>0</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_TXD_M2F</cell>
 <cell>net</cell>
 <cell>MMUART_0_TXD_M2F</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>10.752</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.752</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.173</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MMUART_0_TXD_M2F</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Recovery (ns)</cell>
 <cell>Minimum Period (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_state[4]:ALn</cell>
 <cell>3.755</cell>
 <cell>5.849</cell>
 <cell>7.826</cell>
 <cell>13.675</cell>
 <cell>0.356</cell>
 <cell>4.151</cell>
 <cell>0.040</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/CONFIG2_DONE_clk_base:ALn</cell>
 <cell>3.754</cell>
 <cell>5.850</cell>
 <cell>7.825</cell>
 <cell>13.675</cell>
 <cell>0.356</cell>
 <cell>4.150</cell>
 <cell>0.040</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_state[1]:ALn</cell>
 <cell>3.754</cell>
 <cell>5.850</cell>
 <cell>7.825</cell>
 <cell>13.675</cell>
 <cell>0.356</cell>
 <cell>4.150</cell>
 <cell>0.040</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_state[0]:ALn</cell>
 <cell>3.754</cell>
 <cell>5.850</cell>
 <cell>7.825</cell>
 <cell>13.675</cell>
 <cell>0.356</cell>
 <cell>4.150</cell>
 <cell>0.040</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_state[6]:ALn</cell>
 <cell>3.754</cell>
 <cell>5.850</cell>
 <cell>7.825</cell>
 <cell>13.675</cell>
 <cell>0.356</cell>
 <cell>4.150</cell>
 <cell>0.040</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/CORERESETP_0/sm0_state[4]:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>13.675</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>7.826</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.849</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.173</cell>
 <cell>2.173</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.288</cell>
 <cell>2.461</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.144</cell>
 <cell>2.605</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.608</cell>
 <cell>3.213</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.320</cell>
 <cell>3.533</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.538</cell>
 <cell>4.071</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.088</cell>
 <cell>4.159</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base_RNIMUV2:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base_0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.796</cell>
 <cell>5.955</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base_RNIMUV2:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.361</cell>
 <cell>6.316</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base_RNIMUV2/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base_RNIMUV2/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.589</cell>
 <cell>6.905</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base_RNIMUV2/U0_RGB1_RGB0:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.320</cell>
 <cell>7.225</cell>
 <cell>18</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_state[4]:ALn</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base_RNIMUV2/U0_RGB1_RGB0_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.601</cell>
 <cell>7.826</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.826</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.173</cell>
 <cell>12.173</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.288</cell>
 <cell>12.461</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.144</cell>
 <cell>12.605</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.587</cell>
 <cell>13.192</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.320</cell>
 <cell>13.512</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_state[4]:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.519</cell>
 <cell>14.031</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_state[4]:ALn</cell>
 <cell>Library recovery time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.356</cell>
 <cell>13.675</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>13.675</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT to EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET FIC2_CLK to EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORECONFIGP_0/control_reg_1[0]:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/CONFIG1_DONE_q1:D</cell>
 <cell>2.476</cell>
 <cell>4.688</cell>
 <cell>9.073</cell>
 <cell>13.761</cell>
 <cell>0.256</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>EDAC_0/CORECONFIGP_0/soft_reset_reg[1]:CLK</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:USER_MSS_RESET_N</cell>
 <cell>2.566</cell>
 <cell>5.018</cell>
 <cell>9.163</cell>
 <cell>14.181</cell>
 <cell></cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>EDAC_0/CORECONFIGP_0/control_reg_1[1]:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/CONFIG2_DONE_q1:D</cell>
 <cell>1.756</cell>
 <cell>5.408</cell>
 <cell>8.353</cell>
 <cell>13.761</cell>
 <cell>0.256</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORECONFIGP_0/control_reg_1[0]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/CORERESETP_0/CONFIG1_DONE_q1:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>13.761</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>9.073</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.688</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>4.740</cell>
 <cell>4.740</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.361</cell>
 <cell>5.101</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.603</cell>
 <cell>5.704</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.319</cell>
 <cell>6.023</cell>
 <cell>68</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/control_reg_1[0]:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.574</cell>
 <cell>6.597</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/control_reg_1[0]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.088</cell>
 <cell>6.685</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/CONFIG1_DONE_q1:D</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORECONFIGP_0_CONFIG1_DONE</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.388</cell>
 <cell>9.073</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>9.073</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.173</cell>
 <cell>12.173</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.288</cell>
 <cell>12.461</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.144</cell>
 <cell>12.605</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.587</cell>
 <cell>13.192</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.320</cell>
 <cell>13.512</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/CONFIG1_DONE_q1:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.505</cell>
 <cell>14.017</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/CONFIG1_DONE_q1:D</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.256</cell>
 <cell>13.761</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>13.761</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Clock Domain EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[7]:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>2.161</cell>
 <cell>17.432</cell>
 <cell>10.621</cell>
 <cell>28.053</cell>
 <cell>0.338</cell>
 <cell>2.568</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[3]:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>2.151</cell>
 <cell>17.442</cell>
 <cell>10.611</cell>
 <cell>28.053</cell>
 <cell>0.338</cell>
 <cell>2.558</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[8]:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>2.087</cell>
 <cell>17.518</cell>
 <cell>10.535</cell>
 <cell>28.053</cell>
 <cell>0.338</cell>
 <cell>2.482</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[9]:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>2.065</cell>
 <cell>17.528</cell>
 <cell>10.525</cell>
 <cell>28.053</cell>
 <cell>0.338</cell>
 <cell>2.472</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[12]:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>2.046</cell>
 <cell>17.595</cell>
 <cell>10.458</cell>
 <cell>28.053</cell>
 <cell>0.338</cell>
 <cell>2.405</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORERESETP_0/count_ddr[7]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>28.053</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>10.621</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>17.432</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.406</cell>
 <cell>1.406</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.154</cell>
 <cell>1.560</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>5.048</cell>
 <cell>6.608</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.361</cell>
 <cell>6.969</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.591</cell>
 <cell>7.560</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.320</cell>
 <cell>7.880</cell>
 <cell>18</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/count_ddr[7]:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0_RCOSC_25_50MHZ_O2F</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.580</cell>
 <cell>8.460</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/count_ddr[7]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.088</cell>
 <cell>8.548</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/ddr_settled4_6:B</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[7]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.622</cell>
 <cell>9.170</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/ddr_settled4_6:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2</cell>
 <cell>+</cell>
 <cell>0.145</cell>
 <cell>9.315</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/ddr_settled4:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/ddr_settled4_6</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.305</cell>
 <cell>9.620</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/ddr_settled4:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.290</cell>
 <cell>9.910</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/ddr_settled4</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.711</cell>
 <cell>10.621</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.621</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>20.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.406</cell>
 <cell>21.406</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.154</cell>
 <cell>21.560</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>5.048</cell>
 <cell>26.608</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.361</cell>
 <cell>26.969</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.591</cell>
 <cell>27.560</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.320</cell>
 <cell>27.880</cell>
 <cell>18</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/ddr_settled:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0_RCOSC_25_50MHZ_O2F</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.511</cell>
 <cell>28.391</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.338</cell>
 <cell>28.053</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>28.053</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Recovery (ns)</cell>
 <cell>Minimum Period (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[4]:ALn</cell>
 <cell>3.647</cell>
 <cell>15.949</cell>
 <cell>12.086</cell>
 <cell>28.035</cell>
 <cell>0.356</cell>
 <cell>4.051</cell>
 <cell>0.048</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/ddr_settled:ALn</cell>
 <cell>3.647</cell>
 <cell>15.949</cell>
 <cell>12.086</cell>
 <cell>28.035</cell>
 <cell>0.356</cell>
 <cell>4.051</cell>
 <cell>0.048</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[8]:ALn</cell>
 <cell>3.647</cell>
 <cell>15.949</cell>
 <cell>12.086</cell>
 <cell>28.035</cell>
 <cell>0.356</cell>
 <cell>4.051</cell>
 <cell>0.048</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[10]:ALn</cell>
 <cell>3.647</cell>
 <cell>15.949</cell>
 <cell>12.086</cell>
 <cell>28.035</cell>
 <cell>0.356</cell>
 <cell>4.051</cell>
 <cell>0.048</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[6]:ALn</cell>
 <cell>3.647</cell>
 <cell>15.949</cell>
 <cell>12.086</cell>
 <cell>28.035</cell>
 <cell>0.356</cell>
 <cell>4.051</cell>
 <cell>0.048</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/CORERESETP_0/count_ddr[4]:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>28.035</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>12.086</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>15.949</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.406</cell>
 <cell>1.406</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.154</cell>
 <cell>1.560</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>5.048</cell>
 <cell>6.608</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.361</cell>
 <cell>6.969</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.608</cell>
 <cell>7.577</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.320</cell>
 <cell>7.897</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.542</cell>
 <cell>8.439</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.088</cell>
 <cell>8.527</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc_RNI2AAD:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.701</cell>
 <cell>10.228</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc_RNI2AAD:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.361</cell>
 <cell>10.589</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc_RNI2AAD/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc_RNI2AAD/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.575</cell>
 <cell>11.164</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc_RNI2AAD/U0_RGB1:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.320</cell>
 <cell>11.484</cell>
 <cell>18</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/count_ddr[4]:ALn</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.602</cell>
 <cell>12.086</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>12.086</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>20.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.406</cell>
 <cell>21.406</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.154</cell>
 <cell>21.560</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>5.048</cell>
 <cell>26.608</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.361</cell>
 <cell>26.969</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.591</cell>
 <cell>27.560</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.320</cell>
 <cell>27.880</cell>
 <cell>18</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/count_ddr[4]:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0_RCOSC_25_50MHZ_O2F</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.511</cell>
 <cell>28.391</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/count_ddr[4]:ALn</cell>
 <cell>Library recovery time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.356</cell>
 <cell>28.035</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>28.035</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain FIC2_CLK</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell>EDAC_0/CORECONFIGP_0/state[0]:D</cell>
 <cell>2.712</cell>
 <cell>3.580</cell>
 <cell>2.712</cell>
 <cell>6.292</cell>
 <cell>0.256</cell>
 <cell>-3.580</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>EDAC_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[13]:D</cell>
 <cell>3.096</cell>
 <cell>16.222</cell>
 <cell>10.061</cell>
 <cell>26.283</cell>
 <cell>0.256</cell>
 <cell>7.556</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>EDAC_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[6]:D</cell>
 <cell>3.095</cell>
 <cell>16.224</cell>
 <cell>10.060</cell>
 <cell>26.284</cell>
 <cell>0.256</cell>
 <cell>7.552</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>EDAC_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[10]:D</cell>
 <cell>3.094</cell>
 <cell>16.235</cell>
 <cell>10.059</cell>
 <cell>26.294</cell>
 <cell>0.256</cell>
 <cell>7.530</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>EDAC_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[9]:D</cell>
 <cell>2.851</cell>
 <cell>16.478</cell>
 <cell>9.816</cell>
 <cell>26.294</cell>
 <cell>0.256</cell>
 <cell>7.044</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/CORECONFIGP_0/state[0]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.292</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>2.712</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.580</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PSEL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MSS_120_IP</cell>
 <cell>+</cell>
 <cell>0.304</cell>
 <cell>0.304</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_o3:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_TMP_0_FIC_2_APB_MASTER_PSELx</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.989</cell>
 <cell>2.293</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_o3:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.145</cell>
 <cell>2.438</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_a3_0_a2:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORECONFIGP_0/N_43</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.100</cell>
 <cell>2.538</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_a3_0_a2:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2</cell>
 <cell>+</cell>
 <cell>0.100</cell>
 <cell>2.638</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/state[0]:D</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORECONFIGP_0/state_ns[0]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.074</cell>
 <cell>2.712</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.712</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell>Max Delay Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>4.740</cell>
 <cell>4.740</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.361</cell>
 <cell>5.101</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.603</cell>
 <cell>5.704</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.319</cell>
 <cell>6.023</cell>
 <cell>68</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/state[0]:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.525</cell>
 <cell>6.548</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/state[0]:D</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.256</cell>
 <cell>6.292</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.292</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to FIC2_CLK</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORERESETP_0/INIT_DONE_int:CLK</cell>
 <cell>EDAC_0/CORECONFIGP_0/INIT_DONE_q1:D</cell>
 <cell>2.515</cell>
 <cell>9.688</cell>
 <cell>6.588</cell>
 <cell>16.276</cell>
 <cell>0.256</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORERESETP_0/INIT_DONE_int:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/CORECONFIGP_0/INIT_DONE_q1:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>16.276</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>6.588</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>9.688</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.173</cell>
 <cell>2.173</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.288</cell>
 <cell>2.461</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.144</cell>
 <cell>2.605</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.587</cell>
 <cell>3.192</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.320</cell>
 <cell>3.512</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/INIT_DONE_int:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.561</cell>
 <cell>4.073</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/INIT_DONE_int:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.088</cell>
 <cell>4.161</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/INIT_DONE_q1:D</cell>
 <cell>net</cell>
 <cell>EDAC_0/INIT_DONE_int</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.427</cell>
 <cell>6.588</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.588</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>4.740</cell>
 <cell>14.740</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.361</cell>
 <cell>15.101</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.603</cell>
 <cell>15.704</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.319</cell>
 <cell>16.023</cell>
 <cell>68</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/INIT_DONE_q1:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.509</cell>
 <cell>16.532</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/INIT_DONE_q1:D</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.256</cell>
 <cell>16.276</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>16.276</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Path Set Pin to Pin</name>
<section>
<name>SET Input to Output</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set User Sets</name>
</section>
</doc>
