# ===========================================================
# Created by Microsemi SmartDesign Tue Mar 14 12:54:00 2017
# 
# Warning: Do not modify this file, it may lead to unexpected
#          simulation failures in your design.
# 
# ===========================================================

DDRC_DYN_REFRESH_1_CR 0x008 0x27de
DDRC_DYN_REFRESH_2_CR 0x00c 0x30f
DDRC_DYN_POWERDOWN_CR 0x010 0x2
DDRC_DYN_DEBUG_CR 0x014 0x0
DDRC_MODE_CR 0x018 0x114
DDRC_ADDR_MAP_BANK_CR 0x01c 0xaaa
DDRC_ECC_DATA_MASK_CR 0x020 0x0
DDRC_ADDR_MAP_COL_1_CR 0x024 0x3333
DDRC_ADDR_MAP_COL_2_CR 0x028 0x3fff
DDRC_ADDR_MAP_COL_3_CR 0x078 0x3300
DDRC_ADDR_MAP_ROW_1_CR 0x02c 0x9999
DDRC_ADDR_MAP_ROW_2_CR 0x030 0x999
DDRC_INIT_1_CR 0x034 0x1
DDRC_CKE_RSTN_CYCLES_1_CR 0x038 0x4242
DDRC_CKE_RSTN_CYCLES_2_CR 0x03c 0x8
DDRC_INIT_MR_CR 0x040 0x528
DDRC_INIT_EMR_CR 0x044 0x0
DDRC_INIT_EMR2_CR 0x048 0x0
DDRC_INIT_EMR3_CR 0x04c 0x0
DDRC_DRAM_BANK_TIMING_PARAM_CR 0x050 0xce0
DDRC_DRAM_RD_WR_LATENCY_CR 0x054 0x86
DDRC_DRAM_RD_WR_PRE_CR 0x058 0x235
DDRC_DRAM_MR_TIMING_PARAM_CR 0x05c 0x64
DDRC_DRAM_RAS_TIMING_CR 0x060 0x10f
DDRC_DRAM_RD_WR_TRNARND_TIME_CR 0x064 0x178
DDRC_DRAM_T_PD_CR 0x068 0x33
DDRC_DRAM_BANK_ACT_TIMING_CR 0x06c 0x1937
DDRC_ODT_PARAM_1_CR 0x070 0x10
DDRC_ODT_PARAM_2_CR 0x074 0x0
DDRC_DEBUG_CR 0x078 0x3300
DDRC_MODE_REG_RD_WR_CR 0x07c 0x0
DDRC_MODE_REG_DATA_CR 0x080 0x0
DDRC_PWR_SAVE_1_CR 0x084 0x40c
DDRC_PWR_SAVE_2_CR 0x088 0x0
DDRC_ZQ_LONG_TIME_CR 0x08c 0x200
DDRC_ZQ_SHORT_TIME_CR 0x090 0x40
DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_1_CR 0x094 0x12
DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_2_CR 0x098 0x2
DDRC_PERF_PARAM_1_CR 0x09c 0x4002
DDRC_HPR_QUEUE_PARAM_1_CR 0x0a0 0x80f8
DDRC_HPR_QUEUE_PARAM_2_CR 0x0a4 0x7
DDRC_LPR_QUEUE_PARAM_1_CR 0x0a8 0x80f8
DDRC_LPR_QUEUE_PARAM_2_CR 0x0ac 0x7
DDRC_WR_QUEUE_PARAM_CR 0x0b0 0x200
DDRC_PERF_PARAM_2_CR 0x0b4 0x400
DDRC_PERF_PARAM_3_CR 0x0b8 0x0
DDRC_DFI_RDDATA_EN_CR 0x0bc 0x5
DDRC_DFI_MIN_CTRLUPD_TIMING_CR 0x0c0 0x3
DDRC_DFI_MAX_CTRLUPD_TIMING_CR 0x0c4 0x40
DDRC_DFI_WR_LVL_CONTROL_1_CR 0x0c8 0x0
DDRC_DFI_WR_LVL_CONTROL_2_CR 0x0cc 0x0
DDRC_DFI_RD_LVL_CONTROL_1_CR 0x0d0 0x0
DDRC_DFI_RD_LVL_CONTROL_2_CR 0x0d4 0x0
DDRC_DFI_CTRLUPD_TIME_INTERVAL_CR 0x0d8 0x309
DDRC_AXI_FABRIC_PRI_ID_CR 0x0e0 0x0
DDRC_ECC_INT_CLR_REG 0x140 0x0
PHY_DYN_BIST_TEST_CR 0x200 0x0
PHY_DYN_BIST_TEST_ERRCLR_1_CR 0x204 0x0
PHY_DYN_BIST_TEST_ERRCLR_2_CR 0x208 0x0
PHY_DYN_BIST_TEST_ERRCLR_3_CR 0x20c 0x0
PHY_BIST_TEST_SHIFT_PATTERN_1_CR 0x210 0x0
PHY_BIST_TEST_SHIFT_PATTERN_2_CR 0x214 0x0
PHY_BIST_TEST_SHIFT_PATTERN_3_CR 0x218 0x0
PHY_LOOPBACK_TEST_CR 0x21c 0x0
PHY_BOARD_LOOPBACK_CR 0x220 0x0
PHY_CTRL_SLAVE_RATIO_CR 0x224 0x80
PHY_CTRL_SLAVE_FORCE_CR 0x228 0x0
PHY_CTRL_SLAVE_DELAY_CR 0x22c 0x0
PHY_DATA_SLICE_IN_USE_CR 0x230 0x1f
PHY_LVL_NUM_OF_DQ0_CR 0x234 0x0
PHY_DQ_OFFSET_1_CR 0x238 0x0
PHY_DQ_OFFSET_2_CR 0x23c 0x0
PHY_DQ_OFFSET_3_CR 0x240 0x0
PHY_DIS_CALIB_RST_CR 0x244 0x0
PHY_DLL_LOCK_DIFF_CR 0x248 0xb
PHY_FIFO_WE_IN_DELAY_1_CR 0x24c 0x0
PHY_FIFO_WE_IN_DELAY_2_CR 0x250 0x0
PHY_FIFO_WE_IN_DELAY_3_CR 0x254 0x0
PHY_FIFO_WE_IN_FORCE_CR 0x258 0x0
PHY_FIFO_WE_SLAVE_RATIO_1_CR 0x25c 0x80
PHY_FIFO_WE_SLAVE_RATIO_2_CR 0x260 0x2004
PHY_FIFO_WE_SLAVE_RATIO_3_CR 0x264 0x100
PHY_FIFO_WE_SLAVE_RATIO_4_CR 0x268 0x8
PHY_GATELVL_INIT_MODE_CR 0x26c 0x0
PHY_GATELVL_INIT_RATIO_1_CR 0x270 0x0
PHY_GATELVL_INIT_RATIO_2_CR 0x274 0x0
PHY_GATELVL_INIT_RATIO_3_CR 0x278 0x0
PHY_GATELVL_INIT_RATIO_4_CR 0x27c 0x0
PHY_LOCAL_ODT_CR 0x280 0x1
PHY_INVERT_CLKOUT_CR 0x284 0x0
PHY_RD_DQS_SLAVE_DELAY_1_CR 0x288 0x0
PHY_RD_DQS_SLAVE_DELAY_2_CR 0x28c 0x0
PHY_RD_DQS_SLAVE_DELAY_3_CR 0x290 0x0
PHY_RD_DQS_SLAVE_FORCE_CR 0x294 0x0
PHY_RD_DQS_SLAVE_RATIO_1_CR 0x298 0x4050
PHY_RD_DQS_SLAVE_RATIO_2_CR 0x29c 0x501
PHY_RD_DQS_SLAVE_RATIO_3_CR 0x2a0 0x5014
PHY_RD_DQS_SLAVE_RATIO_4_CR 0x2a4 0x0
PHY_WR_DQS_SLAVE_DELAY_1_CR 0x2a8 0x0
PHY_WR_DQS_SLAVE_DELAY_2_CR 0x2ac 0x0
PHY_WR_DQS_SLAVE_DELAY_3_CR 0x2b0 0x0
PHY_WR_DQS_SLAVE_FORCE_CR 0x2b4 0x0
PHY_WR_DQS_SLAVE_RATIO_1_CR 0x2b8 0x0
PHY_WR_DQS_SLAVE_RATIO_2_CR 0x2bc 0x0
PHY_WR_DQS_SLAVE_RATIO_3_CR 0x2c0 0x0
PHY_WR_DQS_SLAVE_RATIO_4_CR 0x2c4 0x0
PHY_WR_DATA_SLAVE_DELAY_1_CR 0x2c8 0x0
PHY_WR_DATA_SLAVE_DELAY_2_CR 0x2cc 0x0
PHY_WR_DATA_SLAVE_DELAY_3_CR 0x2d0 0x0
PHY_WR_DATA_SLAVE_FORCE_CR 0x2d4 0x0
PHY_WR_DATA_SLAVE_RATIO_1_CR 0x2d8 0x50
PHY_WR_DATA_SLAVE_RATIO_2_CR 0x2dc 0x501
PHY_WR_DATA_SLAVE_RATIO_3_CR 0x2e0 0x5010
PHY_WR_DATA_SLAVE_RATIO_4_CR 0x2e4 0x0
PHY_WRLVL_INIT_MODE_CR 0x2e8 0x0
PHY_WRLVL_INIT_RATIO_1_CR 0x2ec 0x0
PHY_WRLVL_INIT_RATIO_2_CR 0x2f0 0x0
PHY_WRLVL_INIT_RATIO_3_CR 0x2f4 0x0
PHY_WRLVL_INIT_RATIO_4_CR 0x2f8 0x0
PHY_WR_RD_RL_CR 0x2fc 0x43
PHY_RDC_FIFO_RST_ERR_CNT_CLR_CR 0x300 0x0
PHY_RDC_WE_TO_RE_DELAY_CR 0x304 0x3
PHY_USE_FIXED_RE_CR 0x308 0x1
PHY_USE_RANK0_DELAYS_CR 0x30c 0x1
PHY_USE_LVL_TRNG_LEVEL_CR 0x310 0x0
PHY_DYN_CONFIG_CR 0x314 0x0
PHY_RD_WR_GATE_LVL_CR 0x318 0x0
PHY_DYN_RESET_CR 0x31c 0x1
DDR_FIC_NB_ADDR_CR 0x400 0x0
DDR_FIC_NBRWB_SIZE_CR 0x404 0x0
DDR_FIC_WB_TIMEOUT_CR 0x408 0x0
DDR_FIC_HPD_SW_RW_EN_CR 0x40c 0x0
DDR_FIC_HPD_SW_RW_INVAL_CR 0x410 0x0
DDR_FIC_SW_WR_ERCLR_CR 0x414 0x0
DDR_FIC_ERR_INT_ENABLE_CR 0x418 0x0
DDR_FIC_NUM_AHB_MASTERS_CR 0x41c 0x0
DDR_FIC_LOCK_TIMEOUTVAL_1_CR 0x440 0x0
DDR_FIC_LOCK_TIMEOUTVAL_2_CR 0x444 0x0
DDR_FIC_LOCK_TIMEOUT_EN_CR 0x448 0x0
