<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
<doc>
<title>Timing Report Min Delay Analysis
</title>
<text>SmartTime Version 11.6.0.34</text>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.6 (Version 11.6.0.34)</text>
<text>Date: Thu Oct 15 11:57:46 2015
</text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>EDAC_top</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2S150TS</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>1152 FC</cell>
</row>
<row>
 <cell>Temperature Range</cell>
 <cell>-40 - 100 C</cell>
</row>
<row>
 <cell>Voltage Range</cell>
 <cell>1.14 - 1.26 V</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Design State</cell>
 <cell>Post-Layout</cell>
</row>
<row>
 <cell>Data source</cell>
 <cell>Production</cell>
</row>
<row>
 <cell>Min Operating Conditions</cell>
 <cell>BEST - 1.26 V - -40 C</cell>
</row>
<row>
 <cell>Max Operating Conditions</cell>
 <cell>WORST - 1.14 V - 100 C</cell>
</row>
<row>
 <cell>Scenario for Timing Analysis</cell>
 <cell>Primary</cell>
</row>
</table>
<text></text>
<section>
<name>Summary</name>
<table>
<header>
 <cell>Clock Domain</cell>
 <cell>Period (ns)</cell>
 <cell>Frequency (MHz)</cell>
 <cell>Required Period (ns)</cell>
 <cell>Required Frequency (MHz)</cell>
 <cell>External Setup (ns)</cell>
 <cell>External Hold (ns)</cell>
 <cell>Min Clock-To-Out (ns)</cell>
 <cell>Max Clock-To-Out (ns)</cell>
</header>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>4.857</cell>
 <cell>205.888</cell>
 <cell>10.000</cell>
 <cell>100.000</cell>
 <cell>1.416</cell>
 <cell>-0.476</cell>
 <cell>5.922</cell>
 <cell>10.752</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>4.051</cell>
 <cell>246.853</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell>8.740</cell>
 <cell>114.416</cell>
 <cell>40.000</cell>
 <cell>25.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
<text></text>
<table>
<header>
 <cell></cell>
 <cell>Min Delay (ns)</cell>
 <cell>Max Delay (ns)</cell>
</header>
<row>
 <cell>Input to Output</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
</section>
<section>
<name>Clock Domain EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<text>Info: The maximum frequency of this clock domain is limited by the period of pin EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</text>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORERESETP_0/CONFIG1_DONE_q1:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/CONFIG1_DONE_clk_base:D</cell>
 <cell>0.286</cell>
 <cell>0.248</cell>
 <cell>2.754</cell>
 <cell>2.506</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_q1:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:D</cell>
 <cell>0.289</cell>
 <cell>0.248</cell>
 <cell>2.750</cell>
 <cell>2.502</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>EDAC_0/CORERESETP_0/POWER_ON_RESET_N_q1:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:D</cell>
 <cell>0.292</cell>
 <cell>0.251</cell>
 <cell>2.757</cell>
 <cell>2.506</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>EDAC_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_q1:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_clk_base:D</cell>
 <cell>0.289</cell>
 <cell>0.252</cell>
 <cell>2.761</cell>
 <cell>2.509</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>EDAC_0/CORERESETP_0/release_sdif0_core_q1:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/release_sdif0_core_clk_base:D</cell>
 <cell>0.292</cell>
 <cell>0.255</cell>
 <cell>2.753</cell>
 <cell>2.498</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORERESETP_0/CONFIG1_DONE_q1:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/CORERESETP_0/CONFIG1_DONE_clk_base:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.754</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>2.506</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.248</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.321</cell>
 <cell>1.321</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.175</cell>
 <cell>1.496</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.086</cell>
 <cell>1.582</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.351</cell>
 <cell>1.933</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.194</cell>
 <cell>2.127</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/CONFIG1_DONE_q1:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.341</cell>
 <cell>2.468</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/CONFIG1_DONE_q1:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.053</cell>
 <cell>2.521</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/CONFIG1_DONE_clk_base:D</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/CONFIG1_DONE_q1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.233</cell>
 <cell>2.754</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.754</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.321</cell>
 <cell>1.321</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.175</cell>
 <cell>1.496</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.086</cell>
 <cell>1.582</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.351</cell>
 <cell>1.933</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.194</cell>
 <cell>2.127</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/CONFIG1_DONE_clk_base:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.379</cell>
 <cell>2.506</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/CONFIG1_DONE_clk_base:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.506</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.506</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
 <cell>External Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MMUART_0_RXD_F2M</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_RXD_F2H_SCP</cell>
 <cell>2.749</cell>
 <cell></cell>
 <cell>2.749</cell>
 <cell></cell>
 <cell>-0.494</cell>
 <cell>-0.476</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MMUART_0_RXD_F2M</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_RXD_F2H_SCP</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.749</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MMUART_0_RXD_F2M</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_RXD_F2M_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>MMUART_0_RXD_F2M</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_RXD_F2M_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.453</cell>
 <cell>1.453</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_RXD_F2M_ibuf/U0/U_IOINFF:A</cell>
 <cell>net</cell>
 <cell>MMUART_0_RXD_F2M_ibuf/U0/YIN1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>1.453</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_RXD_F2M_ibuf/U0/U_IOINFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOINFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.055</cell>
 <cell>1.508</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_241:A</cell>
 <cell>net</cell>
 <cell>MMUART_0_RXD_F2M_c</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.089</cell>
 <cell>2.597</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_241:IPA</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>2.717</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_RXD_F2H_SCP</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/MMUART0_RXD_F2H_SCP_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.032</cell>
 <cell>2.749</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.749</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.321</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.194</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.096</cell>
 <cell>N/C</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.406</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.216</cell>
 <cell>N/C</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.305</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.143</cell>
 <cell>N/C</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.086</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_RXD_F2H_SCP</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:MSS_120_IP</cell>
 <cell>+</cell>
 <cell>-0.494</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Clock to Output</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Clock to Out (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell>MMUART_0_TXD_M2F</cell>
 <cell>3.301</cell>
 <cell></cell>
 <cell>5.922</cell>
 <cell></cell>
 <cell>5.922</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MMUART_0_TXD_M2F</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.922</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.321</cell>
 <cell>1.321</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.175</cell>
 <cell>1.496</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.086</cell>
 <cell>1.582</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.365</cell>
 <cell>1.947</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.194</cell>
 <cell>2.141</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.275</cell>
 <cell>2.416</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.128</cell>
 <cell>2.544</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.077</cell>
 <cell>2.621</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_TXD_MGPIO27B_H2F_A</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MSS_120_IP</cell>
 <cell>+</cell>
 <cell>0.625</cell>
 <cell>3.246</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_TXD_M2F_obuf/U0/U_IOOUTFF:A</cell>
 <cell>net</cell>
 <cell>MMUART_0_TXD_M2F_c</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.068</cell>
 <cell>4.314</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_TXD_M2F_obuf/U0/U_IOOUTFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOOUTFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.207</cell>
 <cell>4.521</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_TXD_M2F_obuf/U0/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>MMUART_0_TXD_M2F_obuf/U0/DOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>4.521</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_TXD_M2F_obuf/U0/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>1.401</cell>
 <cell>5.922</cell>
 <cell>0</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_TXD_M2F</cell>
 <cell>net</cell>
 <cell>MMUART_0_TXD_M2F</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>5.922</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.922</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.321</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MMUART_0_TXD_M2F</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:ALn</cell>
 <cell>0.383</cell>
 <cell>0.338</cell>
 <cell>2.853</cell>
 <cell>2.515</cell>
 <cell>0.000</cell>
 <cell>-0.045</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>EDAC_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/mss_ready_state:ALn</cell>
 <cell>0.383</cell>
 <cell>0.344</cell>
 <cell>2.853</cell>
 <cell>2.509</cell>
 <cell>0.000</cell>
 <cell>-0.039</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>EDAC_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/mss_ready_select:ALn</cell>
 <cell>0.383</cell>
 <cell>0.344</cell>
 <cell>2.853</cell>
 <cell>2.509</cell>
 <cell>0.000</cell>
 <cell>-0.039</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:ALn</cell>
 <cell>2.221</cell>
 <cell>2.197</cell>
 <cell>4.699</cell>
 <cell>2.502</cell>
 <cell>0.000</cell>
 <cell>-0.024</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_q1:ALn</cell>
 <cell>2.221</cell>
 <cell>2.202</cell>
 <cell>4.699</cell>
 <cell>2.497</cell>
 <cell>0.000</cell>
 <cell>-0.019</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.853</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>2.515</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.338</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.321</cell>
 <cell>1.321</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.175</cell>
 <cell>1.496</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.086</cell>
 <cell>1.582</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.365</cell>
 <cell>1.947</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.194</cell>
 <cell>2.141</cell>
 <cell>7</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.329</cell>
 <cell>2.470</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.053</cell>
 <cell>2.523</cell>
 <cell>3</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:ALn</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/POWER_ON_RESET_N_clk_base</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.330</cell>
 <cell>2.853</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.853</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.321</cell>
 <cell>1.321</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.175</cell>
 <cell>1.496</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.086</cell>
 <cell>1.582</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.365</cell>
 <cell>1.947</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.194</cell>
 <cell>2.141</cell>
 <cell>7</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.374</cell>
 <cell>2.515</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.515</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.515</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT to EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET FIC2_CLK to EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORECONFIGP_0/control_reg_1[1]:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/CONFIG2_DONE_q1:D</cell>
 <cell>1.031</cell>
 <cell>26.529</cell>
 <cell>5.031</cell>
 <cell>-21.498</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>EDAC_0/CORECONFIGP_0/control_reg_1[0]:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/CONFIG1_DONE_q1:D</cell>
 <cell>1.482</cell>
 <cell>26.976</cell>
 <cell>5.482</cell>
 <cell>-21.494</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>EDAC_0/CORECONFIGP_0/soft_reset_reg[1]:CLK</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:USER_MSS_RESET_N</cell>
 <cell>1.555</cell>
 <cell>27.012</cell>
 <cell>5.555</cell>
 <cell>-21.457</cell>
 <cell></cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORECONFIGP_0/control_reg_1[1]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/CORERESETP_0/CONFIG2_DONE_q1:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.031</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>-21.498</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>26.529</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.881</cell>
 <cell>2.881</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.216</cell>
 <cell>3.097</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.360</cell>
 <cell>3.457</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.194</cell>
 <cell>3.651</cell>
 <cell>68</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/control_reg_1[1]:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.349</cell>
 <cell>4.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/control_reg_1[1]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.065</cell>
 <cell>4.065</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/CONFIG2_DONE_q1:D</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORECONFIGP_0_CONFIG2_DONE</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.966</cell>
 <cell>5.031</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.031</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Min Delay Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-24.000</cell>
 <cell>-24.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>-24.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.321</cell>
 <cell>-22.679</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.175</cell>
 <cell>-22.504</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.086</cell>
 <cell>-22.418</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.366</cell>
 <cell>-22.052</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB0:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.194</cell>
 <cell>-21.858</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/CONFIG2_DONE_q1:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB0_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.360</cell>
 <cell>-21.498</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/CONFIG2_DONE_q1:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>-21.498</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-21.498</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Clock Domain EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr_enable_q1:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr_enable_rcosc:D</cell>
 <cell>0.296</cell>
 <cell>0.254</cell>
 <cell>5.401</cell>
 <cell>5.147</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_q1:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc:D</cell>
 <cell>0.296</cell>
 <cell>0.255</cell>
 <cell>5.411</cell>
 <cell>5.156</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[0]:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[0]:D</cell>
 <cell>0.365</cell>
 <cell>0.329</cell>
 <cell>5.473</cell>
 <cell>5.144</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[7]:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[7]:D</cell>
 <cell>0.397</cell>
 <cell>0.358</cell>
 <cell>5.529</cell>
 <cell>5.171</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[5]:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[5]:D</cell>
 <cell>0.398</cell>
 <cell>0.359</cell>
 <cell>5.529</cell>
 <cell>5.170</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORERESETP_0/count_ddr_enable_q1:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/CORERESETP_0/count_ddr_enable_rcosc:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.401</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>5.147</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.254</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.855</cell>
 <cell>0.855</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.093</cell>
 <cell>0.948</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.068</cell>
 <cell>4.016</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.216</cell>
 <cell>4.232</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.353</cell>
 <cell>4.585</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.194</cell>
 <cell>4.779</cell>
 <cell>18</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/count_ddr_enable_q1:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0_RCOSC_25_50MHZ_O2F</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.326</cell>
 <cell>5.105</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/count_ddr_enable_q1:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.053</cell>
 <cell>5.158</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/count_ddr_enable_rcosc:D</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr_enable_q1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.243</cell>
 <cell>5.401</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.401</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.855</cell>
 <cell>0.855</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.093</cell>
 <cell>0.948</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.068</cell>
 <cell>4.016</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.216</cell>
 <cell>4.232</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.353</cell>
 <cell>4.585</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.194</cell>
 <cell>4.779</cell>
 <cell>18</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/count_ddr_enable_rcosc:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0_RCOSC_25_50MHZ_O2F</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.368</cell>
 <cell>5.147</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/count_ddr_enable_rcosc:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>5.147</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.147</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[13]:ALn</cell>
 <cell>2.177</cell>
 <cell>2.152</cell>
 <cell>7.296</cell>
 <cell>5.144</cell>
 <cell>0.000</cell>
 <cell>-0.025</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[0]:ALn</cell>
 <cell>2.177</cell>
 <cell>2.152</cell>
 <cell>7.296</cell>
 <cell>5.144</cell>
 <cell>0.000</cell>
 <cell>-0.025</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[7]:ALn</cell>
 <cell>2.206</cell>
 <cell>2.154</cell>
 <cell>7.325</cell>
 <cell>5.171</cell>
 <cell>0.000</cell>
 <cell>-0.052</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[5]:ALn</cell>
 <cell>2.206</cell>
 <cell>2.155</cell>
 <cell>7.325</cell>
 <cell>5.170</cell>
 <cell>0.000</cell>
 <cell>-0.051</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[3]:ALn</cell>
 <cell>2.206</cell>
 <cell>2.155</cell>
 <cell>7.325</cell>
 <cell>5.170</cell>
 <cell>0.000</cell>
 <cell>-0.051</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/CORERESETP_0/count_ddr[13]:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.296</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>5.144</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.152</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.855</cell>
 <cell>0.855</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.093</cell>
 <cell>0.948</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.068</cell>
 <cell>4.016</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.216</cell>
 <cell>4.232</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.364</cell>
 <cell>4.596</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.194</cell>
 <cell>4.790</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.329</cell>
 <cell>5.119</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.053</cell>
 <cell>5.172</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc_RNI2AAD:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.034</cell>
 <cell>6.206</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc_RNI2AAD:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.216</cell>
 <cell>6.422</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc_RNI2AAD/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc_RNI2AAD/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.344</cell>
 <cell>6.766</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc_RNI2AAD/U0_RGB1:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.194</cell>
 <cell>6.960</cell>
 <cell>18</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/count_ddr[13]:ALn</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.336</cell>
 <cell>7.296</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.296</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.855</cell>
 <cell>0.855</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.093</cell>
 <cell>0.948</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.068</cell>
 <cell>4.016</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.216</cell>
 <cell>4.232</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.353</cell>
 <cell>4.585</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.194</cell>
 <cell>4.779</cell>
 <cell>18</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/count_ddr[13]:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0_RCOSC_25_50MHZ_O2F</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.365</cell>
 <cell>5.144</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/count_ddr[13]:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>5.144</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.144</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain FIC2_CLK</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORECONFIGP_0/MDDR_PENABLE:CLK</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PENABLE</cell>
 <cell>0.547</cell>
 <cell>20.349</cell>
 <cell>4.716</cell>
 <cell>-15.633</cell>
 <cell>0.292</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>EDAC_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PSEL</cell>
 <cell>0.925</cell>
 <cell>20.445</cell>
 <cell>5.099</cell>
 <cell>-15.346</cell>
 <cell>0.579</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>EDAC_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>EDAC_0/CORECONFIGP_0/state[1]:D</cell>
 <cell>0.539</cell>
 <cell>20.674</cell>
 <cell>4.713</cell>
 <cell>-15.961</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>EDAC_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[9]:D</cell>
 <cell>0.760</cell>
 <cell>20.887</cell>
 <cell>4.934</cell>
 <cell>-15.953</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>EDAC_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[10]:D</cell>
 <cell>0.760</cell>
 <cell>20.887</cell>
 <cell>4.934</cell>
 <cell>-15.953</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORECONFIGP_0/MDDR_PENABLE:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PENABLE</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.716</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>-15.633</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>20.349</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.096</cell>
 <cell>3.096</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.225</cell>
 <cell>3.321</cell>
 <cell>3</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.347</cell>
 <cell>3.668</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.150</cell>
 <cell>3.818</cell>
 <cell>68</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/MDDR_PENABLE:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.351</cell>
 <cell>4.169</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/MDDR_PENABLE:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.053</cell>
 <cell>4.222</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_365:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORECONFIGP_0_MDDR_APBmslave_PENABLE</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.354</cell>
 <cell>4.576</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_365:IPA</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.119</cell>
 <cell>4.695</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PENABLE</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/MDDR_FABRIC_PENABLE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.021</cell>
 <cell>4.716</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.716</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-20.000</cell>
 <cell>-20.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>-20.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.881</cell>
 <cell>-17.119</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.216</cell>
 <cell>-16.903</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.361</cell>
 <cell>-16.542</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.194</cell>
 <cell>-16.348</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_361:B</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.272</cell>
 <cell>-16.076</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_361:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.128</cell>
 <cell>-15.948</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_MDDR_APB</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/CLK_MDDR_APB_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.023</cell>
 <cell>-15.925</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PENABLE</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:MSS_120_IP</cell>
 <cell>+</cell>
 <cell>0.292</cell>
 <cell>-15.633</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-15.633</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to FIC2_CLK</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORERESETP_0/INIT_DONE_int:CLK</cell>
 <cell>EDAC_0/CORECONFIGP_0/INIT_DONE_q1:D</cell>
 <cell>1.525</cell>
 <cell>-0.040</cell>
 <cell>3.993</cell>
 <cell>4.033</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORERESETP_0/INIT_DONE_int:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/CORECONFIGP_0/INIT_DONE_q1:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.993</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>4.033</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-0.040</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.321</cell>
 <cell>1.321</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.175</cell>
 <cell>1.496</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.086</cell>
 <cell>1.582</cell>
 <cell>5</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.351</cell>
 <cell>1.933</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.194</cell>
 <cell>2.127</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/INIT_DONE_int:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.341</cell>
 <cell>2.468</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/INIT_DONE_int:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.065</cell>
 <cell>2.533</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/INIT_DONE_q1:D</cell>
 <cell>net</cell>
 <cell>EDAC_0/INIT_DONE_int</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.460</cell>
 <cell>3.993</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.993</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.881</cell>
 <cell>2.881</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.216</cell>
 <cell>3.097</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.360</cell>
 <cell>3.457</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.194</cell>
 <cell>3.651</cell>
 <cell>68</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/INIT_DONE_q1:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.382</cell>
 <cell>4.033</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/INIT_DONE_q1:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>4.033</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.033</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Path Set Pin to Pin</name>
<section>
<name>SET Input to Output</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set User Sets</name>
</section>
</doc>
