<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
<doc>
<title>Timing Report Min Delay Analysis
</title>
<text>SmartTime Version 11.8.0.26</text>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.8 (Version 11.8.0.26)</text>
<text>Date: Tue Mar 14 14:51:34 2017
</text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>EDAC_top</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2S150TS</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>1152 FC</cell>
</row>
<row>
 <cell>Temperature Range</cell>
 <cell>-40 - 100 C</cell>
</row>
<row>
 <cell>Voltage Range</cell>
 <cell>1.14 - 1.26 V</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Design State</cell>
 <cell>Post-Layout</cell>
</row>
<row>
 <cell>Data source</cell>
 <cell>Production</cell>
</row>
<row>
 <cell>Min Operating Conditions</cell>
 <cell>BEST - 1.26 V - -40 C</cell>
</row>
<row>
 <cell>Max Operating Conditions</cell>
 <cell>WORST - 1.14 V - 100 C</cell>
</row>
<row>
 <cell>Scenario for Timing Analysis</cell>
 <cell>Primary</cell>
</row>
</table>
<text></text>
<section>
<name>Summary</name>
<table>
<header>
 <cell>Clock Domain</cell>
 <cell>Period (ns)</cell>
 <cell>Frequency (MHz)</cell>
 <cell>Required Period (ns)</cell>
 <cell>Required Frequency (MHz)</cell>
 <cell>External Setup (ns)</cell>
 <cell>External Hold (ns)</cell>
 <cell>Min Clock-To-Out (ns)</cell>
 <cell>Max Clock-To-Out (ns)</cell>
</header>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>4.857</cell>
 <cell>205.888</cell>
 <cell>10.000</cell>
 <cell>100.000</cell>
 <cell>1.670</cell>
 <cell>-0.743</cell>
 <cell>6.748</cell>
 <cell>11.318</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>3.463</cell>
 <cell>288.767</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell>8.511</cell>
 <cell>117.495</cell>
 <cell>40.000</cell>
 <cell>25.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
<text></text>
<table>
<header>
 <cell></cell>
 <cell>Min Delay (ns)</cell>
 <cell>Max Delay (ns)</cell>
</header>
<row>
 <cell>Input to Output</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
</section>
<section>
<name>Clock Domain EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<text>Info: The maximum frequency of this clock domain is limited by the period of pin EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</text>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_q1:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_clk_base:D</cell>
 <cell>0.308</cell>
 <cell>0.296</cell>
 <cell>2.977</cell>
 <cell>2.681</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>EDAC_0/CORERESETP_0/release_sdif0_core_q1:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/release_sdif0_core_clk_base:D</cell>
 <cell>0.317</cell>
 <cell>0.298</cell>
 <cell>3.000</cell>
 <cell>2.702</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>EDAC_0/CORERESETP_0/POWER_ON_RESET_N_q1:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:D</cell>
 <cell>0.308</cell>
 <cell>0.304</cell>
 <cell>3.003</cell>
 <cell>2.699</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_q1:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:D</cell>
 <cell>0.315</cell>
 <cell>0.304</cell>
 <cell>2.993</cell>
 <cell>2.689</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>EDAC_0/CORERESETP_0/CONFIG1_DONE_q1:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/CONFIG1_DONE_clk_base:D</cell>
 <cell>0.317</cell>
 <cell>0.305</cell>
 <cell>3.004</cell>
 <cell>2.699</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_q1:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_clk_base:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.977</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>2.681</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.296</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.423</cell>
 <cell>1.423</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.188</cell>
 <cell>1.611</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.093</cell>
 <cell>1.704</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.397</cell>
 <cell>2.101</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>2.310</cell>
 <cell>7</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_q1:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.359</cell>
 <cell>2.669</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_q1:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.057</cell>
 <cell>2.726</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_clk_base:D</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_q1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.251</cell>
 <cell>2.977</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.977</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.423</cell>
 <cell>1.423</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.188</cell>
 <cell>1.611</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.093</cell>
 <cell>1.704</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.397</cell>
 <cell>2.101</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>2.310</cell>
 <cell>7</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_clk_base:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.371</cell>
 <cell>2.681</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_clk_base:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.681</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.681</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
 <cell>External Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MMUART_0_RXD_F2M</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_RXD_F2H_SCP</cell>
 <cell>3.096</cell>
 <cell></cell>
 <cell>3.096</cell>
 <cell></cell>
 <cell>-0.559</cell>
 <cell>-0.743</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MMUART_0_RXD_F2M</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_RXD_F2H_SCP</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.096</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MMUART_0_RXD_F2M</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MMUART_0_RXD_F2M_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>MMUART_0_RXD_F2M</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MMUART_0_RXD_F2M_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.460</cell>
 <cell>1.460</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MMUART_0_RXD_F2M_ibuf/U0/U_IOINFF:A</cell>
 <cell>net</cell>
 <cell>MMUART_0_RXD_F2M_ibuf/U0/YIN1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.216</cell>
 <cell>1.676</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MMUART_0_RXD_F2M_ibuf/U0/U_IOINFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOINFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.055</cell>
 <cell>1.731</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_241:A</cell>
 <cell>net</cell>
 <cell>MMUART_0_RXD_F2M_c</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.203</cell>
 <cell>2.934</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_241:IPA</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.128</cell>
 <cell>3.062</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_RXD_F2H_SCP</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/MMUART0_RXD_F2H_SCP_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.034</cell>
 <cell>3.096</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.096</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.467</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.194</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.096</cell>
 <cell>N/C</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.405</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.216</cell>
 <cell>N/C</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.305</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.143</cell>
 <cell>N/C</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.086</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_RXD_F2H_SCP</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:MSS_120_IP</cell>
 <cell>+</cell>
 <cell>-0.559</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Clock to Output</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Clock to Out (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell>MMUART_0_TXD_M2F</cell>
 <cell>3.924</cell>
 <cell></cell>
 <cell>6.748</cell>
 <cell></cell>
 <cell>6.748</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MMUART_0_TXD_M2F</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.748</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.423</cell>
 <cell>1.423</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.188</cell>
 <cell>1.611</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.093</cell>
 <cell>1.704</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.393</cell>
 <cell>2.097</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>2.306</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.296</cell>
 <cell>2.602</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.138</cell>
 <cell>2.740</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.084</cell>
 <cell>2.824</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_TXD_MGPIO27B_H2F_A</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MSS_120_IP</cell>
 <cell>+</cell>
 <cell>0.673</cell>
 <cell>3.497</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_TXD_M2F_obuf/U0/U_IOOUTFF:A</cell>
 <cell>net</cell>
 <cell>MMUART_0_TXD_M2F_c</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.154</cell>
 <cell>4.651</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_TXD_M2F_obuf/U0/U_IOOUTFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOOUTFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.224</cell>
 <cell>4.875</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_TXD_M2F_obuf/U0/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>MMUART_0_TXD_M2F_obuf/U0/DOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.363</cell>
 <cell>5.238</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_TXD_M2F_obuf/U0/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>1.510</cell>
 <cell>6.748</cell>
 <cell>0</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_TXD_M2F</cell>
 <cell>net</cell>
 <cell>MMUART_0_TXD_M2F</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>6.748</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.748</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.423</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MMUART_0_TXD_M2F</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:ALn</cell>
 <cell>0.775</cell>
 <cell>0.781</cell>
 <cell>3.462</cell>
 <cell>2.681</cell>
 <cell>0.000</cell>
 <cell>0.006</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>EDAC_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/mss_ready_state:ALn</cell>
 <cell>0.775</cell>
 <cell>0.781</cell>
 <cell>3.462</cell>
 <cell>2.681</cell>
 <cell>0.000</cell>
 <cell>0.006</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>EDAC_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/mss_ready_select:ALn</cell>
 <cell>0.775</cell>
 <cell>0.781</cell>
 <cell>3.462</cell>
 <cell>2.681</cell>
 <cell>0.000</cell>
 <cell>0.006</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_q1:ALn</cell>
 <cell>1.027</cell>
 <cell>1.008</cell>
 <cell>3.697</cell>
 <cell>2.689</cell>
 <cell>0.000</cell>
 <cell>-0.019</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:ALn</cell>
 <cell>1.027</cell>
 <cell>1.008</cell>
 <cell>3.697</cell>
 <cell>2.689</cell>
 <cell>0.000</cell>
 <cell>-0.019</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.462</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>2.681</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.781</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.423</cell>
 <cell>1.423</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.188</cell>
 <cell>1.611</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.093</cell>
 <cell>1.704</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.397</cell>
 <cell>2.101</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>2.310</cell>
 <cell>12</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.377</cell>
 <cell>2.687</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.057</cell>
 <cell>2.744</cell>
 <cell>3</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:ALn</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/POWER_ON_RESET_N_clk_base</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.718</cell>
 <cell>3.462</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.462</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.423</cell>
 <cell>1.423</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.188</cell>
 <cell>1.611</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.093</cell>
 <cell>1.704</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.397</cell>
 <cell>2.101</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>2.310</cell>
 <cell>7</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.371</cell>
 <cell>2.681</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.681</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.681</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT to EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET FIC2_CLK to EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORECONFIGP_0/soft_reset_reg[1]:CLK</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:USER_MSS_RESET_N</cell>
 <cell>1.474</cell>
 <cell>27.058</cell>
 <cell>5.797</cell>
 <cell>-21.261</cell>
 <cell></cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>EDAC_0/CORECONFIGP_0/control_reg_1[0]:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/CONFIG1_DONE_q1:D</cell>
 <cell>3.120</cell>
 <cell>28.734</cell>
 <cell>7.433</cell>
 <cell>-21.301</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>EDAC_0/CORECONFIGP_0/control_reg_1[1]:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/CONFIG2_DONE_q1:D</cell>
 <cell>3.153</cell>
 <cell>28.780</cell>
 <cell>7.482</cell>
 <cell>-21.298</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORECONFIGP_0/soft_reset_reg[1]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:USER_MSS_RESET_N</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.797</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>-21.261</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>27.058</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.122</cell>
 <cell>3.122</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.233</cell>
 <cell>3.355</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.388</cell>
 <cell>3.743</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>3.952</cell>
 <cell>53</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/soft_reset_reg[1]:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.371</cell>
 <cell>4.323</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/soft_reset_reg[1]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.070</cell>
 <cell>4.393</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/soft_reset_reg_RNIQTRD[1]:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORECONFIGP_0/CORECONFIGP_0_SOFT_RESET_F2M</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.214</cell>
 <cell>4.607</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/soft_reset_reg_RNIQTRD[1]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1</cell>
 <cell>+</cell>
 <cell>0.066</cell>
 <cell>4.673</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_204:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORECONFIGP_0_SOFT_RESET_F2M_i</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.962</cell>
 <cell>5.635</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_204:IPA</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.128</cell>
 <cell>5.763</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:USER_MSS_RESET_N</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/USER_MSS_RESET_N_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.034</cell>
 <cell>5.797</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.797</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Min Delay Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-24.000</cell>
 <cell>-24.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>-24.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.423</cell>
 <cell>-22.577</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.188</cell>
 <cell>-22.389</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.093</cell>
 <cell>-22.296</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.393</cell>
 <cell>-21.903</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>-21.694</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.296</cell>
 <cell>-21.398</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.138</cell>
 <cell>-21.260</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.086</cell>
 <cell>-21.174</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:USER_MSS_RESET_N</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:MSS_120_IP</cell>
 <cell>+</cell>
 <cell>-0.087</cell>
 <cell>-21.261</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-21.261</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Clock Domain EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc_q1:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:D</cell>
 <cell>0.313</cell>
 <cell>0.302</cell>
 <cell>5.841</cell>
 <cell>5.539</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr_enable_q1:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr_enable_rcosc:D</cell>
 <cell>0.315</cell>
 <cell>0.310</cell>
 <cell>5.834</cell>
 <cell>5.524</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr_enable_rcosc:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[13]:EN</cell>
 <cell>0.420</cell>
 <cell>0.390</cell>
 <cell>5.933</cell>
 <cell>5.543</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr_enable_rcosc:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[0]:EN</cell>
 <cell>0.420</cell>
 <cell>0.390</cell>
 <cell>5.933</cell>
 <cell>5.543</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[0]:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[0]:D</cell>
 <cell>0.392</cell>
 <cell>0.392</cell>
 <cell>5.924</cell>
 <cell>5.532</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc_q1:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.841</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>5.539</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.302</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.921</cell>
 <cell>0.921</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.100</cell>
 <cell>1.021</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.306</cell>
 <cell>4.327</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.233</cell>
 <cell>4.560</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.401</cell>
 <cell>4.961</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>5.170</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc_q1:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.358</cell>
 <cell>5.528</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc_q1:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.057</cell>
 <cell>5.585</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:D</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_q1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.256</cell>
 <cell>5.841</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.841</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.921</cell>
 <cell>0.921</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.100</cell>
 <cell>1.021</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.306</cell>
 <cell>4.327</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.233</cell>
 <cell>4.560</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.401</cell>
 <cell>4.961</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>5.170</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.369</cell>
 <cell>5.539</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>5.539</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.539</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[5]:ALn</cell>
 <cell>2.031</cell>
 <cell>1.995</cell>
 <cell>7.559</cell>
 <cell>5.564</cell>
 <cell>0.000</cell>
 <cell>-0.036</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[3]:ALn</cell>
 <cell>2.031</cell>
 <cell>1.995</cell>
 <cell>7.559</cell>
 <cell>5.564</cell>
 <cell>0.000</cell>
 <cell>-0.036</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[9]:ALn</cell>
 <cell>2.031</cell>
 <cell>1.995</cell>
 <cell>7.559</cell>
 <cell>5.564</cell>
 <cell>0.000</cell>
 <cell>-0.036</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[11]:ALn</cell>
 <cell>2.031</cell>
 <cell>1.995</cell>
 <cell>7.559</cell>
 <cell>5.564</cell>
 <cell>0.000</cell>
 <cell>-0.036</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>EDAC_0/CORERESETP_0/count_ddr[1]:ALn</cell>
 <cell>2.031</cell>
 <cell>1.995</cell>
 <cell>7.559</cell>
 <cell>5.564</cell>
 <cell>0.000</cell>
 <cell>-0.036</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/CORERESETP_0/count_ddr[5]:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.559</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>5.564</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.995</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.921</cell>
 <cell>0.921</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.100</cell>
 <cell>1.021</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.306</cell>
 <cell>4.327</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.233</cell>
 <cell>4.560</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.401</cell>
 <cell>4.961</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>5.170</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.358</cell>
 <cell>5.528</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.057</cell>
 <cell>5.585</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.739</cell>
 <cell>6.324</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.233</cell>
 <cell>6.557</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.398</cell>
 <cell>6.955</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>7.164</cell>
 <cell>15</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/count_ddr[5]:ALn</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.395</cell>
 <cell>7.559</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.559</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.921</cell>
 <cell>0.921</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.100</cell>
 <cell>1.021</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.306</cell>
 <cell>4.327</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.233</cell>
 <cell>4.560</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.401</cell>
 <cell>4.961</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>5.170</cell>
 <cell>15</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/count_ddr[5]:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.394</cell>
 <cell>5.564</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/count_ddr[5]:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>5.564</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.564</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain FIC2_CLK</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORECONFIGP_0/MDDR_PENABLE:CLK</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PENABLE</cell>
 <cell>0.537</cell>
 <cell>20.368</cell>
 <cell>5.068</cell>
 <cell>-15.300</cell>
 <cell>0.292</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>EDAC_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PSEL</cell>
 <cell>1.223</cell>
 <cell>20.763</cell>
 <cell>5.750</cell>
 <cell>-15.013</cell>
 <cell>0.579</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>EDAC_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[0]:D</cell>
 <cell>0.685</cell>
 <cell>20.877</cell>
 <cell>5.212</cell>
 <cell>-15.665</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell>EDAC_0/CORECONFIGP_0/soft_reset_reg[15]:D</cell>
 <cell>1.225</cell>
 <cell>20.885</cell>
 <cell>1.225</cell>
 <cell>-19.660</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell>EDAC_0/CORECONFIGP_0/pwdata[15]:D</cell>
 <cell>1.225</cell>
 <cell>20.885</cell>
 <cell>1.225</cell>
 <cell>-19.660</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORECONFIGP_0/MDDR_PENABLE:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PENABLE</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.068</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>-15.300</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>20.368</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.368</cell>
 <cell>3.368</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.242</cell>
 <cell>3.610</cell>
 <cell>3</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.375</cell>
 <cell>3.985</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.162</cell>
 <cell>4.147</cell>
 <cell>53</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/MDDR_PENABLE:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.384</cell>
 <cell>4.531</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/MDDR_PENABLE:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.057</cell>
 <cell>4.588</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_365:A</cell>
 <cell>net</cell>
 <cell>EDAC_0/CORECONFIGP_0_MDDR_APBmslave_PENABLE</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.329</cell>
 <cell>4.917</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_365:IPA</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.128</cell>
 <cell>5.045</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PENABLE</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/MDDR_FABRIC_PENABLE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.023</cell>
 <cell>5.068</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.068</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-20.000</cell>
 <cell>-20.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>-20.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.122</cell>
 <cell>-16.878</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.233</cell>
 <cell>-16.645</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.389</cell>
 <cell>-16.256</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>-16.047</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_361:B</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.294</cell>
 <cell>-15.753</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_361:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.138</cell>
 <cell>-15.615</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_MDDR_APB</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/CLK_MDDR_APB_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.023</cell>
 <cell>-15.592</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PENABLE</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:MSS_120_IP</cell>
 <cell>+</cell>
 <cell>0.292</cell>
 <cell>-15.300</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-15.300</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to FIC2_CLK</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>EDAC_0/CORERESETP_0/INIT_DONE_int:CLK</cell>
 <cell>EDAC_0/CORECONFIGP_0/INIT_DONE_q1:D</cell>
 <cell>3.095</cell>
 <cell>1.450</cell>
 <cell>5.782</cell>
 <cell>4.332</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: EDAC_0/CORERESETP_0/INIT_DONE_int:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: EDAC_0/CORECONFIGP_0/INIT_DONE_q1:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.782</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>4.332</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.450</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.423</cell>
 <cell>1.423</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.188</cell>
 <cell>1.611</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.093</cell>
 <cell>1.704</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.397</cell>
 <cell>2.101</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>2.310</cell>
 <cell>12</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/INIT_DONE_int:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.377</cell>
 <cell>2.687</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORERESETP_0/INIT_DONE_int:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.057</cell>
 <cell>2.744</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/INIT_DONE_q1:D</cell>
 <cell>net</cell>
 <cell>EDAC_0/INIT_DONE_int</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.038</cell>
 <cell>5.782</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.782</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.122</cell>
 <cell>3.122</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.233</cell>
 <cell>3.355</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.388</cell>
 <cell>3.743</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>3.952</cell>
 <cell>53</cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/INIT_DONE_q1:CLK</cell>
 <cell>net</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.380</cell>
 <cell>4.332</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>EDAC_0/CORECONFIGP_0/INIT_DONE_q1:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>4.332</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.332</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Path Set Pin to Pin</name>
<section>
<name>SET Input to Output</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set User Sets</name>
</section>
</doc>
