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<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
<doc>
<text>SmartTime Version 11.8.0.26</text>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.8 (Version 11.8.0.26)
Date: Tue Mar 14 14:51:34 2017 </text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>EDAC_top</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2S150TS</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>1152 FC</cell>
</row>
<row>
 <cell>Temperature Range</cell>
 <cell>-40 - 100 C</cell>
</row>
<row>
 <cell>Voltage Range</cell>
 <cell>1.14 - 1.26 V</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
</table>
<text></text>
<text></text>
<section>
<name>Coverage Summary</name>
<text></text>
<table>
<header>
 <cell>Type of check</cell>
 <cell>Constrained</cell>
 <cell>UnConstrained</cell>
 <cell>Total</cell>
</header>
<row>
 <cell>Setup</cell>
 <cell>          243</cell>
 <cell>            5</cell>
 <cell>          248</cell>
</row>
<row>
 <cell>Recovery</cell>
 <cell>           43</cell>
 <cell>           83</cell>
 <cell>          126</cell>
</row>
<row>
 <cell>Output Setup</cell>
 <cell>            0</cell>
 <cell>            1</cell>
 <cell>            1</cell>
</row>
<row>
 <cell>Total Setup</cell>
 <cell>          286</cell>
 <cell>           89</cell>
 <cell>          375</cell>
</row>
<separator/>
<row>
 <cell>Hold</cell>
 <cell>          243</cell>
 <cell>            5</cell>
 <cell>          248</cell>
</row>
<row>
 <cell>Removal</cell>
 <cell>           43</cell>
 <cell>           83</cell>
 <cell>          126</cell>
</row>
<row>
 <cell>Output Hold</cell>
 <cell>            0</cell>
 <cell>            1</cell>
 <cell>            1</cell>
</row>
<row>
 <cell>Total Hold</cell>
 <cell>          286</cell>
 <cell>           89</cell>
 <cell>          375</cell>
</row>
</table>
<section>
<name>Clock domain: </name>
<text>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</text>
<text></text>
<table>
<header>
 <cell>Type of check</cell>
 <cell>Constrained</cell>
 <cell>UnConstrained</cell>
 <cell>Total</cell>
</header>
<row>
 <cell>Setup</cell>
 <cell>           23</cell>
 <cell>            4</cell>
 <cell>           27</cell>
</row>
<row>
 <cell>Recovery</cell>
 <cell>           25</cell>
 <cell>            6</cell>
 <cell>           31</cell>
</row>
<row>
 <cell>Output Setup</cell>
 <cell>            0</cell>
 <cell>            1</cell>
 <cell>            1</cell>
</row>
<row>
 <cell>Total Setup</cell>
 <cell>           48</cell>
 <cell>           11</cell>
 <cell>           59</cell>
</row>
<separator/>
<row>
 <cell>Hold</cell>
 <cell>           23</cell>
 <cell>            4</cell>
 <cell>           27</cell>
</row>
<row>
 <cell>Removal</cell>
 <cell>           25</cell>
 <cell>            6</cell>
 <cell>           31</cell>
</row>
<row>
 <cell>Output Hold</cell>
 <cell>            0</cell>
 <cell>            1</cell>
 <cell>            1</cell>
</row>
<row>
 <cell>Total Hold</cell>
 <cell>           48</cell>
 <cell>           11</cell>
 <cell>           59</cell>
</row>
</table>
<section>
<name>Enhancement Suggestions</name>
<text></text>
<text> - Max input delay constraint missing on  port:</text>
<text>   </text>
<list>
 <item>MMUART_0_RXD_F2M</item>
</list>
<text></text>
<text> - Min input delay constraint missing on  port:</text>
<text>   </text>
<list>
 <item>MMUART_0_RXD_F2M</item>
</list>
<text></text>
<text></text>
<text> - Max output delay constraint missing on  port:</text>
<text>   </text>
<list>
 <item>MMUART_0_TXD_M2F</item>
</list>
<text></text>
<text> - Min output delay constraint missing on  port:</text>
<text>   </text>
<list>
 <item>MMUART_0_TXD_M2F</item>
</list>
<text></text>
<text></text>
<text> - Setup uncconstrained for the following pins:</text>
<text>   </text>
<list>
 <item>EDAC_0/CORERESETP_0/ddr_settled_q1:D</item>
 <item>EDAC_0/CORERESETP_0/release_sdif0_core_q1:D</item>
 <item>EDAC_0/CORERESETP_0/sm0_state[0]:D</item>
 <item>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_RXD_F2H_SCP</item>
</list>
<text></text>
<text> - Recovery uncconstrained for the following pins:</text>
<text>   </text>
<list>
 <item>EDAC_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_clk_base:ALn</item>
 <item>EDAC_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_q1:ALn</item>
 <item>EDAC_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:ALn</item>
 <item>EDAC_0/CORERESETP_0/POWER_ON_RESET_N_q1:ALn</item>
 <item>EDAC_0/CORERESETP_0/RESET_N_M2F_clk_base:ALn</item>
 <item>EDAC_0/CORERESETP_0/RESET_N_M2F_q1:ALn</item>
</list>
<text></text>
<text> - Hold uncconstrained for the following pins:</text>
<text>   </text>
<list>
 <item>EDAC_0/CORERESETP_0/ddr_settled_q1:D</item>
 <item>EDAC_0/CORERESETP_0/release_sdif0_core_q1:D</item>
 <item>EDAC_0/CORERESETP_0/sm0_state[0]:D</item>
 <item>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_RXD_F2H_SCP</item>
</list>
<text></text>
<text> - Removal uncconstrained for the following pins:</text>
<text>   </text>
<list>
 <item>EDAC_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_clk_base:ALn</item>
 <item>EDAC_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_q1:ALn</item>
 <item>EDAC_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:ALn</item>
 <item>EDAC_0/CORERESETP_0/POWER_ON_RESET_N_q1:ALn</item>
 <item>EDAC_0/CORERESETP_0/RESET_N_M2F_clk_base:ALn</item>
 <item>EDAC_0/CORERESETP_0/RESET_N_M2F_q1:ALn</item>
</list>
<text></text>
</section>
</section>
<section>
<name>Clock domain: </name>
<text>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</text>
<text></text>
<table>
<header>
 <cell>Type of check</cell>
 <cell>Constrained</cell>
 <cell>UnConstrained</cell>
 <cell>Total</cell>
</header>
<row>
 <cell>Setup</cell>
 <cell>           31</cell>
 <cell>            1</cell>
 <cell>           32</cell>
</row>
<row>
 <cell>Recovery</cell>
 <cell>           18</cell>
 <cell>            2</cell>
 <cell>           20</cell>
</row>
<row>
 <cell>Output Setup</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<row>
 <cell>Total Setup</cell>
 <cell>           49</cell>
 <cell>            3</cell>
 <cell>           52</cell>
</row>
<separator/>
<row>
 <cell>Hold</cell>
 <cell>           31</cell>
 <cell>            1</cell>
 <cell>           32</cell>
</row>
<row>
 <cell>Removal</cell>
 <cell>           18</cell>
 <cell>            2</cell>
 <cell>           20</cell>
</row>
<row>
 <cell>Output Hold</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<row>
 <cell>Total Hold</cell>
 <cell>           49</cell>
 <cell>            3</cell>
 <cell>           52</cell>
</row>
</table>
<section>
<name>Enhancement Suggestions</name>
<text></text>
<text></text>
<text></text>
<text> - Setup uncconstrained for the following pin:</text>
<text>   </text>
<list>
 <item>EDAC_0/CORERESETP_0/count_ddr_enable_q1:D</item>
</list>
<text></text>
<text> - Recovery uncconstrained for the following pins:</text>
<text>   </text>
<list>
 <item>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc_q1:ALn</item>
 <item>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:ALn</item>
</list>
<text></text>
<text> - Hold uncconstrained for the following pin:</text>
<text>   </text>
<list>
 <item>EDAC_0/CORERESETP_0/count_ddr_enable_q1:D</item>
</list>
<text></text>
<text> - Removal uncconstrained for the following pins:</text>
<text>   </text>
<list>
 <item>EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc_q1:ALn</item>
 <item>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:ALn</item>
</list>
<text></text>
</section>
</section>
<section>
<name>Clock domain: </name>
<text>FIC2_CLK</text>
<text></text>
<table>
<header>
 <cell>Type of check</cell>
 <cell>Constrained</cell>
 <cell>UnConstrained</cell>
 <cell>Total</cell>
</header>
<row>
 <cell>Setup</cell>
 <cell>          189</cell>
 <cell>            0</cell>
 <cell>          189</cell>
</row>
<row>
 <cell>Recovery</cell>
 <cell>            0</cell>
 <cell>           75</cell>
 <cell>           75</cell>
</row>
<row>
 <cell>Output Setup</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<row>
 <cell>Total Setup</cell>
 <cell>          189</cell>
 <cell>           75</cell>
 <cell>          264</cell>
</row>
<separator/>
<row>
 <cell>Hold</cell>
 <cell>          189</cell>
 <cell>            0</cell>
 <cell>          189</cell>
</row>
<row>
 <cell>Removal</cell>
 <cell>            0</cell>
 <cell>           75</cell>
 <cell>           75</cell>
</row>
<row>
 <cell>Output Hold</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<row>
 <cell>Total Hold</cell>
 <cell>          189</cell>
 <cell>           75</cell>
 <cell>          264</cell>
</row>
</table>
<section>
<name>Enhancement Suggestions</name>
<text></text>
<text></text>
<text></text>
<text> - Recovery uncconstrained for the following pins:</text>
<text>   </text>
<list>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[0]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[10]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[11]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[12]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[13]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[14]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[15]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[16]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[17]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[1]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[2]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[3]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[4]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[5]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[6]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[7]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[8]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[9]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PSLVERR:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/INIT_DONE_q1:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/INIT_DONE_q2:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/MDDR_PENABLE:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/control_reg_1[0]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/control_reg_1[1]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[10]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[12]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[13]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[15]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[16]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[2]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[3]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[4]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[5]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[6]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[7]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[8]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[9]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/psel:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[0]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[10]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[11]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[12]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[13]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[14]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[15]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[1]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[2]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[3]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[4]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[5]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[6]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[7]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[8]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[9]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwrite:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[0]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[10]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[11]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[12]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[13]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[14]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[15]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[16]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[1]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[2]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[3]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[4]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[5]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[6]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[7]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[8]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[9]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/state[0]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/state[1]:ALn</item>
</list>
<text></text>
<text> - Removal uncconstrained for the following pins:</text>
<text>   </text>
<list>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[0]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[10]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[11]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[12]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[13]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[14]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[15]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[16]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[17]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[1]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[2]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[3]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[4]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[5]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[6]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[7]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[8]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[9]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PSLVERR:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/INIT_DONE_q1:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/INIT_DONE_q2:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/MDDR_PENABLE:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/control_reg_1[0]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/control_reg_1[1]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[10]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[12]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[13]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[15]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[16]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[2]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[3]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[4]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[5]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[6]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[7]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[8]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/paddr[9]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/psel:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[0]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[10]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[11]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[12]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[13]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[14]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[15]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[1]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[2]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[3]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[4]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[5]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[6]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[7]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[8]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwdata[9]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/pwrite:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[0]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[10]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[11]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[12]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[13]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[14]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[15]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[16]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[1]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[2]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[3]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[4]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[5]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[6]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[7]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[8]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/soft_reset_reg[9]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/state[0]:ALn</item>
 <item>EDAC_0/CORECONFIGP_0/state[1]:ALn</item>
</list>
<text></text>
</section>
</section>
<section>
<name>Input to Output</name>
<table>
<header>
 <cell>Type of check</cell>
 <cell>Constrained</cell>
 <cell>UnConstrained</cell>
 <cell>Total</cell>
</header>
<row>
 <cell>Output Setup</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<separator/>
<row>
 <cell>Output Hold</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
</table>
</section>
</section>
</doc>
