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<doc>
<title>Global Net Report</title>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.8 (Version 11.8.0.26)</text>
<text>Date: Tue Mar 14 14:33:54 2017
</text>
<section>
<name>Global Nets Information</name>
<table>
<header>
 <cell/>
 <cell> From </cell>
 <cell> GB Location </cell>
 <cell> Net Name </cell>
 <cell> Fanout </cell>
</header>
<row>
 <cell>1</cell>
 <cell>GB[1] </cell>
 <cell>(723, 156)</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6/U0_YWn</cell>
 <cell>78</cell>
</row>
<row>
 <cell>2</cell>
 <cell>GB[5] </cell>
 <cell>(727, 156)</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_YWn_GEast</cell>
 <cell>76</cell>
</row>
<row>
 <cell>3</cell>
 <cell>GB[7] </cell>
 <cell>(729, 156)</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn</cell>
 <cell>31</cell>
</row>
<row>
 <cell>4</cell>
 <cell>GB[3] </cell>
 <cell>(725, 156)</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn</cell>
 <cell>20</cell>
</row>
<row>
 <cell>5</cell>
 <cell>GB[2] </cell>
 <cell>(724, 156)</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base_RNIMUV2/U0_YWn_GEast</cell>
 <cell>19</cell>
</row>
<row>
 <cell>6</cell>
 <cell>GB[6] </cell>
 <cell>(728, 156)</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683/U0_YWn</cell>
 <cell>18</cell>
</row>
</table>
<text></text>
</section>
<section>
<name>I/O to GB Connections</name>
<text>(none)</text>
</section>
<section>
<name>Fabric to GB Connections</name>
<table>
<header>
 <cell/>
 <cell> From </cell>
 <cell> From Location </cell>
 <cell> To </cell>
 <cell> Net Name </cell>
 <cell> Net Type </cell>
 <cell> Fanout </cell>
</header>
<row>
 <cell>1</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CONFIG_PRESET_N</cell>
 <cell>(1200, 314)</cell>
 <cell>GB[1] </cell>
 <cell>EDAC_0/EDAC_MSS_0/CONFIG_PRESET_N</cell>
 <cell>ROUTED</cell>
 <cell>1</cell>
</row>
<row>
 <cell>2</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell>(1200, 314)</cell>
 <cell>GB[5] </cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK</cell>
 <cell>ROUTED</cell>
 <cell>1</cell>
</row>
<row>
 <cell>3</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>(25, 302)</cell>
 <cell>GB[3] </cell>
 <cell>EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell>ROUTED</cell>
 <cell>1</cell>
</row>
<row>
 <cell>4</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:Q</cell>
 <cell>(723, 160)</cell>
 <cell>GB[2] </cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base_0</cell>
 <cell>ROUTED</cell>
 <cell>1</cell>
</row>
<row>
 <cell>5</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:Q</cell>
 <cell>(725, 160)</cell>
 <cell>GB[6] </cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_0</cell>
 <cell>ROUTED</cell>
 <cell>1</cell>
</row>
</table>
<text></text>
</section>
<section>
<name>CCC to GB Connections</name>
<table>
<header>
 <cell/>
 <cell> From </cell>
 <cell> From Location </cell>
 <cell>Pin Swapped for Back Annotation Only</cell>
 <cell> To </cell>
 <cell> Net Name </cell>
 <cell> Net Type </cell>
 <cell> Fanout </cell>
</header>
<row>
 <cell>1</cell>
 <cell>EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>CCC-NW1 (18, 302)</cell>
 <cell>GL0 =&gt; GL3</cell>
 <cell>GB[7] </cell>
 <cell>EDAC_0/CCC_0/GL0_net</cell>
 <cell>HARDWIRED</cell>
 <cell>1</cell>
</row>
</table>
<text></text>
</section>
<section>
<name>CCC Input Connections</name>
<text>(none)</text>
</section>
<section>
<name>Local Clock Nets to RGB Connections</name>
<text>(none)</text>
</section>
<section>
<name>Global Clock Nets to RGB Connections</name>
<table>
<header>
 <cell/>
 <cell> From </cell>
 <cell> From Location </cell>
 <cell> Net Name </cell>
 <cell> Fanout </cell>
 <cell> </cell>
 <cell> RGB Location </cell>
 <cell> Local Fanout </cell>
</header>
<row>
 <cell>1</cell>
 <cell>GB[1] </cell>
 <cell>(723, 156)</cell>
 <cell>EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6/U0_YWn</cell>
 <cell>78</cell>
 <cell>1</cell>
 <cell>(362, 159)</cell>
 <cell>2</cell>
</row>
<row>
 <cell> </cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2</cell>
 <cell>(1095, 306)</cell>
 <cell>22</cell>
</row>
<row>
 <cell> </cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3</cell>
 <cell>(1095, 309)</cell>
 <cell>53</cell>
</row>
<row>
 <cell> </cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4</cell>
 <cell>(1095, 312)</cell>
 <cell>1</cell>
</row>
<row>
 <cell>2</cell>
 <cell>GB[5] </cell>
 <cell>(727, 156)</cell>
 <cell>EDAC_0/EDAC_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI959C/U0_YWn_GEast</cell>
 <cell>76</cell>
 <cell>1</cell>
 <cell>(1094, 306)</cell>
 <cell>22</cell>
</row>
<row>
 <cell> </cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2</cell>
 <cell>(1094, 309)</cell>
 <cell>53</cell>
</row>
<row>
 <cell> </cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3</cell>
 <cell>(1094, 312)</cell>
 <cell>1</cell>
</row>
<row>
 <cell>3</cell>
 <cell>GB[7] </cell>
 <cell>(729, 156)</cell>
 <cell>EDAC_0/CCC_0/GL0_INST/U0_YWn</cell>
 <cell>31</cell>
 <cell>1</cell>
 <cell>(364, 159)</cell>
 <cell>7</cell>
</row>
<row>
 <cell> </cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2</cell>
 <cell>(364, 162)</cell>
 <cell>2</cell>
</row>
<row>
 <cell> </cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3</cell>
 <cell>(1094, 294)</cell>
 <cell>1</cell>
</row>
<row>
 <cell> </cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4</cell>
 <cell>(1095, 159)</cell>
 <cell>12</cell>
</row>
<row>
 <cell> </cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5</cell>
 <cell>(1097, 162)</cell>
 <cell>9</cell>
</row>
<row>
 <cell>4</cell>
 <cell>GB[3] </cell>
 <cell>(725, 156)</cell>
 <cell>EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn</cell>
 <cell>20</cell>
 <cell>1</cell>
 <cell>(363, 159)</cell>
 <cell>2</cell>
</row>
<row>
 <cell> </cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2</cell>
 <cell>(363, 162)</cell>
 <cell>15</cell>
</row>
<row>
 <cell> </cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3</cell>
 <cell>(1095, 162)</cell>
 <cell>3</cell>
</row>
<row>
 <cell>5</cell>
 <cell>GB[2] </cell>
 <cell>(724, 156)</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_clk_base_RNIMUV2/U0_YWn_GEast</cell>
 <cell>19</cell>
 <cell>1</cell>
 <cell>(1094, 159)</cell>
 <cell>10</cell>
</row>
<row>
 <cell> </cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2</cell>
 <cell>(1096, 162)</cell>
 <cell>9</cell>
</row>
<row>
 <cell>6</cell>
 <cell>GB[6] </cell>
 <cell>(728, 156)</cell>
 <cell>EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683/U0_YWn</cell>
 <cell>18</cell>
 <cell>1</cell>
 <cell>(362, 162)</cell>
 <cell>15</cell>
</row>
<row>
 <cell> </cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2</cell>
 <cell>(1094, 162)</cell>
 <cell>3</cell>
</row>
</table>
<text></text>
</section>
</doc>
