#Build: Synplify Pro (R) Q-2020.03M-SP1, Build 166R, Oct 19 2020 #install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro #OS: Windows 8 6.2 #Hostname: HYD-LT-I52881 # Sun Mar 28 21:10:12 2021 #Implementation: synthesis Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys HDL Compiler, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys Verilog Compiler, Version comp202003synp2, Build 170R, Built Oct 21 2020 10:52:30, @ @N: : | Running in 64-bit mode @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\smartfusion2.v" (library work) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DATA_CAPTURE.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\SYNC_ENC.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CLOCK_GEN_RX.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DATA_SYNC_BUF.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DESCRAMBLER.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_SHIFT.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DEC_ERR.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DEC_DATA.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DEC_RD_L.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\SYNC_FSM.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DECODER_L.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DEC_RD_U.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DECODER_U.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DEC_WA.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\FL_AMC.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\FADM_OR.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\EB_CTRL.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\EB_RAM_RTL.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\ADJ_BUF.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\ILA_FSM.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\LINK_COMP.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\LABDM.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\ADJ_CTRL.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CGS.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\RX_CTRL.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\JESD204BRX_LANE.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\RESET_SYNC.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\DATA_CAPTURE.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\PHASE_CHECK.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CLOCK_GEN_TX.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\MUX4X1.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\MUX32X1.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\MUX32X6.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\ENC_D.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\ENC_FLIP.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\ENC_K.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\ENCODER_L.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\ENCODER_N.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\ENCODER_U.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\BUF_DATA.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\ENCODER_64B80B.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\SCRAMBLER.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ACG.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_CTRL.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ILA.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\JESD204BTX_LANE.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\RESET_SYNC.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\DATA_SYNC_BUF_TX.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\SYNC_DEC.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\DATA_HANDLE_FSM.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\PRBS_GENERATOR.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\PRBS_WAV_SEL.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\wav_gen_16bit.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\DATA_GENERATOR\DATA_GENERATOR.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\ERR_GEN.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\LED_BLOCK_2.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\PRBS_CHECKER.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\SERDES_EPCS\SERDES_IF2_0\SERDES_EPCS_SERDES_IF2_0_SERDES_IF2_syn.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\SERDES_EPCS\SERDES_IF2_0\SERDES_EPCS_SERDES_IF2_0_SERDES_IF2.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\delay_line.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\epcs_rx_intf.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\epcs_tx_intf.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\SERDES_EPCS\SERDES_EPCS.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\SF2_JESD204B_DEMO_sb\CCC_0\SF2_JESD204B_DEMO_sb_CCC_0_FCCC.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\SF2_JESD204B_DEMO_sb\FABOSC_0\SF2_JESD204B_DEMO_sb_FABOSC_0_OSC.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\SF2_JESD204B_DEMO_sb_MSS\SF2_JESD204B_DEMO_sb_MSS_syn.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\SF2_JESD204B_DEMO_sb_MSS\SF2_JESD204B_DEMO_sb_MSS.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_muxptob3.v" (library COREAPB3_LIB) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_iaddr_reg.v" (library COREAPB3_LIB) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v" (library COREAPB3_LIB) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\SF2_JESD204B_DEMO_sb\SF2_JESD204B_DEMO_sb.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\top\TPSRAM_0\top_TPSRAM_0_TPSRAM.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\top\TPSRAM_1\top_TPSRAM_1_TPSRAM.v" (library work) @I::"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\top\top.v" (library work) Verilog syntax check successful! Selecting top level module top @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT in library work. Running optimization stage 1 on CLKINT ....... @N:CG364 : DATA_CAPTURE.v(19) | Synthesizing module CJESDRX_DATA_CAPTURE in library work. DATA_WIDTH=32'b00000000000000000000000000010100 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDRX_DATA_CAPTURE_20s_0s Running optimization stage 1 on CJESDRX_DATA_CAPTURE_20s_0s ....... @N:CG364 : DATA_CAPTURE.v(19) | Synthesizing module CJESDRX_DATA_CAPTURE in library work. DATA_WIDTH=32'b00000000000000000000000000000010 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDRX_DATA_CAPTURE_2s_0s Running optimization stage 1 on CJESDRX_DATA_CAPTURE_2s_0s ....... @N:CG364 : DATA_CAPTURE.v(19) | Synthesizing module CJESDRX_DATA_CAPTURE in library work. DATA_WIDTH=32'b00000000000000000000000000010000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDRX_DATA_CAPTURE_16s_0s Running optimization stage 1 on CJESDRX_DATA_CAPTURE_16s_0s ....... @N:CG364 : SYNC_ENC.v(18) | Synthesizing module CJESDRX_SYNC_ENC in library work. K_WIDTH=32'b00000000000000000000000000000010 SYNC_RESET=32'b00000000000000000000000000000000 L=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 SYNC_DUR_MIN=32'b00000000000000000000000000110110 SUBCLASSV=32'b00000000000000000000000000000000 SG_INIT=2'b00 SG_ASSERT=2'b01 SG_DEASSERT=2'b10 Generated name = CJESDRX_SYNC_ENC_2s_0s_0s_2s_9s_54s_0s_0_1_2 @N:CG179 : SYNC_ENC.v(131) | Removing redundant assignment. Running optimization stage 1 on CJESDRX_SYNC_ENC_2s_0s_0s_2s_9s_54s_0s_0_1_2 ....... @N:CG364 : CLOCK_GEN_RX.v(18) | Synthesizing module CJESDRX_CLOCK_GEN_RX in library work. D_WIDTH=32'b00000000000000000000000000010000 SYNC_RESET=32'b00000000000000000000000000000000 R=32'b00000000000000000000000000000100 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 SUBCLASSV=32'b00000000000000000000000000000000 JESDV=32'b00000000000000000000000000000001 lmfc_period=32'b00000000000000000000000000010010 fc_period=32'b00000000000000000000000000000010 sysref_high=32'b00000000000000000000000000000100 ERR_TRIG_EVEN=32'b00000000000000000000000000001110 ERR_TRIG_ODD_0=32'b00000000000000000000000000001101 ERR_TRIG_ODD_1=32'b00000000000000000000000000001111 ERR_ST0=2'b00 ERR_ST1=2'b01 ERR_ST2=2'b10 INC_VAL=4'b0010 Generated name = CJESDRX_CLOCK_GEN_RX_Z1 @W:CG133 : CLOCK_GEN_RX.v(236) | Object sys_st is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CLOCK_GEN_RX.v(237) | Object sys_cnt is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CLOCK_GEN_RX.v(238) | Object sysref_in_pulse_last is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on CJESDRX_CLOCK_GEN_RX_Z1 ....... @W:CL169 : CLOCK_GEN_RX.v(165) | Pruning unused register err_state[1:0]. Make sure that there are no unused intermediate registers. @W:CL113 : CLOCK_GEN_RX.v(347) | Feedback mux created for signal genblk3.F_PHASE_ST. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL113 : CLOCK_GEN_RX.v(347) | Feedback mux created for signal genblk3.FC_CNT[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL113 : CLOCK_GEN_RX.v(299) | Feedback mux created for signal genblk3.MF_PHASE_ST. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL177 : CLOCK_GEN_RX.v(299) | Sharing sequential element genblk3.MF_PHASE_ST. Add a syn_preserve attribute to the element to prevent sharing. @W:CL113 : CLOCK_GEN_RX.v(299) | Feedback mux created for signal genblk3.LMFC_CNT[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL177 : CLOCK_GEN_RX.v(299) | Sharing sequential element genblk3.LMFC_CNT. Add a syn_preserve attribute to the element to prevent sharing. @W:CL250 : CLOCK_GEN_RX.v(347) | All reachable assignments to genblk3.FC_CNT[3:0] assign 0, register removed by optimization @W:CL250 : CLOCK_GEN_RX.v(347) | All reachable assignments to genblk3.F_PHASE_ST assign 0, register removed by optimization @N:CG364 : CGS.v(18) | Synthesizing module CJESDRX_CGS in library work. SYNC_RESET=32'b00000000000000000000000000000000 CS_INIT=2'b00 CS_CHECK=2'b01 CS_DATA=2'b10 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 Generated name = CJESDRX_CGS_0s_0_1_2_16s_2s Running optimization stage 1 on CJESDRX_CGS_0s_0_1_2_16s_2s ....... @N:CG364 : ADJ_CTRL.v(19) | Synthesizing module CJESDRX_ADJ_CTRL in library work. SYNC_RESET=32'b00000000000000000000000000000000 SUBCLASSV=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 fc_period=32'b00000000000000000000000000000010 lmfc_period=32'b00000000000000000000000000010010 FRAME_MID=32'b00000000000000000000000000000001 LANE_MID=32'b00000000000000000000000000001001 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 L_MODE=3'b010 F_MODE=3'b010 Generated name = CJESDRX_ADJ_CTRL_Z2 Running optimization stage 1 on CJESDRX_ADJ_CTRL_Z2 ....... @W:CL169 : ADJ_CTRL.v(112) | Pruning unused register f_phase_st_reg[3:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ADJ_CTRL.v(112) | Pruning unused register lmfc_cnt_reg[11:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ADJ_CTRL.v(112) | Pruning unused register fc_cnt_reg[11:0]. Make sure that there are no unused intermediate registers. @N:CG364 : RX_CTRL.v(19) | Synthesizing module CJESDRX_RX_CTRL in library work. SYNC_RESET=32'b00000000000000000000000000000000 SUBCLASSV=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 lmfc_period=32'b00000000000000000000000000010010 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 Generated name = CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s Running optimization stage 1 on CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s ....... @N:CG364 : ILA_FSM.v(18) | Synthesizing module CJESDRX_ILA_FSM in library work. D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 SYNC_RESET=32'b00000000000000000000000000000000 SUBCLASSV=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 ERR_R=32'b00000000000000000000000001011100 RI_INIT=2'b00 RI_CHECK=2'b01 RI_DATA=2'b10 ILA_INIT=3'b000 ILA_BEGIN=3'b001 ILA_RDET=3'b010 ILA_AA=3'b011 ILA_DATA=3'b100 Generated name = CJESDRX_ILA_FSM_Z3 Running optimization stage 1 on CJESDRX_ILA_FSM_Z3 ....... @N:CG364 : EB_CTRL.v(19) | Synthesizing module CJESDRX_EB_CTRL in library work. SYNC_RESET=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 lmfc_period=32'b00000000000000000000000000010010 RAM_DEPTH=32'b00000000000000000000000000110110 EB_INIT=1'b0 EB_HOLD=1'b1 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 Generated name = CJESDRX_EB_CTRL_0s_2s_9s_18s_54s_0_1_16s_2s @N:CG179 : EB_CTRL.v(140) | Removing redundant assignment. @N:CG179 : EB_CTRL.v(200) | Removing redundant assignment. @N:CG179 : EB_CTRL.v(214) | Removing redundant assignment. @N:CG179 : EB_CTRL.v(291) | Removing redundant assignment. Running optimization stage 1 on CJESDRX_EB_CTRL_0s_2s_9s_18s_54s_0_1_16s_2s ....... @N:CG364 : EB_RAM_RTL.v(18) | Synthesizing module CJESDRX_RAM_EB in library work. SYNC_RESET=32'b00000000000000000000000000000000 RAM_DEPTH=32'b00000000000000000000000000110110 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 DATA_K_WIDTH=32'b00000000000000000000000000010010 Generated name = CJESDRX_RAM_EB_0s_54s_16s_2s_18s Running optimization stage 1 on CJESDRX_RAM_EB_0s_54s_16s_2s_18s ....... @N:CL134 : EB_RAM_RTL.v(69) | Found RAM EB_RAM, depth=54, width=18 @N:CG364 : ADJ_BUF.v(18) | Synthesizing module CJESDRX_ADJ_BUF in library work. SYNC_RESET=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 lmfc_period=32'b00000000000000000000000000010010 RAM_DEPTH=32'b00000000000000000000000000110110 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 adj_num_value=32'b00000000000000000000000000001001 DATA_K_WIDTH=32'b00000000000000000000000000010010 Generated name = CJESDRX_ADJ_BUF_0s_2s_9s_18s_54s_16s_2s_9s_18s Running optimization stage 1 on CJESDRX_ADJ_BUF_0s_2s_9s_18s_54s_16s_2s_9s_18s ....... @N:CG364 : LABDM.v(19) | Synthesizing module CJESDRX_LABDM in library work. SYNC_RESET=32'b00000000000000000000000000000000 SCR=32'b00000000000000000000000000000000 L=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 M=32'b00000000000000000000000000000001 CS=32'b00000000000000000000000000000000 N=32'b00000000000000000000000000001110 SUBCLASSV=32'b00000000000000000000000000000000 Na=32'b00000000000000000000000000010000 JESDV=32'b00000000000000000000000000000001 S=32'b00000000000000000000000000000010 HD=32'b00000000000000000000000000000000 CF=32'b00000000000000000000000000000000 LID=32'b00000000000000000000000000000000 FIELD_OCTET=32'b00000000000000000000000000000001 lmfc_period=32'b00000000000000000000000000010010 RAM_DEPTH=32'b00000000000000000000000000110110 RAM_SEL=32'b00000000000000000000000000000000 LCD_EN=32'b00000000000000000000000000000001 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 Generated name = CJESDRX_LABDM_Z4 @W:CG1283 : LABDM.v(232) | Ignoring localparam RES1 on the instance and using locally defined value @W:CG1283 : LABDM.v(232) | Ignoring localparam RES2 on the instance and using locally defined value @N:CG364 : LINK_COMP.v(18) | Synthesizing module CJESDRX_LINK_COMP in library work. SCR=32'b00000000000000000000000000000000 L=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 M=32'b00000000000000000000000000000001 CS=32'b00000000000000000000000000000000 N=32'b00000000000000000000000000001110 SUBCLASSV=32'b00000000000000000000000000000000 Na=32'b00000000000000000000000000010000 JESDV=32'b00000000000000000000000000000001 S=32'b00000000000000000000000000000010 HD=32'b00000000000000000000000000000000 CF=32'b00000000000000000000000000000000 LID=32'b00000000000000000000000000000000 RES1=32'b00000000000000000000000000000000 RES2=32'b00000000000000000000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 K28_0=8'b00011100 K28_3=8'b01111100 K28_4=8'b10011100 K28_5=8'b10111100 K28_7=8'b11111100 CD_INIT=3'b000 CD_R_DET=3'b001 CD_Q=3'b010 CD_COMP=3'b011 CD_ERR=3'b100 CD_WAIT=3'b101 CD_SYNC=3'b110 INIT_S=2'b00 WAIT_S=2'b01 COMP_S=2'b10 lmfc_period=32'b00000000000000000000000000010010 FIELD_OCTET=32'b00000000000000000000000000000001 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 EVEN_ODD=1'b0 Generated name = CJESDRX_LINK_COMP_Z5 @W:CG291 : LINK_COMP.v(400) | Ignoring parameter EVEN_ODD in sensitivity list. @N:CG179 : LINK_COMP.v(562) | Removing redundant assignment. @N:CG179 : LINK_COMP.v(563) | Removing redundant assignment. @N:CG179 : LINK_COMP.v(564) | Removing redundant assignment. @N:CG179 : LINK_COMP.v(565) | Removing redundant assignment. @N:CG179 : LINK_COMP.v(566) | Removing redundant assignment. @N:CG179 : LINK_COMP.v(571) | Removing redundant assignment. @N:CG179 : LINK_COMP.v(572) | Removing redundant assignment. @N:CG179 : LINK_COMP.v(573) | Removing redundant assignment. @N:CG179 : LINK_COMP.v(574) | Removing redundant assignment. @N:CG179 : LINK_COMP.v(575) | Removing redundant assignment. Running optimization stage 1 on CJESDRX_LINK_COMP_Z5 ....... @W:CL169 : LINK_COMP.v(518) | Pruning unused register genblk6.ADJCNT[3:0]. Make sure that there are no unused intermediate registers. @W:CL169 : LINK_COMP.v(518) | Pruning unused register genblk6.ADJDIR. Make sure that there are no unused intermediate registers. @W:CL169 : LINK_COMP.v(518) | Pruning unused register genblk6.PHADJ. Make sure that there are no unused intermediate registers. Running optimization stage 1 on CJESDRX_LABDM_Z4 ....... @N:CG364 : FL_AMC.v(18) | Synthesizing module CJESDRX_FL_AMC in library work. SYNC_RESET=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 FAC_EN=32'b00000000000000000000000000000001 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 Generated name = CJESDRX_FL_AMC_0s_2s_9s_1s_16s_2s @N:CG179 : FL_AMC.v(365) | Removing redundant assignment. @N:CG179 : FL_AMC.v(782) | Removing redundant assignment. Running optimization stage 1 on CJESDRX_FL_AMC_0s_2s_9s_1s_16s_2s ....... @N:CG364 : IFS_POS.v(18) | Synthesizing module CJESDRX_IFS_POS in library work. ILA_MFS=32'b00000000000000000000000000000100 SYNC_RESET=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 ila_period=32'b00000000000000000000000001001000 FS_INIT=2'b00 FS_CHECK=2'b01 FS_ILA=2'b10 FS_DATA=2'b11 CC_INIT_ST=1'b0 CC_WAIT_F=1'b1 Generated name = CJESDRX_IFS_POS_Z6 @N:CG179 : IFS_POS.v(4394) | Removing redundant assignment. Running optimization stage 1 on CJESDRX_IFS_POS_Z6 ....... @W:CL113 : IFS_POS.v(4333) | Feedback mux created for signal genblk6.FCOUNT_L_6[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL113 : IFS_POS.v(4333) | Feedback mux created for signal genblk6.FCOUNT_L_5[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL177 : IFS_POS.v(4333) | Sharing sequential element genblk6.FCOUNT_L_5. Add a syn_preserve attribute to the element to prevent sharing. @W:CL113 : IFS_POS.v(4333) | Feedback mux created for signal genblk6.FCOUNT_L_4[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL177 : IFS_POS.v(4333) | Sharing sequential element genblk6.FCOUNT_L_4. Add a syn_preserve attribute to the element to prevent sharing. @W:CL113 : IFS_POS.v(4333) | Feedback mux created for signal genblk6.FCOUNT_L_3[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL177 : IFS_POS.v(4333) | Sharing sequential element genblk6.FCOUNT_L_3. Add a syn_preserve attribute to the element to prevent sharing. @W:CL113 : IFS_POS.v(4333) | Feedback mux created for signal genblk6.FCOUNT_L_2[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL177 : IFS_POS.v(4333) | Sharing sequential element genblk6.FCOUNT_L_2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL113 : IFS_POS.v(4333) | Feedback mux created for signal genblk6.FCOUNT_L_1[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL177 : IFS_POS.v(4333) | Sharing sequential element genblk6.FCOUNT_L_1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL250 : IFS_POS.v(4333) | All reachable assignments to genblk6.FCOUNT_L_6[3:0] assign 0, register removed by optimization @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_L_1[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_L_1[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_L_2[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_L_2[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_L_3[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_L_3[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_L_4[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_L_4[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_L_5[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_L_5[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_L_6[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_L_6[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_U[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : IFS_POS.v(4293) | Pruning register bit 1 of genblk6.OCOUNT_U[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL169 : IFS_POS.v(4293) | Pruning unused register genblk6.OCOUNT_L_1[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : IFS_POS.v(4293) | Pruning unused register genblk6.OCOUNT_L_2[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : IFS_POS.v(4293) | Pruning unused register genblk6.OCOUNT_L_3[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : IFS_POS.v(4293) | Pruning unused register genblk6.OCOUNT_L_4[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : IFS_POS.v(4293) | Pruning unused register genblk6.OCOUNT_L_5[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : IFS_POS.v(4293) | Pruning unused register genblk6.OCOUNT_L_6[1:0]. Make sure that there are no unused intermediate registers. @N:CG364 : FADM_OR.v(18) | Synthesizing module CJESDRX_FADM_OR in library work. ILA_MFS=32'b00000000000000000000000000000100 SYNC_RESET=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 SCR=32'b00000000000000000000000000000000 FAC_EN=32'b00000000000000000000000000000001 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 Generated name = CJESDRX_FADM_OR_4s_0s_2s_9s_0s_1s_16s_2s @N:CG179 : FADM_OR.v(854) | Removing redundant assignment. Running optimization stage 1 on CJESDRX_FADM_OR_4s_0s_2s_9s_0s_1s_16s_2s ....... @W:CL169 : FADM_OR.v(179) | Pruning unused register genblk2.FS_reg[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : FADM_OR.v(179) | Pruning unused register genblk2.MFS_reg[1:0]. Make sure that there are no unused intermediate registers. @N:CG364 : JESD204BRX_LANE.v(19) | Synthesizing module CJESDRX_JESD204BRX_LANE in library work. SCR=32'b00000000000000000000000000000000 L=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 M=32'b00000000000000000000000000000001 CS=32'b00000000000000000000000000000000 N=32'b00000000000000000000000000001110 SUBCLASSV=32'b00000000000000000000000000000000 Na=32'b00000000000000000000000000010000 JESDV=32'b00000000000000000000000000000001 S=32'b00000000000000000000000000000010 HD=32'b00000000000000000000000000000000 CF=32'b00000000000000000000000000000000 LID=32'b00000000000000000000000000000000 FIELD_OCTET=32'b00000000000000000000000000000001 ILA_MFS=32'b00000000000000000000000000000100 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 E_WIDTH=32'b00000000000000000000000000010100 SERDES_MODE=32'b00000000000000000000000000000001 DECODER_EN=32'b00000000000000000000000000000001 SYNC_RESET=32'b00000000000000000000000000000000 DATA_DW_SIZE=32'b00000000000000000000000000010100 LANE_DATA=32'b00000000000000000000000000010100 lmfc_period=32'b00000000000000000000000000010010 FAC_EN=32'b00000000000000000000000000000001 RAM_SEL=32'b00000000000000000000000000000000 RAM_DEPTH=32'b00000000000000000000000000110110 LCD_EN=32'b00000000000000000000000000000001 Generated name = CJESDRX_JESD204BRX_LANE_Z7 @N:CG364 : DEC_ERR.v(21) | Synthesizing module CJESDRX_DEC_ERR in library work. Running optimization stage 1 on CJESDRX_DEC_ERR ....... @N:CG364 : DEC_DATA.v(21) | Synthesizing module CJESDRX_DEC_DATA in library work. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDRX_DEC_DATA_0s Running optimization stage 1 on CJESDRX_DEC_DATA_0s ....... @N:CG364 : SYNC_FSM.v(21) | Synthesizing module CJESDRX_SYNC_FSM in library work. SYNC_RESET=32'b00000000000000000000000000000000 SEARCH_1=3'b000 SEARCH_2=3'b001 SYNC_0=3'b010 SYNC_1=3'b011 SYNC_2=3'b100 TRIGGER=4'b0100 Generated name = CJESDRX_SYNC_FSM_0s_0_1_2_3_4_4 Running optimization stage 1 on CJESDRX_SYNC_FSM_0s_0_1_2_3_4_4 ....... @N:CG364 : DEC_RD_U.v(22) | Synthesizing module CJESDRX_DEC_RD_U in library work. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDRX_DEC_RD_U_0s Running optimization stage 1 on CJESDRX_DEC_RD_U_0s ....... @N:CG364 : DECODER_U.v(21) | Synthesizing module CJESDRX_DECODER_U in library work. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDRX_DECODER_U_0s Running optimization stage 1 on CJESDRX_DECODER_U_0s ....... @N:CG364 : WORD_ALIGNER.v(18) | Synthesizing module CJESDRX_WORD_ALIGNER in library work. D_WIDTH=32'b00000000000000000000000000010000 E_WIDTH=32'b00000000000000000000000000010100 K_WIDTH=32'b00000000000000000000000000000010 SYNC_RESET=32'b00000000000000000000000000000000 WA_INIT=2'b00 WA_SEL=2'b01 WA_WAIT_0=2'b10 WA_WAIT_1=2'b11 K28_5_p_10=10'b1100000101 K28_5_n_10=10'b0011111010 K28_5_p_20=20'b11000001010011111010 K28_5_n_20=20'b00111110101100000101 K28_5_p_40=40'b1100000101001111101011000001010011111010 K28_5_n_40=40'b0011111010110000010100111110101100000101 K28_5_p_sel=40'b0000000000000000000000000000001100000101 K28_5_n_sel=40'b0000000000000000000000000000000011111010 SEL_NONE=10'b0000000000 SEL_DET0=10'b0000000001 SEL_DET1=10'b0000000010 SEL_DET2=10'b0000000100 SEL_DET3=10'b0000001000 SEL_DET4=10'b0000010000 SEL_DET5=10'b0000100000 SEL_DET6=10'b0001000000 SEL_DET7=10'b0010000000 SEL_DET8=10'b0100000000 SEL_DET9=10'b1000000000 Generated name = CJESDRX_WORD_ALIGNER_Z8 @N:CG179 : WORD_ALIGNER.v(199) | Removing redundant assignment. @N:CG179 : WORD_ALIGNER.v(527) | Removing redundant assignment. @N:CG179 : WORD_ALIGNER.v(553) | Removing redundant assignment. @N:CG179 : WORD_ALIGNER.v(578) | Removing redundant assignment. @N:CG179 : WORD_ALIGNER.v(603) | Removing redundant assignment. @N:CG179 : WORD_ALIGNER.v(628) | Removing redundant assignment. @N:CG179 : WORD_ALIGNER.v(653) | Removing redundant assignment. @N:CG179 : WORD_ALIGNER.v(678) | Removing redundant assignment. @N:CG179 : WORD_ALIGNER.v(703) | Removing redundant assignment. @N:CG179 : WORD_ALIGNER.v(728) | Removing redundant assignment. @N:CG179 : WORD_ALIGNER.v(753) | Removing redundant assignment. @N:CG179 : WORD_ALIGNER.v(788) | Removing redundant assignment. Running optimization stage 1 on CJESDRX_WORD_ALIGNER_Z8 ....... @W:CL271 : WORD_ALIGNER.v(177) | Pruning unused bits 39 to 30 of buf_data[39:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL190 : WORD_ALIGNER.v(379) | Optimizing register bit genblk5.wa_sel_d[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : WORD_ALIGNER.v(379) | Optimizing register bit genblk5.wa_sel_d[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL279 : WORD_ALIGNER.v(379) | Pruning register bits 2 to 1 of genblk5.wa_sel_d[2:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @N:CG364 : DEC_WA.v(18) | Synthesizing module CJESDRX_DEC_WA in library work. SYNC_RESET=32'b00000000000000000000000000000000 SERDES_MODE=32'b00000000000000000000000000000001 D_WIDTH=32'b00000000000000000000000000010000 E_WIDTH=32'b00000000000000000000000000010100 K_WIDTH=32'b00000000000000000000000000000010 Generated name = CJESDRX_DEC_WA_0s_1s_16s_20s_2s @N:CG364 : DEC_RD_L.v(22) | Synthesizing module CJESDRX_DEC_RD_L in library work. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDRX_DEC_RD_L_0s Running optimization stage 1 on CJESDRX_DEC_RD_L_0s ....... @W:CL169 : DEC_RD_L.v(97) | Pruning unused register RD. Make sure that there are no unused intermediate registers. @N:CG364 : DECODER_L.v(21) | Synthesizing module CJESDRX_DECODER_L in library work. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDRX_DECODER_L_0s Running optimization stage 1 on CJESDRX_DECODER_L_0s ....... Running optimization stage 1 on CJESDRX_DEC_WA_0s_1s_16s_20s_2s ....... Running optimization stage 1 on CJESDRX_JESD204BRX_LANE_Z7 ....... @N:CG364 : RESET_SYNC.v(24) | Synthesizing module CJESDRX_RESET_SYNC in library work. SYNC_RESET=32'b00000000000000000000000000000000 L=32'b00000000000000000000000000000000 Generated name = CJESDRX_RESET_SYNC_0s_0s @W:CG360 : RESET_SYNC.v(49) | Removing wire laneclk_rxvalid_sync, as there is no assignment to it. Running optimization stage 1 on CJESDRX_RESET_SYNC_0s_0s ....... @W:CL177 : RESET_SYNC.v(223) | Sharing sequential element genblk1.lane_active. Add a syn_preserve attribute to the element to prevent sharing. @N:CG364 : CoreJESD204BRX.v(19) | Synthesizing module CoreJESD204BRX in library work. SCR=32'b00000000000000000000000000000000 L=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 M=32'b00000000000000000000000000000001 CS=32'b00000000000000000000000000000000 N=32'b00000000000000000000000000001110 SUBCLASSV=32'b00000000000000000000000000000000 Na=32'b00000000000000000000000000010000 JESDV=32'b00000000000000000000000000000001 S=32'b00000000000000000000000000000010 HD=32'b00000000000000000000000000000000 CF=32'b00000000000000000000000000000000 FIELD_OCTET=32'b00000000000000000000000000000001 ILA_MFS=32'b00000000000000000000000000000100 DECODER_EN=32'b00000000000000000000000000000001 D_WIDTH=32'b00000000000000000000000000010000 E_WIDTH=32'b00000000000000000000000000010100 K_WIDTH=32'b00000000000000000000000000000010 LCD_EN=32'b00000000000000000000000000000001 SERDES_MODE=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000010011 SYNC_RESET=32'b00000000000000000000000000000000 lmfc_period=32'b00000000000000000000000000010010 K_WIDTH_IN=32'b00000000000000000000000000000010 EPCS_WIDTH=32'b00000000000000000000000000010100 DATA_K_WIDTH=32'b00000000000000000000000000010000 LANE_DATA=32'b00000000000000000000000000010100 DATA_DW_SIZE=32'b00000000000000000000000000010100 FAC_EN=32'b00000000000000000000000000000001 RAM_SEL=32'b00000000000000000000000000000000 RAM_DEPTH=32'b00000000000000000000000000110110 FORCE_SYNC_MAX=32'b00000000000000000000000010011010 EPCS_CNT_WIDTH=32'b00000000000000000000000000001000 Generated name = CoreJESD204BRX_Z9 @W:CG291 : CoreJESD204BRX.v(724) | Ignoring parameter DECODER_EN in sensitivity list. @N:CG364 : DATA_SYNC_BUF.v(19) | Synthesizing module CJESDRX_DATA_SYNC_BUF in library work. BD_WIDTH_IN=32'b00000000000000000000000000010100 BK_WIDTH_IN=32'b00000000000000000000000000000010 BD_WIDTH_OUT=32'b00000000000000000000000000010100 BK_WIDTH_OUT=32'b00000000000000000000000000000010 SYNC_RESET=32'b00000000000000000000000000000000 DECODER_EN=32'b00000000000000000000000000000001 Generated name = CJESDRX_DATA_SYNC_BUF_20s_2s_20s_2s_0s_1s @N:CG179 : DATA_SYNC_BUF.v(213) | Removing redundant assignment. @N:CG179 : DATA_SYNC_BUF.v(235) | Removing redundant assignment. Running optimization stage 1 on CJESDRX_DATA_SYNC_BUF_20s_2s_20s_2s_0s_1s ....... @W:CL169 : DATA_SYNC_BUF.v(356) | Pruning unused register genblk6.dw_cnt[2:0]. Make sure that there are no unused intermediate registers. @W:CL169 : DATA_SYNC_BUF.v(207) | Pruning unused register d_cnt[1:0]. Make sure that there are no unused intermediate registers. @A:CL282 : DATA_SYNC_BUF.v(220) | Feedback mux created for signal valid_buf[3][1:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : DATA_SYNC_BUF.v(220) | Feedback mux created for signal valid_buf[2][1:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : DATA_SYNC_BUF.v(220) | Feedback mux created for signal valid_buf[1][1:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : DATA_SYNC_BUF.v(220) | Feedback mux created for signal valid_buf[0][1:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : DATA_SYNC_BUF.v(220) | Feedback mux created for signal k_buf[3][1:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : DATA_SYNC_BUF.v(220) | Feedback mux created for signal k_buf[2][1:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : DATA_SYNC_BUF.v(220) | Feedback mux created for signal k_buf[1][1:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : DATA_SYNC_BUF.v(220) | Feedback mux created for signal k_buf[0][1:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : DATA_SYNC_BUF.v(220) | Feedback mux created for signal data_buf[3][19:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : DATA_SYNC_BUF.v(220) | Feedback mux created for signal data_buf[2][19:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : DATA_SYNC_BUF.v(220) | Feedback mux created for signal data_buf[1][19:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : DATA_SYNC_BUF.v(220) | Feedback mux created for signal data_buf[0][19:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @W:CG360 : CoreJESD204BRX.v(344) | Removing wire DATA_OUT_1_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(345) | Removing wire DATA_OUT_2_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(346) | Removing wire DATA_OUT_3_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(347) | Removing wire DATA_OUT_4_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(348) | Removing wire DATA_OUT_5_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(349) | Removing wire DATA_OUT_6_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(350) | Removing wire DATA_OUT_7_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(352) | Removing wire SOF_1_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(353) | Removing wire SOF_2_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(354) | Removing wire SOF_3_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(355) | Removing wire SOF_4_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(356) | Removing wire SOF_5_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(357) | Removing wire SOF_6_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(358) | Removing wire SOF_7_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(360) | Removing wire SOMF_1_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(361) | Removing wire SOMF_2_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(362) | Removing wire SOMF_3_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(363) | Removing wire SOMF_4_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(364) | Removing wire SOMF_5_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(365) | Removing wire SOMF_6_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(366) | Removing wire SOMF_7_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(368) | Removing wire RX_STATE_1_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(369) | Removing wire RX_STATE_2_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(370) | Removing wire RX_STATE_3_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(371) | Removing wire RX_STATE_4_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(372) | Removing wire RX_STATE_5_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(373) | Removing wire RX_STATE_6_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(374) | Removing wire RX_STATE_7_dc, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(380) | Removing wire epcs_syncd_rst_n_1, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(381) | Removing wire epcs_syncd_rst_n_2, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(382) | Removing wire epcs_syncd_rst_n_3, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(383) | Removing wire epcs_syncd_rst_n_4, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(384) | Removing wire epcs_syncd_rst_n_5, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(385) | Removing wire epcs_syncd_rst_n_6, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(386) | Removing wire epcs_syncd_rst_n_7, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(433) | Removing wire data_in_1, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(434) | Removing wire data_in_2, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(435) | Removing wire data_in_3, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(436) | Removing wire data_in_4, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(437) | Removing wire data_in_5, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(438) | Removing wire data_in_6, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(439) | Removing wire data_in_7, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(440) | Removing wire valid_in_0, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(441) | Removing wire valid_in_1, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(442) | Removing wire valid_in_2, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(443) | Removing wire valid_in_3, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(444) | Removing wire valid_in_4, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(445) | Removing wire valid_in_5, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(446) | Removing wire valid_in_6, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(447) | Removing wire valid_in_7, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(448) | Removing wire k_in_0, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(449) | Removing wire k_in_1, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(450) | Removing wire k_in_2, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(451) | Removing wire k_in_3, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(452) | Removing wire k_in_4, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(453) | Removing wire k_in_5, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(454) | Removing wire k_in_6, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(455) | Removing wire k_in_7, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(457) | Removing wire aresetn, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(458) | Removing wire sresetn, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(464) | Removing wire RX_VALID, as there is no assignment to it. Running optimization stage 1 on CoreJESD204BRX_Z9 ....... @W:CL168 : CoreJESD204BRX.v(524) | Removing instance DC_RXD_7 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(523) | Removing instance DC_RXD_6 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(522) | Removing instance DC_RXD_5 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(521) | Removing instance DC_RXD_4 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(520) | Removing instance DC_RXD_3 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(519) | Removing instance DC_RXD_2 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(518) | Removing instance DC_RXD_1 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(517) | Removing instance DC_RXD_0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(515) | Removing instance DC_RK_7 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(514) | Removing instance DC_RK_6 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(513) | Removing instance DC_RK_5 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(512) | Removing instance DC_RK_4 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(511) | Removing instance DC_RK_3 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(510) | Removing instance DC_RK_2 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(509) | Removing instance DC_RK_1 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(508) | Removing instance DC_RK_0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(506) | Removing instance DC_RCV_7 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(505) | Removing instance DC_RCV_6 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(504) | Removing instance DC_RCV_5 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(503) | Removing instance DC_RCV_4 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(502) | Removing instance DC_RCV_3 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(501) | Removing instance DC_RCV_2 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(500) | Removing instance DC_RCV_1 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(499) | Removing instance DC_RCV_0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(497) | Removing instance DC_RDE_7 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(496) | Removing instance DC_RDE_6 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(495) | Removing instance DC_RDE_5 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(494) | Removing instance DC_RDE_4 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(493) | Removing instance DC_RDE_3 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(492) | Removing instance DC_RDE_2 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(491) | Removing instance DC_RDE_1 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(490) | Removing instance DC_RDE_0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(488) | Removing instance DC_ERD_7 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(487) | Removing instance DC_ERD_6 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(486) | Removing instance DC_ERD_5 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(485) | Removing instance DC_ERD_4 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(484) | Removing instance DC_ERD_3 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(483) | Removing instance DC_ERD_2 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BRX.v(482) | Removing instance DC_ERD_1 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @N:CG364 : DATA_CAPTURE.v(19) | Synthesizing module CJESDTX_DATA_CAPTURE in library work. DATA_WIDTH=32'b00000000000000000000000000010000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDTX_DATA_CAPTURE_16s_0s Running optimization stage 1 on CJESDTX_DATA_CAPTURE_16s_0s ....... @N:CG364 : DATA_CAPTURE.v(19) | Synthesizing module CJESDTX_DATA_CAPTURE in library work. DATA_WIDTH=32'b00000000000000000000000000010100 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDTX_DATA_CAPTURE_20s_0s Running optimization stage 1 on CJESDTX_DATA_CAPTURE_20s_0s ....... @N:CG364 : DATA_CAPTURE.v(19) | Synthesizing module CJESDTX_DATA_CAPTURE in library work. DATA_WIDTH=32'b00000000000000000000000000000010 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDTX_DATA_CAPTURE_2s_0s Running optimization stage 1 on CJESDTX_DATA_CAPTURE_2s_0s ....... @N:CG364 : SYNC_DEC.v(19) | Synthesizing module CJESDTX_SYNC_DEC in library work. F=32'b00000000000000000000000000000010 SUBCLASSV=32'b00000000000000000000000000000000 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 SYNC_RESET=32'b00000000000000000000000000000000 MIN_SYNC_REQ=32'b00000000000000000000000000000110 Generated name = CJESDTX_SYNC_DEC_2s_0s_16s_2s_0s_6s @N:CG179 : SYNC_DEC.v(86) | Removing redundant assignment. @W:CG133 : SYNC_DEC.v(61) | Object sync_req_cnt is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on CJESDTX_SYNC_DEC_2s_0s_16s_2s_0s_6s ....... @N:CG364 : CLOCK_GEN_TX.v(19) | Synthesizing module CJESDTX_CLOCK_GEN_TX in library work. F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 SUBCLASSV=32'b00000000000000000000000000000000 D_WIDTH=32'b00000000000000000000000000010000 INC_VAL=32'b00000000000000000000000000000010 SYNC_RESET=32'b00000000000000000000000000000000 R=32'b00000000000000000000000000000100 fc_period=32'b00000000000000000000000000000010 lmfc_period=32'b00000000000000000000000000010010 sysref_high=32'b00000000000000000000000000000100 Generated name = CJESDTX_CLOCK_GEN_TX_2s_9s_0s_16s_2s_0s_4s_2s_18s_4s Running optimization stage 1 on CJESDTX_CLOCK_GEN_TX_2s_9s_0s_16s_2s_0s_4s_2s_18s_4s ....... @W:CL169 : CLOCK_GEN_TX.v(206) | Pruning unused register genblk2.FC_PHASE_ST. Make sure that there are no unused intermediate registers. @W:CL169 : CLOCK_GEN_TX.v(206) | Pruning unused register genblk2.fc_cnt[3:0]. Make sure that there are no unused intermediate registers. @W:CL169 : CLOCK_GEN_TX.v(158) | Pruning unused register genblk2.lmfc_cnt[3:0]. Make sure that there are no unused intermediate registers. @W:CL113 : CLOCK_GEN_TX.v(158) | Feedback mux created for signal genblk2.LMFC_PHASE_ST. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL250 : CLOCK_GEN_TX.v(158) | All reachable assignments to genblk2.LMFC_PHASE_ST assign 0, register removed by optimization @N:CG364 : DATA_SYNC_BUF_TX.v(19) | Synthesizing module CJESDTX_SYNC_BUF_TX in library work. SERDES_MODE=32'b00000000000000000000000000000001 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 K_WIDTH_OUT=32'b00000000000000000000000000000010 LANE_DATA=32'b00000000000000000000000000010100 SYNC_RESET=32'b00000000000000000000000000000000 DATA_IN_SIZE=32'b00000000000000000000000000010100 FSM_STATES=32'b00000000000000000000000000000000 LAST_ADDR=3'b001 Generated name = CJESDTX_SYNC_BUF_TX_1s_16s_2s_2s_20s_0s_20s_0s_1 @N:CG179 : DATA_SYNC_BUF_TX.v(305) | Removing redundant assignment. Running optimization stage 1 on CJESDTX_SYNC_BUF_TX_1s_16s_2s_2s_20s_0s_20s_0s_1 ....... @W:CL207 : DATA_SYNC_BUF_TX.v(231) | All reachable assignments to genblk4.st_fsm[0] assign 1, register removed by optimization. @N:CG364 : TX_ACG.v(19) | Synthesizing module CJESDTX_TX_ACG in library work. SYNC_RESET=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 SCR=32'b00000000000000000000000000000000 D_WIDTH=32'b00000000000000000000000000010000 DET_LENGTH=32'b00000000000000000000000000000010 Generated name = CJESDTX_TX_ACG_0s_2s_9s_0s_16s_2s Running optimization stage 1 on CJESDTX_TX_ACG_0s_2s_9s_0s_16s_2s ....... @W:CL169 : TX_ACG.v(2173) | Pruning unused register genblk6.FCount_L_6[3:0]. Make sure that there are no unused intermediate registers. @W:CL169 : TX_ACG.v(2173) | Pruning unused register genblk6.FCount_L_5[3:0]. Make sure that there are no unused intermediate registers. @W:CL169 : TX_ACG.v(2173) | Pruning unused register genblk6.FCount_L_4[3:0]. Make sure that there are no unused intermediate registers. @W:CL169 : TX_ACG.v(2173) | Pruning unused register genblk6.FCount_L_3[3:0]. Make sure that there are no unused intermediate registers. @W:CL169 : TX_ACG.v(2173) | Pruning unused register genblk6.FCount_L_2[3:0]. Make sure that there are no unused intermediate registers. @W:CL169 : TX_ACG.v(2173) | Pruning unused register genblk6.FCount_L_1[3:0]. Make sure that there are no unused intermediate registers. @W:CL169 : TX_ACG.v(2137) | Pruning unused register genblk6.OCount_L_1[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : TX_ACG.v(2137) | Pruning unused register genblk6.OCount_L_2[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : TX_ACG.v(2137) | Pruning unused register genblk6.OCount_L_3[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : TX_ACG.v(2137) | Pruning unused register genblk6.OCount_L_4[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : TX_ACG.v(2137) | Pruning unused register genblk6.OCount_L_5[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : TX_ACG.v(2137) | Pruning unused register genblk6.OCount_L_6[1:0]. Make sure that there are no unused intermediate registers. @W:CL190 : TX_ACG.v(2137) | Optimizing register bit genblk6.OCount_U[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : TX_ACG.v(2137) | Pruning register bit 1 of genblk6.OCount_U[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CG1283 : JESD204BTX_LANE.v(500) | Ignoring localparam DID on the instance and using locally defined value @W:CG1283 : JESD204BTX_LANE.v(500) | Ignoring localparam BID on the instance and using locally defined value @W:CG1283 : JESD204BTX_LANE.v(500) | Ignoring localparam RES1 on the instance and using locally defined value @N:CG364 : TX_ILA.v(19) | Synthesizing module CJESDTX_TX_ILA in library work. SCR=32'b00000000000000000000000000000000 L=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 M=32'b00000000000000000000000000000001 CS=32'b00000000000000000000000000000000 N=32'b00000000000000000000000000001110 SUBCLASSV=32'b00000000000000000000000000000000 Na=32'b00000000000000000000000000010000 JESDV=32'b00000000000000000000000000000001 S=32'b00000000000000000000000000000010 HD=32'b00000000000000000000000000000000 CF=32'b00000000000000000000000000000000 FIELD_OCTET=32'b00000000000000000000000000000001 LID=32'b00000000000000000000000000000000 DID=32'b00000000000000000000000000000000 BID=32'b00000000000000000000000000000000 RES1=32'b00000000000000000000000000000000 RES2=32'b00000000000000000000000000000000 D_WIDTH=32'b00000000000000000000000000010000 E_WIDTH=32'b00000000000000000000000000010100 K_WIDTH=32'b00000000000000000000000000000010 ILA_4MF_END=32'b00000000000000000000000001000111 ILA_MFS=32'b00000000000000000000000000000100 lmfc_period=32'b00000000000000000000000000010010 ila_period=32'b00000000000000000000000001001000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDTX_TX_ILA_Z10 Running optimization stage 1 on CJESDTX_TX_ILA_Z10 ....... @W:CL169 : TX_ILA.v(368) | Pruning unused register genblk4.alignment_sent. Make sure that there are no unused intermediate registers. @N:CG364 : TX_CTRL.v(19) | Synthesizing module CJESDTX_TX_CTRL in library work. F=32'b00000000000000000000000000000010 SCR=32'b00000000000000000000000000000000 SYNC_ST=2'b00 INIT_LANE_ST=2'b01 DATA_ENC_ST=2'b10 SYNC_RESET=32'b00000000000000000000000000000000 D_WIDTH=32'b00000000000000000000000000010000 E_WIDTH=32'b00000000000000000000000000010100 K_WIDTH=32'b00000000000000000000000000000010 ILA_DATA_SEL=32'b00000000000000000000000000000000 Generated name = CJESDTX_TX_CTRL_2s_0s_0_1_2_0s_16s_20s_2s_0 @N:CG179 : TX_CTRL.v(166) | Removing redundant assignment. @N:CG179 : TX_CTRL.v(216) | Removing redundant assignment. @N:CG179 : TX_CTRL.v(217) | Removing redundant assignment. Running optimization stage 1 on CJESDTX_TX_CTRL_2s_0s_0_1_2_0s_16s_20s_2s_0 ....... @N:CG364 : JESD204BTX_LANE.v(19) | Synthesizing module CJESDTX_JESD204BTX_LANE in library work. LID=32'b00000000000000000000000000000000 SCR=32'b00000000000000000000000000000000 L=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 M=32'b00000000000000000000000000000001 CS=32'b00000000000000000000000000000000 N=32'b00000000000000000000000000001110 SUBCLASSV=32'b00000000000000000000000000000000 Na=32'b00000000000000000000000000010000 JESDV=32'b00000000000000000000000000000001 S=32'b00000000000000000000000000000010 HD=32'b00000000000000000000000000000000 CF=32'b00000000000000000000000000000000 FIELD_OCTET=32'b00000000000000000000000000000001 ENCODER_EN=32'b00000000000000000000000000000001 D_WIDTH=32'b00000000000000000000000000010000 E_WIDTH=32'b00000000000000000000000000010100 K_WIDTH=32'b00000000000000000000000000000010 DATA_OUT_SIZE=32'b00000000000000000000000000010100 SYNC_RESET=32'b00000000000000000000000000000000 ILA_MFS=32'b00000000000000000000000000000100 SERDES_MODE=32'b00000000000000000000000000000001 ILA_MFE=32'b00000000000000000000000001001000 ILA_DATA_SEL=32'b00000000000000000000000000000000 Generated name = CJESDTX_JESD204BTX_LANE_Z11 @W:CG1283 : ENCODER_64B80B.v(60) | Type of parameter K_WIDTH on the instance BUF_DATA_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : BUF_DATA.v(1) | Synthesizing module CJESDTX_BUF_DATA in library work. SYNC_RESET=32'b00000000000000000000000000000000 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 Generated name = CJESDTX_BUF_DATA_0s_16s_2s Running optimization stage 1 on CJESDTX_BUF_DATA_0s_16s_2s ....... @N:CG364 : ENC_FLIP.v(26) | Synthesizing module CJESDTX_ENC_FLIP in library work. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDTX_ENC_FLIP_0s Running optimization stage 1 on CJESDTX_ENC_FLIP_0s ....... @N:CG364 : ENC_K.v(53) | Synthesizing module CJESDTX_ENC_K in library work. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDTX_ENC_K_0s Running optimization stage 1 on CJESDTX_ENC_K_0s ....... @N:CG364 : MUX4X1.v(22) | Synthesizing module CJESDTX_MUX4X1 in library work. Running optimization stage 1 on CJESDTX_MUX4X1 ....... @N:CG364 : MUX32X1.v(22) | Synthesizing module CJESDTX_MUX32X1 in library work. Running optimization stage 1 on CJESDTX_MUX32X1 ....... @N:CG364 : MUX32X6.v(22) | Synthesizing module CJESDTX_MUX32X6 in library work. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDTX_MUX32X6_0s Running optimization stage 1 on CJESDTX_MUX32X6_0s ....... @W:CL177 : MUX32X6.v(85) | Sharing sequential element SEL_R4. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : MUX32X6.v(85) | Sharing sequential element SEL_R3. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : MUX32X6.v(85) | Sharing sequential element SEL_R2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : MUX32X6.v(85) | Sharing sequential element SEL_R0. Add a syn_preserve attribute to the element to prevent sharing. @W:CL169 : MUX32X6.v(85) | Pruning unused register SEL_R5[1:0]. Make sure that there are no unused intermediate registers. @N:CG364 : ENC_D.v(26) | Synthesizing module CJESDTX_ENC_D in library work. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDTX_ENC_D_0s Running optimization stage 1 on CJESDTX_ENC_D_0s ....... @N:CG364 : ENCODER_U.v(22) | Synthesizing module CJESDTX_ENCODER_U in library work. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDTX_ENCODER_U_0s @W:CG360 : ENCODER_U.v(58) | Removing wire RST_N0, as there is no assignment to it. Running optimization stage 1 on CJESDTX_ENCODER_U_0s ....... @N:CG364 : ENCODER_64B80B.v(19) | Synthesizing module CJESDTX_ENCODER_64B80B in library work. SYNC_RESET=32'b00000000000000000000000000000000 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 E_WIDTH=32'b00000000000000000000000000010100 Generated name = CJESDTX_ENCODER_64B80B_0s_16s_2s_20s @N:CG364 : ENCODER_L.v(22) | Synthesizing module CJESDTX_ENCODER_L in library work. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDTX_ENCODER_L_0s Running optimization stage 1 on CJESDTX_ENCODER_L_0s ....... @N:CG364 : ENCODER_N.v(22) | Synthesizing module CJESDTX_ENCODER_N in library work. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDTX_ENCODER_N_0s Running optimization stage 1 on CJESDTX_ENCODER_N_0s ....... @W:CL169 : ENCODER_N.v(69) | Pruning unused register INV_6B. Make sure that there are no unused intermediate registers. @W:CL169 : ENCODER_N.v(69) | Pruning unused register INV_4B. Make sure that there are no unused intermediate registers. Running optimization stage 1 on CJESDTX_ENCODER_64B80B_0s_16s_2s_20s ....... Running optimization stage 1 on CJESDTX_JESD204BTX_LANE_Z11 ....... @N:CG364 : RESET_SYNC.v(24) | Synthesizing module CJESDTX_RESET_SYNC in library work. SYNC_RESET=32'b00000000000000000000000000000000 L=32'b00000000000000000000000000000000 Generated name = CJESDTX_RESET_SYNC_0s_0s Running optimization stage 1 on CJESDTX_RESET_SYNC_0s_0s ....... @W:CL177 : RESET_SYNC.v(222) | Sharing sequential element genblk1.lane_active. Add a syn_preserve attribute to the element to prevent sharing. @N:CG364 : CoreJESD204BTX.v(19) | Synthesizing module CoreJESD204BTX in library work. SCR=32'b00000000000000000000000000000000 L=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 M=32'b00000000000000000000000000000001 CS=32'b00000000000000000000000000000000 N=32'b00000000000000000000000000001110 SUBCLASSV=32'b00000000000000000000000000000000 Na=32'b00000000000000000000000000010000 JESDV=32'b00000000000000000000000000000001 S=32'b00000000000000000000000000000010 HD=32'b00000000000000000000000000000000 CF=32'b00000000000000000000000000000000 FIELD_OCTET=32'b00000000000000000000000000000001 ENCODER_EN=32'b00000000000000000000000000000001 SERDES_MODE=32'b00000000000000000000000000000001 D_WIDTH=32'b00000000000000000000000000010000 E_WIDTH=32'b00000000000000000000000000010100 K_WIDTH=32'b00000000000000000000000000000010 K_WIDTH_OUT=32'b00000000000000000000000000000010 FAMILY=32'b00000000000000000000000000010011 SYNC_RESET=32'b00000000000000000000000000000000 ILA_MFS=32'b00000000000000000000000000000100 lmfc_period=32'b00000000000000000000000000010010 EPCS_WIDTH=32'b00000000000000000000000000010100 DATA_K_WIDTH=32'b00000000000000000000000000010000 LANE_DATA=32'b00000000000000000000000000010100 DATA_OUT_SIZE=32'b00000000000000000000000000010100 Generated name = CoreJESD204BTX_Z12 @W:CG360 : CoreJESD204BTX.v(199) | Removing wire epcs_syncd_rst_n_1, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(200) | Removing wire epcs_syncd_rst_n_2, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(201) | Removing wire epcs_syncd_rst_n_3, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(202) | Removing wire epcs_syncd_rst_n_4, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(203) | Removing wire epcs_syncd_rst_n_5, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(204) | Removing wire epcs_syncd_rst_n_6, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(205) | Removing wire epcs_syncd_rst_n_7, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(243) | Removing wire LANE_K_OUT_1, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(244) | Removing wire LANE_K_OUT_2, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(245) | Removing wire LANE_K_OUT_3, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(246) | Removing wire LANE_K_OUT_4, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(247) | Removing wire LANE_K_OUT_5, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(248) | Removing wire LANE_K_OUT_6, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(249) | Removing wire LANE_K_OUT_7, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(251) | Removing wire LANE_DATA_OUT_1, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(252) | Removing wire LANE_DATA_OUT_2, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(253) | Removing wire LANE_DATA_OUT_3, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(254) | Removing wire LANE_DATA_OUT_4, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(255) | Removing wire LANE_DATA_OUT_5, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(256) | Removing wire LANE_DATA_OUT_6, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(257) | Removing wire LANE_DATA_OUT_7, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(259) | Removing wire BUF_DATA_OUT_1, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(260) | Removing wire BUF_DATA_OUT_2, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(261) | Removing wire BUF_DATA_OUT_3, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(262) | Removing wire BUF_DATA_OUT_4, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(263) | Removing wire BUF_DATA_OUT_5, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(264) | Removing wire BUF_DATA_OUT_6, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(265) | Removing wire BUF_DATA_OUT_7, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(281) | Removing wire TX_K_1_int, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(282) | Removing wire TX_K_2_int, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(283) | Removing wire TX_K_3_int, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(284) | Removing wire TX_K_4_int, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(285) | Removing wire TX_K_5_int, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(286) | Removing wire TX_K_6_int, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(287) | Removing wire TX_K_7_int, as there is no assignment to it. Running optimization stage 1 on CoreJESD204BTX_Z12 ....... @W:CL168 : CoreJESD204BTX.v(479) | Removing instance DC_DI_7 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BTX.v(478) | Removing instance DC_DI_6 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BTX.v(477) | Removing instance DC_DI_5 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BTX.v(476) | Removing instance DC_DI_4 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BTX.v(475) | Removing instance DC_DI_3 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BTX.v(474) | Removing instance DC_DI_2 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : CoreJESD204BTX.v(473) | Removing instance DC_DI_1 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @N:CG364 : PRBS_GENERATOR.v(19) | Synthesizing module PRBS_GENERATOR in library work. Running optimization stage 1 on PRBS_GENERATOR ....... @W:CL169 : PRBS_GENERATOR.v(56) | Pruning unused register data[31:0]. Make sure that there are no unused intermediate registers. @W:CL169 : PRBS_GENERATOR.v(45) | Pruning unused register PRBS_SEL_d[1:0]. Make sure that there are no unused intermediate registers. @W:CL260 : PRBS_GENERATOR.v(56) | Pruning register bit 31 of PRBS[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CG364 : PRBS_WAV_SEL.v(20) | Synthesizing module PRBS_WAV_SEL in library work. Running optimization stage 1 on PRBS_WAV_SEL ....... @N:CG364 : wav_gen_16bit.v(4) | Synthesizing module waveform_gen in library work. @N:CG179 : wav_gen_16bit.v(156) | Removing redundant assignment. Running optimization stage 1 on waveform_gen ....... @N:CG364 : DATA_GENERATOR.v(9) | Synthesizing module DATA_GENERATOR in library work. Running optimization stage 1 on DATA_GENERATOR ....... @N:CG364 : DATA_HANDLE_FSM.v(22) | Synthesizing module DATAHANDLE_FSM in library work. @W:CG296 : DATA_HANDLE_FSM.v(152) | Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list. @W:CG290 : DATA_HANDLE_FSM.v(154) | Referenced variable RDATA_EN is not in sensitivity list. @W:CG290 : DATA_HANDLE_FSM.v(155) | Referenced variable DATA_OUT is not in sensitivity list. @W:CG290 : DATA_HANDLE_FSM.v(157) | Referenced variable DATA_OUT1 is not in sensitivity list. @W:CG133 : DATA_HANDLE_FSM.v(110) | Object SEL is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on DATAHANDLE_FSM ....... @W:CL208 : DATA_HANDLE_FSM.v(190) | All reachable assignments to bit 4 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization. @W:CL208 : DATA_HANDLE_FSM.v(190) | All reachable assignments to bit 5 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization. @W:CL208 : DATA_HANDLE_FSM.v(190) | All reachable assignments to bit 6 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization. @W:CL208 : DATA_HANDLE_FSM.v(190) | All reachable assignments to bit 7 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization. @W:CL208 : DATA_HANDLE_FSM.v(190) | All reachable assignments to bit 8 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization. @W:CL208 : DATA_HANDLE_FSM.v(190) | All reachable assignments to bit 9 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization. @W:CL208 : DATA_HANDLE_FSM.v(190) | All reachable assignments to bit 10 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization. @W:CL208 : DATA_HANDLE_FSM.v(190) | All reachable assignments to bit 17 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization. @W:CL208 : DATA_HANDLE_FSM.v(190) | All reachable assignments to bit 18 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization. @W:CL208 : DATA_HANDLE_FSM.v(190) | All reachable assignments to bit 19 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization. @W:CL208 : DATA_HANDLE_FSM.v(190) | All reachable assignments to bit 20 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization. @W:CL190 : DATA_HANDLE_FSM.v(199) | Optimizing register bit PREADY to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : DATA_HANDLE_FSM.v(199) | Pruning unused register PREADY. Make sure that there are no unused intermediate registers. @N:CG364 : ERR_GEN.v(19) | Synthesizing module ERR_GEN in library work. Running optimization stage 1 on ERR_GEN ....... @N:CG364 : LED_BLOCK_2.v(19) | Synthesizing module LED_DEBUG_BLK in library work. @W:CG133 : LED_BLOCK_2.v(76) | Object data_0_led is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on LED_DEBUG_BLK ....... @N:CG364 : PRBS_CHECKER.v(19) | Synthesizing module PRBS_CHECKER in library work. Running optimization stage 1 on PRBS_CHECKER ....... @W:CL169 : PRBS_CHECKER.v(57) | Pruning unused register PRBS_DATA_p2[15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : PRBS_CHECKER.v(57) | Pruning unused register PRBS_DATA_p3[15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : PRBS_CHECKER.v(57) | Pruning unused register d[31:0]. Make sure that there are no unused intermediate registers. @W:CL169 : PRBS_CHECKER.v(57) | Pruning unused register ec[7:0]. Make sure that there are no unused intermediate registers. @W:CL265 : PRBS_CHECKER.v(57) | Removing unused bit 15 of PRBS_DATA_p1[15:0]. Either assign all bits or reduce the width of the signal. @W:CL271 : PRBS_CHECKER.v(57) | Pruning unused bits 31 to 16 of prbs_15[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL271 : PRBS_CHECKER.v(57) | Pruning unused bits 31 to 16 of prbs_23[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL271 : PRBS_CHECKER.v(57) | Pruning unused bits 31 to 16 of prbs_31[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL271 : PRBS_CHECKER.v(57) | Pruning unused bits 31 to 16 of prbs_7[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : PRBS_CHECKER.v(57) | Pruning register bits 15 to 10 of prbs_7[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @N:CG364 : delay_line.v(19) | Synthesizing module delay_line in library work. @N:CG364 : delay_line.v(48) | Synthesizing module bufd_bus in library work. BUS_WIDTH=32'b00000000000000000000000000010100 Generated name = bufd_bus_20s @N:CG364 : smartfusion2.v(234) | Synthesizing module BUFD in library work. Running optimization stage 1 on BUFD ....... Running optimization stage 1 on bufd_bus_20s ....... @W:CG133 : delay_line.v(32) | Object j is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on delay_line ....... @N:CG364 : epcs_rx_intf.v(18) | Synthesizing module epcs_rx_intf in library work. Running optimization stage 1 on epcs_rx_intf ....... @N:CG364 : epcs_tx_intf.v(19) | Synthesizing module epcs_tx_intf in library work. Running optimization stage 1 on epcs_tx_intf ....... @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC in library work. Running optimization stage 1 on VCC ....... @N:CG364 : smartfusion2.v(372) | Synthesizing module GND in library work. Running optimization stage 1 on GND ....... @N:CG364 : SERDES_EPCS_SERDES_IF2_0_SERDES_IF2_syn.v(5) | Synthesizing module SERDESIF_075 in library work. Running optimization stage 1 on SERDESIF_075 ....... @N:CG364 : SERDES_EPCS_SERDES_IF2_0_SERDES_IF2.v(5) | Synthesizing module SERDES_EPCS_SERDES_IF2_0_SERDES_IF2 in library work. Running optimization stage 1 on SERDES_EPCS_SERDES_IF2_0_SERDES_IF2 ....... @N:CG364 : SERDES_EPCS.v(9) | Synthesizing module SERDES_EPCS in library work. Running optimization stage 1 on SERDES_EPCS ....... @N:CG364 : smartfusion2.v(729) | Synthesizing module CCC in library work. Running optimization stage 1 on CCC ....... @N:CG364 : SF2_JESD204B_DEMO_sb_CCC_0_FCCC.v(5) | Synthesizing module SF2_JESD204B_DEMO_sb_CCC_0_FCCC in library work. Running optimization stage 1 on SF2_JESD204B_DEMO_sb_CCC_0_FCCC ....... @N:CG775 : coreapb3.v(31) | Component CoreAPB3 not found in library "work" or "__hyper__lib__", but found in library COREAPB3_LIB @N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3 in library COREAPB3_LIB. Running optimization stage 1 on COREAPB3_MUXPTOB3 ....... @N:CG364 : coreapb3.v(31) | Synthesizing module CoreAPB3 in library COREAPB3_LIB. APB_DWIDTH=6'b100000 IADDR_OPTION=32'b00000000000000000000000000000000 APBSLOT0ENABLE=1'b1 APBSLOT1ENABLE=1'b0 APBSLOT2ENABLE=1'b0 APBSLOT3ENABLE=1'b0 APBSLOT4ENABLE=1'b0 APBSLOT5ENABLE=1'b0 APBSLOT6ENABLE=1'b0 APBSLOT7ENABLE=1'b0 APBSLOT8ENABLE=1'b0 APBSLOT9ENABLE=1'b0 APBSLOT10ENABLE=1'b0 APBSLOT11ENABLE=1'b0 APBSLOT12ENABLE=1'b0 APBSLOT13ENABLE=1'b0 APBSLOT14ENABLE=1'b0 APBSLOT15ENABLE=1'b0 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 MADDR_BITS=6'b010000 UPR_NIBBLE_POSN=4'b0011 FAMILY=32'b00000000000000000000000000010011 SYNC_RESET=32'b00000000000000000000000000000000 IADDR_NOTINUSE=32'b00000000000000000000000000000000 IADDR_EXTERNAL=32'b00000000000000000000000000000001 IADDR_SLOT0=32'b00000000000000000000000000000010 IADDR_SLOT1=32'b00000000000000000000000000000011 IADDR_SLOT2=32'b00000000000000000000000000000100 IADDR_SLOT3=32'b00000000000000000000000000000101 IADDR_SLOT4=32'b00000000000000000000000000000110 IADDR_SLOT5=32'b00000000000000000000000000000111 IADDR_SLOT6=32'b00000000000000000000000000001000 IADDR_SLOT7=32'b00000000000000000000000000001001 IADDR_SLOT8=32'b00000000000000000000000000001010 IADDR_SLOT9=32'b00000000000000000000000000001011 IADDR_SLOT10=32'b00000000000000000000000000001100 IADDR_SLOT11=32'b00000000000000000000000000001101 IADDR_SLOT12=32'b00000000000000000000000000001110 IADDR_SLOT13=32'b00000000000000000000000000001111 IADDR_SLOT14=32'b00000000000000000000000000010000 IADDR_SLOT15=32'b00000000000000000000000000010001 SL0=16'b0000000000000001 SL1=16'b0000000000000000 SL2=16'b0000000000000000 SL3=16'b0000000000000000 SL4=16'b0000000000000000 SL5=16'b0000000000000000 SL6=16'b0000000000000000 SL7=16'b0000000000000000 SL8=16'b0000000000000000 SL9=16'b0000000000000000 SL10=16'b0000000000000000 SL11=16'b0000000000000000 SL12=16'b0000000000000000 SL13=16'b0000000000000000 SL14=16'b0000000000000000 SL15=16'b0000000000000000 SC=16'b0000000000000000 SC_qual=16'b0000000000000000 Generated name = CoreAPB3_Z13 @W:CG360 : coreapb3.v(244) | Removing wire IA_PRDATA, as there is no assignment to it. Running optimization stage 1 on CoreAPB3_Z13 ....... @N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP in library work. FAMILY=32'b00000000000000000000000000010011 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000001 VERSION_MAJOR=32'b00000000000000000000000000000111 VERSION_MINOR=32'b00000000000000000000000000000000 VERSION_MAJOR_VECTOR=16'b0000000000000111 VERSION_MINOR_VECTOR=16'b0000000000000000 S0=2'b00 S1=2'b01 S2=2'b10 Generated name = CoreConfigP_Z14 Running optimization stage 1 on CoreConfigP_Z14 ....... @W:CL207 : coreconfigp.v(461) | All reachable assignments to SDIF1_PENABLE assign 0, register removed by optimization. @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP in library work. FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000001 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z15 Running optimization stage 1 on CoreResetP_Z15 ....... @W:CL169 : coreresetp.v(1613) | Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1581) | Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1549) | Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1517) | Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1365) | Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1300) | Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1235) | Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1089) | Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers. @W:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : coreresetp.v(1089) | Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers. @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB in library work. Running optimization stage 1 on RCOSC_25_50MHZ_FAB ....... @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ in library work. Running optimization stage 1 on RCOSC_25_50MHZ ....... @N:CG364 : SF2_JESD204B_DEMO_sb_FABOSC_0_OSC.v(5) | Synthesizing module SF2_JESD204B_DEMO_sb_FABOSC_0_OSC in library work. Running optimization stage 1 on SF2_JESD204B_DEMO_sb_FABOSC_0_OSC ....... @W:CL318 : SF2_JESD204B_DEMO_sb_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : SF2_JESD204B_DEMO_sb_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : SF2_JESD204B_DEMO_sb_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : SF2_JESD204B_DEMO_sb_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF in library work. Running optimization stage 1 on INBUF ....... @N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF in library work. Running optimization stage 1 on TRIBUFF ....... @N:CG364 : SF2_JESD204B_DEMO_sb_MSS_syn.v(5) | Synthesizing module MSS_075 in library work. Running optimization stage 1 on MSS_075 ....... @N:CG364 : SF2_JESD204B_DEMO_sb_MSS.v(9) | Synthesizing module SF2_JESD204B_DEMO_sb_MSS in library work. Running optimization stage 1 on SF2_JESD204B_DEMO_sb_MSS ....... @N:CG364 : smartfusion2.v(720) | Synthesizing module SYSRESET in library work. Running optimization stage 1 on SYSRESET ....... @N:CG364 : SF2_JESD204B_DEMO_sb.v(9) | Synthesizing module SF2_JESD204B_DEMO_sb in library work. Running optimization stage 1 on SF2_JESD204B_DEMO_sb ....... @N:CG364 : smartfusion2.v(382) | Synthesizing module RAM1K18 in library work. Running optimization stage 1 on RAM1K18 ....... @N:CG364 : top_TPSRAM_0_TPSRAM.v(5) | Synthesizing module top_TPSRAM_0_TPSRAM in library work. Running optimization stage 1 on top_TPSRAM_0_TPSRAM ....... @N:CG364 : top_TPSRAM_1_TPSRAM.v(5) | Synthesizing module top_TPSRAM_1_TPSRAM in library work. Running optimization stage 1 on top_TPSRAM_1_TPSRAM ....... @N:CG364 : top.v(9) | Synthesizing module top in library work. Running optimization stage 1 on top ....... Running optimization stage 2 on top ....... Running optimization stage 2 on top_TPSRAM_1_TPSRAM ....... Running optimization stage 2 on top_TPSRAM_0_TPSRAM ....... Running optimization stage 2 on RAM1K18 ....... Running optimization stage 2 on SF2_JESD204B_DEMO_sb ....... Running optimization stage 2 on SYSRESET ....... Running optimization stage 2 on SF2_JESD204B_DEMO_sb_MSS ....... Running optimization stage 2 on MSS_075 ....... Running optimization stage 2 on TRIBUFF ....... Running optimization stage 2 on INBUF ....... Running optimization stage 2 on SF2_JESD204B_DEMO_sb_FABOSC_0_OSC ....... @N:CL159 : SF2_JESD204B_DEMO_sb_FABOSC_0_OSC.v(14) | Input XTL is unused. Running optimization stage 2 on RCOSC_25_50MHZ ....... Running optimization stage 2 on RCOSC_25_50MHZ_FAB ....... Running optimization stage 2 on CoreResetP_Z15 ....... @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state. Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state. Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state. Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state. Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state. Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @N:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused. @N:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused. @N:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused. @N:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused. @N:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused. @N:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused. @N:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused. @N:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused. @N:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused. @N:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused. @N:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused. @N:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused. @N:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused. @N:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused. Running optimization stage 2 on CoreConfigP_Z14 ....... @N:CL201 : coreconfigp.v(447) | Trying to extract state machine for register state. Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL159 : coreconfigp.v(71) | Input SDIF1_PREADY is unused. @N:CL159 : coreconfigp.v(72) | Input SDIF1_PSLVERR is unused. Running optimization stage 2 on CoreAPB3_Z13 ....... @N:CL159 : coreapb3.v(72) | Input IADDR is unused. @N:CL159 : coreapb3.v(73) | Input PRESETN is unused. @N:CL159 : coreapb3.v(74) | Input PCLK is unused. @N:CL159 : coreapb3.v(105) | Input PRDATAS1 is unused. @N:CL159 : coreapb3.v(106) | Input PRDATAS2 is unused. @N:CL159 : coreapb3.v(107) | Input PRDATAS3 is unused. @N:CL159 : coreapb3.v(108) | Input PRDATAS4 is unused. @N:CL159 : coreapb3.v(109) | Input PRDATAS5 is unused. @N:CL159 : coreapb3.v(110) | Input PRDATAS6 is unused. @N:CL159 : coreapb3.v(111) | Input PRDATAS7 is unused. @N:CL159 : coreapb3.v(112) | Input PRDATAS8 is unused. @N:CL159 : coreapb3.v(113) | Input PRDATAS9 is unused. @N:CL159 : coreapb3.v(114) | Input PRDATAS10 is unused. @N:CL159 : coreapb3.v(115) | Input PRDATAS11 is unused. @N:CL159 : coreapb3.v(116) | Input PRDATAS12 is unused. @N:CL159 : coreapb3.v(117) | Input PRDATAS13 is unused. @N:CL159 : coreapb3.v(118) | Input PRDATAS14 is unused. @N:CL159 : coreapb3.v(119) | Input PRDATAS15 is unused. @N:CL159 : coreapb3.v(122) | Input PREADYS1 is unused. @N:CL159 : coreapb3.v(123) | Input PREADYS2 is unused. @N:CL159 : coreapb3.v(124) | Input PREADYS3 is unused. @N:CL159 : coreapb3.v(125) | Input PREADYS4 is unused. @N:CL159 : coreapb3.v(126) | Input PREADYS5 is unused. @N:CL159 : coreapb3.v(127) | Input PREADYS6 is unused. @N:CL159 : coreapb3.v(128) | Input PREADYS7 is unused. @N:CL159 : coreapb3.v(129) | Input PREADYS8 is unused. @N:CL159 : coreapb3.v(130) | Input PREADYS9 is unused. @N:CL159 : coreapb3.v(131) | Input PREADYS10 is unused. @N:CL159 : coreapb3.v(132) | Input PREADYS11 is unused. @N:CL159 : coreapb3.v(133) | Input PREADYS12 is unused. @N:CL159 : coreapb3.v(134) | Input PREADYS13 is unused. @N:CL159 : coreapb3.v(135) | Input PREADYS14 is unused. @N:CL159 : coreapb3.v(136) | Input PREADYS15 is unused. @N:CL159 : coreapb3.v(139) | Input PSLVERRS1 is unused. @N:CL159 : coreapb3.v(140) | Input PSLVERRS2 is unused. @N:CL159 : coreapb3.v(141) | Input PSLVERRS3 is unused. @N:CL159 : coreapb3.v(142) | Input PSLVERRS4 is unused. @N:CL159 : coreapb3.v(143) | Input PSLVERRS5 is unused. @N:CL159 : coreapb3.v(144) | Input PSLVERRS6 is unused. @N:CL159 : coreapb3.v(145) | Input PSLVERRS7 is unused. @N:CL159 : coreapb3.v(146) | Input PSLVERRS8 is unused. @N:CL159 : coreapb3.v(147) | Input PSLVERRS9 is unused. @N:CL159 : coreapb3.v(148) | Input PSLVERRS10 is unused. @N:CL159 : coreapb3.v(149) | Input PSLVERRS11 is unused. @N:CL159 : coreapb3.v(150) | Input PSLVERRS12 is unused. @N:CL159 : coreapb3.v(151) | Input PSLVERRS13 is unused. @N:CL159 : coreapb3.v(152) | Input PSLVERRS14 is unused. @N:CL159 : coreapb3.v(153) | Input PSLVERRS15 is unused. Running optimization stage 2 on COREAPB3_MUXPTOB3 ....... Running optimization stage 2 on SF2_JESD204B_DEMO_sb_CCC_0_FCCC ....... Running optimization stage 2 on CCC ....... Running optimization stage 2 on SERDES_EPCS ....... Running optimization stage 2 on SERDES_EPCS_SERDES_IF2_0_SERDES_IF2 ....... Running optimization stage 2 on SERDESIF_075 ....... Running optimization stage 2 on GND ....... Running optimization stage 2 on VCC ....... Running optimization stage 2 on epcs_tx_intf ....... Running optimization stage 2 on epcs_rx_intf ....... Running optimization stage 2 on BUFD ....... Running optimization stage 2 on bufd_bus_20s ....... Running optimization stage 2 on delay_line ....... Running optimization stage 2 on PRBS_CHECKER ....... Running optimization stage 2 on LED_DEBUG_BLK ....... @N:CL159 : LED_BLOCK_2.v(53) | Input SOMF_L is unused. Running optimization stage 2 on ERR_GEN ....... Running optimization stage 2 on DATAHANDLE_FSM ....... @N:CL201 : DATA_HANDLE_FSM.v(199) | Trying to extract state machine for register fsm. Extracted state machine for register fsm State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL246 : DATA_HANDLE_FSM.v(69) | Input port bits 15 to 13 of PADDR[15:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : DATA_HANDLE_FSM.v(69) | Input port bits 1 to 0 of PADDR[15:0] are unused. Assign logic for all port bits or change the input port size. @A:CL153 : DATA_HANDLE_FSM.v(110) | *Unassigned bits of SEL are referenced and tied to 0 -- simulation mismatch possible. @N:CL159 : DATA_HANDLE_FSM.v(68) | Input PENABLE is unused. @N:CL159 : DATA_HANDLE_FSM.v(70) | Input PWDATA is unused. Running optimization stage 2 on DATA_GENERATOR ....... Running optimization stage 2 on waveform_gen ....... Running optimization stage 2 on PRBS_WAV_SEL ....... Running optimization stage 2 on PRBS_GENERATOR ....... Running optimization stage 2 on CoreJESD204BTX_Z12 ....... @W:CL156 : CoreJESD204BTX.v(199) | *Input epcs_syncd_rst_n_1 to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(259) | *Input BUF_DATA_OUT_1[19:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(200) | *Input epcs_syncd_rst_n_2 to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(260) | *Input BUF_DATA_OUT_2[19:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(201) | *Input epcs_syncd_rst_n_3 to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(261) | *Input BUF_DATA_OUT_3[19:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(202) | *Input epcs_syncd_rst_n_4 to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(262) | *Input BUF_DATA_OUT_4[19:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(203) | *Input epcs_syncd_rst_n_5 to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(263) | *Input BUF_DATA_OUT_5[19:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(204) | *Input epcs_syncd_rst_n_6 to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(264) | *Input BUF_DATA_OUT_6[19:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(205) | *Input epcs_syncd_rst_n_7 to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(265) | *Input BUF_DATA_OUT_7[19:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(199) | *Input epcs_syncd_rst_n_1 to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(281) | *Input TX_K_1_int[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(200) | *Input epcs_syncd_rst_n_2 to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(282) | *Input TX_K_2_int[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(201) | *Input epcs_syncd_rst_n_3 to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(283) | *Input TX_K_3_int[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(202) | *Input epcs_syncd_rst_n_4 to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(284) | *Input TX_K_4_int[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(203) | *Input epcs_syncd_rst_n_5 to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(285) | *Input TX_K_5_int[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(204) | *Input epcs_syncd_rst_n_6 to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(286) | *Input TX_K_6_int[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(205) | *Input epcs_syncd_rst_n_7 to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BTX.v(287) | *Input TX_K_7_int[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @N:CL159 : CoreJESD204BTX.v(129) | Input DATA_IN_1 is unused. @N:CL159 : CoreJESD204BTX.v(130) | Input DATA_IN_2 is unused. @N:CL159 : CoreJESD204BTX.v(131) | Input DATA_IN_3 is unused. @N:CL159 : CoreJESD204BTX.v(132) | Input DATA_IN_4 is unused. @N:CL159 : CoreJESD204BTX.v(133) | Input DATA_IN_5 is unused. @N:CL159 : CoreJESD204BTX.v(134) | Input DATA_IN_6 is unused. @N:CL159 : CoreJESD204BTX.v(135) | Input DATA_IN_7 is unused. @N:CL159 : CoreJESD204BTX.v(149) | Input EPCS_1_TX_STABLE is unused. @N:CL159 : CoreJESD204BTX.v(150) | Input EPCS_2_TX_STABLE is unused. @N:CL159 : CoreJESD204BTX.v(151) | Input EPCS_3_TX_STABLE is unused. @N:CL159 : CoreJESD204BTX.v(152) | Input EPCS_4_TX_STABLE is unused. @N:CL159 : CoreJESD204BTX.v(153) | Input EPCS_5_TX_STABLE is unused. @N:CL159 : CoreJESD204BTX.v(154) | Input EPCS_6_TX_STABLE is unused. @N:CL159 : CoreJESD204BTX.v(155) | Input EPCS_7_TX_STABLE is unused. Running optimization stage 2 on CJESDTX_RESET_SYNC_0s_0s ....... Running optimization stage 2 on CJESDTX_ENCODER_N_0s ....... Running optimization stage 2 on CJESDTX_ENCODER_L_0s ....... Running optimization stage 2 on CJESDTX_ENCODER_64B80B_0s_16s_2s_20s ....... Running optimization stage 2 on CJESDTX_ENCODER_U_0s ....... Running optimization stage 2 on CJESDTX_ENC_D_0s ....... Running optimization stage 2 on CJESDTX_MUX32X6_0s ....... Running optimization stage 2 on CJESDTX_MUX32X1 ....... Running optimization stage 2 on CJESDTX_MUX4X1 ....... Running optimization stage 2 on CJESDTX_ENC_K_0s ....... @W:CL260 : ENC_K.v(163) | Pruning register bit 1 of K_SEL[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL189 : ENC_K.v(163) | Register bit KCODE_6B[1] is always 1. @W:CL260 : ENC_K.v(163) | Pruning register bit 1 of KCODE_6B[5:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. Running optimization stage 2 on CJESDTX_ENC_FLIP_0s ....... Running optimization stage 2 on CJESDTX_BUF_DATA_0s_16s_2s ....... Running optimization stage 2 on CJESDTX_JESD204BTX_LANE_Z11 ....... Running optimization stage 2 on CJESDTX_TX_CTRL_2s_0s_0_1_2_0s_16s_20s_2s_0 ....... @N:CL201 : TX_CTRL.v(104) | Trying to extract state machine for register TX_STATE. Extracted state machine for register TX_STATE State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL159 : TX_CTRL.v(54) | Input OCTET_FC is unused. @N:CL159 : TX_CTRL.v(55) | Input OCTET_7C is unused. Running optimization stage 2 on CJESDTX_TX_ILA_Z10 ....... @W:CL190 : TX_ILA.v(300) | Optimizing register bit ILAValue_0[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : TX_ILA.v(300) | Pruning register bit 0 of ILAValue_0[6:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL247 : TX_ILA.v(100) | Input port bit 0 of MULTI_FRAME_START[1:0] is unused @W:CL247 : TX_ILA.v(101) | Input port bit 1 of MULTI_FRAME_END[1:0] is unused @N:CL159 : TX_ILA.v(93) | Input LMFC is unused. @N:CL159 : TX_ILA.v(99) | Input FRAME_END is unused. Running optimization stage 2 on CJESDTX_TX_ACG_0s_2s_9s_0s_16s_2s ....... @W:CL190 : TX_ACG.v(2137) | Optimizing register bit genblk6.OCount_U[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : TX_ACG.v(2137) | Pruning unused register genblk6.OCount_U[0]. Make sure that there are no unused intermediate registers. Running optimization stage 2 on CJESDTX_SYNC_BUF_TX_1s_16s_2s_2s_20s_0s_20s_0s_1 ....... @N:CL134 : DATA_SYNC_BUF_TX.v(371) | Found RAM data_buf, depth=4, width=20 @N:CL134 : DATA_SYNC_BUF_TX.v(371) | Found RAM k_buf, depth=4, width=2 Running optimization stage 2 on CJESDTX_CLOCK_GEN_TX_2s_9s_0s_16s_2s_0s_4s_2s_18s_4s ....... @W:CL190 : CLOCK_GEN_TX.v(206) | Optimizing register bit genblk2.FC_PHASE[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CLOCK_GEN_TX.v(158) | Optimizing register bit genblk2.LMFC_PHASE[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : CLOCK_GEN_TX.v(158) | Pruning register bit 0 of genblk2.LMFC_PHASE[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : CLOCK_GEN_TX.v(206) | Pruning register bit 0 of genblk2.FC_PHASE[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL189 : CLOCK_GEN_TX.v(206) | Register bit genblk2.FC_PHASE[1] is always 0. @W:CL169 : CLOCK_GEN_TX.v(206) | Pruning unused register genblk2.FC_PHASE[1]. Make sure that there are no unused intermediate registers. @N:CL159 : CLOCK_GEN_TX.v(53) | Input SYSREF_IN is unused. @N:CL159 : CLOCK_GEN_TX.v(54) | Input SYNC_N is unused. Running optimization stage 2 on CJESDTX_SYNC_DEC_2s_0s_16s_2s_0s_6s ....... @N:CL159 : SYNC_DEC.v(51) | Input LMFC is unused. @N:CL159 : SYNC_DEC.v(53) | Input FORCE_SYNC is unused. Running optimization stage 2 on CJESDTX_DATA_CAPTURE_2s_0s ....... Running optimization stage 2 on CJESDTX_DATA_CAPTURE_20s_0s ....... Running optimization stage 2 on CJESDTX_DATA_CAPTURE_16s_0s ....... Running optimization stage 2 on CJESDRX_DATA_SYNC_BUF_20s_2s_20s_2s_0s_1s ....... @N:CL134 : DATA_SYNC_BUF.v(220) | Found RAM data_buf, depth=4, width=20 @N:CL134 : DATA_SYNC_BUF.v(220) | Found RAM k_buf, depth=4, width=2 @N:CL134 : DATA_SYNC_BUF.v(220) | Found RAM valid_buf, depth=4, width=2 Running optimization stage 2 on CoreJESD204BRX_Z9 ....... @W:CL156 : CoreJESD204BRX.v(344) | *Input DATA_OUT_1_dc[15:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(345) | *Input DATA_OUT_2_dc[15:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(346) | *Input DATA_OUT_3_dc[15:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(347) | *Input DATA_OUT_4_dc[15:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(348) | *Input DATA_OUT_5_dc[15:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(349) | *Input DATA_OUT_6_dc[15:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(350) | *Input DATA_OUT_7_dc[15:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(352) | *Input SOF_1_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(353) | *Input SOF_2_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(354) | *Input SOF_3_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(355) | *Input SOF_4_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(356) | *Input SOF_5_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(357) | *Input SOF_6_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(358) | *Input SOF_7_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(360) | *Input SOMF_1_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(361) | *Input SOMF_2_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(362) | *Input SOMF_3_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(363) | *Input SOMF_4_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(364) | *Input SOMF_5_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(365) | *Input SOMF_6_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(366) | *Input SOMF_7_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(368) | *Input RX_STATE_1_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(369) | *Input RX_STATE_2_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(370) | *Input RX_STATE_3_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(371) | *Input RX_STATE_4_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(372) | *Input RX_STATE_5_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(373) | *Input RX_STATE_6_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(374) | *Input RX_STATE_7_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(448) | *Input k_in_0[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(440) | *Input valid_in_0[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @N:CL159 : CoreJESD204BRX.v(188) | Input EPCS_1_RX_DATA is unused. @N:CL159 : CoreJESD204BRX.v(189) | Input EPCS_2_RX_DATA is unused. @N:CL159 : CoreJESD204BRX.v(190) | Input EPCS_3_RX_DATA is unused. @N:CL159 : CoreJESD204BRX.v(191) | Input EPCS_4_RX_DATA is unused. @N:CL159 : CoreJESD204BRX.v(192) | Input EPCS_5_RX_DATA is unused. @N:CL159 : CoreJESD204BRX.v(193) | Input EPCS_6_RX_DATA is unused. @N:CL159 : CoreJESD204BRX.v(194) | Input EPCS_7_RX_DATA is unused. Only the first 100 messages of id 'CL159' are reported. To see all messages use 'report_messages -log C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\synthesis\synlog\top_compiler.srr -id CL159' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL159} -count unlimited' in the Tcl shell. Running optimization stage 2 on CJESDRX_RESET_SYNC_0s_0s ....... Running optimization stage 2 on CJESDRX_DECODER_L_0s ....... Running optimization stage 2 on CJESDRX_DEC_RD_L_0s ....... Running optimization stage 2 on CJESDRX_DEC_WA_0s_1s_16s_20s_2s ....... Running optimization stage 2 on CJESDRX_WORD_ALIGNER_Z8 ....... @W:CL260 : WORD_ALIGNER.v(188) | Pruning register bit 2 of wa_sel_d_mon[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL189 : WORD_ALIGNER.v(188) | Register bit wa_sel_d_mon[1] is always 0. @W:CL177 : WORD_ALIGNER.v(458) | Sharing sequential element D1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : WORD_ALIGNER.v(458) | Sharing sequential element D2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : WORD_ALIGNER.v(458) | Sharing sequential element D3. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : WORD_ALIGNER.v(458) | Sharing sequential element D4. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : WORD_ALIGNER.v(458) | Sharing sequential element D5. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : WORD_ALIGNER.v(458) | Sharing sequential element D6. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : WORD_ALIGNER.v(458) | Sharing sequential element D7. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : WORD_ALIGNER.v(458) | Sharing sequential element D8. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : WORD_ALIGNER.v(458) | Sharing sequential element D9. Add a syn_preserve attribute to the element to prevent sharing. @W:CL260 : WORD_ALIGNER.v(188) | Pruning register bit 1 of wa_sel_d_mon[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL201 : WORD_ALIGNER.v(769) | Trying to extract state machine for register WA_FSM_STATE. Running optimization stage 2 on CJESDRX_DECODER_U_0s ....... Running optimization stage 2 on CJESDRX_DEC_RD_U_0s ....... Running optimization stage 2 on CJESDRX_SYNC_FSM_0s_0_1_2_3_4_4 ....... @N:CL201 : SYNC_FSM.v(50) | Trying to extract state machine for register SYNC_STATE. Extracted state machine for register SYNC_STATE State machine has 5 reachable states with original encodings of: 000 001 010 011 100 Running optimization stage 2 on CJESDRX_DEC_DATA_0s ....... Running optimization stage 2 on CJESDRX_DEC_ERR ....... Running optimization stage 2 on CJESDRX_JESD204BRX_LANE_Z7 ....... Running optimization stage 2 on CJESDRX_FADM_OR_4s_0s_2s_9s_0s_1s_16s_2s ....... Running optimization stage 2 on CJESDRX_IFS_POS_Z6 ....... @W:CL190 : IFS_POS.v(4385) | Optimizing register bit genblk6.ILAValue[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(198) | Optimizing register bit Kcounter[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(198) | Optimizing register bit Kcounter[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(198) | Optimizing register bit Kcounter[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL279 : IFS_POS.v(198) | Pruning register bits 4 to 3 of Kcounter[4:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : IFS_POS.v(198) | Pruning register bit 0 of Kcounter[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : IFS_POS.v(4385) | Pruning register bit 0 of genblk6.ILAValue[6:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL201 : IFS_POS.v(295) | Trying to extract state machine for register CC_state. Extracted state machine for register CC_state State machine has 2 reachable states with original encodings of: 00 01 @N:CL201 : IFS_POS.v(198) | Trying to extract state machine for register FS_STATE. Extracted state machine for register FS_STATE State machine has 4 reachable states with original encodings of: 00 01 10 11 Running optimization stage 2 on CJESDRX_FL_AMC_0s_2s_9s_1s_16s_2s ....... Running optimization stage 2 on CJESDRX_LINK_COMP_Z5 ....... @W:CL190 : LINK_COMP.v(370) | Optimizing register bit genblk6.map_cnt[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : LINK_COMP.v(370) | Pruning register bit 0 of genblk6.map_cnt[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL201 : LINK_COMP.v(294) | Trying to extract state machine for register CD_M_state. Extracted state machine for register CD_M_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 Running optimization stage 2 on CJESDRX_LABDM_Z4 ....... Running optimization stage 2 on CJESDRX_ADJ_BUF_0s_2s_9s_18s_54s_16s_2s_9s_18s ....... Running optimization stage 2 on CJESDRX_RAM_EB_0s_54s_16s_2s_18s ....... Running optimization stage 2 on CJESDRX_EB_CTRL_0s_2s_9s_18s_54s_0_1_16s_2s ....... Running optimization stage 2 on CJESDRX_ILA_FSM_Z3 ....... @N:CL201 : ILA_FSM.v(505) | Trying to extract state machine for register RIstate. Extracted state machine for register RIstate State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL201 : ILA_FSM.v(306) | Trying to extract state machine for register ILA_state. Extracted state machine for register ILA_state State machine has 5 reachable states with original encodings of: 000 001 010 011 100 Running optimization stage 2 on CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s ....... @N:CL135 : RX_CTRL.v(149) | Found sequential shift mf_phase_reg with address depth of 4 words and data bit width of 5. @N:CL135 : RX_CTRL.v(149) | Found sequential shift f_phase_reg with address depth of 4 words and data bit width of 2. Running optimization stage 2 on CJESDRX_ADJ_CTRL_Z2 ....... @N:CL135 : ADJ_CTRL.v(112) | Found sequential shift mf_phase_reg with address depth of 3 words and data bit width of 5. @N:CL135 : ADJ_CTRL.v(112) | Found sequential shift f_phase_reg with address depth of 3 words and data bit width of 2. Running optimization stage 2 on CJESDRX_CGS_0s_0_1_2_16s_2s ....... @N:CL201 : CGS.v(370) | Trying to extract state machine for register CG_state. Extracted state machine for register CG_state State machine has 3 reachable states with original encodings of: 00 01 10 Running optimization stage 2 on CJESDRX_CLOCK_GEN_RX_Z1 ....... @W:CL190 : CLOCK_GEN_RX.v(347) | Optimizing register bit genblk3.F_PHASE[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CLOCK_GEN_RX.v(299) | Optimizing register bit genblk3.MF_PHASE[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : CLOCK_GEN_RX.v(299) | Pruning register bit 0 of genblk3.MF_PHASE[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : CLOCK_GEN_RX.v(347) | Pruning register bit 0 of genblk3.F_PHASE[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL189 : CLOCK_GEN_RX.v(347) | Register bit genblk3.F_PHASE[1] is always 0. @W:CL169 : CLOCK_GEN_RX.v(347) | Pruning unused register genblk3.F_PHASE[1]. Make sure that there are no unused intermediate registers. Running optimization stage 2 on CJESDRX_SYNC_ENC_2s_0s_0s_2s_9s_54s_0s_0_1_2 ....... @N:CL201 : SYNC_ENC.v(95) | Trying to extract state machine for register SYNC_GEN_ST. Extracted state machine for register SYNC_GEN_ST State machine has 3 reachable states with original encodings of: 00 01 10 Running optimization stage 2 on CJESDRX_DATA_CAPTURE_16s_0s ....... Running optimization stage 2 on CJESDRX_DATA_CAPTURE_2s_0s ....... Running optimization stage 2 on CJESDRX_DATA_CAPTURE_20s_0s ....... Running optimization stage 2 on CLKINT ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:19s; CPU Time elapsed 0h:00m:19s; Memory used current: 132MB peak: 152MB) Process took 0h:00m:19s realtime, 0h:00m:19s cputime Process completed successfully. # Sun Mar 28 21:10:32 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Sun Mar 28 21:10:33 2021 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: top_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:20s; Memory used current: 23MB peak: 32MB) Process took 0h:00m:20s realtime, 0h:00m:20s cputime Process completed successfully. # Sun Mar 28 21:10:33 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 107MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Sun Mar 28 21:10:35 2021 ###########################################################] Premap Report # Sun Mar 28 21:10:36 2021 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys Generic Technology Pre-mapping, Version map202003act, Build 160R, Built Oct 22 2020 12:05:41, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) Reading constraint file: C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\designer\top\synthesis.fdc Linked File: top_scck.rpt See clock summary report "C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\synthesis\top_scck.rpt" @W:BN544 : synthesis.fdc(11) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 147MB) @W:BN132 : corejesd204brx.v(561) | Removing user instance CoreJESD204BRX_0.DC_RS_7 because it is equivalent to instance CoreJESD204BRX_0.DC_RS_6. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corejesd204brx.v(560) | Removing user instance CoreJESD204BRX_0.DC_RS_6 because it is equivalent to instance CoreJESD204BRX_0.DC_RS_5. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corejesd204brx.v(559) | Removing user instance CoreJESD204BRX_0.DC_RS_5 because it is equivalent to instance CoreJESD204BRX_0.DC_RS_4. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corejesd204brx.v(558) | Removing user instance CoreJESD204BRX_0.DC_RS_4 because it is equivalent to instance CoreJESD204BRX_0.DC_RS_3. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corejesd204brx.v(557) | Removing user instance CoreJESD204BRX_0.DC_RS_3 because it is equivalent to instance CoreJESD204BRX_0.DC_RS_2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corejesd204brx.v(556) | Removing user instance CoreJESD204BRX_0.DC_RS_2 because it is equivalent to instance CoreJESD204BRX_0.DC_RS_1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corejesd204brx.v(552) | Removing user instance CoreJESD204BRX_0.DC_SMOF_7 because it is equivalent to instance CoreJESD204BRX_0.DC_RS_1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corejesd204brx.v(551) | Removing user instance CoreJESD204BRX_0.DC_SMOF_6 because it is equivalent to instance CoreJESD204BRX_0.DC_RS_1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corejesd204brx.v(550) | Removing user instance CoreJESD204BRX_0.DC_SMOF_5 because it is equivalent to instance CoreJESD204BRX_0.DC_RS_1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corejesd204brx.v(549) | Removing user instance CoreJESD204BRX_0.DC_SMOF_4 because it is equivalent to instance CoreJESD204BRX_0.DC_RS_1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corejesd204brx.v(548) | Removing user instance CoreJESD204BRX_0.DC_SMOF_3 because it is equivalent to instance CoreJESD204BRX_0.DC_RS_1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corejesd204brx.v(547) | Removing user instance CoreJESD204BRX_0.DC_SMOF_2 because it is equivalent to instance CoreJESD204BRX_0.DC_RS_1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corejesd204brx.v(546) | Removing user instance CoreJESD204BRX_0.DC_SMOF_1 because it is equivalent to instance CoreJESD204BRX_0.DC_RS_1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corejesd204brx.v(543) | Removing user instance CoreJESD204BRX_0.DC_SOF_7 because it is equivalent to instance CoreJESD204BRX_0.DC_RS_1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corejesd204brx.v(542) | Removing user instance CoreJESD204BRX_0.DC_SOF_6 because it is equivalent to instance CoreJESD204BRX_0.DC_RS_1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corejesd204brx.v(541) | Removing user instance CoreJESD204BRX_0.DC_SOF_5 because it is equivalent to instance CoreJESD204BRX_0.DC_RS_1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corejesd204brx.v(540) | Removing user instance CoreJESD204BRX_0.DC_SOF_4 because it is equivalent to instance CoreJESD204BRX_0.DC_RS_1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corejesd204brx.v(539) | Removing user instance CoreJESD204BRX_0.DC_SOF_3 because it is equivalent to instance CoreJESD204BRX_0.DC_RS_1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corejesd204brx.v(538) | Removing user instance CoreJESD204BRX_0.DC_SOF_2 because it is equivalent to instance CoreJESD204BRX_0.DC_RS_1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corejesd204brx.v(537) | Removing user instance CoreJESD204BRX_0.DC_SOF_1 because it is equivalent to instance CoreJESD204BRX_0.DC_RS_1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corejesd204brx.v(534) | Removing user instance CoreJESD204BRX_0.DC_DO_7 because it is equivalent to instance CoreJESD204BRX_0.DC_DO_6. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corejesd204brx.v(533) | Removing user instance CoreJESD204BRX_0.DC_DO_6 because it is equivalent to instance CoreJESD204BRX_0.DC_DO_5. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corejesd204brx.v(532) | Removing user instance CoreJESD204BRX_0.DC_DO_5 because it is equivalent to instance CoreJESD204BRX_0.DC_DO_4. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corejesd204brx.v(531) | Removing user instance CoreJESD204BRX_0.DC_DO_4 because it is equivalent to instance CoreJESD204BRX_0.DC_DO_3. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corejesd204brx.v(530) | Removing user instance CoreJESD204BRX_0.DC_DO_3 because it is equivalent to instance CoreJESD204BRX_0.DC_DO_2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : corejesd204brx.v(529) | Removing user instance CoreJESD204BRX_0.DC_DO_2 because it is equivalent to instance CoreJESD204BRX_0.DC_DO_1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(1089) | Removing sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MO111 : sf2_jesd204b_demo_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.SF2_JESD204B_DEMO_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.SF2_JESD204B_DEMO_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : sf2_jesd204b_demo_sb_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.SF2_JESD204B_DEMO_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.SF2_JESD204B_DEMO_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : sf2_jesd204b_demo_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.SF2_JESD204B_DEMO_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.SF2_JESD204B_DEMO_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : sf2_jesd204b_demo_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.SF2_JESD204B_DEMO_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.SF2_JESD204B_DEMO_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @W:MO129 : coreresetp.v(676) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(1388) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation. @N:BN115 : corejesd204brx.v(528) | Removing instance DC_DO_1 (in view: work.CoreJESD204BRX_Z9(verilog)) of type view:work.CJESDRX_DATA_CAPTURE_16s_0s_0(verilog) because it does not drive other instances. @N:BN115 : corejesd204brx.v(555) | Removing instance DC_RS_1 (in view: work.CoreJESD204BRX_Z9(verilog)) of type view:work.CJESDRX_DATA_CAPTURE_2s_0s_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(85) | Removing instance UT1B5 (in view: work.CJESDTX_MUX32X1_3_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_15_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(86) | Removing instance UT1B6 (in view: work.CJESDTX_MUX32X1_3_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_14_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(87) | Removing instance UT1B7 (in view: work.CJESDTX_MUX32X1_3_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_13_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(83) | Removing instance UT1B3 (in view: work.CJESDTX_MUX32X1_2_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_27_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(84) | Removing instance UT1B4 (in view: work.CJESDTX_MUX32X1_2_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_26_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(85) | Removing instance UT1B5 (in view: work.CJESDTX_MUX32X1_2_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_25_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(81) | Removing instance UT1B1 (in view: work.CJESDTX_MUX32X1_1_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_39_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(82) | Removing instance UT1B2 (in view: work.CJESDTX_MUX32X1_1_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_38_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(84) | Removing instance UT1B4 (in view: work.CJESDTX_MUX32X1_1_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_36_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(85) | Removing instance UT1B5 (in view: work.CJESDTX_MUX32X1_1_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_35_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(86) | Removing instance UT1B6 (in view: work.CJESDTX_MUX32X1_1_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_34_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(87) | Removing instance UT1B7 (in view: work.CJESDTX_MUX32X1_1_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_33_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(92) | Removing instance UT2B1 (in view: work.CJESDTX_MUX32X1_1_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_31_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(80) | Removing instance UT1B0 (in view: work.CJESDTX_MUX32X1_0_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_50_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(85) | Removing instance UT1B5 (in view: work.CJESDTX_MUX32X1_3_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_15_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(86) | Removing instance UT1B6 (in view: work.CJESDTX_MUX32X1_3_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_14_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(87) | Removing instance UT1B7 (in view: work.CJESDTX_MUX32X1_3_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_13_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(83) | Removing instance UT1B3 (in view: work.CJESDTX_MUX32X1_2_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_27_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(84) | Removing instance UT1B4 (in view: work.CJESDTX_MUX32X1_2_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_26_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(85) | Removing instance UT1B5 (in view: work.CJESDTX_MUX32X1_2_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_25_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(81) | Removing instance UT1B1 (in view: work.CJESDTX_MUX32X1_1_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_39_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(82) | Removing instance UT1B2 (in view: work.CJESDTX_MUX32X1_1_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_38_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(84) | Removing instance UT1B4 (in view: work.CJESDTX_MUX32X1_1_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_36_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(85) | Removing instance UT1B5 (in view: work.CJESDTX_MUX32X1_1_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_35_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(86) | Removing instance UT1B6 (in view: work.CJESDTX_MUX32X1_1_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_34_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(87) | Removing instance UT1B7 (in view: work.CJESDTX_MUX32X1_1_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_33_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(92) | Removing instance UT2B1 (in view: work.CJESDTX_MUX32X1_1_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_31_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(80) | Removing instance UT1B0 (in view: work.CJESDTX_MUX32X1_0_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_50_1(verilog) because it does not drive other instances. @N:BN115 : corejesd204btx.v(519) | Removing instance CJESDTX_CLOCK_GEN_TX (in view: work.CoreJESD204BTX_Z12(verilog)) of type view:work.CJESDTX_CLOCK_GEN_TX_2s_9s_0s_16s_2s_0s_4s_2s_18s_4s(verilog) because it does not drive other instances. @N:BN115 : corejesd204btx.v(483) | Removing instance DC_BDO_1 (in view: work.CoreJESD204BTX_Z12(verilog)) of type view:work.CJESDTX_DATA_CAPTURE_20s_0s_6(verilog) because it does not drive other instances. @N:BN115 : corejesd204btx.v(484) | Removing instance DC_BDO_2 (in view: work.CoreJESD204BTX_Z12(verilog)) of type view:work.CJESDTX_DATA_CAPTURE_20s_0s_5(verilog) because it does not drive other instances. @N:BN115 : corejesd204btx.v(485) | Removing instance DC_BDO_3 (in view: work.CoreJESD204BTX_Z12(verilog)) of type view:work.CJESDTX_DATA_CAPTURE_20s_0s_4(verilog) because it does not drive other instances. @N:BN115 : corejesd204btx.v(486) | Removing instance DC_BDO_4 (in view: work.CoreJESD204BTX_Z12(verilog)) of type view:work.CJESDTX_DATA_CAPTURE_20s_0s_3(verilog) because it does not drive other instances. @N:BN115 : corejesd204btx.v(487) | Removing instance DC_BDO_5 (in view: work.CoreJESD204BTX_Z12(verilog)) of type view:work.CJESDTX_DATA_CAPTURE_20s_0s_2(verilog) because it does not drive other instances. @N:BN115 : corejesd204btx.v(488) | Removing instance DC_BDO_6 (in view: work.CoreJESD204BTX_Z12(verilog)) of type view:work.CJESDTX_DATA_CAPTURE_20s_0s_1(verilog) because it does not drive other instances. @N:BN115 : corejesd204btx.v(489) | Removing instance DC_BDO_7 (in view: work.CoreJESD204BTX_Z12(verilog)) of type view:work.CJESDTX_DATA_CAPTURE_20s_0s_0(verilog) because it does not drive other instances. @N:BN115 : corejesd204btx.v(492) | Removing instance DC_TK_1 (in view: work.CoreJESD204BTX_Z12(verilog)) of type view:work.CJESDTX_DATA_CAPTURE_2s_0s_6(verilog) because it does not drive other instances. @N:BN115 : corejesd204btx.v(493) | Removing instance DC_TK_2 (in view: work.CoreJESD204BTX_Z12(verilog)) of type view:work.CJESDTX_DATA_CAPTURE_2s_0s_5(verilog) because it does not drive other instances. @N:BN115 : corejesd204btx.v(494) | Removing instance DC_TK_3 (in view: work.CoreJESD204BTX_Z12(verilog)) of type view:work.CJESDTX_DATA_CAPTURE_2s_0s_4(verilog) because it does not drive other instances. @N:BN115 : corejesd204btx.v(495) | Removing instance DC_TK_4 (in view: work.CoreJESD204BTX_Z12(verilog)) of type view:work.CJESDTX_DATA_CAPTURE_2s_0s_3(verilog) because it does not drive other instances. @N:BN115 : corejesd204btx.v(496) | Removing instance DC_TK_5 (in view: work.CoreJESD204BTX_Z12(verilog)) of type view:work.CJESDTX_DATA_CAPTURE_2s_0s_2(verilog) because it does not drive other instances. @N:BN115 : corejesd204btx.v(497) | Removing instance DC_TK_6 (in view: work.CoreJESD204BTX_Z12(verilog)) of type view:work.CJESDTX_DATA_CAPTURE_2s_0s_1(verilog) because it does not drive other instances. @N:BN115 : corejesd204btx.v(498) | Removing instance DC_TK_7 (in view: work.CoreJESD204BTX_Z12(verilog)) of type view:work.CJESDTX_DATA_CAPTURE_2s_0s_0(verilog) because it does not drive other instances. @N:BN362 : enc_k.v(163) | Removing sequential instance K_ERR (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(163) | Removing sequential instance KCODE_6B_1[0] (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances. @N:BN362 : enc_k.v(163) | Removing sequential instance KCODE_6B_1[5:2] (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffpatr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(163) | Removing sequential instance KCODE_4B[3:0] (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffpatr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(163) | Removing sequential instance SP_4B_RDP (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(163) | Removing sequential instance SP_4B_RDN (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_flip.v(89) | Removing sequential instance EN_INV_6B (in view: work.CJESDTX_ENC_FLIP_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_flip.v(89) | Removing sequential instance EN_INV_4B (in view: work.CJESDTX_ENC_FLIP_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_flip.v(89) | Removing sequential instance INV_4B_RD (in view: work.CJESDTX_ENC_FLIP_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : encoder_u.v(84) | Removing sequential instance INVALID_K (in view: work.CJESDTX_ENCODER_U_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : encoder_l.v(83) | Removing sequential instance INVALID_K (in view: work.CJESDTX_ENCODER_L_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance MDDR_PENABLE (in view: work.CoreConfigP_Z14(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE (in view: work.CoreConfigP_Z14(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE (in view: work.CoreConfigP_Z14(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF3_PENABLE (in view: work.CoreConfigP_Z14(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : corejesd204brx.v(554) | Removing instance DC_RS_0 (in view: work.CoreJESD204BRX_Z9(verilog)) of type view:work.CJESDRX_DATA_CAPTURE_2s_0s_1(verilog) because it does not drive other instances. @N:BN362 : corejesd204btx.v(450) | Removing sequential instance SOF[1:0] (in view: work.CoreJESD204BTX_Z12(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : corejesd204btx.v(450) | Removing sequential instance SOMF[1:0] (in view: work.CoreJESD204BTX_Z12(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : corejesd204btx.v(450) | Removing sequential instance TX_STATE[1:0] (in view: work.CoreJESD204BTX_Z12(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN115 : corejesd204btx.v(491) | Removing instance DC_TK_0 (in view: work.CoreJESD204BTX_Z12(verilog)) of type view:work.CJESDTX_DATA_CAPTURE_2s_0s_7(verilog) because it does not drive other instances. @N:BN362 : data_handle_fsm.v(199) | Removing sequential instance WR_ENABLE (in view: work.DATAHANDLE_FSM(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : encoder_u.v(84) | Removing sequential instance BAD_K (in view: work.CJESDTX_ENCODER_U_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : encoder_l.v(83) | Removing sequential instance BAD_K (in view: work.CJESDTX_ENCODER_L_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : data_capture.v(35) | Removing sequential instance DATA_OUT[1:0] (in view: work.CJESDRX_DATA_CAPTURE_2s_0s_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : corejesd204btx.v(450) | Removing sequential instance SOF_0_int_1[1:0] (in view: work.CoreJESD204BTX_Z12(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : corejesd204btx.v(450) | Removing sequential instance SOMF_0_int_1[1:0] (in view: work.CoreJESD204BTX_Z12(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : data_capture.v(35) | Removing sequential instance DATA_OUT[1:0] (in view: work.CJESDTX_DATA_CAPTURE_2s_0s_7(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_flip.v(57) | Removing sequential instance X_7 (in view: work.CJESDTX_ENC_FLIP_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_flip.v(57) | Removing sequential instance Y_3 (in view: work.CJESDTX_ENC_FLIP_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : data_sync_buf_tx.v(231) | Removing sequential instance genblk4\.TX_K_OUT[1:0] (in view: work.CJESDTX_SYNC_BUF_TX_1s_16s_2s_2s_20s_0s_20s_0s_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(117) | Removing sequential instance X_DLY[4:0] (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffpatr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(117) | Removing sequential instance X_EQ_14 (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(117) | Removing sequential instance X_EQ_13 (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(117) | Removing sequential instance X_EQ_11 (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(117) | Removing sequential instance X_EQ_20 (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(117) | Removing sequential instance X_EQ_18 (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(117) | Removing sequential instance X_EQ_17 (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(163) | Removing sequential instance K_ERR (in view: work.CJESDTX_ENC_K_0s_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(163) | Removing sequential instance K_ERR (in view: work.CJESDTX_ENC_K_0s_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : fadm_or.v(135) | Removing sequential instance FPC[1:0] (in view: work.CJESDRX_FADM_OR_4s_0s_2s_9s_0s_1s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : data_sync_buf_tx.v(371) | Removing sequential instance k_buf[1:0] (in view: work.CJESDTX_SYNC_BUF_TX_1s_16s_2s_2s_20s_0s_20s_0s_1(verilog)) of type view:PrimLib.ram2(prim) because it does not drive other instances. @N:BN362 : enc_k.v(117) | Removing sequential instance Y_DLY[2:0] (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffpatr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:FX1184 : | Applying syn_allowed_resources blockrams=109 on top level netlist top Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB) @W:MT688 : synthesis.fdc(11) | No path from master pin (-source) to source of clock SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 due to black box SF2_JESD204B_DEMO_sb_0.CCC_0.CCC_INST Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ 0 - SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] 100.0 MHz 10.000 declared default_clkgroup 1136 0 - SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] 100.0 MHz 10.000 declared default_clkgroup 605 0 - SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 20.000 declared default_clkgroup 30 1 . SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 100.0 MHz 10.000 generated (from SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT) default_clkgroup 101 0 - SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB 25.0 MHz 40.000 declared default_clkgroup 111 ================================================================================================================================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] 1136 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST.EPCS_RXCLK[0](SERDESIF_075) SERDES_EPCS_0.epcs_rx_intf_0.rxval_l.C - SERDES_EPCS_0.epcs_rx_intf_0.un1_clk.I[0](inv) SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] 605 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST.EPCS_TXCLK[0](SERDESIF_075) SERDES_EPCS_0.epcs_tx_intf_0.txdin_p[19:0].C - - SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 30 SF2_JESD204B_DEMO_sb_0.FABOSC_0.I_RCOSC_25_50MHZ.CLKOUT(RCOSC_25_50MHZ) SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_enable_q1.C - SF2_JESD204B_DEMO_sb_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB.A(RCOSC_25_50MHZ_FAB) SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 101 SF2_JESD204B_DEMO_sb_0.CCC_0.CCC_INST.GL0(CCC) TPSRAM_1.top_TPSRAM_1_TPSRAM_R0C3.B_DOUT_CLK - CLKINT_0.I(BUFG) SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB 111 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST.CLK_CONFIG_APB(MSS_075) SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.psel.C - SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.un1_FIC_2_APB_M_PCLK.I[0](inv) ======================================================================================================================================================================================================================================================================================================================================== @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\synthesis\top.sap. Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 186MB) Encoding state machine SYNC_GEN_ST[2:0] (in view: work.CJESDRX_SYNC_ENC_2s_0s_0s_2s_9s_54s_0s_0_1_2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine CG_state[2:0] (in view: work.CJESDRX_CGS_0s_0_1_2_16s_2s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine RIstate[2:0] (in view: work.CJESDRX_ILA_FSM_Z3(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine ILA_state[4:0] (in view: work.CJESDRX_ILA_FSM_Z3(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 Encoding state machine CD_M_state[6:0] (in view: work.CJESDRX_LINK_COMP_Z5(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine SYNC_STATE[4:0] (in view: work.CJESDRX_SYNC_FSM_0s_0_1_2_4_4_0(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 Encoding state machine SYNC_STATE[4:0] (in view: work.CJESDRX_SYNC_FSM_0s_0_1_2_4_4_1(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 Encoding state machine FS_STATE_1[3:0] (in view: work.CJESDRX_IFS_POS_Z6(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : ifs_pos.v(198) | There are no possible illegal states for state machine FS_STATE_1[3:0] (in view: work.CJESDRX_IFS_POS_Z6(verilog)); safe FSM implementation is not required. Encoding state machine CC_state[1:0] (in view: work.CJESDRX_IFS_POS_Z6(verilog)) original code -> new code 00 -> 0 01 -> 1 @N:MO225 : ifs_pos.v(295) | There are no possible illegal states for state machine CC_state[1:0] (in view: work.CJESDRX_IFS_POS_Z6(verilog)); safe FSM implementation is not required. Encoding state machine TX_STATE_1[2:0] (in view: work.CJESDTX_TX_CTRL_2s_0s_0_1_2_0s_16s_20s_2s_0(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine fsm[3:0] (in view: work.DATAHANDLE_FSM(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : data_handle_fsm.v(199) | There are no possible illegal states for state machine fsm[3:0] (in view: work.DATAHANDLE_FSM(verilog)); safe FSM implementation is not required. Encoding state machine state[2:0] (in view: work.CoreConfigP_Z14(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z15(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sdif0_state[3:0] (in view: work.CoreResetP_Z15(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : coreresetp.v(1170) | There are no possible illegal states for state machine sdif0_state[3:0] (in view: work.CoreResetP_Z15(verilog)); safe FSM implementation is not required. Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 186MB peak: 186MB) @W:MF511 : | Found issues with constraints. Please check constraint checker report "C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\synthesis\top_cck.rpt" . Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 188MB peak: 188MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 101MB peak: 188MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Sun Mar 28 21:10:38 2021 ###########################################################] Map & Optimize Report # Sun Mar 28 21:10:38 2021 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys Generic Technology Mapper, Version map202003act, Build 160R, Built Oct 22 2020 12:05:41, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 129MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 129MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 129MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 123MB peak: 129MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB) @N:MO111 : sf2_jesd204b_demo_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.SF2_JESD204B_DEMO_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.SF2_JESD204B_DEMO_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : sf2_jesd204b_demo_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.SF2_JESD204B_DEMO_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.SF2_JESD204B_DEMO_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : sf2_jesd204b_demo_sb_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.SF2_JESD204B_DEMO_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.SF2_JESD204B_DEMO_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : sf2_jesd204b_demo_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.SF2_JESD204B_DEMO_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.SF2_JESD204B_DEMO_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @W:BN132 : mux32x1.v(86) | Removing user instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB5.UT1B6 because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB5.UT1B2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : mux32x1.v(82) | Removing user instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB5.UT1B2 because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB5.UT1B1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : mux32x1.v(87) | Removing user instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB5.UT1B7 because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB5.UT1B5. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : mux32x1.v(85) | Removing user instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB5.UT1B5 because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB5.UT1B4. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : mux32x1.v(85) | Removing user instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB4.UT1B5 because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB4.UT1B3. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : mux32x1.v(86) | Removing user instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB4.UT1B6 because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB4.UT1B4. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : mux32x1.v(84) | Removing user instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB4.UT1B4 because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB4.UT1B2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : mux32x1.v(82) | Removing user instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB4.UT1B2 because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB4.UT1B1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : mux32x1.v(84) | Removing user instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB3.UT1B4 because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB3.UT1B2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : mux32x1.v(87) | Removing user instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB2.UT1B7 because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB2.UT1B0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : mux32x1.v(86) | Removing user instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB2.UT1B6 because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB2.UT1B2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : mux32x1.v(84) | Removing user instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB0.UT1B4 because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB0.UT1B2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : mux32x1.v(82) | Removing user instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB0.UT1B2 because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB0.UT1B1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : mux32x1.v(86) | Removing user instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB0.UT1B6 because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB0.UT1B5. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(963) | Removing sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sdif3_spll_lock_q1 because it is equivalent to instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sdif0_spll_lock_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(963) | Removing sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sdif3_spll_lock_q2 because it is equivalent to instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sdif0_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : reset_sync.v(134) | Removing sequential instance CoreJESD204BRX_0.RESET_SYNC.genblk1.genblk1[0].epcs_rxclk_rst_n_sync_f1[0] because it is equivalent to instance CoreJESD204BRX_0.RESET_SYNC.genblk1.laneclk_rst_n_sync_f1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : reset_sync.v(133) | Removing sequential instance CoreJESD204BTX_0.RESET_SYNC.genblk1.genblk1[0].epcs_txclk_rst_n_sync_f1[0] because it is equivalent to instance CoreJESD204BTX_0.RESET_SYNC.genblk1.laneclk_rst_n_sync_f1. To keep the instance, apply constraint syn_preserve=1 on the instance. Available hyper_sources - for debug and ip models None Found @W:BN132 : rx_ctrl.v(149) | Removing sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_RX_CTRL.lmfc_cnt_reg[15:0] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_RX_CTRL.fc_cnt_reg[15:0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : rx_ctrl.v(149) | Removing sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_RX_CTRL.mf_phase_st_reg[3:0] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_RX_CTRL.f_phase_st_reg[3:0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance fc_cnt_reg[15:0] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : sync_dec.v(100) | Removing sequential instance genblk1\.sync_state (in view: work.CJESDTX_SYNC_DEC_2s_0s_16s_2s_0s_6s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 180MB peak: 180MB) @N:MF135 : data_sync_buf.v(220) | RAM UBUF0\.DATA_SYNC_BUF_0.data_buf[19:0] (in view: work.CoreJESD204BRX_Z9(verilog)) is 4 words by 20 bits. Encoding state machine SYNC_GEN_ST[2:0] (in view: work.CJESDRX_SYNC_ENC_2s_0s_0s_2s_9s_54s_0s_0_1_2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @W:MO129 : sync_enc.v(95) | Sequential instance CoreJESD204BRX_0.SYNC_ENC_0.SYNC_GEN_ST[0] is reduced to a combinational gate by constant propagation. @N:MO231 : sync_enc.v(95) | Found counter in view:work.CJESDRX_SYNC_ENC_2s_0s_0s_2s_9s_54s_0s_0_1_2(verilog) instance sync_cnt[5:0] Encoding state machine CG_state[2:0] (in view: work.CJESDRX_CGS_0s_0_1_2_16s_2s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:MF135 : eb_ram_rtl.v(69) | RAM CJESDRX_ADJ_BUF.CJESDRX_RAM_EB.EB_RAM[17:0] (in view: work.CJESDRX_LABDM_Z4(verilog)) is 64 words by 18 bits. @W:BN132 : adj_buf.v(89) | Removing sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.ram_data[0] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.DATA_IN_reg_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : adj_buf.v(89) | Removing sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.ram_data[1] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.DATA_IN_reg_1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : adj_buf.v(89) | Removing sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.ram_data[2] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.DATA_IN_reg_1[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : adj_buf.v(89) | Removing sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.ram_data[3] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.DATA_IN_reg_1[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : adj_buf.v(89) | Removing sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.ram_data[4] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.DATA_IN_reg_1[4]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : adj_buf.v(89) | Removing sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.ram_data[5] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.DATA_IN_reg_1[5]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : adj_buf.v(89) | Removing sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.ram_data[6] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.DATA_IN_reg_1[6]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : adj_buf.v(89) | Removing sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.ram_data[7] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.DATA_IN_reg_1[7]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : adj_buf.v(89) | Removing sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.ram_data[8] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.DATA_IN_reg_1[8]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : adj_buf.v(89) | Removing sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.ram_data[9] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.DATA_IN_reg_1[9]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : adj_buf.v(89) | Removing sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.ram_data[10] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.DATA_IN_reg_1[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : adj_buf.v(89) | Removing sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.ram_data[11] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.DATA_IN_reg_1[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : adj_buf.v(89) | Removing sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.ram_data[12] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.DATA_IN_reg_1[12]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : adj_buf.v(89) | Removing sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.ram_data[13] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.DATA_IN_reg_1[13]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : adj_buf.v(89) | Removing sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.ram_data[14] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.DATA_IN_reg_1[14]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : adj_buf.v(89) | Removing sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.ram_data[15] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.DATA_IN_reg_1[15]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : adj_buf.v(89) | Removing sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.ram_data[16] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.K_IN_reg_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : adj_buf.v(89) | Removing sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.ram_data[17] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.K_IN_reg_1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. Encoding state machine RIstate[2:0] (in view: work.CJESDRX_ILA_FSM_Z3(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine ILA_state[4:0] (in view: work.CJESDRX_ILA_FSM_Z3(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 @N:MO231 : ila_fsm.v(306) | Found counter in view:work.CJESDRX_ILA_FSM_Z3(verilog) instance R_cnt[6:0] Encoding state machine CD_M_state[6:0] (in view: work.CJESDRX_LINK_COMP_Z5(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 @N:MF179 : link_comp.v(488) | Found 16 by 16 bit equality operator ('==') genblk6\.COMP_ERR33 (in view: work.CJESDRX_LINK_COMP_Z5(verilog)) @N:MO231 : eb_ctrl.v(125) | Found counter in view:work.CJESDRX_EB_CTRL_0s_2s_9s_18s_54s_0_1_16s_2s(verilog) instance WADDR[5:0] Encoding state machine SYNC_STATE[4:0] (in view: work.CJESDRX_SYNC_FSM_0s_0_1_2_3_4_4(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 Encoding state machine FS_STATE_1[3:0] (in view: work.CJESDRX_IFS_POS_Z6(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : ifs_pos.v(198) | There are no possible illegal states for state machine FS_STATE_1[3:0] (in view: work.CJESDRX_IFS_POS_Z6(verilog)); safe FSM implementation is not required. Encoding state machine CC_state[1:0] (in view: work.CJESDRX_IFS_POS_Z6(verilog)) original code -> new code 00 -> 0 01 -> 1 @N:MO225 : ifs_pos.v(295) | There are no possible illegal states for state machine CC_state[1:0] (in view: work.CJESDRX_IFS_POS_Z6(verilog)); safe FSM implementation is not required. @W:BN132 : ifs_pos.v(295) | Removing instance CoreJESD204BRX_0.LANE_0.CJESDRX_FADM_OR.CJESDRX_IFS_POS.CC because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_FADM_OR.CJESDRX_IFS_POS.CC_state[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MF135 : data_sync_buf_tx.v(371) | RAM DATA_SYNC_BUF_0.data_buf[19:0] (in view: work.CoreJESD204BTX_Z12(verilog)) is 4 words by 20 bits. @N:MF135 : data_sync_buf_tx.v(371) | RAM DATA_SYNC_BUF_0.data_buf[19:0] (in view: work.CoreJESD204BTX_Z12(verilog)) is 4 words by 20 bits. @N:BN362 : tx_acg.v(2137) | Removing sequential instance CJESDTX_TX_ACG.genblk6\.OCount_L_0[1] (in view: work.CJESDTX_JESD204BTX_LANE_Z11(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_7[6] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_7[5] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_7[4] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_7[3] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO161 : tx_ila.v(300) | Register bit ILAValue_7[2] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO161 : tx_ila.v(300) | Register bit ILAValue_7[1] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO161 : tx_ila.v(300) | Register bit ILAValue_7[0] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_6[6] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_6[5] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_6[4] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_6[3] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO161 : tx_ila.v(300) | Register bit ILAValue_6[2] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO161 : tx_ila.v(300) | Register bit ILAValue_6[1] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_6[0] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_5[6] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_5[5] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_5[4] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_5[3] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO161 : tx_ila.v(300) | Register bit ILAValue_5[2] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_5[1] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO161 : tx_ila.v(300) | Register bit ILAValue_5[0] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_4[6] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_4[5] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_4[4] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_4[3] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO161 : tx_ila.v(300) | Register bit ILAValue_4[2] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_4[1] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_4[0] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_3[6] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_3[5] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_3[4] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_3[3] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_3[2] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO161 : tx_ila.v(300) | Register bit ILAValue_3[1] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO161 : tx_ila.v(300) | Register bit ILAValue_3[0] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_2[6] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_2[5] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_2[4] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_2[3] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_2[2] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO161 : tx_ila.v(300) | Register bit ILAValue_2[1] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_2[0] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine TX_STATE_1[2:0] (in view: work.CJESDTX_TX_CTRL_2s_0s_0_1_2_0s_16s_20s_2s_0(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @W:MO160 : wav_gen_16bit.v(135) | Register bit SQR_DATA16[10] (in view view:work.waveform_gen(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO161 : wav_gen_16bit.v(135) | Register bit SQR_DATA16[9] (in view view:work.waveform_gen(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : wav_gen_16bit.v(135) | Register bit SQR_DATA16[4] (in view view:work.waveform_gen(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : wav_gen_16bit.v(135) | Register bit SQR_DATA16[2] (in view view:work.waveform_gen(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : wav_gen_16bit.v(135) | Register bit SQR_DATA16[1] (in view view:work.waveform_gen(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : wav_gen_16bit.v(135) | Register bit SQR_DATA16[0] (in view view:work.waveform_gen(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:BN132 : wav_gen_16bit.v(163) | Removing instance DATA_GENERATOR_0.waveform_gen_0.SAW_DATA16[1] because it is equivalent to instance DATA_GENERATOR_0.waveform_gen_0.SAW_DATA16[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : wav_gen_16bit.v(135) | Removing instance DATA_GENERATOR_0.waveform_gen_0.SQR_DATA16[6] because it is equivalent to instance DATA_GENERATOR_0.waveform_gen_0.SQR_DATA16[15]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : wav_gen_16bit.v(135) | Removing instance DATA_GENERATOR_0.waveform_gen_0.SQR_DATA16[15] because it is equivalent to instance DATA_GENERATOR_0.waveform_gen_0.SQR_DATA16[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : wav_gen_16bit.v(135) | Removing instance DATA_GENERATOR_0.waveform_gen_0.SQR_DATA16[5] because it is equivalent to instance DATA_GENERATOR_0.waveform_gen_0.SQR_DATA16[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : wav_gen_16bit.v(135) | Removing instance DATA_GENERATOR_0.waveform_gen_0.SQR_DATA16[14] because it is equivalent to instance DATA_GENERATOR_0.waveform_gen_0.SQR_DATA16[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : wav_gen_16bit.v(135) | Removing instance DATA_GENERATOR_0.waveform_gen_0.SQR_DATA16[13] because it is equivalent to instance DATA_GENERATOR_0.waveform_gen_0.SQR_DATA16[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : wav_gen_16bit.v(135) | Removing instance DATA_GENERATOR_0.waveform_gen_0.SQR_DATA16[8] because it is equivalent to instance DATA_GENERATOR_0.waveform_gen_0.SQR_DATA16[7]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : wav_gen_16bit.v(135) | Removing instance DATA_GENERATOR_0.waveform_gen_0.SQR_DATA16[7] because it is equivalent to instance DATA_GENERATOR_0.waveform_gen_0.SQR_DATA16[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : wav_gen_16bit.v(135) | Removing instance DATA_GENERATOR_0.waveform_gen_0.SQR_DATA16[12] because it is equivalent to instance DATA_GENERATOR_0.waveform_gen_0.SQR_DATA16[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. Encoding state machine fsm[3:0] (in view: work.DATAHANDLE_FSM(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : data_handle_fsm.v(199) | There are no possible illegal states for state machine fsm[3:0] (in view: work.DATAHANDLE_FSM(verilog)); safe FSM implementation is not required. @N:MO231 : data_handle_fsm.v(134) | Found counter in view:work.DATAHANDLE_FSM(verilog) instance DATA_WADDR1[10:0] Encoding state machine CORECONFIGP_0.state[2:0] (in view: work.SF2_JESD204B_DEMO_sb(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @W:MO160 : coreconfigp.v(255) | Register bit CORECONFIGP_0.paddr[16] (in view view:work.SF2_JESD204B_DEMO_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z15(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sdif0_state[3:0] (in view: work.CoreResetP_Z15(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : coreresetp.v(1170) | There are no possible illegal states for state machine sdif0_state[3:0] (in view: work.CoreResetP_Z15(verilog)); safe FSM implementation is not required. @N:MO231 : coreresetp.v(1485) | Found counter in view:work.CoreResetP_Z15(verilog) instance count_sdif0[12:0] @W:BN132 : coreresetp.v(1089) | Removing instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF_READY_int because it is equivalent to instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sm0_state[6]. To keep the instance, apply constraint syn_preserve=1 on the instance. Starting factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 188MB peak: 189MB) @W:BN132 : sync_fsm.v(50) | Removing instance CoreJESD204BRX_0.LANE_0.genblk3.CJESDRX_DEC_WA.genblk5.CJESDRX_DECODER_L_0.USYNC.COMMA_FOUND because it is equivalent to instance CoreJESD204BRX_0.LANE_0.genblk3.CJESDRX_DEC_WA.CJESDRX_DECODER_U_0.USYNC.COMMA_FOUND. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : link_comp.v(165) | Removing instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.genblk1.CJESDRX_LINK_COMP.genblk2.DATA_IN_reg[0] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_FADM_OR.DATA_IN_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : link_comp.v(165) | Removing instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.genblk1.CJESDRX_LINK_COMP.genblk2.DATA_IN_reg[1] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_FADM_OR.DATA_IN_reg[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : link_comp.v(165) | Removing instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.genblk1.CJESDRX_LINK_COMP.genblk2.DATA_IN_reg[2] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_FADM_OR.DATA_IN_reg[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : link_comp.v(165) | Removing instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.genblk1.CJESDRX_LINK_COMP.genblk2.DATA_IN_reg[3] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_FADM_OR.DATA_IN_reg[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : link_comp.v(165) | Removing instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.genblk1.CJESDRX_LINK_COMP.genblk2.DATA_IN_reg[4] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_FADM_OR.DATA_IN_reg[4]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : link_comp.v(165) | Removing instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.genblk1.CJESDRX_LINK_COMP.genblk2.DATA_IN_reg[5] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_FADM_OR.DATA_IN_reg[5]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : link_comp.v(165) | Removing instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.genblk1.CJESDRX_LINK_COMP.genblk2.DATA_IN_reg[6] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_FADM_OR.DATA_IN_reg[6]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : link_comp.v(165) | Removing instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.genblk1.CJESDRX_LINK_COMP.genblk2.DATA_IN_reg[7] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_FADM_OR.DATA_IN_reg[7]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : link_comp.v(165) | Removing instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.genblk1.CJESDRX_LINK_COMP.genblk2.DATA_IN_reg[8] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_FADM_OR.DATA_IN_reg[8]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : link_comp.v(165) | Removing instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.genblk1.CJESDRX_LINK_COMP.genblk2.DATA_IN_reg[9] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_FADM_OR.DATA_IN_reg[9]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : link_comp.v(165) | Removing instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.genblk1.CJESDRX_LINK_COMP.genblk2.DATA_IN_reg[10] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_FADM_OR.DATA_IN_reg[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : link_comp.v(165) | Removing instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.genblk1.CJESDRX_LINK_COMP.genblk2.DATA_IN_reg[11] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_FADM_OR.DATA_IN_reg[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : link_comp.v(165) | Removing instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.genblk1.CJESDRX_LINK_COMP.genblk2.DATA_IN_reg[12] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_FADM_OR.DATA_IN_reg[12]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : link_comp.v(165) | Removing instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.genblk1.CJESDRX_LINK_COMP.genblk2.DATA_IN_reg[13] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_FADM_OR.DATA_IN_reg[13]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : link_comp.v(165) | Removing instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.genblk1.CJESDRX_LINK_COMP.genblk2.DATA_IN_reg[14] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_FADM_OR.DATA_IN_reg[14]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : link_comp.v(165) | Removing instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.genblk1.CJESDRX_LINK_COMP.genblk2.DATA_IN_reg[15] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_FADM_OR.DATA_IN_reg[15]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : link_comp.v(165) | Removing instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.genblk1.CJESDRX_LINK_COMP.genblk2.K_IN_reg[0] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_FADM_OR.VALID_IN_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : link_comp.v(165) | Removing instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.genblk1.CJESDRX_LINK_COMP.genblk2.K_IN_reg[1] because it is equivalent to instance CoreJESD204BRX_0.LANE_0.CJESDRX_FADM_OR.VALID_IN_reg[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:BN362 : adj_ctrl.v(112) | Removing sequential instance CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.mf_phase_st_reg[0] (in view: work.CJESDRX_JESD204BRX_LANE_Z7(verilog)) because it does not drive other instances. @N:BN362 : adj_ctrl.v(112) | Removing sequential instance CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.mf_phase_st_reg[1] (in view: work.CJESDRX_JESD204BRX_LANE_Z7(verilog)) because it does not drive other instances. @N:BN362 : adj_ctrl.v(112) | Removing sequential instance CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.mf_phase_st_reg[2] (in view: work.CJESDRX_JESD204BRX_LANE_Z7(verilog)) because it does not drive other instances. @N:BN362 : adj_ctrl.v(112) | Removing sequential instance CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.mf_phase_st_reg[3] (in view: work.CJESDRX_JESD204BRX_LANE_Z7(verilog)) because it does not drive other instances. @W:BN132 : reset_sync.v(196) | Removing instance CoreJESD204BRX_0.RESET_SYNC.genblk1.laneclk_rst_n_sync_f1 because it is equivalent to instance DATAHANDLE_FSM_0.STATUS_OUT_REG_1[20]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : enc_k.v(117) | Removing instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.genblk1.ENCODER_N_0.UK.K_DLY because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.BUF_DATA_0.kout[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : enc_k.v(117) | Removing instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.genblk1.ENCODER_L_0.UK.X_DLY[0] because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.genblk1.ENCODER_L_0.UD.URN.SEL_R1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : enc_k.v(117) | Removing instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.genblk1.ENCODER_L_0.UK.X_DLY[1] because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.genblk1.ENCODER_L_0.UD.URN.SEL_R1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : enc_k.v(117) | Removing instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.genblk1.ENCODER_L_0.UK.Y_DLY[1] because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.genblk1.ENCODER_L_0.UD.Y[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : enc_k.v(117) | Removing instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UK.X_DLY[0] because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.SEL_R1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : enc_k.v(117) | Removing instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UK.X_DLY[1] because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.SEL_R1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : enc_k.v(117) | Removing instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UK.Y_DLY[1] because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.Y[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:BN362 : coreresetp.v(1170) | Removing sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF0_PHY_RESET_N_int (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : wav_gen_16bit.v(163) | Removing sequential instance DATA_GENERATOR_0.waveform_gen_0.SAW_DATA16[0] (in view: work.top(verilog)) because it does not drive other instances. Finished factoring (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 213MB peak: 213MB) @N:BN362 : wav_gen_16bit.v(27) | Removing sequential instance DATA_GENERATOR_0.waveform_gen_0.DATA_OUT[0] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : wav_gen_16bit.v(27) | Removing sequential instance DATA_GENERATOR_0.waveform_gen_0.DATA_OUT[1] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : wav_gen_16bit.v(183) | Removing sequential instance DATA_GENERATOR_0.waveform_gen_0.TRI_DATA16[0] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : wav_gen_16bit.v(183) | Removing sequential instance DATA_GENERATOR_0.waveform_gen_0.TRI_DATA16[1] (in view: work.top(verilog)) because it does not drive other instances. @W:FX739 : top.v(340) | Removed BUFG instance CLKINT_0 because it is cascaded to another clock buffer (SF2_JESD204B_DEMO_sb_0.CCC_0.GL0_INST). Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 212MB peak: 219MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 213MB peak: 219MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 213MB peak: 219MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 213MB peak: 219MB) @N:MO106 : dec_data.v(78) | Found ROM CoreJESD204BRX_0.LANE_0.genblk3\.CJESDRX_DEC_WA.genblk5\.CJESDRX_DECODER_L_0.UB.DATA_5B_0[4:0] (in view: work.top(verilog)) with 48 words by 5 bits. @N:MO106 : dec_data.v(78) | Found ROM CoreJESD204BRX_0.LANE_0.genblk3\.CJESDRX_DEC_WA.CJESDRX_DECODER_U_0.UB.DATA_5B_0[4:0] (in view: work.top(verilog)) with 48 words by 5 bits. Finished preparing to map (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 214MB peak: 219MB) Finished technology mapping (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 247MB peak: 247MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:11s -2.08ns 3551 / 2857 2 0h:00m:11s -2.08ns 3237 / 2857 3 0h:00m:11s -2.08ns 3237 / 2857 @N:FX271 : rx_ctrl.v(136) | Replicating instance CoreJESD204BRX_0.LANE_0.CJESDRX_RX_CTRL.SYNC_REQUEST (in view: work.top(verilog)) with 9 loads 1 time to improve timing. @N:FX271 : eb_ctrl.v(280) | Replicating instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.SC[1] (in view: work.top(verilog)) with 9 loads 1 time to improve timing. @N:FX271 : eb_ctrl.v(280) | Replicating instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.SC[2] (in view: work.top(verilog)) with 9 loads 1 time to improve timing. @N:FX271 : eb_ctrl.v(280) | Replicating instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.SC[3] (in view: work.top(verilog)) with 9 loads 1 time to improve timing. @N:FX271 : ila_fsm.v(505) | Replicating instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ILA_FSM.RE_INIT (in view: work.top(verilog)) with 5 loads 1 time to improve timing. Timing driven replication report Added 5 Registers via timing driven replication Added 2 LUTs via timing driven replication 4 0h:00m:12s -1.84ns 3240 / 2862 5 0h:00m:12s -1.64ns 3245 / 2862 6 0h:00m:12s -1.64ns 3247 / 2862 7 0h:00m:12s -1.64ns 3249 / 2862 8 0h:00m:13s -1.64ns 3247 / 2862 9 0h:00m:13s -1.16ns 3247 / 2862 10 0h:00m:13s -1.08ns 3247 / 2862 @N:FP130 : | Promoting Net SERDES_EPCS_0_EPCS_2_RX_CLK on CLKINT I_1067 @N:FP130 : | Promoting Net CoreJESD204BRX_0.genblk1\.lane_syncd_rst_n_arst on CLKINT I_1068 @N:FP130 : | Promoting Net SERDES_EPCS_0_EPCS_2_TX_CLK_0 on CLKINT I_1069 @N:FP130 : | Promoting Net CoreJESD204BTX_0.genblk1\.lane_syncd_rst_n_arst on CLKINT I_1070 @N:FP130 : | Promoting Net EPCS_2_RX_RESET_N_arst on CLKINT I_1071 @N:FP130 : | Promoting Net SF2_JESD204B_DEMO_sb_0.FIC_2_APB_M_PRESET_N_arst on CLKINT I_1072 @N:FP130 : | Promoting Net SF2_JESD204B_DEMO_sb_0_INIT_APB_S_PCLK on CLKINT I_1073 @N:FP130 : | Promoting Net EPCS_2_TX_RESET_N_arst on CLKINT I_1074 @N:FP130 : | Promoting Net CoreJESD204BRX_0.genblk1\.genblk1\[0\]\.epcs_rxclk_rxvalid_sync_f2_arst0 on CLKINT I_1075 @N:FP130 : | Promoting Net CoreJESD204BTX_0.RESET_SYNC.genblk1\.genblk1\[0\]\.epcs_txclk_txstbl_sync_f2[0] on CLKINT I_1076 @N:FP130 : | Promoting Net SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT I_1077 @N:FP130 : | Promoting Net SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sdif0_areset_n_rcosc on CLKINT I_1078 @N:FP130 : | Promoting Net SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sm0_areset_n_arst on CLKINT I_1079 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 251MB peak: 251MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 251MB peak: 252MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 4 non-gated/non-generated clock tree(s) driving 2799 clock pin(s) of sequential element(s) 1 gated/generated clock tree(s) driving 93 clock pin(s) of sequential element(s) 0 instances converted, 93 sequential instances remain driven by gated/generated clocks =============================================================================== Non-Gated/Non-Generated Clocks =============================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0002 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST clock definition on SERDESIF_075 2065 SERDES_EPCS_0.epcs_rx_intf_0.rxvalo ClockId0003 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST clock definition on SERDESIF_075 595 SERDES_EPCS_0.epcs_tx_intf_0.txdin_p[7] ClockId0004 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST clock definition on MSS_075 109 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.SDIF_RELEASED_q2 ClockId0005 SF2_JESD204B_DEMO_sb_0.FABOSC_0.I_RCOSC_25_50MHZ clock definition on RCOSC_25_50MHZ 30 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[12] ============================================================================================================================================================================================== =================================================================================================== Gated/Generated Clocks =================================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ClockId0001 SF2_JESD204B_DEMO_sb_0.CCC_0.CCC_INST CCC 93 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_075 ============================================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 199MB peak: 252MB) Writing Analyst data base C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\synthesis\synwork\top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 239MB peak: 252MB) Writing EDIF Netlist and constraint files @N:FX1056 : | Writing EDF file: C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\synthesis\top.edn @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Writing FDC file C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\synthesis\top_synplify.fdc Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 241MB peak: 252MB) Start final timing analysis (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 235MB peak: 252MB) @W:MT246 : sf2_jesd204b_demo_sb_ccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N:MT615 : | Found clock SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] with period 10.00ns @N:MT615 : | Found clock SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] with period 10.00ns @N:MT615 : | Found clock SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT with period 20.00ns @N:MT615 : | Found clock SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB with period 40.00ns @N:MT615 : | Found clock SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 with period 10.00ns ##### START OF TIMING REPORT #####[ # Timing report written on Sun Mar 28 21:10:57 2021 # Top view: top Requested Frequency: 25.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\designer\top\synthesis.fdc @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: 0.769 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] 100.0 MHz 116.2 MHz 10.000 8.608 1.392 declared default_clkgroup SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] 100.0 MHz 133.6 MHz 10.000 7.487 2.514 declared default_clkgroup SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 100.0 MHz 108.3 MHz 10.000 9.230 0.769 generated (from SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT) default_clkgroup SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 437.2 MHz 20.000 2.287 17.713 declared default_clkgroup SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB 25.0 MHz 91.7 MHz 40.000 10.904 14.548 declared default_clkgroup ===================================================================================================================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] | 10.000 1.392 | No paths - | No paths - | 5.000 4.409 SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] | 10.000 8.188 | No paths - | No paths - | No paths - SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 | 10.000 6.677 | No paths - | No paths - | No paths - SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] | 10.000 2.514 | No paths - | No paths - | No paths - SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 20.000 17.713 | No paths - | No paths - | No paths - SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 | 10.000 False | No paths - | No paths - | No paths - SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB | 40.000 32.768 | No paths - | 20.000 17.962 | 20.000 14.548 SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 | 10.000 False | No paths - | No paths - | No paths - SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] | 10.000 4.857 | No paths - | No paths - | No paths - SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] | 10.000 2.689 | No paths - | No paths - | No paths - SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 10.000 False | No paths - | No paths - | No paths - SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB | 10.000 False | No paths - | No paths - | No paths - SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 | 10.000 0.770 | No paths - | 5.000 3.912 | 5.000 3.061 ============================================================================================================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreJESD204BRX_0.LANE_0.CJESDRX_RX_CTRL.SYNC_REQUEST_fast SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] SLE Q SYNC_REQUEST_fast 0.087 1.392 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.SC[4] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] SLE Q SC[4] 0.087 1.483 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.SC[5] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] SLE Q SC[5] 0.087 1.522 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ILA_FSM.ILA_state[2] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] SLE Q ILA_state[2] 0.108 1.603 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.SC_fast[1] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] SLE Q SC_fast[1] 0.087 1.633 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ILA_FSM.RE_INIT_fast SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] SLE Q RE_INIT_fast 0.087 1.703 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.SC_fast[2] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] SLE Q SC_fast[2] 0.087 1.715 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ILA_FSM.ILA_state[1] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] SLE Q ILA_state[1] 0.108 1.717 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.SC_fast[3] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] SLE Q SC_fast[3] 0.087 1.758 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[1] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] SLE Q eb2ram_raddr[1] 0.108 1.770 ======================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[5] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] SLE D RADDR_RNO_S[5] 9.745 1.392 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[2] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] SLE D un1_RADDR_3_iv_RNIE9MQI_S[2] 9.745 1.423 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[4] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] SLE D un1_RADDR_3_iv_RNI43VP93_S[4] 9.745 1.423 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[3] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] SLE D un1_RADDR_3_iv_RNIRR0RB1_S[3] 9.745 1.457 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[1] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] SLE D un1_RADDR_3_iv_RNI6H797_S[1] 9.745 1.707 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[0] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] SLE D un1_RADDR_3_iv_RNISQ8C1_S[0] 9.745 1.856 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.WADDR[0] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] SLE EN WADDRe 9.662 2.956 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.WADDR[1] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] SLE EN WADDRe 9.662 2.956 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.WADDR[2] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] SLE EN WADDRe 9.662 2.956 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.WADDR[3] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] SLE EN WADDRe 9.662 2.956 =================================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.745 - Propagation time: 8.353 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 1.392 Number of logic level(s): 15 Starting point: CoreJESD204BRX_0.LANE_0.CJESDRX_RX_CTRL.SYNC_REQUEST_fast / Q Ending point: CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[5] / D The start point is clocked by SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK The end point is clocked by SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreJESD204BRX_0.LANE_0.CJESDRX_RX_CTRL.SYNC_REQUEST_fast SLE Q Out 0.087 0.087 r - SYNC_REQUEST_fast Net - - 0.896 - 6 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ILA_FSM.RE_INIT_fast_RNIOAGF CFG2 A In - 0.983 r - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ILA_FSM.RE_INIT_fast_RNIOAGF CFG2 Y Out 0.077 1.060 r - N_3_0_i Net - - 0.896 - 6 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ILA_FSM.ILA_state_RNI057P_0[4] CFG2 A In - 1.956 r - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ILA_FSM.ILA_state_RNI057P_0[4] CFG2 Y Out 0.100 2.056 f - ILA_state_RNI057P_0[4] Net - - 0.248 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ILA_FSM.ILA_state_RNI7M1S2[3] CFG4 B In - 2.305 f - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ILA_FSM.ILA_state_RNI7M1S2[3] CFG4 Y Out 0.148 2.453 r - N_131_mux Net - - 1.233 - 26 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR_0_sqmuxa_4_0_RNIFSVC3 CFG4 D In - 3.686 r - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR_0_sqmuxa_4_0_RNIFSVC3 CFG4 Y Out 0.326 4.013 f - RADDR_0_sqmuxa_8 Net - - 1.017 - 9 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR_0_sqmuxa_13 CFG2 A In - 5.030 f - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR_0_sqmuxa_13 CFG2 Y Out 0.087 5.117 f - RADDR_0_sqmuxa_13 Net - - 1.102 - 11 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_1_iv_0_0[1] CFG4 D In - 6.219 f - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_1_iv_0_0[1] CFG4 Y Out 0.288 6.507 f - un13_1_iv_0_0[1] Net - - 0.248 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_1_iv_0[1] CFG4 B In - 6.755 f - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_1_iv_0[1] CFG4 Y Out 0.164 6.919 f - un13_1_iv_0[1] Net - - 0.497 - 2 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_3_iv_RNISMB19[1] ARI1 B In - 7.416 f - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_3_iv_RNISMB19[1] ARI1 Y Out 0.164 7.580 f - un1_RADDR_3_iv_RNISMB19_Y[1] Net - - 0.248 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_3_iv_RNIE9MQI[2] ARI1 A In - 7.829 f - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_3_iv_RNIE9MQI[2] ARI1 FCO Out 0.121 7.950 f - un1_RADDR_3_iv_RNIE9MQI_FCO[2] Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_3_iv_RNI45LIJ[2] ARI1 FCI In - 7.950 f - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_3_iv_RNI45LIJ[2] ARI1 FCO Out 0.016 7.966 f - un1_RADDR_3_iv_RNI45LIJ_FCO[2] Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_3_iv_RNIRR0RB1[3] ARI1 FCI In - 7.966 f - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_3_iv_RNIRR0RB1[3] ARI1 FCO Out 0.016 7.982 f - un1_RADDR_3_iv_RNIRR0RB1_FCO[3] Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_3_iv_RNIEDNGG1[3] ARI1 FCI In - 7.982 f - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_3_iv_RNIEDNGG1[3] ARI1 FCO Out 0.016 7.999 f - un1_RADDR_3_iv_RNIEDNGG1_FCO[3] Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_3_iv_RNI43VP93[4] ARI1 FCI In - 7.999 f - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_3_iv_RNI43VP93[4] ARI1 FCO Out 0.016 8.015 f - un1_RADDR_3_iv_RNI43VP93_FCO[4] Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_3_iv_RNICBFII3[4] ARI1 FCI In - 8.015 f - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_3_iv_RNICBFII3[4] ARI1 FCO Out 0.016 8.031 f - un1_RADDR_3_iv_RNICBFII3_FCO[4] Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR_RNO[5] ARI1 FCI In - 8.031 f - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR_RNO[5] ARI1 S Out 0.073 8.104 r - RADDR_RNO_S[5] Net - - 0.248 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[5] SLE D In - 8.353 r - ================================================================================================================================================================ Total path delay (propagation time + setup) of 8.608 is 1.974(22.9%) logic and 6.634(77.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreJESD204BTX_0.LANE_0.CJESDTX_TX_CTRL_0.SEND_LANE_SEQ SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] SLE Q SEND_LANE_SEQ 0.087 2.514 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_CTRL_0.TX_STATE_1[1] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] SLE Q TX_STATE[1] 0.087 2.753 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.ILAValue_0[2] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] SLE Q ILAValue_0[2] 0.108 2.813 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_CTRL_0.TX_STATE_1[0] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] SLE Q TX_STATE[0] 0.108 2.820 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.ILAValue_0[3] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] SLE Q ILAValue_0[3] 0.108 2.821 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.ILAValue_0[1] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] SLE Q ILAValue_0[1] 0.087 2.981 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.ILAValue_0[4] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] SLE Q ILAValue_0[4] 0.108 3.061 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.ILAValue_0[5] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] SLE Q ILAValue_0[5] 0.108 3.075 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.ILAValue_0[6] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] SLE Q ILAValue_0[6] 0.087 3.167 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ACG.genblk6\.FCount_U[2] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] SLE Q FCount_U[2] 0.108 3.428 =============================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.genblk4\.DATA_ILA[6] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] SLE D DATA_ILA_28[6] 9.745 2.514 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.genblk4\.DATA_ILA[10] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] SLE D DATA_ILA_28[10] 9.745 2.514 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.genblk4\.DATA_ILA[2] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] SLE D DATA_ILA_28[2] 9.745 2.867 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.genblk4\.DATA_ILA[3] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] SLE D DATA_ILA_28[3] 9.745 2.867 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.genblk4\.DATA_ILA[12] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] SLE D DATA_ILA_28[12] 9.745 2.904 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.genblk4\.DATA_ILA[5] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] SLE D DATA_ILA_28[5] 9.745 2.942 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.genblk4\.DATA_ILA[13] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] SLE D DATA_ILA_28[13] 9.745 2.965 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.genblk4\.DATA_ILA[0] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] SLE D DATA_ILA_28[0] 9.745 3.033 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.genblk4\.DATA_ILA[7] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] SLE D DATA_ILA_28[7] 9.745 3.033 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.genblk4\.DATA_ILA[9] SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] SLE D DATA_ILA_28[9] 9.745 3.033 =================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.745 - Propagation time: 7.231 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 2.513 Number of logic level(s): 6 Starting point: CoreJESD204BTX_0.LANE_0.CJESDTX_TX_CTRL_0.SEND_LANE_SEQ / Q Ending point: CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.genblk4\.DATA_ILA[6] / D The start point is clocked by SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK The end point is clocked by SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------- CoreJESD204BTX_0.LANE_0.CJESDTX_TX_CTRL_0.SEND_LANE_SEQ SLE Q Out 0.087 0.087 r - SEND_LANE_SEQ Net - - 1.411 - 56 CoreJESD204BTX_0.LANE_0.tc2ta_m_en CFG3 B In - 1.498 r - CoreJESD204BTX_0.LANE_0.tc2ta_m_en CFG3 Y Out 0.143 1.642 f - SOF[1] Net - - 0.896 - 7 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.genblk4\.un27 CFG4 D In - 2.537 f - CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.genblk4\.un27 CFG4 Y Out 0.317 2.855 r - DATA_m2_e_1 Net - - 0.855 - 5 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.DATA_ILA_10_sqmuxa CFG4 D In - 3.710 r - CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.DATA_ILA_10_sqmuxa CFG4 Y Out 0.326 4.036 f - DATA_ILA_10_sqmuxa Net - - 1.058 - 10 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.DATA_ILA_10_sqmuxa_RNIVFUH5 CFG4 B In - 5.094 f - CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.DATA_ILA_10_sqmuxa_RNIVFUH5 CFG4 Y Out 0.148 5.242 r - un1_N_3_mux Net - - 1.017 - 9 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.DATA_ILA_28_1_iv_RNO[6] CFG4 C In - 6.260 r - CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.DATA_ILA_28_1_iv_RNO[6] CFG4 Y Out 0.203 6.463 r - DATA_ILA_cnst_m[1] Net - - 0.248 - 1 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.DATA_ILA_28_1_iv[6] CFG4 D In - 6.711 r - CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.DATA_ILA_28_1_iv[6] CFG4 Y Out 0.271 6.983 r - DATA_ILA_28[6] Net - - 0.248 - 1 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.genblk4\.DATA_ILA[6] SLE D In - 7.231 r - ================================================================================================================================= Total path delay (propagation time + setup) of 7.487 is 1.753(23.4%) logic and 5.734(76.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[12] DATAHANDLE_FSM_0_DATA_RADDR[10] 3.583 0.769 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[15] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PADDR[15] 3.594 1.443 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 MSS_075 F_HM0_SEL SF2_JESD204B_DEMO_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx 3.626 1.467 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[13] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PADDR[13] 3.548 1.947 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[14] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PADDR[14] 3.542 1.996 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 MSS_075 I2C1_SDA_MGPIO0A_H2F_B SF2_JESD204B_DEMO_sb_0_GPIO_0_M2F 3.774 2.185 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 MSS_075 CAN_RXBUS_MGPIO3A_H2F_B SF2_JESD204B_DEMO_sb_0_GPIO_3_M2F 3.373 2.689 DATAHANDLE_FSM_0.DATA_WADDR[0] SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 SLE Q DATAHANDLE_FSM_0_DATA_WADDR[0] 0.108 3.061 DATAHANDLE_FSM_0.DATA_WADDR[1] SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 SLE Q DATAHANDLE_FSM_0_DATA_WADDR[1] 0.108 3.061 DATAHANDLE_FSM_0.DATA_WADDR[2] SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 SLE Q DATAHANDLE_FSM_0_DATA_WADDR[2] 0.108 3.061 ============================================================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 MSS_075 F_HM0_RDATA[2] AMBA_SLAVE_0_PRDATAS0_m[2] 8.591 0.769 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 MSS_075 F_HM0_RDATA[22] AMBA_SLAVE_0_PRDATAS0_m[22] 8.523 0.780 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 MSS_075 F_HM0_RDATA[18] AMBA_SLAVE_0_PRDATAS0_m[18] 8.609 0.911 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 MSS_075 F_HM0_RDATA[13] AMBA_SLAVE_0_PRDATAS0_m[13] 8.815 0.994 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 MSS_075 F_HM0_RDATA[30] AMBA_SLAVE_0_PRDATAS0_m[30] 8.750 1.007 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 MSS_075 F_HM0_RDATA[29] AMBA_SLAVE_0_PRDATAS0_m[29] 8.754 1.011 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 MSS_075 F_HM0_RDATA[15] AMBA_SLAVE_0_PRDATAS0_m[15] 8.834 1.012 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 MSS_075 F_HM0_RDATA[26] AMBA_SLAVE_0_PRDATAS0_m[26] 8.762 1.019 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 MSS_075 F_HM0_RDATA[17] AMBA_SLAVE_0_PRDATAS0_m[17] 8.723 1.025 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 MSS_075 F_HM0_RDATA[21] AMBA_SLAVE_0_PRDATAS0_m[21] 8.780 1.037 ============================================================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 1.409 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.591 - Propagation time: 7.822 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 0.769 Number of logic level(s): 2 Starting point: SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[12] Ending point: SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[2] The start point is clocked by SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK_BASE The end point is clocked by SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK_BASE Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST MSS_075 F_HM0_ADDR[12] Out 3.583 3.583 r - DATAHANDLE_FSM_0_DATA_RADDR[10] Net - - 1.208 - 7 SF2_JESD204B_DEMO_sb_0.CoreAPB3_0.iPSELS[0] CFG4 D In - 4.791 r - SF2_JESD204B_DEMO_sb_0.CoreAPB3_0.iPSELS[0] CFG4 Y Out 0.326 5.117 f - SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PSELx Net - - 1.299 - 33 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST_RNO_1 CFG4 D In - 6.417 f - SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST_RNO_1 CFG4 Y Out 0.288 6.704 f - AMBA_SLAVE_0_PRDATAS0_m[2] Net - - 1.117 - 1 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST MSS_075 F_HM0_RDATA[2] In - 7.822 f - ================================================================================================================================================== Total path delay (propagation time + setup) of 9.231 is 5.606(60.7%) logic and 3.624(39.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[0] SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[0] 0.087 17.713 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[1] SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[1] 0.087 18.039 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[3] SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[3] 0.087 18.062 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[6] SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[6] 0.108 18.102 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[2] SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[2] 0.108 18.135 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[4] SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[4] 0.087 18.144 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[5] SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[5] 0.108 18.181 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[8] SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[8] 0.108 18.181 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[10] SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[10] 0.087 18.187 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[11] SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[11] 0.108 18.226 =========================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SF2_JESD204B_DEMO_sb_0.CORERESETP_0.release_sdif0_core SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE EN release_sdif0_core4 19.663 17.713 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[12] SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[12] 19.745 18.190 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[11] SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[11] 19.745 18.206 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[10] SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[10] 19.745 18.222 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[9] SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[9] 19.745 18.238 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[8] SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[8] 19.745 18.255 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[7] SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[7] 19.745 18.271 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[6] SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[6] 19.745 18.287 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[5] SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[5] 19.745 18.304 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[4] SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[4] 19.745 18.320 =================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 0.337 + Clock delay at ending point: 0.000 (ideal) = Required time: 19.663 - Propagation time: 1.950 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 17.713 Number of logic level(s): 2 Starting point: SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[0] / Q Ending point: SF2_JESD204B_DEMO_sb_0.CORERESETP_0.release_sdif0_core / EN The start point is clocked by SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK The end point is clocked by SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------ SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[0] SLE Q Out 0.087 0.087 r - count_sdif0[0] Net - - 0.745 - 3 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.release_sdif0_core4_8 CFG4 D In - 0.833 r - SF2_JESD204B_DEMO_sb_0.CORERESETP_0.release_sdif0_core4_8 CFG4 Y Out 0.326 1.159 f - release_sdif0_core4_8 Net - - 0.248 - 1 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.release_sdif0_core4 CFG4 D In - 1.408 f - SF2_JESD204B_DEMO_sb_0.CORERESETP_0.release_sdif0_core4 CFG4 Y Out 0.288 1.695 f - release_sdif0_core4 Net - - 0.254 - 1 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.release_sdif0_core SLE EN In - 1.950 f - ======================================================================================================================== Total path delay (propagation time + setup) of 2.287 is 1.039(45.4%) logic and 1.248(54.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.psel SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB SLE Q psel 0.108 14.548 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.SDIF0_PENABLE SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB SLE Q SF2_JESD204B_DEMO_sb_0_SDIF0_INIT_APB_PENABLE 0.108 17.912 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.state[1] SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB SLE Q state[1] 0.087 17.962 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.paddr[15] SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB SLE Q SF2_JESD204B_DEMO_sb_0_SDIF0_INIT_APB_PADDR[15] 0.087 18.389 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.state[0] SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB SLE Q state[0] 0.087 18.430 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PREADY SF2_JESD204B_DEMO_sb_0_SDIF0_INIT_APB_PREADY 5.566 32.768 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PRDATA[25] SF2_JESD204B_DEMO_sb_0_SDIF0_INIT_APB_PRDATA[25] 6.291 32.792 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PRDATA[29] SF2_JESD204B_DEMO_sb_0_SDIF0_INIT_APB_PRDATA[29] 6.158 32.925 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PRDATA[24] SF2_JESD204B_DEMO_sb_0_SDIF0_INIT_APB_PRDATA[24] 6.152 32.931 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PRDATA[28] SF2_JESD204B_DEMO_sb_0_SDIF0_INIT_APB_PRDATA[28] 6.137 32.946 ======================================================================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PSEL SF2_JESD204B_DEMO_sb_0_SDIF0_INIT_APB_PSELx 16.788 14.548 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[0] SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[0] 19.745 15.699 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[1] SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[1] 19.745 15.699 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[2] SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[2] 19.745 15.699 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[3] SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[3] 19.745 15.699 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[4] SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[4] 19.745 15.699 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[5] SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[5] 19.745 15.699 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[6] SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[6] 19.745 15.699 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[7] SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[7] 19.745 15.699 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[8] SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[8] 19.745 15.699 ===================================================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 3.212 + Clock delay at ending point: 0.000 (ideal) = Required time: 16.788 - Propagation time: 2.240 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 14.548 Number of logic level(s): 1 Starting point: SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.psel / Q Ending point: SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST / APB_PSEL The start point is clocked by SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB [falling] (rise=0.000 fall=20.000 period=40.000) on pin CLK The end point is clocked by SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB [rising] (rise=0.000 fall=20.000 period=40.000) on pin APB_CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------- SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.psel SLE Q Out 0.108 0.108 f - psel Net - - 0.745 - 3 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.R_SDIF0_PSEL CFG2 A In - 0.854 f - SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.R_SDIF0_PSEL CFG2 Y Out 0.087 0.941 f - SF2_JESD204B_DEMO_sb_0_SDIF0_INIT_APB_PSELx Net - - 1.299 - 34 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST SERDESIF_075 APB_PSEL In - 2.240 f - ============================================================================================================================ Total path delay (propagation time + setup) of 5.452 is 3.407(62.5%) logic and 2.045(37.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied @W:MT447 : synthesis.fdc(14) | Timing constraint (from [get_cells { SF2_JESD204B_DEMO_sb_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sm0_areset_n_rcosc SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(15) | Timing constraint (from [get_cells { SF2_JESD204B_DEMO_sb_0.CORERESETP_0.MSS_HPMS_READY_int SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(17) | Timing constraint (through [get_pins { SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST.CONFIG_PRESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(18) | Timing constraint (through [get_pins { SF2_JESD204B_DEMO_sb_0.SYSRESET_POR.POWER_ON_RESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT443 : synthesis.fdc(19) | Timing constraint (through [get_nets { SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.FIC_2_APB_M_PSEL SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.FIC_2_APB_M_PENABLE }] to [get_cells { SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.FIC_2_APB_M_PREADY* SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.state[0] }]) (max delay 0.000000) was not applied to the design because none of the paths specified by the constraint exist in the design None Finished final timing analysis (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 236MB peak: 252MB) Finished timing report (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 236MB peak: 252MB) --------------------------------------- Resource Usage Report for top Mapping to part: m2s090tfbga484std Cell usage: BUFD 80 uses CCC 1 use CLKINT 15 uses MSS_075 1 use RCOSC_25_50MHZ 1 use RCOSC_25_50MHZ_FAB 1 use SERDESIF_075 1 use SYSRESET 1 use CFG1 20 uses CFG2 441 uses CFG3 746 uses CFG4 1027 uses Carry cells: ARI1 141 uses - used for arithmetic functions ARI1 826 uses - used for Wide-Mux implementation Total ARI1 967 uses Sequential Cells: SLE 2865 uses DSP Blocks: 0 of 84 (0%) I/O ports: 33 I/O primitives: 16 INBUF 6 uses OUTBUF 8 uses TRIBUFF 2 uses Global Clock Buffers: 15 RAM/ROM usage summary Total Block RAMs (RAM1K18) : 6 of 109 (5%) Total LUTs: 3201 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 216; LUTs = 216; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 2865 + 0 + 216 + 0 = 3081; Total number of LUTs after P&R: 3201 + 0 + 216 + 0 = 3417; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 81MB peak: 252MB) Process took 0h:00m:18s realtime, 0h:00m:18s cputime # Sun Mar 28 21:10:57 2021 ###########################################################]