Project Settings Project Name top_syn Device Name synthesis: Microchip SmartFusion2 : M2S090T Implementation Name synthesis Top Module top Retiming 0 Resource Sharing 1 Fanout Guide 10000 Disable I/O Insertion 0 Disable Sequential Optimizations 0 FSM Compiler 1 Run Status Job Name Status CPU Time Real Time Memory Date/Time (compiler) Complete 265 408 0 - 00m:21s - 28-03-2021 21:10:33 (premap) Complete 118 45 0 0m:02s 0m:02s 188MB 28-03-2021 21:10:38 (fpga_mapper) Complete 64 133 0 0m:18s 0m:18s 252MB 28-03-2021 21:10:57 Multi-srs Generator Complete 00m:01s 28-03-2021 21:10:35 Area Summary Carry Cells 967 Sequential Cells 2865 DSP Blocks (dsp_used) 0 I/O Cells 16 Global Clock Buffers 15 RAM1K18 (v_ram) 6 LUTs (total_luts) 3201 Timing Summary Clock Name Req Freq Est Freq Slack SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] 100.0 MHz 116.2 MHz 1.392 SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] 100.0 MHz 133.6 MHz 2.514 SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 100.0 MHz 108.3 MHz 0.769 SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 437.2 MHz 17.713 SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB 25.0 MHz 91.7 MHz 14.548 Optimizations Summary Combined Clock Conversion 4 / 1