#Build: Synplify Pro L-2016.09M-2, Build 065R, Nov 16 2016 #install: D:\Microsemi\Libero_SoC_v11.8\SynplifyPro #OS: Windows 7 6.1 #Hostname: W764-AITHAS # Tue Mar 14 16:14:14 2017 #Implementation: synthesis Synopsys HDL Compiler, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Synopsys Verilog Compiler, version comp2016q3p1, Build 127R, built Nov 24 2016 @N: : | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. @I::"D:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.v" (library work) @I::"D:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CLOCK_GEN_RX.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\DATA_SYNC_BUF.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\DEC_ERR.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\DEC_DATA.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\DEC_RD_L.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\SYNC_FSM.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\DECODER_L.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\DEC_RD_U.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\DECODER_U.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\WORD_ALIGNER.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\DEC_WA.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\DESCRAMBLER.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\FL_AMC.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\FADM_OR.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\EB_CTRL.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\EB_RAM_RTL.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\ADJ_BUF.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\ILA_FSM.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\LINK_COMP.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\LABDM.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\ADJ_CTRL.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CGS.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\RX_CTRL.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\WORD_SHIFT.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\JESD204BRX_LANE.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\SYNC_ENC.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CLOCK_GEN_TX.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\BUF_DATA.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\MUX4X1.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\MUX32X1.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\MUX32X6.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\ENC_D.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\ENC_FLIP.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\ENC_K.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\ENCODER_L.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\ENCODER_N.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\ENCODER_U.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\ENCODER_64B80B.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\SCRAMBLER.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\TX_ACG.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\TX_CTRL.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\TX_ILA.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\JESD204BTX_LANE.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\PHASE_CHECK.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\DATA_SYNC_BUF_TX.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\SYNC_DEC.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\DATA_HANDLE_FSM.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\PRBS_GENERATOR.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\PRBS_WAV_SEL.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\wav_gen_16bit.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\work\DATA_GENERATOR\DATA_GENERATOR.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\ERR_GEN.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\LED_BLOCK_2.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\PRBS_CHECKER.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\work\SERDES_EPCS\SERDES_IF2_0\SERDES_EPCS_SERDES_IF2_0_SERDES_IF2_syn.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\work\SERDES_EPCS\SERDES_IF2_0\SERDES_EPCS_SERDES_IF2_0_SERDES_IF2.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\delay_line.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\epcs_rx_intf.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\epcs_tx_intf.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\work\SERDES_EPCS\SERDES_EPCS.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\work\SF2_JESD204B_DEMO\TPSRAM_0\SF2_JESD204B_DEMO_TPSRAM_0_TPSRAM.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\work\SF2_JESD204B_DEMO\TPSRAM_1\SF2_JESD204B_DEMO_TPSRAM_1_TPSRAM.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\work\SF2_JESD204B_DEMO_sb\CCC_0\SF2_JESD204B_DEMO_sb_CCC_0_FCCC.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\work\SF2_JESD204B_DEMO_sb\FABOSC_0\SF2_JESD204B_DEMO_sb_FABOSC_0_OSC.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\work\SF2_JESD204B_DEMO_sb_MSS\SF2_JESD204B_DEMO_sb_MSS_syn.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\work\SF2_JESD204B_DEMO_sb_MSS\SF2_JESD204B_DEMO_sb_MSS.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_muxptob3.v" (library COREAPB3_LIB) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_iaddr_reg.v" (library COREAPB3_LIB) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v" (library COREAPB3_LIB) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\work\SF2_JESD204B_DEMO_sb\SF2_JESD204B_DEMO_sb.v" (library work) @I::"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\work\SF2_JESD204B_DEMO\SF2_JESD204B_DEMO.v" (library work) Verilog syntax check successful! Options changed - recompiling Selecting top level module SF2_JESD204B_DEMO @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT in library work. @N:CG364 : SYNC_ENC.v(18) | Synthesizing module CJESDRX_SYNC_ENC in library work. K_WIDTH=32'b00000000000000000000000000000010 SYNC_RESET=32'b00000000000000000000000000000000 L=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 SYNC_DUR_MIN=32'b00000000000000000000000000110110 SUBCLASSV=32'b00000000000000000000000000000000 SG_INIT=2'b00 SG_ASSERT=2'b01 SG_DEASSERT=2'b10 Generated name = CJESDRX_SYNC_ENC_2s_0s_0s_2s_9s_54s_0s_0_1_2 @N:CG179 : SYNC_ENC.v(117) | Removing redundant assignment. @N:CG364 : CLOCK_GEN_RX.v(18) | Synthesizing module CJESDRX_CLOCK_GEN_RX in library work. D_WIDTH=32'b00000000000000000000000000010000 SYNC_RESET=32'b00000000000000000000000000000000 R=32'b00000000000000000000000000000100 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 SUBCLASSV=32'b00000000000000000000000000000000 JESDV=32'b00000000000000000000000000000001 lmfc_period=32'b00000000000000000000000000010010 fc_period=32'b00000000000000000000000000000010 sysref_high=32'b00000000000000000000000000000100 ERR_TRIG_EVEN=32'b00000000000000000000000000001110 ERR_TRIG_ODD_0=32'b00000000000000000000000000001101 ERR_TRIG_ODD_1=32'b00000000000000000000000000001111 ERR_ST0=2'b00 ERR_ST1=2'b01 ERR_ST2=2'b10 INC_VAL=4'b0010 Generated name = CJESDRX_CLOCK_GEN_RX_Z1 @W:CG133 : CLOCK_GEN_RX.v(240) | Object sys_st is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CLOCK_GEN_RX.v(241) | Object sys_cnt is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CLOCK_GEN_RX.v(242) | Object sysref_in_pulse_last is declared but not assigned. Either assign a value or remove the declaration. @W:CL169 : CLOCK_GEN_RX.v(169) | Pruning unused register err_state[1:0]. Make sure that there are no unused intermediate registers. @W:CL113 : CLOCK_GEN_RX.v(351) | Feedback mux created for signal genblk3.F_PHASE_ST. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL113 : CLOCK_GEN_RX.v(351) | Feedback mux created for signal genblk3.FC_CNT[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL113 : CLOCK_GEN_RX.v(303) | Feedback mux created for signal genblk3.MF_PHASE_ST. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL177 : CLOCK_GEN_RX.v(303) | Sharing sequential element genblk3.MF_PHASE_ST. Add a syn_preserve attribute to the element to prevent sharing. @W:CL113 : CLOCK_GEN_RX.v(303) | Feedback mux created for signal genblk3.LMFC_CNT[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL177 : CLOCK_GEN_RX.v(303) | Sharing sequential element genblk3.LMFC_CNT. Add a syn_preserve attribute to the element to prevent sharing. @W:CL250 : CLOCK_GEN_RX.v(351) | All reachable assignments to genblk3.FC_CNT[3:0] assign 0, register removed by optimization @W:CL250 : CLOCK_GEN_RX.v(351) | All reachable assignments to genblk3.F_PHASE_ST assign 0, register removed by optimization @N:CG364 : CGS.v(18) | Synthesizing module CJESDRX_CGS in library work. SYNC_RESET=32'b00000000000000000000000000000000 CS_INIT=2'b00 CS_CHECK=2'b01 CS_DATA=2'b10 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 Generated name = CJESDRX_CGS_0s_0_1_2_16s_2s @N:CG364 : ADJ_CTRL.v(19) | Synthesizing module CJESDRX_ADJ_CTRL in library work. SYNC_RESET=32'b00000000000000000000000000000000 SUBCLASSV=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 fc_period=32'b00000000000000000000000000000010 lmfc_period=32'b00000000000000000000000000010010 FRAME_MID=32'b00000000000000000000000000000001 LANE_MID=32'b00000000000000000000000000001001 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 L_MODE=3'b010 F_MODE=3'b010 Generated name = CJESDRX_ADJ_CTRL_Z2 @W:CL169 : ADJ_CTRL.v(112) | Pruning unused register f_phase_st_reg[3:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ADJ_CTRL.v(112) | Pruning unused register lmfc_cnt_reg[11:0]. Make sure that there are no unused intermediate registers. @W:CL169 : ADJ_CTRL.v(112) | Pruning unused register fc_cnt_reg[11:0]. Make sure that there are no unused intermediate registers. @N:CG364 : RX_CTRL.v(19) | Synthesizing module CJESDRX_RX_CTRL in library work. SYNC_RESET=32'b00000000000000000000000000000000 SUBCLASSV=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 lmfc_period=32'b00000000000000000000000000010010 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 Generated name = CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s @N:CG364 : ILA_FSM.v(18) | Synthesizing module CJESDRX_ILA_FSM in library work. D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 SYNC_RESET=32'b00000000000000000000000000000000 SUBCLASSV=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 ERR_R=32'b00000000000000000000000001001000 RI_INIT=2'b00 RI_CHECK=2'b01 RI_DATA=2'b10 ILA_INIT=3'b000 ILA_BEGIN=3'b001 ILA_RDET=3'b010 ILA_AA=3'b011 ILA_DATA=3'b100 Generated name = CJESDRX_ILA_FSM_Z3 @N:CG364 : EB_CTRL.v(19) | Synthesizing module CJESDRX_EB_CTRL in library work. SYNC_RESET=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 lmfc_period=32'b00000000000000000000000000010010 RAM_DEPTH=32'b00000000000000000000000000110110 EB_INIT=1'b0 EB_HOLD=1'b1 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 Generated name = CJESDRX_EB_CTRL_0s_2s_9s_18s_54s_0_1_16s_2s @N:CG179 : EB_CTRL.v(140) | Removing redundant assignment. @N:CG179 : EB_CTRL.v(200) | Removing redundant assignment. @N:CG179 : EB_CTRL.v(214) | Removing redundant assignment. @N:CG179 : EB_CTRL.v(291) | Removing redundant assignment. @N:CG364 : EB_RAM_RTL.v(18) | Synthesizing module CJESDRX_RAM_EB in library work. SYNC_RESET=32'b00000000000000000000000000000000 RAM_DEPTH=32'b00000000000000000000000000110110 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 DATA_K_WIDTH=32'b00000000000000000000000000010010 Generated name = CJESDRX_RAM_EB_0s_54s_16s_2s_18s @N:CL134 : EB_RAM_RTL.v(69) | Found RAM EB_RAM, depth=54, width=18 @N:CG364 : ADJ_BUF.v(18) | Synthesizing module CJESDRX_ADJ_BUF in library work. SYNC_RESET=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 lmfc_period=32'b00000000000000000000000000010010 RAM_DEPTH=32'b00000000000000000000000000110110 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 adj_num_value=32'b00000000000000000000000000001001 DATA_K_WIDTH=32'b00000000000000000000000000010010 Generated name = CJESDRX_ADJ_BUF_0s_2s_9s_18s_54s_16s_2s_9s_18s @N:CG364 : LABDM.v(19) | Synthesizing module CJESDRX_LABDM in library work. SYNC_RESET=32'b00000000000000000000000000000000 SCR=32'b00000000000000000000000000000000 L=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 M=32'b00000000000000000000000000000001 CS=32'b00000000000000000000000000000000 N=32'b00000000000000000000000000001110 SUBCLASSV=32'b00000000000000000000000000000000 Na=32'b00000000000000000000000000010000 JESDV=32'b00000000000000000000000000000001 S=32'b00000000000000000000000000000010 HD=32'b00000000000000000000000000000000 CF=32'b00000000000000000000000000000000 LID=32'b00000000000000000000000000000000 FIELD_OCTET=32'b00000000000000000000000000000001 lmfc_period=32'b00000000000000000000000000010010 RAM_DEPTH=32'b00000000000000000000000000110110 RAM_SEL=32'b00000000000000000000000000000000 LCD_EN=32'b00000000000000000000000000000001 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 Generated name = CJESDRX_LABDM_Z4 @W:CG1283 : LABDM.v(229) | Ignoring localparam RES1 on the instance and using locally defined value @W:CG1283 : LABDM.v(229) | Ignoring localparam RES2 on the instance and using locally defined value @N:CG364 : LINK_COMP.v(18) | Synthesizing module CJESDRX_LINK_COMP in library work. SCR=32'b00000000000000000000000000000000 L=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 M=32'b00000000000000000000000000000001 CS=32'b00000000000000000000000000000000 N=32'b00000000000000000000000000001110 SUBCLASSV=32'b00000000000000000000000000000000 Na=32'b00000000000000000000000000010000 JESDV=32'b00000000000000000000000000000001 S=32'b00000000000000000000000000000010 HD=32'b00000000000000000000000000000000 CF=32'b00000000000000000000000000000000 LID=32'b00000000000000000000000000000000 RES1=32'b00000000000000000000000000000000 RES2=32'b00000000000000000000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 K28_0=8'b00011100 K28_3=8'b01111100 K28_4=8'b10011100 K28_5=8'b10111100 K28_7=8'b11111100 CD_INIT=3'b000 CD_R_DET=3'b001 CD_Q=3'b010 CD_COMP=3'b011 CD_ERR=3'b100 CD_WAIT=3'b101 CD_SYNC=3'b110 INIT_S=2'b00 WAIT_S=2'b01 COMP_S=2'b10 lmfc_period=32'b00000000000000000000000000010010 FIELD_OCTET=32'b00000000000000000000000000000001 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 EVEN_ODD=1'b0 Generated name = CJESDRX_LINK_COMP_Z5 @W:CG296 : LINK_COMP.v(400) | Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list. @W:CG290 : LINK_COMP.v(424) | Referenced variable lcp_octet_4 is not in sensitivity list. @W:CG290 : LINK_COMP.v(424) | Referenced variable lcp_octet_5 is not in sensitivity list. @W:CG290 : LINK_COMP.v(440) | Referenced variable lcp_octet_6 is not in sensitivity list. @W:CG290 : LINK_COMP.v(440) | Referenced variable lcp_octet_7 is not in sensitivity list. @W:CG290 : LINK_COMP.v(456) | Referenced variable lcp_octet_8 is not in sensitivity list. @W:CG290 : LINK_COMP.v(456) | Referenced variable lcp_octet_9 is not in sensitivity list. @W:CG290 : LINK_COMP.v(472) | Referenced variable lcp_octet_10 is not in sensitivity list. @W:CG290 : LINK_COMP.v(472) | Referenced variable lcp_octet_11 is not in sensitivity list. @W:CG290 : LINK_COMP.v(489) | Referenced variable lcp_octet_12 is not in sensitivity list. @W:CG290 : LINK_COMP.v(489) | Referenced variable lcp_octet_13 is not in sensitivity list. @W:CG290 : LINK_COMP.v(408) | Referenced variable lcp_octet_3 is not in sensitivity list. @N:CG179 : LINK_COMP.v(562) | Removing redundant assignment. @N:CG179 : LINK_COMP.v(563) | Removing redundant assignment. @N:CG179 : LINK_COMP.v(564) | Removing redundant assignment. @N:CG179 : LINK_COMP.v(565) | Removing redundant assignment. @N:CG179 : LINK_COMP.v(566) | Removing redundant assignment. @N:CG179 : LINK_COMP.v(571) | Removing redundant assignment. @N:CG179 : LINK_COMP.v(572) | Removing redundant assignment. @N:CG179 : LINK_COMP.v(573) | Removing redundant assignment. @N:CG179 : LINK_COMP.v(574) | Removing redundant assignment. @N:CG179 : LINK_COMP.v(575) | Removing redundant assignment. @W:CL169 : LINK_COMP.v(518) | Pruning unused register genblk6.ADJCNT[3:0]. Make sure that there are no unused intermediate registers. @W:CL169 : LINK_COMP.v(518) | Pruning unused register genblk6.ADJDIR. Make sure that there are no unused intermediate registers. @W:CL169 : LINK_COMP.v(518) | Pruning unused register genblk6.PHADJ. Make sure that there are no unused intermediate registers. @N:CG364 : FL_AMC.v(18) | Synthesizing module CJESDRX_FL_AMC in library work. SYNC_RESET=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 FAC_EN=32'b00000000000000000000000000000001 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 Generated name = CJESDRX_FL_AMC_0s_2s_9s_1s_16s_2s @N:CG179 : FL_AMC.v(357) | Removing redundant assignment. @N:CG179 : FL_AMC.v(774) | Removing redundant assignment. @N:CG364 : IFS_POS.v(18) | Synthesizing module CJESDRX_IFS_POS in library work. ILA_MFS=32'b00000000000000000000000000000100 SYNC_RESET=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 ila_period=32'b00000000000000000000000001001000 FS_INIT=2'b00 FS_CHECK=2'b01 FS_ILA=2'b10 FS_DATA=2'b11 CC_INIT_ST=1'b0 CC_WAIT_F=1'b1 Generated name = CJESDRX_IFS_POS_Z6 @N:CG179 : IFS_POS.v(4394) | Removing redundant assignment. @W:CL113 : IFS_POS.v(4333) | Feedback mux created for signal genblk6.FCOUNT_L_6[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL113 : IFS_POS.v(4333) | Feedback mux created for signal genblk6.FCOUNT_L_5[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL177 : IFS_POS.v(4333) | Sharing sequential element genblk6.FCOUNT_L_5. Add a syn_preserve attribute to the element to prevent sharing. @W:CL113 : IFS_POS.v(4333) | Feedback mux created for signal genblk6.FCOUNT_L_4[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL177 : IFS_POS.v(4333) | Sharing sequential element genblk6.FCOUNT_L_4. Add a syn_preserve attribute to the element to prevent sharing. @W:CL113 : IFS_POS.v(4333) | Feedback mux created for signal genblk6.FCOUNT_L_3[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL177 : IFS_POS.v(4333) | Sharing sequential element genblk6.FCOUNT_L_3. Add a syn_preserve attribute to the element to prevent sharing. @W:CL113 : IFS_POS.v(4333) | Feedback mux created for signal genblk6.FCOUNT_L_2[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL177 : IFS_POS.v(4333) | Sharing sequential element genblk6.FCOUNT_L_2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL113 : IFS_POS.v(4333) | Feedback mux created for signal genblk6.FCOUNT_L_1[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL177 : IFS_POS.v(4333) | Sharing sequential element genblk6.FCOUNT_L_1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL250 : IFS_POS.v(4333) | All reachable assignments to genblk6.FCOUNT_L_6[3:0] assign 0, register removed by optimization @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_L_1[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_L_1[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_L_2[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_L_2[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_L_3[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_L_3[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_L_4[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_L_4[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_L_5[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_L_5[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_L_6[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_L_6[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(4293) | Optimizing register bit genblk6.OCOUNT_U[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : IFS_POS.v(4293) | Pruning register bit 1 of genblk6.OCOUNT_U[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL169 : IFS_POS.v(4293) | Pruning unused register genblk6.OCOUNT_L_1[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : IFS_POS.v(4293) | Pruning unused register genblk6.OCOUNT_L_2[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : IFS_POS.v(4293) | Pruning unused register genblk6.OCOUNT_L_3[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : IFS_POS.v(4293) | Pruning unused register genblk6.OCOUNT_L_4[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : IFS_POS.v(4293) | Pruning unused register genblk6.OCOUNT_L_5[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : IFS_POS.v(4293) | Pruning unused register genblk6.OCOUNT_L_6[1:0]. Make sure that there are no unused intermediate registers. @N:CG364 : FADM_OR.v(18) | Synthesizing module CJESDRX_FADM_OR in library work. ILA_MFS=32'b00000000000000000000000000000100 SYNC_RESET=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 SCR=32'b00000000000000000000000000000000 FAC_EN=32'b00000000000000000000000000000001 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 Generated name = CJESDRX_FADM_OR_4s_0s_2s_9s_0s_1s_16s_2s @N:CG179 : FADM_OR.v(854) | Removing redundant assignment. @W:CL169 : FADM_OR.v(179) | Pruning unused register genblk2.FS_reg[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : FADM_OR.v(179) | Pruning unused register genblk2.MFS_reg[1:0]. Make sure that there are no unused intermediate registers. @N:CG364 : JESD204BRX_LANE.v(19) | Synthesizing module CJESDRX_JESD204BRX_LANE in library work. SCR=32'b00000000000000000000000000000000 L=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 M=32'b00000000000000000000000000000001 CS=32'b00000000000000000000000000000000 N=32'b00000000000000000000000000001110 SUBCLASSV=32'b00000000000000000000000000000000 Na=32'b00000000000000000000000000010000 JESDV=32'b00000000000000000000000000000001 S=32'b00000000000000000000000000000010 HD=32'b00000000000000000000000000000000 CF=32'b00000000000000000000000000000000 LID=32'b00000000000000000000000000000000 FIELD_OCTET=32'b00000000000000000000000000000001 ILA_MFS=32'b00000000000000000000000000000100 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 E_WIDTH=32'b00000000000000000000000000010100 SERDES_MODE=32'b00000000000000000000000000000001 DECODER_EN=32'b00000000000000000000000000000001 K_WIDTH_IN=32'b00000000000000000000000000000010 SYNC_RESET=32'b00000000000000000000000000000000 DATA_DW_SIZE=32'b00000000000000000000000000010100 LANE_DATA=32'b00000000000000000000000000010100 lmfc_period=32'b00000000000000000000000000010010 FAC_EN=32'b00000000000000000000000000000001 RAM_SEL=32'b00000000000000000000000000000000 RAM_DEPTH=32'b00000000000000000000000000110110 LCD_EN=32'b00000000000000000000000000000001 Generated name = CJESDRX_JESD204BRX_LANE_Z7 @N:CG364 : DEC_ERR.v(21) | Synthesizing module CJESDRX_DEC_ERR in library work. @N:CG364 : DEC_DATA.v(21) | Synthesizing module CJESDRX_DEC_DATA in library work. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDRX_DEC_DATA_0s @N:CG364 : SYNC_FSM.v(21) | Synthesizing module CJESDRX_SYNC_FSM in library work. SYNC_RESET=32'b00000000000000000000000000000000 SEARCH_1=3'b000 SEARCH_2=3'b001 SYNC_0=3'b010 SYNC_1=3'b011 SYNC_2=3'b100 TRIGGER=4'b0100 Generated name = CJESDRX_SYNC_FSM_0s_0_1_2_3_4_4 @N:CG364 : DEC_RD_U.v(22) | Synthesizing module CJESDRX_DEC_RD_U in library work. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDRX_DEC_RD_U_0s @N:CG364 : DECODER_U.v(21) | Synthesizing module CJESDRX_DECODER_U in library work. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDRX_DECODER_U_0s @N:CG364 : WORD_ALIGNER.v(18) | Synthesizing module CJESDRX_WORD_ALIGNER in library work. D_WIDTH=32'b00000000000000000000000000010000 E_WIDTH=32'b00000000000000000000000000010100 K_WIDTH=32'b00000000000000000000000000000010 SYNC_RESET=32'b00000000000000000000000000000000 WA_INIT=2'b00 WA_SEL=2'b01 WA_WAIT_0=2'b10 WA_WAIT_1=2'b11 K28_5_p_10=10'b1100000101 K28_5_n_10=10'b0011111010 K28_5_p_20=20'b11000001010011111010 K28_5_n_20=20'b00111110101100000101 K28_5_p_40=40'b1100000101001111101011000001010011111010 K28_5_n_40=40'b0011111010110000010100111110101100000101 K28_5_p_sel=40'b0000000000000000000000000000001100000101 K28_5_n_sel=40'b0000000000000000000000000000000011111010 SEL_NONE=10'b0000000000 SEL_DET0=10'b0000000001 SEL_DET1=10'b0000000010 SEL_DET2=10'b0000000100 SEL_DET3=10'b0000001000 SEL_DET4=10'b0000010000 SEL_DET5=10'b0000100000 SEL_DET6=10'b0001000000 SEL_DET7=10'b0010000000 SEL_DET8=10'b0100000000 SEL_DET9=10'b1000000000 Generated name = CJESDRX_WORD_ALIGNER_Z8 @N:CG179 : WORD_ALIGNER.v(199) | Removing redundant assignment. @N:CG179 : WORD_ALIGNER.v(527) | Removing redundant assignment. @N:CG179 : WORD_ALIGNER.v(553) | Removing redundant assignment. @N:CG179 : WORD_ALIGNER.v(578) | Removing redundant assignment. @N:CG179 : WORD_ALIGNER.v(603) | Removing redundant assignment. @N:CG179 : WORD_ALIGNER.v(628) | Removing redundant assignment. @N:CG179 : WORD_ALIGNER.v(653) | Removing redundant assignment. @N:CG179 : WORD_ALIGNER.v(678) | Removing redundant assignment. @N:CG179 : WORD_ALIGNER.v(703) | Removing redundant assignment. @N:CG179 : WORD_ALIGNER.v(728) | Removing redundant assignment. @N:CG179 : WORD_ALIGNER.v(753) | Removing redundant assignment. @N:CG179 : WORD_ALIGNER.v(788) | Removing redundant assignment. @W:CL271 : WORD_ALIGNER.v(177) | Pruning unused bits 39 to 30 of buf_data[39:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL190 : WORD_ALIGNER.v(379) | Optimizing register bit genblk5.wa_sel_d[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : WORD_ALIGNER.v(379) | Optimizing register bit genblk5.wa_sel_d[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL279 : WORD_ALIGNER.v(379) | Pruning register bits 2 to 1 of genblk5.wa_sel_d[2:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @N:CG364 : DEC_WA.v(18) | Synthesizing module CJESDRX_DEC_WA in library work. SYNC_RESET=32'b00000000000000000000000000000000 SERDES_MODE=32'b00000000000000000000000000000001 D_WIDTH=32'b00000000000000000000000000010000 E_WIDTH=32'b00000000000000000000000000010100 K_WIDTH=32'b00000000000000000000000000000010 Generated name = CJESDRX_DEC_WA_0s_1s_16s_20s_2s @N:CG364 : DEC_RD_L.v(22) | Synthesizing module CJESDRX_DEC_RD_L in library work. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDRX_DEC_RD_L_0s @W:CL169 : DEC_RD_L.v(97) | Pruning unused register RD. Make sure that there are no unused intermediate registers. @N:CG364 : DECODER_L.v(21) | Synthesizing module CJESDRX_DECODER_L in library work. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDRX_DECODER_L_0s @W:CL169 : JESD204BRX_LANE.v(261) | Pruning unused register genblk4.dw_k[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : JESD204BRX_LANE.v(261) | Pruning unused register genblk4.dw_valid[1:0]. Make sure that there are no unused intermediate registers. @N:CG364 : CoreJESD204BRX.v(19) | Synthesizing module CoreJESD204BRX in library work. SCR=32'b00000000000000000000000000000000 L=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 M=32'b00000000000000000000000000000001 CS=32'b00000000000000000000000000000000 N=32'b00000000000000000000000000001110 SUBCLASSV=32'b00000000000000000000000000000000 Na=32'b00000000000000000000000000010000 JESDV=32'b00000000000000000000000000000001 S=32'b00000000000000000000000000000010 HD=32'b00000000000000000000000000000000 CF=32'b00000000000000000000000000000000 FIELD_OCTET=32'b00000000000000000000000000000001 ILA_MFS=32'b00000000000000000000000000000100 DECODER_EN=32'b00000000000000000000000000000001 D_WIDTH=32'b00000000000000000000000000010000 E_WIDTH=32'b00000000000000000000000000010100 K_WIDTH=32'b00000000000000000000000000000010 LCD_EN=32'b00000000000000000000000000000001 SERDES_MODE=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000010011 SYNC_RESET=32'b00000000000000000000000000000000 lmfc_period=32'b00000000000000000000000000010010 K_WIDTH_IN=32'b00000000000000000000000000000010 EPCS_WIDTH=32'b00000000000000000000000000010100 DATA_K_WIDTH=32'b00000000000000000000000000010000 LANE_DATA=32'b00000000000000000000000000010100 FAC_EN=32'b00000000000000000000000000000001 RAM_SEL=32'b00000000000000000000000000000000 RAM_DEPTH=32'b00000000000000000000000000110110 Generated name = CoreJESD204BRX_Z9 @N:CG364 : DATA_SYNC_BUF.v(19) | Synthesizing module CJESDRX_DATA_SYNC_BUF in library work. LANE_DATA=32'b00000000000000000000000000010100 SYNC_RESET=32'b00000000000000000000000000000000 K_WIDTH_IN=32'b00000000000000000000000000000010 Generated name = CJESDRX_DATA_SYNC_BUF_20s_0s_2s @N:CG179 : DATA_SYNC_BUF.v(84) | Removing redundant assignment. @A:CL282 : DATA_SYNC_BUF.v(91) | Feedback mux created for signal valid_buf_2_[1:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : DATA_SYNC_BUF.v(91) | Feedback mux created for signal valid_buf_1_[1:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : DATA_SYNC_BUF.v(91) | Feedback mux created for signal valid_buf_0_[1:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : DATA_SYNC_BUF.v(91) | Feedback mux created for signal k_buf_2_[1:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : DATA_SYNC_BUF.v(91) | Feedback mux created for signal k_buf_1_[1:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : DATA_SYNC_BUF.v(91) | Feedback mux created for signal k_buf_0_[1:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : DATA_SYNC_BUF.v(91) | Feedback mux created for signal data_buf_2_[19:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : DATA_SYNC_BUF.v(91) | Feedback mux created for signal data_buf_1_[19:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : DATA_SYNC_BUF.v(91) | Feedback mux created for signal data_buf_0_[19:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @W:CG133 : CoreJESD204BRX.v(301) | Object syncd_rst_n_1 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreJESD204BRX.v(302) | Object syncd_rst_n_2 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreJESD204BRX.v(303) | Object syncd_rst_n_3 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreJESD204BRX.v(304) | Object syncd_rst_n_4 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreJESD204BRX.v(305) | Object syncd_rst_n_5 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreJESD204BRX.v(306) | Object syncd_rst_n_6 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreJESD204BRX.v(307) | Object syncd_rst_n_7 is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : CoreJESD204BRX.v(353) | Removing wire data_in_1, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(354) | Removing wire data_in_2, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(355) | Removing wire data_in_3, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(356) | Removing wire data_in_4, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(357) | Removing wire data_in_5, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(358) | Removing wire data_in_6, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(359) | Removing wire data_in_7, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(360) | Removing wire valid_in_0, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(361) | Removing wire valid_in_1, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(362) | Removing wire valid_in_2, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(363) | Removing wire valid_in_3, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(364) | Removing wire valid_in_4, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(365) | Removing wire valid_in_5, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(366) | Removing wire valid_in_6, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(367) | Removing wire valid_in_7, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(368) | Removing wire k_in_0, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(369) | Removing wire k_in_1, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(370) | Removing wire k_in_2, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(371) | Removing wire k_in_3, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(372) | Removing wire k_in_4, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(373) | Removing wire k_in_5, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(374) | Removing wire k_in_6, as there is no assignment to it. @W:CG360 : CoreJESD204BRX.v(375) | Removing wire k_in_7, as there is no assignment to it. @N:CG364 : SYNC_DEC.v(19) | Synthesizing module CJESDTX_SYNC_DEC in library work. F=32'b00000000000000000000000000000010 SUBCLASSV=32'b00000000000000000000000000000000 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 SYNC_RESET=32'b00000000000000000000000000000000 MIN_SYNC_REQ=32'b00000000000000000000000000000110 Generated name = CJESDTX_SYNC_DEC_2s_0s_16s_2s_0s_6s @N:CG179 : SYNC_DEC.v(86) | Removing redundant assignment. @W:CG133 : SYNC_DEC.v(61) | Object sync_req_cnt is declared but not assigned. Either assign a value or remove the declaration. @N:CG364 : CLOCK_GEN_TX.v(19) | Synthesizing module CJESDTX_CLOCK_GEN_TX in library work. F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 SUBCLASSV=32'b00000000000000000000000000000000 D_WIDTH=32'b00000000000000000000000000010000 INC_VAL=32'b00000000000000000000000000000010 SYNC_RESET=32'b00000000000000000000000000000000 R=32'b00000000000000000000000000000100 fc_period=32'b00000000000000000000000000000010 lmfc_period=32'b00000000000000000000000000010010 sysref_high=32'b00000000000000000000000000000100 Generated name = CJESDTX_CLOCK_GEN_TX_2s_9s_0s_16s_2s_0s_4s_2s_18s_4s @W:CL169 : CLOCK_GEN_TX.v(206) | Pruning unused register genblk2.FC_PHASE_ST. Make sure that there are no unused intermediate registers. @W:CL169 : CLOCK_GEN_TX.v(206) | Pruning unused register genblk2.fc_cnt[3:0]. Make sure that there are no unused intermediate registers. @W:CL169 : CLOCK_GEN_TX.v(158) | Pruning unused register genblk2.lmfc_cnt[3:0]. Make sure that there are no unused intermediate registers. @W:CL113 : CLOCK_GEN_TX.v(158) | Feedback mux created for signal genblk2.LMFC_PHASE_ST. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL250 : CLOCK_GEN_TX.v(158) | All reachable assignments to genblk2.LMFC_PHASE_ST assign 0, register removed by optimization @N:CG364 : DATA_SYNC_BUF_TX.v(19) | Synthesizing module CJESDTX_SYNC_BUF_TX in library work. SERDES_MODE=32'b00000000000000000000000000000001 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 K_WIDTH_OUT=32'b00000000000000000000000000000010 LANE_DATA=32'b00000000000000000000000000010100 SYNC_RESET=32'b00000000000000000000000000000000 DATA_IN_SIZE=32'b00000000000000000000000000010100 FSM_STATES=32'b00000000000000000000000000000000 LAST_ADDR=3'b001 Generated name = CJESDTX_SYNC_BUF_TX_1s_16s_2s_2s_20s_0s_20s_0s_1 @N:CG179 : DATA_SYNC_BUF_TX.v(234) | Removing redundant assignment. @N:CG179 : DATA_SYNC_BUF_TX.v(248) | Removing redundant assignment. @W:CL113 : DATA_SYNC_BUF_TX.v(207) | Feedback mux created for signal genblk4.st_fsm[0:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL251 : DATA_SYNC_BUF_TX.v(207) | All reachable assignments to genblk4.st_fsm[0] assign 1, register removed by optimization @N:CG364 : TX_ACG.v(19) | Synthesizing module CJESDTX_TX_ACG in library work. SYNC_RESET=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 SCR=32'b00000000000000000000000000000000 D_WIDTH=32'b00000000000000000000000000010000 DET_LENGTH=32'b00000000000000000000000000000010 Generated name = CJESDTX_TX_ACG_0s_2s_9s_0s_16s_2s @W:CL169 : TX_ACG.v(2173) | Pruning unused register genblk6.FCount_L_6[3:0]. Make sure that there are no unused intermediate registers. @W:CL169 : TX_ACG.v(2173) | Pruning unused register genblk6.FCount_L_5[3:0]. Make sure that there are no unused intermediate registers. @W:CL169 : TX_ACG.v(2173) | Pruning unused register genblk6.FCount_L_4[3:0]. Make sure that there are no unused intermediate registers. @W:CL169 : TX_ACG.v(2173) | Pruning unused register genblk6.FCount_L_3[3:0]. Make sure that there are no unused intermediate registers. @W:CL169 : TX_ACG.v(2173) | Pruning unused register genblk6.FCount_L_2[3:0]. Make sure that there are no unused intermediate registers. @W:CL169 : TX_ACG.v(2173) | Pruning unused register genblk6.FCount_L_1[3:0]. Make sure that there are no unused intermediate registers. @W:CL169 : TX_ACG.v(2137) | Pruning unused register genblk6.OCount_L_1[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : TX_ACG.v(2137) | Pruning unused register genblk6.OCount_L_2[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : TX_ACG.v(2137) | Pruning unused register genblk6.OCount_L_3[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : TX_ACG.v(2137) | Pruning unused register genblk6.OCount_L_4[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : TX_ACG.v(2137) | Pruning unused register genblk6.OCount_L_5[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : TX_ACG.v(2137) | Pruning unused register genblk6.OCount_L_6[1:0]. Make sure that there are no unused intermediate registers. @W:CL190 : TX_ACG.v(2137) | Optimizing register bit genblk6.OCount_U[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : TX_ACG.v(2137) | Pruning register bit 1 of genblk6.OCount_U[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CG1283 : JESD204BTX_LANE.v(500) | Ignoring localparam DID on the instance and using locally defined value @W:CG1283 : JESD204BTX_LANE.v(500) | Ignoring localparam BID on the instance and using locally defined value @W:CG1283 : JESD204BTX_LANE.v(500) | Ignoring localparam RES1 on the instance and using locally defined value @N:CG364 : TX_ILA.v(19) | Synthesizing module CJESDTX_TX_ILA in library work. SCR=32'b00000000000000000000000000000000 L=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 M=32'b00000000000000000000000000000001 CS=32'b00000000000000000000000000000000 N=32'b00000000000000000000000000001110 SUBCLASSV=32'b00000000000000000000000000000000 Na=32'b00000000000000000000000000010000 JESDV=32'b00000000000000000000000000000001 S=32'b00000000000000000000000000000010 HD=32'b00000000000000000000000000000000 CF=32'b00000000000000000000000000000000 FIELD_OCTET=32'b00000000000000000000000000000001 LID=32'b00000000000000000000000000000000 DID=32'b00000000000000000000000000000000 BID=32'b00000000000000000000000000000000 RES1=32'b00000000000000000000000000000000 RES2=32'b00000000000000000000000000000000 D_WIDTH=32'b00000000000000000000000000010000 E_WIDTH=32'b00000000000000000000000000010100 K_WIDTH=32'b00000000000000000000000000000010 ILA_4MF_END=32'b00000000000000000000000001000111 ILA_MFS=32'b00000000000000000000000000000100 lmfc_period=32'b00000000000000000000000000010010 ila_period=32'b00000000000000000000000001001000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDTX_TX_ILA_Z10 @W:CL169 : TX_ILA.v(368) | Pruning unused register genblk4.alignment_sent. Make sure that there are no unused intermediate registers. @N:CG364 : TX_CTRL.v(19) | Synthesizing module CJESDTX_TX_CTRL in library work. F=32'b00000000000000000000000000000010 SCR=32'b00000000000000000000000000000000 SYNC_ST=2'b00 INIT_LANE_ST=2'b01 DATA_ENC_ST=2'b10 SYNC_RESET=32'b00000000000000000000000000000000 D_WIDTH=32'b00000000000000000000000000010000 E_WIDTH=32'b00000000000000000000000000010100 K_WIDTH=32'b00000000000000000000000000000010 ILA_DATA_SEL=32'b00000000000000000000000000000000 Generated name = CJESDTX_TX_CTRL_2s_0s_0_1_2_0s_16s_20s_2s_0 @N:CG179 : TX_CTRL.v(166) | Removing redundant assignment. @N:CG179 : TX_CTRL.v(214) | Removing redundant assignment. @N:CG179 : TX_CTRL.v(215) | Removing redundant assignment. @N:CG364 : JESD204BTX_LANE.v(19) | Synthesizing module CJESDTX_JESD204BTX_LANE in library work. LID=32'b00000000000000000000000000000000 SCR=32'b00000000000000000000000000000000 L=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 M=32'b00000000000000000000000000000001 CS=32'b00000000000000000000000000000000 N=32'b00000000000000000000000000001110 SUBCLASSV=32'b00000000000000000000000000000000 Na=32'b00000000000000000000000000010000 JESDV=32'b00000000000000000000000000000001 S=32'b00000000000000000000000000000010 HD=32'b00000000000000000000000000000000 CF=32'b00000000000000000000000000000000 FIELD_OCTET=32'b00000000000000000000000000000001 ENCODER_EN=32'b00000000000000000000000000000001 D_WIDTH=32'b00000000000000000000000000010000 E_WIDTH=32'b00000000000000000000000000010100 K_WIDTH=32'b00000000000000000000000000000010 DATA_OUT_SIZE=32'b00000000000000000000000000010100 SYNC_RESET=32'b00000000000000000000000000000000 ILA_MFS=32'b00000000000000000000000000000100 SERDES_MODE=32'b00000000000000000000000000000001 ILA_MFE=32'b00000000000000000000000001001000 ILA_DATA_SEL=32'b00000000000000000000000000000000 Generated name = CJESDTX_JESD204BTX_LANE_Z11 @N:CG364 : BUF_DATA.v(1) | Synthesizing module CJESDTX_BUF_DATA in library work. SYNC_RESET=32'b00000000000000000000000000000000 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 Generated name = CJESDTX_BUF_DATA_0s_16s_2s @N:CG364 : ENC_FLIP.v(26) | Synthesizing module CJESDTX_ENC_FLIP in library work. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDTX_ENC_FLIP_0s @N:CG364 : ENC_K.v(53) | Synthesizing module CJESDTX_ENC_K in library work. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDTX_ENC_K_0s @N:CG364 : MUX4X1.v(22) | Synthesizing module CJESDTX_MUX4X1 in library work. @N:CG364 : MUX32X1.v(22) | Synthesizing module CJESDTX_MUX32X1 in library work. @N:CG364 : MUX32X6.v(22) | Synthesizing module CJESDTX_MUX32X6 in library work. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDTX_MUX32X6_0s @W:CL177 : MUX32X6.v(85) | Sharing sequential element SEL_R4. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : MUX32X6.v(85) | Sharing sequential element SEL_R3. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : MUX32X6.v(85) | Sharing sequential element SEL_R2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : MUX32X6.v(85) | Sharing sequential element SEL_R0. Add a syn_preserve attribute to the element to prevent sharing. @W:CL169 : MUX32X6.v(85) | Pruning unused register SEL_R5[1:0]. Make sure that there are no unused intermediate registers. @N:CG364 : ENC_D.v(26) | Synthesizing module CJESDTX_ENC_D in library work. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDTX_ENC_D_0s @N:CG364 : ENCODER_U.v(22) | Synthesizing module CJESDTX_ENCODER_U in library work. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDTX_ENCODER_U_0s @W:CG360 : ENCODER_U.v(58) | Removing wire RST_N0, as there is no assignment to it. @N:CG364 : ENCODER_64B80B.v(19) | Synthesizing module CJESDTX_ENCODER_64B80B in library work. SYNC_RESET=32'b00000000000000000000000000000000 D_WIDTH=32'b00000000000000000000000000010000 K_WIDTH=32'b00000000000000000000000000000010 E_WIDTH=32'b00000000000000000000000000010100 Generated name = CJESDTX_ENCODER_64B80B_0s_16s_2s_20s @N:CG364 : ENCODER_L.v(22) | Synthesizing module CJESDTX_ENCODER_L in library work. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDTX_ENCODER_L_0s @N:CG364 : ENCODER_N.v(22) | Synthesizing module CJESDTX_ENCODER_N in library work. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CJESDTX_ENCODER_N_0s @W:CL169 : ENCODER_N.v(69) | Pruning unused register INV_6B. Make sure that there are no unused intermediate registers. @W:CL169 : ENCODER_N.v(69) | Pruning unused register INV_4B. Make sure that there are no unused intermediate registers. @N:CG364 : CoreJESD204BTX.v(19) | Synthesizing module CoreJESD204BTX in library work. SCR=32'b00000000000000000000000000000000 L=32'b00000000000000000000000000000000 F=32'b00000000000000000000000000000010 K=32'b00000000000000000000000000001001 M=32'b00000000000000000000000000000001 CS=32'b00000000000000000000000000000000 N=32'b00000000000000000000000000001110 SUBCLASSV=32'b00000000000000000000000000000000 Na=32'b00000000000000000000000000010000 JESDV=32'b00000000000000000000000000000001 S=32'b00000000000000000000000000000010 HD=32'b00000000000000000000000000000000 CF=32'b00000000000000000000000000000000 FIELD_OCTET=32'b00000000000000000000000000000001 ENCODER_EN=32'b00000000000000000000000000000001 SERDES_MODE=32'b00000000000000000000000000000001 D_WIDTH=32'b00000000000000000000000000010000 E_WIDTH=32'b00000000000000000000000000010100 K_WIDTH=32'b00000000000000000000000000000010 K_WIDTH_OUT=32'b00000000000000000000000000000010 FAMILY=32'b00000000000000000000000000010011 SYNC_RESET=32'b00000000000000000000000000000000 ILA_MFS=32'b00000000000000000000000000000100 lmfc_period=32'b00000000000000000000000000010010 EPCS_WIDTH=32'b00000000000000000000000000010100 DATA_K_WIDTH=32'b00000000000000000000000000010000 LANE_DATA=32'b00000000000000000000000000010100 DATA_OUT_SIZE=32'b00000000000000000000000000010100 Generated name = CoreJESD204BTX_Z12 @W:CG133 : CoreJESD204BTX.v(181) | Object syncd_rst_n_1 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreJESD204BTX.v(182) | Object syncd_rst_n_2 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreJESD204BTX.v(183) | Object syncd_rst_n_3 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreJESD204BTX.v(184) | Object syncd_rst_n_4 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreJESD204BTX.v(185) | Object syncd_rst_n_5 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreJESD204BTX.v(186) | Object syncd_rst_n_6 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreJESD204BTX.v(187) | Object syncd_rst_n_7 is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : CoreJESD204BTX.v(225) | Removing wire LANE_K_OUT_1, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(226) | Removing wire LANE_K_OUT_2, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(227) | Removing wire LANE_K_OUT_3, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(228) | Removing wire LANE_K_OUT_4, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(229) | Removing wire LANE_K_OUT_5, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(230) | Removing wire LANE_K_OUT_6, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(231) | Removing wire LANE_K_OUT_7, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(233) | Removing wire LANE_DATA_OUT_1, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(234) | Removing wire LANE_DATA_OUT_2, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(235) | Removing wire LANE_DATA_OUT_3, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(236) | Removing wire LANE_DATA_OUT_4, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(237) | Removing wire LANE_DATA_OUT_5, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(238) | Removing wire LANE_DATA_OUT_6, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(239) | Removing wire LANE_DATA_OUT_7, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(241) | Removing wire BUF_DATA_OUT_1, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(242) | Removing wire BUF_DATA_OUT_2, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(243) | Removing wire BUF_DATA_OUT_3, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(244) | Removing wire BUF_DATA_OUT_4, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(245) | Removing wire BUF_DATA_OUT_5, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(246) | Removing wire BUF_DATA_OUT_6, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(247) | Removing wire BUF_DATA_OUT_7, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(261) | Removing wire TX_K_1_int, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(262) | Removing wire TX_K_2_int, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(263) | Removing wire TX_K_3_int, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(264) | Removing wire TX_K_4_int, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(265) | Removing wire TX_K_5_int, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(266) | Removing wire TX_K_6_int, as there is no assignment to it. @W:CG360 : CoreJESD204BTX.v(267) | Removing wire TX_K_7_int, as there is no assignment to it. @N:CG364 : PRBS_GENERATOR.v(19) | Synthesizing module PRBS_GENERATOR in library work. @W:CL169 : PRBS_GENERATOR.v(56) | Pruning unused register data[31:0]. Make sure that there are no unused intermediate registers. @W:CL169 : PRBS_GENERATOR.v(45) | Pruning unused register PRBS_SEL_d[1:0]. Make sure that there are no unused intermediate registers. @W:CL260 : PRBS_GENERATOR.v(56) | Pruning register bit 31 of PRBS[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CG364 : PRBS_WAV_SEL.v(20) | Synthesizing module PRBS_WAV_SEL in library work. @N:CG364 : wav_gen_16bit.v(4) | Synthesizing module waveform_gen in library work. @N:CG179 : wav_gen_16bit.v(156) | Removing redundant assignment. @N:CG364 : DATA_GENERATOR.v(9) | Synthesizing module DATA_GENERATOR in library work. @N:CG364 : DATA_HANDLE_FSM.v(22) | Synthesizing module DATAHANDLE_FSM in library work. @W:CG296 : DATA_HANDLE_FSM.v(152) | Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list. @W:CG290 : DATA_HANDLE_FSM.v(154) | Referenced variable RDATA_EN is not in sensitivity list. @W:CG290 : DATA_HANDLE_FSM.v(155) | Referenced variable DATA_OUT is not in sensitivity list. @W:CG290 : DATA_HANDLE_FSM.v(157) | Referenced variable DATA_OUT1 is not in sensitivity list. @W:CG133 : DATA_HANDLE_FSM.v(110) | Object SEL is declared but not assigned. Either assign a value or remove the declaration. @W:CL208 : DATA_HANDLE_FSM.v(190) | All reachable assignments to bit 4 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization. @W:CL208 : DATA_HANDLE_FSM.v(190) | All reachable assignments to bit 5 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization. @W:CL208 : DATA_HANDLE_FSM.v(190) | All reachable assignments to bit 6 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization. @W:CL208 : DATA_HANDLE_FSM.v(190) | All reachable assignments to bit 7 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization. @W:CL208 : DATA_HANDLE_FSM.v(190) | All reachable assignments to bit 8 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization. @W:CL208 : DATA_HANDLE_FSM.v(190) | All reachable assignments to bit 9 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization. @W:CL208 : DATA_HANDLE_FSM.v(190) | All reachable assignments to bit 10 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization. @W:CL208 : DATA_HANDLE_FSM.v(190) | All reachable assignments to bit 17 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization. @W:CL208 : DATA_HANDLE_FSM.v(190) | All reachable assignments to bit 18 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization. @W:CL208 : DATA_HANDLE_FSM.v(190) | All reachable assignments to bit 19 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization. @W:CL208 : DATA_HANDLE_FSM.v(190) | All reachable assignments to bit 20 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization. @W:CL190 : DATA_HANDLE_FSM.v(199) | Optimizing register bit PREADY to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : DATA_HANDLE_FSM.v(199) | Pruning unused register PREADY. Make sure that there are no unused intermediate registers. @N:CG364 : ERR_GEN.v(19) | Synthesizing module ERR_GEN in library work. @N:CG364 : LED_BLOCK_2.v(19) | Synthesizing module LED_DEBUG_BLK in library work. @W:CG133 : LED_BLOCK_2.v(76) | Object data_0_led is declared but not assigned. Either assign a value or remove the declaration. @N:CG364 : PRBS_CHECKER.v(19) | Synthesizing module PRBS_CHECKER in library work. @W:CL169 : PRBS_CHECKER.v(57) | Pruning unused register PRBS_DATA_p2[15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : PRBS_CHECKER.v(57) | Pruning unused register PRBS_DATA_p3[15:0]. Make sure that there are no unused intermediate registers. @W:CL169 : PRBS_CHECKER.v(57) | Pruning unused register d[31:0]. Make sure that there are no unused intermediate registers. @W:CL169 : PRBS_CHECKER.v(57) | Pruning unused register ec[7:0]. Make sure that there are no unused intermediate registers. @W:CL265 : PRBS_CHECKER.v(57) | Removing unused bit 15 of PRBS_DATA_p1[15:0]. Either assign all bits or reduce the width of the signal. @W:CL271 : PRBS_CHECKER.v(57) | Pruning unused bits 31 to 16 of prbs_15[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL271 : PRBS_CHECKER.v(57) | Pruning unused bits 31 to 16 of prbs_23[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL271 : PRBS_CHECKER.v(57) | Pruning unused bits 31 to 16 of prbs_31[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL271 : PRBS_CHECKER.v(57) | Pruning unused bits 31 to 16 of prbs_7[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : PRBS_CHECKER.v(57) | Pruning register bits 15 to 10 of prbs_7[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @N:CG364 : delay_line.v(19) | Synthesizing module delay_line in library work. @N:CG364 : delay_line.v(48) | Synthesizing module bufd_bus in library work. BUS_WIDTH=32'b00000000000000000000000000010100 Generated name = bufd_bus_20s @N:CG364 : smartfusion2.v(234) | Synthesizing module BUFD in library work. @W:CG133 : delay_line.v(32) | Object j is declared but not assigned. Either assign a value or remove the declaration. @N:CG364 : epcs_rx_intf.v(18) | Synthesizing module epcs_rx_intf in library work. @N:CG364 : epcs_tx_intf.v(19) | Synthesizing module epcs_tx_intf in library work. @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC in library work. @N:CG364 : smartfusion2.v(372) | Synthesizing module GND in library work. @N:CG364 : SERDES_EPCS_SERDES_IF2_0_SERDES_IF2_syn.v(5) | Synthesizing module SERDESIF_075 in library work. @N:CG364 : SERDES_EPCS_SERDES_IF2_0_SERDES_IF2.v(5) | Synthesizing module SERDES_EPCS_SERDES_IF2_0_SERDES_IF2 in library work. @N:CG364 : SERDES_EPCS.v(9) | Synthesizing module SERDES_EPCS in library work. @N:CG364 : smartfusion2.v(727) | Synthesizing module CCC in library work. @N:CG364 : SF2_JESD204B_DEMO_sb_CCC_0_FCCC.v(5) | Synthesizing module SF2_JESD204B_DEMO_sb_CCC_0_FCCC in library work. @W:CG775 : coreapb3.v(31) | Found Component CoreAPB3 in library COREAPB3_LIB @N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3 in library COREAPB3_LIB. @N:CG364 : coreapb3.v(31) | Synthesizing module CoreAPB3 in library COREAPB3_LIB. APB_DWIDTH=6'b100000 IADDR_OPTION=32'b00000000000000000000000000000000 APBSLOT0ENABLE=1'b1 APBSLOT1ENABLE=1'b0 APBSLOT2ENABLE=1'b0 APBSLOT3ENABLE=1'b0 APBSLOT4ENABLE=1'b0 APBSLOT5ENABLE=1'b0 APBSLOT6ENABLE=1'b0 APBSLOT7ENABLE=1'b0 APBSLOT8ENABLE=1'b0 APBSLOT9ENABLE=1'b0 APBSLOT10ENABLE=1'b0 APBSLOT11ENABLE=1'b0 APBSLOT12ENABLE=1'b0 APBSLOT13ENABLE=1'b0 APBSLOT14ENABLE=1'b0 APBSLOT15ENABLE=1'b0 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 MADDR_BITS=6'b010000 UPR_NIBBLE_POSN=4'b0011 FAMILY=32'b00000000000000000000000000010011 SYNC_RESET=32'b00000000000000000000000000000000 IADDR_NOTINUSE=32'b00000000000000000000000000000000 IADDR_EXTERNAL=32'b00000000000000000000000000000001 IADDR_SLOT0=32'b00000000000000000000000000000010 IADDR_SLOT1=32'b00000000000000000000000000000011 IADDR_SLOT2=32'b00000000000000000000000000000100 IADDR_SLOT3=32'b00000000000000000000000000000101 IADDR_SLOT4=32'b00000000000000000000000000000110 IADDR_SLOT5=32'b00000000000000000000000000000111 IADDR_SLOT6=32'b00000000000000000000000000001000 IADDR_SLOT7=32'b00000000000000000000000000001001 IADDR_SLOT8=32'b00000000000000000000000000001010 IADDR_SLOT9=32'b00000000000000000000000000001011 IADDR_SLOT10=32'b00000000000000000000000000001100 IADDR_SLOT11=32'b00000000000000000000000000001101 IADDR_SLOT12=32'b00000000000000000000000000001110 IADDR_SLOT13=32'b00000000000000000000000000001111 IADDR_SLOT14=32'b00000000000000000000000000010000 IADDR_SLOT15=32'b00000000000000000000000000010001 SL0=16'b0000000000000001 SL1=16'b0000000000000000 SL2=16'b0000000000000000 SL3=16'b0000000000000000 SL4=16'b0000000000000000 SL5=16'b0000000000000000 SL6=16'b0000000000000000 SL7=16'b0000000000000000 SL8=16'b0000000000000000 SL9=16'b0000000000000000 SL10=16'b0000000000000000 SL11=16'b0000000000000000 SL12=16'b0000000000000000 SL13=16'b0000000000000000 SL14=16'b0000000000000000 SL15=16'b0000000000000000 SC=16'b0000000000000000 SC_qual=16'b0000000000000000 Generated name = CoreAPB3_Z13 @W:CG360 : coreapb3.v(244) | Removing wire IA_PRDATA, as there is no assignment to it. @N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP in library work. FAMILY=32'b00000000000000000000000000010011 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000001 VERSION_MAJOR=32'b00000000000000000000000000000111 VERSION_MINOR=32'b00000000000000000000000000000000 VERSION_MAJOR_VECTOR=16'b0000000000000111 VERSION_MINOR_VECTOR=16'b0000000000000000 S0=2'b00 S1=2'b01 S2=2'b10 Generated name = CoreConfigP_Z14 @W:CL207 : coreconfigp.v(461) | All reachable assignments to SDIF1_PENABLE assign 0, register removed by optimization. @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP in library work. FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000001 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z15 @W:CL169 : coreresetp.v(1613) | Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1581) | Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1549) | Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1517) | Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1365) | Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1300) | Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1235) | Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1089) | Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers. @W:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : coreresetp.v(1089) | Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers. @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB in library work. @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ in library work. @N:CG364 : SF2_JESD204B_DEMO_sb_FABOSC_0_OSC.v(5) | Synthesizing module SF2_JESD204B_DEMO_sb_FABOSC_0_OSC in library work. @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF in library work. @N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF in library work. @N:CG364 : SF2_JESD204B_DEMO_sb_MSS_syn.v(5) | Synthesizing module MSS_075 in library work. @N:CG364 : SF2_JESD204B_DEMO_sb_MSS.v(9) | Synthesizing module SF2_JESD204B_DEMO_sb_MSS in library work. @N:CG364 : smartfusion2.v(718) | Synthesizing module SYSRESET in library work. @N:CG364 : SF2_JESD204B_DEMO_sb.v(9) | Synthesizing module SF2_JESD204B_DEMO_sb in library work. @N:CG364 : smartfusion2.v(382) | Synthesizing module RAM1K18 in library work. @N:CG364 : SF2_JESD204B_DEMO_TPSRAM_0_TPSRAM.v(5) | Synthesizing module SF2_JESD204B_DEMO_TPSRAM_0_TPSRAM in library work. @N:CG364 : SF2_JESD204B_DEMO_TPSRAM_1_TPSRAM.v(5) | Synthesizing module SF2_JESD204B_DEMO_TPSRAM_1_TPSRAM in library work. @N:CG364 : SF2_JESD204B_DEMO.v(9) | Synthesizing module SF2_JESD204B_DEMO in library work. @W:CL157 : SF2_JESD204B_DEMO_sb_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : SF2_JESD204B_DEMO_sb_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : SF2_JESD204B_DEMO_sb_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : SF2_JESD204B_DEMO_sb_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @N:CL159 : SF2_JESD204B_DEMO_sb_FABOSC_0_OSC.v(14) | Input XTL is unused. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state. Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state. Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state. Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state. Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state. Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @N:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused. @N:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused. @N:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused. @N:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused. @N:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused. @N:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused. @N:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused. @N:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused. @N:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused. @N:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused. @N:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused. @N:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused. @N:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused. @N:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused. @N:CL201 : coreconfigp.v(447) | Trying to extract state machine for register state. Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL159 : coreconfigp.v(71) | Input SDIF1_PREADY is unused. @N:CL159 : coreconfigp.v(72) | Input SDIF1_PSLVERR is unused. @N:CL159 : coreapb3.v(72) | Input IADDR is unused. @N:CL159 : coreapb3.v(73) | Input PRESETN is unused. @N:CL159 : coreapb3.v(74) | Input PCLK is unused. @N:CL159 : coreapb3.v(105) | Input PRDATAS1 is unused. @N:CL159 : coreapb3.v(106) | Input PRDATAS2 is unused. @N:CL159 : coreapb3.v(107) | Input PRDATAS3 is unused. @N:CL159 : coreapb3.v(108) | Input PRDATAS4 is unused. @N:CL159 : coreapb3.v(109) | Input PRDATAS5 is unused. @N:CL159 : coreapb3.v(110) | Input PRDATAS6 is unused. @N:CL159 : coreapb3.v(111) | Input PRDATAS7 is unused. @N:CL159 : coreapb3.v(112) | Input PRDATAS8 is unused. @N:CL159 : coreapb3.v(113) | Input PRDATAS9 is unused. @N:CL159 : coreapb3.v(114) | Input PRDATAS10 is unused. @N:CL159 : coreapb3.v(115) | Input PRDATAS11 is unused. @N:CL159 : coreapb3.v(116) | Input PRDATAS12 is unused. @N:CL159 : coreapb3.v(117) | Input PRDATAS13 is unused. @N:CL159 : coreapb3.v(118) | Input PRDATAS14 is unused. @N:CL159 : coreapb3.v(119) | Input PRDATAS15 is unused. @N:CL159 : coreapb3.v(122) | Input PREADYS1 is unused. @N:CL159 : coreapb3.v(123) | Input PREADYS2 is unused. @N:CL159 : coreapb3.v(124) | Input PREADYS3 is unused. @N:CL159 : coreapb3.v(125) | Input PREADYS4 is unused. @N:CL159 : coreapb3.v(126) | Input PREADYS5 is unused. @N:CL159 : coreapb3.v(127) | Input PREADYS6 is unused. @N:CL159 : coreapb3.v(128) | Input PREADYS7 is unused. @N:CL159 : coreapb3.v(129) | Input PREADYS8 is unused. @N:CL159 : coreapb3.v(130) | Input PREADYS9 is unused. @N:CL159 : coreapb3.v(131) | Input PREADYS10 is unused. @N:CL159 : coreapb3.v(132) | Input PREADYS11 is unused. @N:CL159 : coreapb3.v(133) | Input PREADYS12 is unused. @N:CL159 : coreapb3.v(134) | Input PREADYS13 is unused. @N:CL159 : coreapb3.v(135) | Input PREADYS14 is unused. @N:CL159 : coreapb3.v(136) | Input PREADYS15 is unused. @N:CL159 : coreapb3.v(139) | Input PSLVERRS1 is unused. @N:CL159 : coreapb3.v(140) | Input PSLVERRS2 is unused. @N:CL159 : coreapb3.v(141) | Input PSLVERRS3 is unused. @N:CL159 : coreapb3.v(142) | Input PSLVERRS4 is unused. @N:CL159 : coreapb3.v(143) | Input PSLVERRS5 is unused. @N:CL159 : coreapb3.v(144) | Input PSLVERRS6 is unused. @N:CL159 : coreapb3.v(145) | Input PSLVERRS7 is unused. @N:CL159 : coreapb3.v(146) | Input PSLVERRS8 is unused. @N:CL159 : coreapb3.v(147) | Input PSLVERRS9 is unused. @N:CL159 : coreapb3.v(148) | Input PSLVERRS10 is unused. @N:CL159 : coreapb3.v(149) | Input PSLVERRS11 is unused. @N:CL159 : coreapb3.v(150) | Input PSLVERRS12 is unused. @N:CL159 : coreapb3.v(151) | Input PSLVERRS13 is unused. @N:CL159 : coreapb3.v(152) | Input PSLVERRS14 is unused. @N:CL159 : coreapb3.v(153) | Input PSLVERRS15 is unused. @N:CL159 : LED_BLOCK_2.v(53) | Input SOMF_L is unused. @N:CL201 : DATA_HANDLE_FSM.v(199) | Trying to extract state machine for register fsm. Extracted state machine for register fsm State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL246 : DATA_HANDLE_FSM.v(69) | Input port bits 15 to 13 of PADDR[15:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : DATA_HANDLE_FSM.v(69) | Input port bits 1 to 0 of PADDR[15:0] are unused. Assign logic for all port bits or change the input port size. @A:CL153 : DATA_HANDLE_FSM.v(110) | *Unassigned bits of SEL are referenced and tied to 0 -- simulation mismatch possible. @N:CL159 : DATA_HANDLE_FSM.v(68) | Input PENABLE is unused. @N:CL159 : DATA_HANDLE_FSM.v(70) | Input PWDATA is unused. @W:CL157 : CoreJESD204BTX.v(147) | *Output EPCS_1_TX_DATA has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BTX.v(148) | *Output EPCS_2_TX_DATA has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BTX.v(149) | *Output EPCS_3_TX_DATA has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BTX.v(150) | *Output EPCS_4_TX_DATA has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BTX.v(151) | *Output EPCS_5_TX_DATA has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BTX.v(152) | *Output EPCS_6_TX_DATA has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BTX.v(153) | *Output EPCS_7_TX_DATA has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BTX.v(189) | *Output TX_K_1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BTX.v(190) | *Output TX_K_2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BTX.v(191) | *Output TX_K_3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BTX.v(192) | *Output TX_K_4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BTX.v(193) | *Output TX_K_5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BTX.v(194) | *Output TX_K_6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BTX.v(195) | *Output TX_K_7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @N:CL159 : CoreJESD204BTX.v(121) | Input DATA_IN_1 is unused. @N:CL159 : CoreJESD204BTX.v(122) | Input DATA_IN_2 is unused. @N:CL159 : CoreJESD204BTX.v(123) | Input DATA_IN_3 is unused. @N:CL159 : CoreJESD204BTX.v(124) | Input DATA_IN_4 is unused. @N:CL159 : CoreJESD204BTX.v(125) | Input DATA_IN_5 is unused. @N:CL159 : CoreJESD204BTX.v(126) | Input DATA_IN_6 is unused. @N:CL159 : CoreJESD204BTX.v(127) | Input DATA_IN_7 is unused. @N:CL159 : CoreJESD204BTX.v(133) | Input EPCS_1_TX_CLK is unused. @N:CL159 : CoreJESD204BTX.v(134) | Input EPCS_2_TX_CLK is unused. @N:CL159 : CoreJESD204BTX.v(135) | Input EPCS_3_TX_CLK is unused. @N:CL159 : CoreJESD204BTX.v(136) | Input EPCS_4_TX_CLK is unused. @N:CL159 : CoreJESD204BTX.v(137) | Input EPCS_5_TX_CLK is unused. @N:CL159 : CoreJESD204BTX.v(138) | Input EPCS_6_TX_CLK is unused. @N:CL159 : CoreJESD204BTX.v(139) | Input EPCS_7_TX_CLK is unused. @W:CL260 : ENC_K.v(163) | Pruning register bit 1 of K_SEL[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL189 : ENC_K.v(163) | Register bit KCODE_6B[1] is always 1. @W:CL260 : ENC_K.v(163) | Pruning register bit 1 of KCODE_6B[5:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL201 : TX_CTRL.v(104) | Trying to extract state machine for register TX_STATE. Extracted state machine for register TX_STATE State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL159 : TX_CTRL.v(54) | Input OCTET_FC is unused. @N:CL159 : TX_CTRL.v(55) | Input OCTET_7C is unused. @W:CL190 : TX_ILA.v(300) | Optimizing register bit ILAValue_0[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : TX_ILA.v(300) | Pruning register bit 0 of ILAValue_0[6:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL247 : TX_ILA.v(100) | Input port bit 0 of MULTI_FRAME_START[1:0] is unused @W:CL247 : TX_ILA.v(101) | Input port bit 1 of MULTI_FRAME_END[1:0] is unused @N:CL159 : TX_ILA.v(93) | Input LMFC is unused. @N:CL159 : TX_ILA.v(99) | Input FRAME_END is unused. @W:CL190 : TX_ACG.v(2137) | Optimizing register bit genblk6.OCount_U[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : TX_ACG.v(2137) | Pruning unused register genblk6.OCount_U[0]. Make sure that there are no unused intermediate registers. @N:CL134 : DATA_SYNC_BUF_TX.v(255) | Found RAM data, depth=4, width=20 @N:CL134 : DATA_SYNC_BUF_TX.v(255) | Found RAM k, depth=4, width=2 @W:CL190 : CLOCK_GEN_TX.v(206) | Optimizing register bit genblk2.FC_PHASE[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CLOCK_GEN_TX.v(158) | Optimizing register bit genblk2.LMFC_PHASE[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : CLOCK_GEN_TX.v(158) | Pruning register bit 0 of genblk2.LMFC_PHASE[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : CLOCK_GEN_TX.v(206) | Pruning register bit 0 of genblk2.FC_PHASE[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL189 : CLOCK_GEN_TX.v(206) | Register bit genblk2.FC_PHASE[1] is always 0. @W:CL169 : CLOCK_GEN_TX.v(206) | Pruning unused register genblk2.FC_PHASE[1]. Make sure that there are no unused intermediate registers. @N:CL159 : CLOCK_GEN_TX.v(53) | Input SYSREF_IN is unused. @N:CL159 : CLOCK_GEN_TX.v(54) | Input SYNC_N is unused. @N:CL159 : SYNC_DEC.v(51) | Input LMFC is unused. @N:CL159 : SYNC_DEC.v(53) | Input FORCE_SYNC is unused. @N:CL134 : DATA_SYNC_BUF.v(91) | Found RAM data_buf, depth=3, width=20 @N:CL134 : DATA_SYNC_BUF.v(91) | Found RAM k_buf, depth=3, width=2 @N:CL134 : DATA_SYNC_BUF.v(91) | Found RAM valid_buf, depth=3, width=2 @W:CL156 : CoreJESD204BRX.v(368) | *Input k_in_0[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : CoreJESD204BRX.v(360) | *Input valid_in_0[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL157 : CoreJESD204BRX.v(252) | *Output DATA_OUT_1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(253) | *Output DATA_OUT_2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(254) | *Output DATA_OUT_3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(255) | *Output DATA_OUT_4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(256) | *Output DATA_OUT_5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(257) | *Output DATA_OUT_6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(258) | *Output DATA_OUT_7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(260) | *Output SOF_1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(261) | *Output SOF_2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(262) | *Output SOF_3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(263) | *Output SOF_4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(264) | *Output SOF_5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(265) | *Output SOF_6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(266) | *Output SOF_7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(268) | *Output SOMF_1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(269) | *Output SOMF_2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(270) | *Output SOMF_3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(271) | *Output SOMF_4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(272) | *Output SOMF_5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(273) | *Output SOMF_6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(274) | *Output SOMF_7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(284) | *Output RX_STATE_1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(285) | *Output RX_STATE_2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(286) | *Output RX_STATE_3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(287) | *Output RX_STATE_4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(288) | *Output RX_STATE_5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(289) | *Output RX_STATE_6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : CoreJESD204BRX.v(290) | *Output RX_STATE_7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @N:CL159 : CoreJESD204BRX.v(185) | Input EPCS_1_RX_DATA is unused. @N:CL159 : CoreJESD204BRX.v(186) | Input EPCS_2_RX_DATA is unused. @N:CL159 : CoreJESD204BRX.v(187) | Input EPCS_3_RX_DATA is unused. @N:CL159 : CoreJESD204BRX.v(188) | Input EPCS_4_RX_DATA is unused. @N:CL159 : CoreJESD204BRX.v(189) | Input EPCS_5_RX_DATA is unused. @N:CL159 : CoreJESD204BRX.v(190) | Input EPCS_6_RX_DATA is unused. @N:CL159 : CoreJESD204BRX.v(191) | Input EPCS_7_RX_DATA is unused. @N:CL159 : CoreJESD204BRX.v(194) | Input EPCS_1_RX_CLK is unused. @N:CL159 : CoreJESD204BRX.v(195) | Input EPCS_2_RX_CLK is unused. @N:CL159 : CoreJESD204BRX.v(196) | Input EPCS_3_RX_CLK is unused. @N:CL159 : CoreJESD204BRX.v(197) | Input EPCS_4_RX_CLK is unused. @N:CL159 : CoreJESD204BRX.v(198) | Input EPCS_5_RX_CLK is unused. @N:CL159 : CoreJESD204BRX.v(199) | Input EPCS_6_RX_CLK is unused. @N:CL159 : CoreJESD204BRX.v(200) | Input EPCS_7_RX_CLK is unused. @N:CL159 : CoreJESD204BRX.v(202) | Input EPCS_1_RX_VAL is unused. @N:CL159 : CoreJESD204BRX.v(203) | Input EPCS_2_RX_VAL is unused. @N:CL159 : CoreJESD204BRX.v(204) | Input EPCS_3_RX_VAL is unused. @N:CL159 : CoreJESD204BRX.v(205) | Input EPCS_4_RX_VAL is unused. @N:CL159 : CoreJESD204BRX.v(206) | Input EPCS_5_RX_VAL is unused. @N:CL159 : CoreJESD204BRX.v(207) | Input EPCS_6_RX_VAL is unused. @N:CL159 : CoreJESD204BRX.v(208) | Input EPCS_7_RX_VAL is unused. @N:CL159 : CoreJESD204BRX.v(210) | Input RX_DATA_0 is unused. @N:CL159 : CoreJESD204BRX.v(211) | Input RX_DATA_1 is unused. @N:CL159 : CoreJESD204BRX.v(212) | Input RX_DATA_2 is unused. @N:CL159 : CoreJESD204BRX.v(213) | Input RX_DATA_3 is unused. @N:CL159 : CoreJESD204BRX.v(214) | Input RX_DATA_4 is unused. @N:CL159 : CoreJESD204BRX.v(215) | Input RX_DATA_5 is unused. @N:CL159 : CoreJESD204BRX.v(216) | Input RX_DATA_6 is unused. @N:CL159 : CoreJESD204BRX.v(217) | Input RX_DATA_7 is unused. @N:CL159 : CoreJESD204BRX.v(219) | Input RX_K_0 is unused. @N:CL159 : CoreJESD204BRX.v(220) | Input RX_K_1 is unused. @N:CL159 : CoreJESD204BRX.v(221) | Input RX_K_2 is unused. @N:CL159 : CoreJESD204BRX.v(222) | Input RX_K_3 is unused. @N:CL159 : CoreJESD204BRX.v(223) | Input RX_K_4 is unused. @N:CL159 : CoreJESD204BRX.v(224) | Input RX_K_5 is unused. @N:CL159 : CoreJESD204BRX.v(225) | Input RX_K_6 is unused. @N:CL159 : CoreJESD204BRX.v(226) | Input RX_K_7 is unused. @N:CL159 : CoreJESD204BRX.v(228) | Input RX_CODE_VIOLATION_0 is unused. @N:CL159 : CoreJESD204BRX.v(229) | Input RX_CODE_VIOLATION_1 is unused. @N:CL159 : CoreJESD204BRX.v(230) | Input RX_CODE_VIOLATION_2 is unused. @N:CL159 : CoreJESD204BRX.v(231) | Input RX_CODE_VIOLATION_3 is unused. @N:CL159 : CoreJESD204BRX.v(232) | Input RX_CODE_VIOLATION_4 is unused. @N:CL159 : CoreJESD204BRX.v(233) | Input RX_CODE_VIOLATION_5 is unused. @N:CL159 : CoreJESD204BRX.v(234) | Input RX_CODE_VIOLATION_6 is unused. @N:CL159 : CoreJESD204BRX.v(235) | Input RX_CODE_VIOLATION_7 is unused. @N:CL159 : CoreJESD204BRX.v(237) | Input RX_DISP_ERR_0 is unused. @N:CL159 : CoreJESD204BRX.v(238) | Input RX_DISP_ERR_1 is unused. @N:CL159 : CoreJESD204BRX.v(239) | Input RX_DISP_ERR_2 is unused. @N:CL159 : CoreJESD204BRX.v(240) | Input RX_DISP_ERR_3 is unused. @N:CL159 : CoreJESD204BRX.v(241) | Input RX_DISP_ERR_4 is unused. @N:CL159 : CoreJESD204BRX.v(242) | Input RX_DISP_ERR_5 is unused. @N:CL159 : CoreJESD204BRX.v(243) | Input RX_DISP_ERR_6 is unused. @N:CL159 : CoreJESD204BRX.v(244) | Input RX_DISP_ERR_7 is unused. @N:CL159 : DEC_RD_L.v(26) | Input RBC1 is unused. @N:CL159 : DEC_RD_L.v(27) | Input RESET_L is unused. @W:CL260 : WORD_ALIGNER.v(188) | Pruning register bit 2 of wa_sel_d_mon[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL189 : WORD_ALIGNER.v(188) | Register bit wa_sel_d_mon[1] is always 0. @W:CL177 : WORD_ALIGNER.v(458) | Sharing sequential element D1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : WORD_ALIGNER.v(458) | Sharing sequential element D2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : WORD_ALIGNER.v(458) | Sharing sequential element D3. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : WORD_ALIGNER.v(458) | Sharing sequential element D4. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : WORD_ALIGNER.v(458) | Sharing sequential element D5. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : WORD_ALIGNER.v(458) | Sharing sequential element D6. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : WORD_ALIGNER.v(458) | Sharing sequential element D7. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : WORD_ALIGNER.v(458) | Sharing sequential element D8. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : WORD_ALIGNER.v(458) | Sharing sequential element D9. Add a syn_preserve attribute to the element to prevent sharing. @W:CL260 : WORD_ALIGNER.v(188) | Pruning register bit 1 of wa_sel_d_mon[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL201 : WORD_ALIGNER.v(769) | Trying to extract state machine for register WA_FSM_STATE. Extracted state machine for register WA_FSM_STATE State machine has 4 reachable states with original encodings of: 00 01 10 11 @N:CL201 : SYNC_FSM.v(50) | Trying to extract state machine for register SYNC_STATE. Extracted state machine for register SYNC_STATE State machine has 5 reachable states with original encodings of: 000 001 010 011 100 @N:CL159 : JESD204BRX_LANE.v(96) | Input K_IN is unused. @N:CL159 : JESD204BRX_LANE.v(97) | Input VALID_IN is unused. @W:CL190 : IFS_POS.v(4385) | Optimizing register bit genblk6.ILAValue[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(198) | Optimizing register bit Kcounter[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(198) | Optimizing register bit Kcounter[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : IFS_POS.v(198) | Optimizing register bit Kcounter[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL279 : IFS_POS.v(198) | Pruning register bits 4 to 3 of Kcounter[4:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : IFS_POS.v(198) | Pruning register bit 0 of Kcounter[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : IFS_POS.v(4385) | Pruning register bit 0 of genblk6.ILAValue[6:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL201 : IFS_POS.v(295) | Trying to extract state machine for register CC_state. Extracted state machine for register CC_state State machine has 2 reachable states with original encodings of: 00 01 @N:CL201 : IFS_POS.v(198) | Trying to extract state machine for register FS_STATE. Extracted state machine for register FS_STATE State machine has 4 reachable states with original encodings of: 00 01 10 11 @N:CL159 : FL_AMC.v(71) | Input FCOUNT_L_1 is unused. @N:CL159 : FL_AMC.v(72) | Input FCOUNT_L_2 is unused. @N:CL159 : FL_AMC.v(73) | Input FCOUNT_L_3 is unused. @N:CL159 : FL_AMC.v(74) | Input FCOUNT_L_4 is unused. @N:CL159 : FL_AMC.v(75) | Input FCOUNT_L_5 is unused. @N:CL159 : FL_AMC.v(76) | Input FCOUNT_L_6 is unused. @N:CL159 : FL_AMC.v(79) | Input OCOUNT_L_1 is unused. @N:CL159 : FL_AMC.v(80) | Input OCOUNT_L_2 is unused. @N:CL159 : FL_AMC.v(81) | Input OCOUNT_L_3 is unused. @N:CL159 : FL_AMC.v(82) | Input OCOUNT_L_4 is unused. @N:CL159 : FL_AMC.v(83) | Input OCOUNT_L_5 is unused. @N:CL159 : FL_AMC.v(84) | Input OCOUNT_L_6 is unused. @W:CL190 : LINK_COMP.v(370) | Optimizing register bit genblk6.map_cnt[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : LINK_COMP.v(370) | Pruning register bit 0 of genblk6.map_cnt[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL201 : LINK_COMP.v(294) | Trying to extract state machine for register CD_M_state. Extracted state machine for register CD_M_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @N:CL201 : ILA_FSM.v(502) | Trying to extract state machine for register RIstate. Extracted state machine for register RIstate State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL201 : ILA_FSM.v(304) | Trying to extract state machine for register ILA_state. Extracted state machine for register ILA_state State machine has 5 reachable states with original encodings of: 000 001 010 011 100 @N:CL159 : ILA_FSM.v(54) | Input LMFC is unused. @N:CL135 : RX_CTRL.v(149) | Found sequential shift mf_phase_reg with address depth of 4 words and data bit width of 5. @N:CL135 : RX_CTRL.v(149) | Found sequential shift f_phase_reg with address depth of 4 words and data bit width of 2. @N:CL135 : ADJ_CTRL.v(112) | Found sequential shift mf_phase_reg with address depth of 3 words and data bit width of 5. @N:CL135 : ADJ_CTRL.v(112) | Found sequential shift f_phase_reg with address depth of 3 words and data bit width of 2. @N:CL159 : ADJ_CTRL.v(61) | Input F_PHASE_ST is unused. @N:CL159 : ADJ_CTRL.v(62) | Input LMFC_CNT is unused. @N:CL159 : ADJ_CTRL.v(63) | Input FC_CNT is unused. @N:CL201 : CGS.v(370) | Trying to extract state machine for register CG_state. Extracted state machine for register CG_state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL190 : CLOCK_GEN_RX.v(351) | Optimizing register bit genblk3.F_PHASE[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CLOCK_GEN_RX.v(303) | Optimizing register bit genblk3.MF_PHASE[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : CLOCK_GEN_RX.v(303) | Pruning register bit 0 of genblk3.MF_PHASE[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : CLOCK_GEN_RX.v(351) | Pruning register bit 0 of genblk3.F_PHASE[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL189 : CLOCK_GEN_RX.v(351) | Register bit genblk3.F_PHASE[1] is always 0. @W:CL169 : CLOCK_GEN_RX.v(351) | Pruning unused register genblk3.F_PHASE[1]. Make sure that there are no unused intermediate registers. @N:CL159 : CLOCK_GEN_RX.v(58) | Input SYSREF_IN is unused. @N:CL159 : CLOCK_GEN_RX.v(59) | Input SYNC_N is unused. @N:CL159 : CLOCK_GEN_RX.v(60) | Input ERR_DET is unused. @N:CL201 : SYNC_ENC.v(81) | Trying to extract state machine for register SYNC_GEN_ST. Extracted state machine for register SYNC_GEN_ST State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL159 : SYNC_ENC.v(48) | Input LMFC is unused. At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 107MB peak: 125MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Mar 14 16:14:16 2017 ###########################################################] Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 79MB peak: 80MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Mar 14 16:14:16 2017 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime Process completed successfully. # Tue Mar 14 16:14:16 2017 ###########################################################] Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode File D:\11.7_SP3_Validate\synplify_J201503MSP1-2\bin64\syn_nfilter.exe changed - recompiling File D:\11.7_SP3_Validate\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\synthesis\synwork\SF2_JESD204B_DEMO_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 84MB peak: 85MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Mar 14 16:14:18 2017 ###########################################################] Pre-mapping Report # Tue Mar 14 16:14:18 2017 Synopsys Generic Technology Pre-mapping, Version map201609actrcp1, Build 005R, Built Jan 25 2017 01:01:33 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.09M-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Reading constraint file: D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\synthesis\SF2_JESD204B_DEMO_syn.fdc Linked File: SF2_JESD204B_DEMO_scck.rpt Printing clock summary report in "D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\synthesis\SF2_JESD204B_DEMO_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 129MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 129MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 129MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 129MB) @W:BN132 : coreresetp.v(1089) | Removing sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MO111 : corejesd204brx.v(252) | Tristate driver DATA_OUT_1_1 (in view: work.CoreJESD204BRX_Z9(verilog)) on net DATA_OUT_1_1 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND. @N:MO111 : corejesd204brx.v(252) | Tristate driver DATA_OUT_1_2 (in view: work.CoreJESD204BRX_Z9(verilog)) on net DATA_OUT_1_2 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND. @N:MO111 : corejesd204brx.v(252) | Tristate driver DATA_OUT_1_3 (in view: work.CoreJESD204BRX_Z9(verilog)) on net DATA_OUT_1_3 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND. @N:MO111 : corejesd204brx.v(252) | Tristate driver DATA_OUT_1_4 (in view: work.CoreJESD204BRX_Z9(verilog)) on net DATA_OUT_1_4 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND. @N:MO111 : corejesd204brx.v(252) | Tristate driver DATA_OUT_1_5 (in view: work.CoreJESD204BRX_Z9(verilog)) on net DATA_OUT_1_5 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND. @N:MO111 : corejesd204brx.v(252) | Tristate driver DATA_OUT_1_6 (in view: work.CoreJESD204BRX_Z9(verilog)) on net DATA_OUT_1_6 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND. @N:MO111 : corejesd204brx.v(252) | Tristate driver DATA_OUT_1_7 (in view: work.CoreJESD204BRX_Z9(verilog)) on net DATA_OUT_1_7 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND. @N:MO111 : corejesd204brx.v(252) | Tristate driver DATA_OUT_1_8 (in view: work.CoreJESD204BRX_Z9(verilog)) on net DATA_OUT_1_8 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND. @N:MO111 : corejesd204brx.v(252) | Tristate driver DATA_OUT_1_9 (in view: work.CoreJESD204BRX_Z9(verilog)) on net DATA_OUT_1_9 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND. @N:MO111 : corejesd204brx.v(252) | Tristate driver DATA_OUT_1_10 (in view: work.CoreJESD204BRX_Z9(verilog)) on net DATA_OUT_1_10 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND. @W:MO129 : coreresetp.v(676) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(1388) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation. @N:BN115 : mux32x1.v(85) | Removing instance UT1B5 (in view: work.CJESDTX_MUX32X1_3_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_15_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(86) | Removing instance UT1B6 (in view: work.CJESDTX_MUX32X1_3_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_14_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(87) | Removing instance UT1B7 (in view: work.CJESDTX_MUX32X1_3_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_13_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(83) | Removing instance UT1B3 (in view: work.CJESDTX_MUX32X1_2_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_27_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(84) | Removing instance UT1B4 (in view: work.CJESDTX_MUX32X1_2_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_26_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(85) | Removing instance UT1B5 (in view: work.CJESDTX_MUX32X1_2_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_25_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(81) | Removing instance UT1B1 (in view: work.CJESDTX_MUX32X1_1_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_39_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(82) | Removing instance UT1B2 (in view: work.CJESDTX_MUX32X1_1_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_38_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(84) | Removing instance UT1B4 (in view: work.CJESDTX_MUX32X1_1_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_36_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(85) | Removing instance UT1B5 (in view: work.CJESDTX_MUX32X1_1_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_35_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(86) | Removing instance UT1B6 (in view: work.CJESDTX_MUX32X1_1_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_34_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(87) | Removing instance UT1B7 (in view: work.CJESDTX_MUX32X1_1_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_33_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(92) | Removing instance UT2B1 (in view: work.CJESDTX_MUX32X1_1_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_31_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(80) | Removing instance UT1B0 (in view: work.CJESDTX_MUX32X1_0_0(verilog)) of type view:work.CJESDTX_MUX4X1_9_50_0(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(85) | Removing instance UT1B5 (in view: work.CJESDTX_MUX32X1_3_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_15_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(86) | Removing instance UT1B6 (in view: work.CJESDTX_MUX32X1_3_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_14_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(87) | Removing instance UT1B7 (in view: work.CJESDTX_MUX32X1_3_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_13_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(83) | Removing instance UT1B3 (in view: work.CJESDTX_MUX32X1_2_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_27_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(84) | Removing instance UT1B4 (in view: work.CJESDTX_MUX32X1_2_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_26_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(85) | Removing instance UT1B5 (in view: work.CJESDTX_MUX32X1_2_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_25_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(81) | Removing instance UT1B1 (in view: work.CJESDTX_MUX32X1_1_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_39_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(82) | Removing instance UT1B2 (in view: work.CJESDTX_MUX32X1_1_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_38_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(84) | Removing instance UT1B4 (in view: work.CJESDTX_MUX32X1_1_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_36_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(85) | Removing instance UT1B5 (in view: work.CJESDTX_MUX32X1_1_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_35_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(86) | Removing instance UT1B6 (in view: work.CJESDTX_MUX32X1_1_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_34_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(87) | Removing instance UT1B7 (in view: work.CJESDTX_MUX32X1_1_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_33_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(92) | Removing instance UT2B1 (in view: work.CJESDTX_MUX32X1_1_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_31_1(verilog) because it does not drive other instances. @N:BN115 : mux32x1.v(80) | Removing instance UT1B0 (in view: work.CJESDTX_MUX32X1_0_1(verilog)) of type view:work.CJESDTX_MUX4X1_9_50_1(verilog) because it does not drive other instances. @N:BN362 : enc_k.v(163) | Removing sequential instance K_ERR (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(163) | Removing sequential instance KCODE_6B_1[0] (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances. @N:BN362 : enc_k.v(163) | Removing sequential instance KCODE_6B_1[5:2] (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffpatr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(163) | Removing sequential instance KCODE_4B[3:0] (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffpatr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(163) | Removing sequential instance SP_4B_RDP (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(163) | Removing sequential instance SP_4B_RDN (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_flip.v(89) | Removing sequential instance EN_INV_6B (in view: work.CJESDTX_ENC_FLIP_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_flip.v(89) | Removing sequential instance EN_INV_4B (in view: work.CJESDTX_ENC_FLIP_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_flip.v(89) | Removing sequential instance INV_4B_RD (in view: work.CJESDTX_ENC_FLIP_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : encoder_u.v(84) | Removing sequential instance INVALID_K (in view: work.CJESDTX_ENCODER_U_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : encoder_l.v(83) | Removing sequential instance INVALID_K (in view: work.CJESDTX_ENCODER_L_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance MDDR_PENABLE (in view: work.CoreConfigP_Z14(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE (in view: work.CoreConfigP_Z14(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE (in view: work.CoreConfigP_Z14(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF3_PENABLE (in view: work.CoreConfigP_Z14(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : corejesd204btx.v(397) | Removing sequential instance SOF[1:0] (in view: work.CoreJESD204BTX_Z12(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : corejesd204btx.v(397) | Removing sequential instance SOMF[1:0] (in view: work.CoreJESD204BTX_Z12(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : data_handle_fsm.v(199) | Removing sequential instance WR_ENABLE (in view: work.DATAHANDLE_FSM(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : encoder_u.v(84) | Removing sequential instance BAD_K (in view: work.CJESDTX_ENCODER_U_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : encoder_l.v(83) | Removing sequential instance BAD_K (in view: work.CJESDTX_ENCODER_L_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN115 : corejesd204btx.v(430) | Removing instance CJESDTX_CLOCK_GEN_TX (in view: work.CoreJESD204BTX_Z12(verilog)) of type view:work.CJESDTX_CLOCK_GEN_TX_2s_9s_0s_16s_2s_0s_4s_2s_18s_4s(verilog) because it does not drive other instances. @N:BN362 : data_sync_buf_tx.v(207) | Removing sequential instance genblk4\.TX_K_OUT[1:0] (in view: work.CJESDTX_SYNC_BUF_TX_1s_16s_2s_2s_20s_0s_20s_0s_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_flip.v(57) | Removing sequential instance X_7 (in view: work.CJESDTX_ENC_FLIP_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_flip.v(57) | Removing sequential instance Y_3 (in view: work.CJESDTX_ENC_FLIP_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : data_sync_buf_tx.v(255) | Removing sequential instance k[1:0] (in view: work.CJESDTX_SYNC_BUF_TX_1s_16s_2s_2s_20s_0s_20s_0s_1(verilog)) of type view:PrimLib.ram2(prim) because it does not drive other instances. @N:BN362 : enc_k.v(117) | Removing sequential instance X_DLY[4:0] (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffpatr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(117) | Removing sequential instance X_EQ_14 (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(117) | Removing sequential instance X_EQ_13 (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(117) | Removing sequential instance X_EQ_11 (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(117) | Removing sequential instance X_EQ_20 (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(117) | Removing sequential instance X_EQ_18 (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(117) | Removing sequential instance X_EQ_17 (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(163) | Removing sequential instance K_ERR (in view: work.CJESDTX_ENC_K_0s_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(163) | Removing sequential instance K_ERR (in view: work.CJESDTX_ENC_K_0s_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : fadm_or.v(135) | Removing sequential instance FPC[1:0] (in view: work.CJESDRX_FADM_OR_4s_0s_2s_9s_0s_1s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enc_k.v(117) | Removing sequential instance Y_DLY[2:0] (in view: work.CJESDTX_ENC_K_0s_2(verilog)) of type view:PrimLib.dffpatr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 (in view: work.CoreResetP_Z15(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. syn_allowed_resources : blockrams=109 set on top level netlist SF2_JESD204B_DEMO Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 154MB peak: 155MB) Clock Summary ***************** Start Requested Requested Clock Clock Clock Clock Frequency Period Type Group Load ---------------------------------------------------------------------------------------------------------------------------------------------- SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_3 1085 SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 559 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK 25.0 MHz 40.000 declared default_clkgroup 111 SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 101 SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_1 30 ============================================================================================================================================== @W:MT530 : data_handle_fsm.v(134) | Found inferred clock SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock which controls 101 sequential elements including DATAHANDLE_FSM_0.DATA_WADDR1[10:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coreresetp.v(1485) | Found inferred clock SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 30 sequential elements including SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[12:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : sync_dec.v(73) | Found inferred clock SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock which controls 559 sequential elements including CoreJESD204BTX_0.CJESDTX_SYNC_DEC.sync_counter[2:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : sync_enc.v(81) | Found inferred clock SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock which controls 1085 sequential elements including CoreJESD204BRX_0.CJESDRX_SYNC_ENC.SYNC_GEN_ST[2:0]. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\synthesis\SF2_JESD204B_DEMO.sap. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 151MB peak: 155MB) Encoding state machine SYNC_GEN_ST[2:0] (in view: work.CJESDRX_SYNC_ENC_2s_0s_0s_2s_9s_54s_0s_0_1_2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine CG_state[2:0] (in view: work.CJESDRX_CGS_0s_0_1_2_16s_2s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine RIstate[2:0] (in view: work.CJESDRX_ILA_FSM_Z3(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine ILA_state[4:0] (in view: work.CJESDRX_ILA_FSM_Z3(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 Encoding state machine CD_M_state[6:0] (in view: work.CJESDRX_LINK_COMP_Z5(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine CC_state[1:0] (in view: work.CJESDRX_IFS_POS_Z6(verilog)) original code -> new code 00 -> 0 01 -> 1 @N:MO225 : ifs_pos.v(295) | There are no possible illegal states for state machine CC_state[1:0] (in view: work.CJESDRX_IFS_POS_Z6(verilog)); safe FSM implementation is not required. Encoding state machine FS_STATE_1[3:0] (in view: work.CJESDRX_IFS_POS_Z6(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : ifs_pos.v(198) | There are no possible illegal states for state machine FS_STATE_1[3:0] (in view: work.CJESDRX_IFS_POS_Z6(verilog)); safe FSM implementation is not required. Encoding state machine SYNC_STATE[4:0] (in view: work.CJESDRX_SYNC_FSM_0s_0_1_2_4_4_0(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 Encoding state machine SYNC_STATE[4:0] (in view: work.CJESDRX_SYNC_FSM_0s_0_1_2_4_4_1(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 Encoding state machine WA_FSM_STATE[3:0] (in view: work.CJESDRX_WORD_ALIGNER_Z8(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : word_aligner.v(769) | There are no possible illegal states for state machine WA_FSM_STATE[3:0] (in view: work.CJESDRX_WORD_ALIGNER_Z8(verilog)); safe FSM implementation is not required. Encoding state machine TX_STATE_1[2:0] (in view: work.CJESDTX_TX_CTRL_2s_0s_0_1_2_0s_16s_20s_2s_0(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine fsm[3:0] (in view: work.DATAHANDLE_FSM(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : data_handle_fsm.v(199) | There are no possible illegal states for state machine fsm[3:0] (in view: work.DATAHANDLE_FSM(verilog)); safe FSM implementation is not required. Encoding state machine state[2:0] (in view: work.CoreConfigP_Z14(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z15(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sdif0_state[3:0] (in view: work.CoreResetP_Z15(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : coreresetp.v(1170) | There are no possible illegal states for state machine sdif0_state[3:0] (in view: work.CoreResetP_Z15(verilog)); safe FSM implementation is not required. @N:BN362 : tx_acg.v(2137) | Removing sequential instance genblk6\.OCount_L_0[1] (in view: work.CJESDTX_TX_ACG_0s_2s_9s_0s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance f_phase_st_reg[3] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance lmfc_cnt_reg[12] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance lmfc_cnt_reg[13] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance lmfc_cnt_reg[14] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance lmfc_cnt_reg[15] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance fc_cnt_reg[12] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance fc_cnt_reg[13] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance fc_cnt_reg[14] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance fc_cnt_reg[15] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance f_phase_st_reg[2] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance lmfc_cnt_reg[8] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance lmfc_cnt_reg[9] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance lmfc_cnt_reg[10] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance lmfc_cnt_reg[11] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance fc_cnt_reg[8] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance fc_cnt_reg[9] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance fc_cnt_reg[10] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance fc_cnt_reg[11] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance f_phase_st_reg[1] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance lmfc_cnt_reg[4] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance lmfc_cnt_reg[5] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance lmfc_cnt_reg[6] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance lmfc_cnt_reg[7] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance fc_cnt_reg[4] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance fc_cnt_reg[5] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance fc_cnt_reg[6] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance fc_cnt_reg[7] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance f_phase_st_reg[0] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance lmfc_cnt_reg[0] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance lmfc_cnt_reg[1] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance lmfc_cnt_reg[2] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance lmfc_cnt_reg[3] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance fc_cnt_reg[0] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance fc_cnt_reg[1] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance fc_cnt_reg[2] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance fc_cnt_reg[3] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. None None Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 153MB peak: 155MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 67MB peak: 155MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Mar 14 16:14:20 2017 ###########################################################] Map & Optimize Report # Tue Mar 14 16:14:20 2017 Synopsys Generic Technology Mapper, Version map201609actrcp1, Build 005R, Built Jan 25 2017 01:01:33 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.09M-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB) @N:MO111 : corejesd204brx.v(290) | Tristate driver RX_STATE_7_1 (in view: work.CoreJESD204BRX_Z9(verilog)) on net RX_STATE_7_1 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND. @N:MO111 : corejesd204brx.v(290) | Tristate driver RX_STATE_7_2 (in view: work.CoreJESD204BRX_Z9(verilog)) on net RX_STATE_7_2 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND. @N:MO111 : corejesd204brx.v(289) | Tristate driver RX_STATE_6_1 (in view: work.CoreJESD204BRX_Z9(verilog)) on net RX_STATE_6_1 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND. @N:MO111 : corejesd204brx.v(289) | Tristate driver RX_STATE_6_2 (in view: work.CoreJESD204BRX_Z9(verilog)) on net RX_STATE_6_2 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND. @N:MO111 : corejesd204brx.v(288) | Tristate driver RX_STATE_5_1 (in view: work.CoreJESD204BRX_Z9(verilog)) on net RX_STATE_5_1 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND. @N:MO111 : corejesd204brx.v(288) | Tristate driver RX_STATE_5_2 (in view: work.CoreJESD204BRX_Z9(verilog)) on net RX_STATE_5_2 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND. @N:MO111 : corejesd204brx.v(287) | Tristate driver RX_STATE_4_1 (in view: work.CoreJESD204BRX_Z9(verilog)) on net RX_STATE_4_1 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND. @N:MO111 : corejesd204brx.v(287) | Tristate driver RX_STATE_4_2 (in view: work.CoreJESD204BRX_Z9(verilog)) on net RX_STATE_4_2 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND. @N:MO111 : corejesd204brx.v(286) | Tristate driver RX_STATE_3_1 (in view: work.CoreJESD204BRX_Z9(verilog)) on net RX_STATE_3_1 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND. @N:MO111 : corejesd204brx.v(286) | Tristate driver RX_STATE_3_2 (in view: work.CoreJESD204BRX_Z9(verilog)) on net RX_STATE_3_2 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND. @W:BN132 : mux32x1.v(86) | Removing user instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB5.UT1B6 because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB5.UT1B2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : mux32x1.v(82) | Removing user instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB5.UT1B2 because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB5.UT1B1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : mux32x1.v(87) | Removing user instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB5.UT1B7 because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB5.UT1B5. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : mux32x1.v(85) | Removing user instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB5.UT1B5 because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB5.UT1B4. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : mux32x1.v(85) | Removing user instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB4.UT1B5 because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB4.UT1B3. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : mux32x1.v(86) | Removing user instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB4.UT1B6 because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB4.UT1B4. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : mux32x1.v(84) | Removing user instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB4.UT1B4 because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB4.UT1B2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : mux32x1.v(82) | Removing user instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB4.UT1B2 because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB4.UT1B1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : mux32x1.v(84) | Removing user instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB3.UT1B4 because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB3.UT1B2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : mux32x1.v(87) | Removing user instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB2.UT1B7 because it is equivalent to instance CoreJESD204BTX_0.LANE_0.genblk10.ENCODER_64B80B_0.ENCODER_U_0.UD.URN.UB2.UT1B0. To keep the instance, apply constraint syn_preserve=1 on the instance. Available hyper_sources - for debug and ip models None Found @N:BN362 : rx_ctrl.v(149) | Removing sequential instance mf_phase_st_reg[3:0] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance lmfc_cnt_reg[15:0] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_ctrl.v(149) | Removing sequential instance fc_cnt_reg[15:0] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : sync_dec.v(100) | Removing sequential instance genblk1\.sync_state (in view: work.CJESDTX_SYNC_DEC_2s_0s_16s_2s_0s_6s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 148MB peak: 151MB) @N:MF135 : data_sync_buf.v(91) | RAM genblk6\.CJESDRX_DATA_SYNC_BUF_0.data_buf[19:0] (in view: work.CoreJESD204BRX_Z9(verilog)) is 4 words by 20 bits. Encoding state machine SYNC_GEN_ST[2:0] (in view: work.CJESDRX_SYNC_ENC_2s_0s_0s_2s_9s_54s_0s_0_1_2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:MO231 : sync_enc.v(81) | Found counter in view:work.CJESDRX_SYNC_ENC_2s_0s_0s_2s_9s_54s_0s_0_1_2(verilog) instance sync_cnt[5:0] @W:MO129 : rx_ctrl.v(149) | Sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_RX_CTRL.f_phase_st_reg[0] is reduced to a combinational gate by constant propagation. Encoding state machine CG_state[2:0] (in view: work.CJESDRX_CGS_0s_0_1_2_16s_2s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @W:MO129 : adj_ctrl.v(112) | Sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.mf_phase_reg_3[0] is reduced to a combinational gate by constant propagation. @N:MF135 : eb_ram_rtl.v(69) | RAM CJESDRX_ADJ_BUF.CJESDRX_RAM_EB.EB_RAM[17:0] (in view: work.CJESDRX_LABDM_Z4(verilog)) is 64 words by 18 bits. Encoding state machine RIstate[2:0] (in view: work.CJESDRX_ILA_FSM_Z3(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine ILA_state[4:0] (in view: work.CJESDRX_ILA_FSM_Z3(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 @N:MO231 : ila_fsm.v(304) | Found counter in view:work.CJESDRX_ILA_FSM_Z3(verilog) instance R_cnt[6:0] @N:MO231 : eb_ctrl.v(125) | Found counter in view:work.CJESDRX_EB_CTRL_0s_2s_9s_18s_54s_0_1_16s_2s(verilog) instance WADDR[5:0] Encoding state machine CD_M_state[6:0] (in view: work.CJESDRX_LINK_COMP_Z5(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 @N:MF179 : link_comp.v(488) | Found 16 by 16 bit equality operator ('==') genblk6\.COMP_ERR33 (in view: work.CJESDRX_LINK_COMP_Z5(verilog)) Encoding state machine CC_state[1:0] (in view: work.CJESDRX_IFS_POS_Z6(verilog)) original code -> new code 00 -> 0 01 -> 1 @N:MO225 : ifs_pos.v(295) | There are no possible illegal states for state machine CC_state[1:0] (in view: work.CJESDRX_IFS_POS_Z6(verilog)); safe FSM implementation is not required. Encoding state machine FS_STATE_1[3:0] (in view: work.CJESDRX_IFS_POS_Z6(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : ifs_pos.v(198) | There are no possible illegal states for state machine FS_STATE_1[3:0] (in view: work.CJESDRX_IFS_POS_Z6(verilog)); safe FSM implementation is not required. Encoding state machine SYNC_STATE[4:0] (in view: work.CJESDRX_SYNC_FSM_0s_0_1_2_3_4_4(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 Encoding state machine WA_FSM_STATE[3:0] (in view: work.CJESDRX_WORD_ALIGNER_Z8(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : word_aligner.v(769) | There are no possible illegal states for state machine WA_FSM_STATE[3:0] (in view: work.CJESDRX_WORD_ALIGNER_Z8(verilog)); safe FSM implementation is not required. @N:MF135 : data_sync_buf_tx.v(255) | RAM DATA_SYNC_BUF_0.data[19:0] (in view: work.CoreJESD204BTX_Z12(verilog)) is 4 words by 20 bits. @N:MF135 : data_sync_buf_tx.v(255) | RAM DATA_SYNC_BUF_0.data[19:0] (in view: work.CoreJESD204BTX_Z12(verilog)) is 4 words by 20 bits. @N:BN362 : tx_acg.v(2137) | Removing sequential instance CJESDTX_TX_ACG.genblk6\.OCount_L_0[1] (in view: work.CJESDTX_JESD204BTX_LANE_Z11(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_7[6] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_7[5] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_7[4] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_7[3] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO161 : tx_ila.v(300) | Register bit ILAValue_7[2] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO161 : tx_ila.v(300) | Register bit ILAValue_7[1] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO161 : tx_ila.v(300) | Register bit ILAValue_7[0] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_6[6] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_6[5] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_6[4] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_6[3] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO161 : tx_ila.v(300) | Register bit ILAValue_6[2] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO161 : tx_ila.v(300) | Register bit ILAValue_6[1] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_6[0] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_5[6] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_5[5] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_5[4] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_5[3] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO161 : tx_ila.v(300) | Register bit ILAValue_5[2] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_5[1] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO161 : tx_ila.v(300) | Register bit ILAValue_5[0] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_4[6] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_4[5] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_4[4] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_4[3] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO161 : tx_ila.v(300) | Register bit ILAValue_4[2] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_4[1] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_4[0] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_3[6] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_3[5] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_3[4] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_3[3] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_3[2] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO161 : tx_ila.v(300) | Register bit ILAValue_3[1] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO161 : tx_ila.v(300) | Register bit ILAValue_3[0] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_2[6] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_2[5] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_2[4] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_2[3] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_2[2] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO161 : tx_ila.v(300) | Register bit ILAValue_2[1] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : tx_ila.v(300) | Register bit ILAValue_2[0] (in view view:work.CJESDTX_TX_ILA_Z10(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine TX_STATE_1[2:0] (in view: work.CJESDTX_TX_CTRL_2s_0s_0_1_2_0s_16s_20s_2s_0(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @W:MO129 : tx_ctrl.v(92) | Sequential instance CoreJESD204BTX_0.LANE_0.CJESDTX_TX_CTRL_0.FRAME_END_int[1] is reduced to a combinational gate by constant propagation. @W:MO129 : tx_ctrl.v(92) | Sequential instance CoreJESD204BTX_0.LANE_0.CJESDTX_TX_CTRL_0.MULTI_FRAME_END_int[1] is reduced to a combinational gate by constant propagation. @W:MO160 : wav_gen_16bit.v(135) | Register bit SQR_DATA16[10] (in view view:work.waveform_gen(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO161 : wav_gen_16bit.v(135) | Register bit SQR_DATA16[9] (in view view:work.waveform_gen(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : wav_gen_16bit.v(135) | Register bit SQR_DATA16[4] (in view view:work.waveform_gen(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : wav_gen_16bit.v(135) | Register bit SQR_DATA16[2] (in view view:work.waveform_gen(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : wav_gen_16bit.v(135) | Register bit SQR_DATA16[1] (in view view:work.waveform_gen(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : wav_gen_16bit.v(135) | Register bit SQR_DATA16[0] (in view view:work.waveform_gen(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine fsm[3:0] (in view: work.DATAHANDLE_FSM(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : data_handle_fsm.v(199) | There are no possible illegal states for state machine fsm[3:0] (in view: work.DATAHANDLE_FSM(verilog)); safe FSM implementation is not required. @N:MO231 : data_handle_fsm.v(134) | Found counter in view:work.DATAHANDLE_FSM(verilog) instance DATA_WADDR1[10:0] Encoding state machine state[2:0] (in view: work.CoreConfigP_Z14(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @W:MO160 : coreconfigp.v(255) | Register bit paddr[16] (in view view:work.CoreConfigP_Z14(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z15(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sdif0_state[3:0] (in view: work.CoreResetP_Z15(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : coreresetp.v(1170) | There are no possible illegal states for state machine sdif0_state[3:0] (in view: work.CoreResetP_Z15(verilog)); safe FSM implementation is not required. @N:MO231 : coreresetp.v(1485) | Found counter in view:work.CoreResetP_Z15(verilog) instance count_sdif0[12:0] Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 155MB peak: 155MB) @N:BN362 : adj_ctrl.v(112) | Removing sequential instance CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.mf_phase_st_reg[0] (in view: work.CJESDRX_JESD204BRX_LANE_Z7(verilog)) because it does not drive other instances. @N:BN362 : adj_ctrl.v(112) | Removing sequential instance CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.mf_phase_st_reg[1] (in view: work.CJESDRX_JESD204BRX_LANE_Z7(verilog)) because it does not drive other instances. @N:BN362 : adj_ctrl.v(112) | Removing sequential instance CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.mf_phase_st_reg[2] (in view: work.CJESDRX_JESD204BRX_LANE_Z7(verilog)) because it does not drive other instances. @N:BN362 : adj_ctrl.v(112) | Removing sequential instance CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.mf_phase_st_reg[3] (in view: work.CJESDRX_JESD204BRX_LANE_Z7(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF0_PHY_RESET_N_int (in view: work.SF2_JESD204B_DEMO(verilog)) because it does not drive other instances. Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 184MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 175MB peak: 185MB) @W:FX739 : sf2_jesd204b_demo.v(340) | Removed BUFG instance CLKINT_0 because it is cascaded to another clock buffer (SF2_JESD204B_DEMO_sb_0.CCC_0.GL0_INST). Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 175MB peak: 185MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 177MB peak: 185MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 177MB peak: 185MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 176MB peak: 185MB) @N:MO106 : dec_data.v(78) | Found ROM .delname. (in view: work.SF2_JESD204B_DEMO(verilog)) with 48 words by 5 bits. @N:MO106 : dec_data.v(78) | Found ROM .delname. (in view: work.SF2_JESD204B_DEMO(verilog)) with 48 words by 5 bits. @N:BN362 : wav_gen_16bit.v(163) | Removing sequential instance DATA_GENERATOR_0.waveform_gen_0.SAW_DATA16[0] (in view: work.SF2_JESD204B_DEMO(verilog)) because it does not drive other instances. @N:BN362 : wav_gen_16bit.v(163) | Removing sequential instance DATA_GENERATOR_0.waveform_gen_0.SAW_DATA16[1] (in view: work.SF2_JESD204B_DEMO(verilog)) because it does not drive other instances. Finished preparing to map (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 176MB peak: 185MB) Finished technology mapping (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 210MB peak: 213MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:07s -7.70ns 3599 / 2726 2 0h:00m:07s -7.70ns 3260 / 2726 3 0h:00m:07s -6.84ns 3260 / 2726 4 0h:00m:07s -6.84ns 3260 / 2726 @N:FX271 : eb_ctrl.v(280) | Replicating instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.SC[0] (in view: work.SF2_JESD204B_DEMO(verilog)) with 13 loads 1 time to improve timing. @N:FX271 : eb_ctrl.v(93) | Replicating instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg[0] (in view: work.SF2_JESD204B_DEMO(verilog)) with 14 loads 1 time to improve timing. @N:FX271 : eb_ctrl.v(93) | Replicating instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg[3] (in view: work.SF2_JESD204B_DEMO(verilog)) with 13 loads 1 time to improve timing. Timing driven replication report Added 3 Registers via timing driven replication Added 0 LUTs via timing driven replication 5 0h:00m:08s -6.67ns 3262 / 2729 6 0h:00m:08s -7.11ns 3264 / 2729 7 0h:00m:08s -6.94ns 3265 / 2729 8 0h:00m:08s -6.18ns 3265 / 2729 9 0h:00m:08s -6.18ns 3266 / 2729 10 0h:00m:08s -6.18ns 3266 / 2729 @N:FX271 : eb_ctrl.v(93) | Replicating instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg[2] (in view: work.SF2_JESD204B_DEMO(verilog)) with 13 loads 2 times to improve timing. @N:FX271 : eb_ctrl.v(93) | Replicating instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg[1] (in view: work.SF2_JESD204B_DEMO(verilog)) with 15 loads 2 times to improve timing. Timing driven replication report Added 4 Registers via timing driven replication Added 0 LUTs via timing driven replication 11 0h:00m:09s -6.18ns 3262 / 2733 @N:FP130 : | Promoting Net SERDES_EPCS_0_EPCS_2_RX_CLK on CLKINT I_964 @N:FP130 : | Promoting Net SERDES_EPCS_0_EPCS_2_TX_CLK_0 on CLKINT I_965 @N:FP130 : | Promoting Net CoreJESD204BTX_0.syncd_rst_n_0[1] on CLKINT I_966 @N:FP130 : | Promoting Net SERDES_EPCS_0_EPCS_2_RX_RESET_N on CLKINT I_967 @N:FP130 : | Promoting Net SF2_JESD204B_DEMO_sb_0_INIT_APB_S_PRESET_N on CLKINT I_968 @N:FP130 : | Promoting Net SF2_JESD204B_DEMO_sb_0_INIT_APB_S_PCLK on CLKINT I_969 @N:FP130 : | Promoting Net SERDES_EPCS_0_EPCS_2_TX_RESET_N on CLKINT I_970 @N:FP130 : | Promoting Net SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT I_971 @N:FP130 : | Promoting Net SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sm0_areset_n_rcosc on CLKINT I_972 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 214MB peak: 218MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:09s; Memory used current: 216MB peak: 218MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 3 non-gated/non-generated clock tree(s) driving 2656 clock pin(s) of sequential element(s) 2 gated/generated clock tree(s) driving 104 clock pin(s) of sequential element(s) 0 instances converted, 104 sequential instances remain driven by gated/generated clocks =============================================================================== Non-Gated/Non-Generated Clocks =============================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0003 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST SERDESIF_075 1994 SERDES_EPCS_0.epcs_rx_intf_0.rxvalo ClockId0004 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST SERDESIF_075 553 SERDES_EPCS_0.epcs_tx_intf_0.txdin_p[4] ClockId0005 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK_keep clock definition on keepbuf 109 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.SDIF_RELEASED_q2 ============================================================================================================================================================================================== ======================================================================================================== Gated/Generated Clocks ========================================================================================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 SF2_JESD204B_DEMO_sb_0.CCC_0.CCC_INST CCC 85 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_075 ClockId0002 SF2_JESD204B_DEMO_sb_0.FABOSC_0.I_RCOSC_25_50MHZ RCOSC_25_50MHZ 19 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[12] No gated clock conversion method for cell cell:ACG4.SLE ========================================================================================================================================================================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 169MB peak: 218MB) Writing Analyst data base D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\synthesis\synwork\SF2_JESD204B_DEMO_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 205MB peak: 218MB) Writing EDIF Netlist and constraint files @N:FX1056 : | Writing EDF file: D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\synthesis\SF2_JESD204B_DEMO.edn @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF L-2016.09M-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 207MB peak: 218MB) Start final timing analysis (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 201MB peak: 218MB) @W:MT246 : sf2_jesd204b_demo_sb_ccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N:MT615 : | Found clock SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK with period 40.00ns @W:MT420 : | Found inferred clock SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:SF2_JESD204B_DEMO_sb_0.FABOSC_0.RCOSC_25_50MHZ_CCC" @W:MT420 : | Found inferred clock SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:SF2_JESD204B_DEMO_sb_0.CCC_0.GL0_net" @W:MT420 : | Found inferred clock SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:SERDES_EPCS_0.SERDES_IF2_0.EPCS_2_RX_CLK" @W:MT420 : | Found inferred clock SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:SERDES_EPCS_0.SERDES_IF2_0.EPCS_2_TX_CLK" ##### START OF TIMING REPORT #####[ # Timing Report written on Tue Mar 14 16:14:33 2017 # Top view: SF2_JESD204B_DEMO Requested Frequency: 25.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\synthesis\SF2_JESD204B_DEMO_syn.fdc @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -0.622 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock 100.0 MHz 94.1 MHz 10.000 10.622 -0.622 inferred Inferred_clkgroup_3 SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock 100.0 MHz 118.3 MHz 10.000 8.454 1.546 inferred Inferred_clkgroup_2 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK 25.0 MHz 90.3 MHz 40.000 11.074 14.463 declared default_clkgroup SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 106.5 MHz 10.000 9.393 0.607 inferred Inferred_clkgroup_0 SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock 100.0 MHz 375.0 MHz 10.000 2.667 7.333 inferred Inferred_clkgroup_1 =========================================================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK | 40.000 31.635 | No paths - | 20.000 17.781 | 20.000 14.463 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock | Diff grp - | No paths - | No paths - | No paths - SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK | Diff grp - | No paths - | No paths - | No paths - SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock | 10.000 0.607 | No paths - | 5.000 3.801 | 5.000 3.137 SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | Diff grp - | No paths - | No paths - | No paths - SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock | Diff grp - | No paths - | No paths - | No paths - SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | 10.000 7.333 | No paths - | No paths - | No paths - SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock | 10.000 1.546 | No paths - | No paths - | No paths - SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock | Diff grp - | No paths - | No paths - | No paths - SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock | 10.000 -0.622 | No paths - | No paths - | 5.000 3.972 =================================================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast[0] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE Q ADJ_NUM_reg_fast[0] 0.108 -0.622 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.SC_fast[0] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE Q SC_fast[0] 0.108 -0.537 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[1] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE Q eb2ram_raddr[1] 0.108 -0.530 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[0] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE Q eb2ram_raddr[0] 0.108 -0.528 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast[2] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE Q RADDR60_2_fast 0.108 -0.467 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[2] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE Q eb2ram_raddr[2] 0.108 -0.300 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[3] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE Q eb2ram_raddr[3] 0.108 -0.267 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.SC[3] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE Q SC[3] 0.108 0.006 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg[0] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE Q RADDR60_0 0.087 0.209 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg[3] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE Q RADDR60_3 0.087 0.234 ============================================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[5] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE D un1_RADDR_4_s_5_S 9.745 -0.622 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[4] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE D un1_RADDR_4_cry_4_S 9.745 -0.606 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[3] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE D un1_RADDR_4_cry_3_S 9.745 -0.589 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[2] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE D un1_RADDR_4_cry_2_0_S 9.745 -0.573 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[1] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE D un1_RADDR_4_cry_1_S 9.745 -0.557 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[0] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE D un1_RADDR_4_cry_0_Y 9.745 -0.466 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.SC[5] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE D SC_7[5] 9.745 2.171 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.SC[0] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE D SC_7[0] 9.745 2.355 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.SC_fast[0] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE D SC_7[0] 9.745 2.355 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.SC[4] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE D SC_7[4] 9.745 2.365 ======================================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.745 - Propagation time: 10.367 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.622 Number of logic level(s): 16 Starting point: CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast[0] / Q Ending point: CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[5] / D The start point is clocked by SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock [rising] on pin CLK The end point is clocked by SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast[0] SLE Q Out 0.108 0.108 - ADJ_NUM_reg_fast[0] Net - - 0.814 - 5 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast_RNI0M6C[2] CFG3 B In - 0.923 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast_RNI0M6C[2] CFG3 Y Out 0.148 1.071 - g0_0_1 Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast_RNI9DK51[3] CFG4 D In - 1.627 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast_RNI9DK51[3] CFG4 Y Out 0.326 1.953 - CLogB2236_0_c4_d Net - - 0.630 - 2 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_cry_5 ARI1 C In - 2.583 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_cry_5 ARI1 FCO Out 0.262 2.845 - CLogB2236_cry_5 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_cry_6 ARI1 FCI In - 2.845 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_cry_6 ARI1 FCO Out 0.016 2.861 - CLogB2236_cry_6 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_s_7 ARI1 FCI In - 2.861 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_s_7 ARI1 S Out 0.073 2.934 - CLogB2236 Net - - 1.137 - 10 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_s_7_RNIQ2301 CFG4 C In - 4.071 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_s_7_RNIQ2301 CFG4 Y Out 0.226 4.297 - RADDR_1_sqmuxa_12_0 Net - - 0.770 - 6 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_0_0_1[0] CFG4 B In - 5.067 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_0_0_1[0] CFG4 Y Out 0.164 5.231 - un13_0_1_iv_0_0_1[0] Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_0_0[0] CFG4 D In - 5.787 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_0_0[0] CFG4 Y Out 0.288 6.074 - un13_0[0] Net - - 0.630 - 2 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_4_m_cry_0_0 ARI1 B In - 6.705 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_4_m_cry_0_0 ARI1 Y Out 0.165 6.869 - un1_RADDR_4_4_m_cry_0_0_Y Net - - 1.117 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_axb_0 CFG4 D In - 7.986 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_axb_0 CFG4 Y Out 0.326 8.313 - un1_RADDR_4_axb_0 Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_0 ARI1 C In - 8.868 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_0 ARI1 FCO Out 0.243 9.111 - un1_RADDR_4_cry_0 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_1 ARI1 FCI In - 9.111 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_1 ARI1 FCO Out 0.016 9.128 - un1_RADDR_4_cry_1 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_2_0 ARI1 FCI In - 9.128 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_2_0 ARI1 FCO Out 0.016 9.144 - un1_RADDR_4_cry_2 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_3 ARI1 FCI In - 9.144 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_3 ARI1 FCO Out 0.016 9.160 - un1_RADDR_4_cry_3 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_4 ARI1 FCI In - 9.160 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_4 ARI1 FCO Out 0.016 9.177 - un1_RADDR_4_cry_4 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_s_5 ARI1 FCI In - 9.177 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_s_5 ARI1 S Out 0.073 9.249 - un1_RADDR_4_s_5_S Net - - 1.117 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[5] SLE D In - 10.367 - ================================================================================================================================================================= Total path delay (propagation time + setup) of 10.622 is 2.740(25.8%) logic and 7.882(74.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.745 - Propagation time: 10.350 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.606 Number of logic level(s): 15 Starting point: CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast[0] / Q Ending point: CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[5] / D The start point is clocked by SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock [rising] on pin CLK The end point is clocked by SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast[0] SLE Q Out 0.108 0.108 - ADJ_NUM_reg_fast[0] Net - - 0.814 - 5 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast_RNI0M6C[2] CFG3 B In - 0.923 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast_RNI0M6C[2] CFG3 Y Out 0.148 1.071 - g0_0_1 Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast_RNI9DK51[3] CFG4 D In - 1.627 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast_RNI9DK51[3] CFG4 Y Out 0.326 1.953 - CLogB2236_0_c4_d Net - - 0.630 - 2 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_cry_6 ARI1 C In - 2.583 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_cry_6 ARI1 FCO Out 0.262 2.845 - CLogB2236_cry_6 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_s_7 ARI1 FCI In - 2.845 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_s_7 ARI1 S Out 0.073 2.918 - CLogB2236 Net - - 1.137 - 10 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_s_7_RNIQ2301 CFG4 C In - 4.055 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_s_7_RNIQ2301 CFG4 Y Out 0.226 4.281 - RADDR_1_sqmuxa_12_0 Net - - 0.770 - 6 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_0_0_1[0] CFG4 B In - 5.051 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_0_0_1[0] CFG4 Y Out 0.164 5.215 - un13_0_1_iv_0_0_1[0] Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_0_0[0] CFG4 D In - 5.771 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_0_0[0] CFG4 Y Out 0.288 6.058 - un13_0[0] Net - - 0.630 - 2 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_4_m_cry_0_0 ARI1 B In - 6.688 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_4_m_cry_0_0 ARI1 Y Out 0.165 6.853 - un1_RADDR_4_4_m_cry_0_0_Y Net - - 1.117 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_axb_0 CFG4 D In - 7.970 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_axb_0 CFG4 Y Out 0.326 8.296 - un1_RADDR_4_axb_0 Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_0 ARI1 C In - 8.852 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_0 ARI1 FCO Out 0.243 9.095 - un1_RADDR_4_cry_0 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_1 ARI1 FCI In - 9.095 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_1 ARI1 FCO Out 0.016 9.111 - un1_RADDR_4_cry_1 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_2_0 ARI1 FCI In - 9.111 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_2_0 ARI1 FCO Out 0.016 9.128 - un1_RADDR_4_cry_2 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_3 ARI1 FCI In - 9.128 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_3 ARI1 FCO Out 0.016 9.144 - un1_RADDR_4_cry_3 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_4 ARI1 FCI In - 9.144 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_4 ARI1 FCO Out 0.016 9.160 - un1_RADDR_4_cry_4 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_s_5 ARI1 FCI In - 9.160 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_s_5 ARI1 S Out 0.073 9.233 - un1_RADDR_4_s_5_S Net - - 1.117 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[5] SLE D In - 10.350 - ================================================================================================================================================================= Total path delay (propagation time + setup) of 10.606 is 2.723(25.7%) logic and 7.882(74.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.745 - Propagation time: 10.350 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.606 Number of logic level(s): 15 Starting point: CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast[0] / Q Ending point: CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[4] / D The start point is clocked by SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock [rising] on pin CLK The end point is clocked by SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast[0] SLE Q Out 0.108 0.108 - ADJ_NUM_reg_fast[0] Net - - 0.814 - 5 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast_RNI0M6C[2] CFG3 B In - 0.923 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast_RNI0M6C[2] CFG3 Y Out 0.148 1.071 - g0_0_1 Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast_RNI9DK51[3] CFG4 D In - 1.627 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast_RNI9DK51[3] CFG4 Y Out 0.326 1.953 - CLogB2236_0_c4_d Net - - 0.630 - 2 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_cry_5 ARI1 C In - 2.583 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_cry_5 ARI1 FCO Out 0.262 2.845 - CLogB2236_cry_5 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_cry_6 ARI1 FCI In - 2.845 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_cry_6 ARI1 FCO Out 0.016 2.861 - CLogB2236_cry_6 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_s_7 ARI1 FCI In - 2.861 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_s_7 ARI1 S Out 0.073 2.934 - CLogB2236 Net - - 1.137 - 10 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_s_7_RNIQ2301 CFG4 C In - 4.071 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_s_7_RNIQ2301 CFG4 Y Out 0.226 4.297 - RADDR_1_sqmuxa_12_0 Net - - 0.770 - 6 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_0_0_1[0] CFG4 B In - 5.067 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_0_0_1[0] CFG4 Y Out 0.164 5.231 - un13_0_1_iv_0_0_1[0] Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_0_0[0] CFG4 D In - 5.787 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_0_0[0] CFG4 Y Out 0.288 6.074 - un13_0[0] Net - - 0.630 - 2 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_4_m_cry_0_0 ARI1 B In - 6.705 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_4_m_cry_0_0 ARI1 Y Out 0.165 6.869 - un1_RADDR_4_4_m_cry_0_0_Y Net - - 1.117 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_axb_0 CFG4 D In - 7.986 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_axb_0 CFG4 Y Out 0.326 8.313 - un1_RADDR_4_axb_0 Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_0 ARI1 C In - 8.868 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_0 ARI1 FCO Out 0.243 9.111 - un1_RADDR_4_cry_0 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_1 ARI1 FCI In - 9.111 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_1 ARI1 FCO Out 0.016 9.128 - un1_RADDR_4_cry_1 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_2_0 ARI1 FCI In - 9.128 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_2_0 ARI1 FCO Out 0.016 9.144 - un1_RADDR_4_cry_2 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_3 ARI1 FCI In - 9.144 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_3 ARI1 FCO Out 0.016 9.160 - un1_RADDR_4_cry_3 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_4 ARI1 FCI In - 9.160 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_4 ARI1 S Out 0.073 9.233 - un1_RADDR_4_cry_4_S Net - - 1.117 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[4] SLE D In - 10.350 - ================================================================================================================================================================= Total path delay (propagation time + setup) of 10.606 is 2.723(25.7%) logic and 7.882(74.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.745 - Propagation time: 10.334 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.589 Number of logic level(s): 14 Starting point: CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast[0] / Q Ending point: CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[3] / D The start point is clocked by SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock [rising] on pin CLK The end point is clocked by SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast[0] SLE Q Out 0.108 0.108 - ADJ_NUM_reg_fast[0] Net - - 0.814 - 5 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast_RNI0M6C[2] CFG3 B In - 0.923 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast_RNI0M6C[2] CFG3 Y Out 0.148 1.071 - g0_0_1 Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast_RNI9DK51[3] CFG4 D In - 1.627 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast_RNI9DK51[3] CFG4 Y Out 0.326 1.953 - CLogB2236_0_c4_d Net - - 0.630 - 2 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_cry_5 ARI1 C In - 2.583 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_cry_5 ARI1 FCO Out 0.262 2.845 - CLogB2236_cry_5 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_cry_6 ARI1 FCI In - 2.845 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_cry_6 ARI1 FCO Out 0.016 2.861 - CLogB2236_cry_6 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_s_7 ARI1 FCI In - 2.861 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_s_7 ARI1 S Out 0.073 2.934 - CLogB2236 Net - - 1.137 - 10 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_s_7_RNIQ2301 CFG4 C In - 4.071 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_s_7_RNIQ2301 CFG4 Y Out 0.226 4.297 - RADDR_1_sqmuxa_12_0 Net - - 0.770 - 6 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_0_0_1[0] CFG4 B In - 5.067 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_0_0_1[0] CFG4 Y Out 0.164 5.231 - un13_0_1_iv_0_0_1[0] Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_0_0[0] CFG4 D In - 5.787 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_0_0[0] CFG4 Y Out 0.288 6.074 - un13_0[0] Net - - 0.630 - 2 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_4_m_cry_0_0 ARI1 B In - 6.705 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_4_m_cry_0_0 ARI1 Y Out 0.165 6.869 - un1_RADDR_4_4_m_cry_0_0_Y Net - - 1.117 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_axb_0 CFG4 D In - 7.986 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_axb_0 CFG4 Y Out 0.326 8.313 - un1_RADDR_4_axb_0 Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_0 ARI1 C In - 8.868 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_0 ARI1 FCO Out 0.243 9.111 - un1_RADDR_4_cry_0 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_1 ARI1 FCI In - 9.111 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_1 ARI1 FCO Out 0.016 9.128 - un1_RADDR_4_cry_1 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_2_0 ARI1 FCI In - 9.128 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_2_0 ARI1 FCO Out 0.016 9.144 - un1_RADDR_4_cry_2 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_3 ARI1 FCI In - 9.144 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_3 ARI1 S Out 0.073 9.217 - un1_RADDR_4_cry_3_S Net - - 1.117 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[3] SLE D In - 10.334 - ================================================================================================================================================================= Total path delay (propagation time + setup) of 10.589 is 2.707(25.6%) logic and 7.882(74.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.745 - Propagation time: 10.334 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.589 Number of logic level(s): 14 Starting point: CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast[0] / Q Ending point: CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[4] / D The start point is clocked by SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock [rising] on pin CLK The end point is clocked by SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast[0] SLE Q Out 0.108 0.108 - ADJ_NUM_reg_fast[0] Net - - 0.814 - 5 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast_RNI0M6C[2] CFG3 B In - 0.923 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast_RNI0M6C[2] CFG3 Y Out 0.148 1.071 - g0_0_1 Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast_RNI9DK51[3] CFG4 D In - 1.627 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast_RNI9DK51[3] CFG4 Y Out 0.326 1.953 - CLogB2236_0_c4_d Net - - 0.630 - 2 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_cry_6 ARI1 C In - 2.583 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_cry_6 ARI1 FCO Out 0.262 2.845 - CLogB2236_cry_6 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_s_7 ARI1 FCI In - 2.845 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_s_7 ARI1 S Out 0.073 2.918 - CLogB2236 Net - - 1.137 - 10 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_s_7_RNIQ2301 CFG4 C In - 4.055 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2236_s_7_RNIQ2301 CFG4 Y Out 0.226 4.281 - RADDR_1_sqmuxa_12_0 Net - - 0.770 - 6 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_0_0_1[0] CFG4 B In - 5.051 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_0_0_1[0] CFG4 Y Out 0.164 5.215 - un13_0_1_iv_0_0_1[0] Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_0_0[0] CFG4 D In - 5.771 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_0_0[0] CFG4 Y Out 0.288 6.058 - un13_0[0] Net - - 0.630 - 2 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_4_m_cry_0_0 ARI1 B In - 6.688 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_4_m_cry_0_0 ARI1 Y Out 0.165 6.853 - un1_RADDR_4_4_m_cry_0_0_Y Net - - 1.117 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_axb_0 CFG4 D In - 7.970 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_axb_0 CFG4 Y Out 0.326 8.296 - un1_RADDR_4_axb_0 Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_0 ARI1 C In - 8.852 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_0 ARI1 FCO Out 0.243 9.095 - un1_RADDR_4_cry_0 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_1 ARI1 FCI In - 9.095 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_1 ARI1 FCO Out 0.016 9.111 - un1_RADDR_4_cry_1 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_2_0 ARI1 FCI In - 9.111 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_2_0 ARI1 FCO Out 0.016 9.128 - un1_RADDR_4_cry_2 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_3 ARI1 FCI In - 9.128 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_3 ARI1 FCO Out 0.016 9.144 - un1_RADDR_4_cry_3 Net - - 0.000 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_4 ARI1 FCI In - 9.144 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_4_cry_4 ARI1 S Out 0.073 9.217 - un1_RADDR_4_cry_4_S Net - - 1.117 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[4] SLE D In - 10.334 - ================================================================================================================================================================= Total path delay (propagation time + setup) of 10.589 is 2.707(25.6%) logic and 7.882(74.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- DATA_GENERATOR_0.waveform_gen_0.DATA_OUT[3] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE Q waveform_gen_0_DATA_OUT[3] 0.108 1.546 DATA_GENERATOR_0.waveform_gen_0.DATA_OUT[4] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE Q waveform_gen_0_DATA_OUT[4] 0.108 1.647 DATA_GENERATOR_0.PRBS_GENERATOR_0.PRBS[3] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE Q PRBS[3] 0.108 1.805 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_CTRL_0.TX_STATE_1[1] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE Q TX_STATE[1] 0.087 1.853 DATA_GENERATOR_0.PRBS_GENERATOR_0.PRBS[4] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE Q PRBS[4] 0.108 1.934 DATA_GENERATOR_0.PRBS_GENERATOR_0.PRBS[1] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE Q PRBS[1] 0.108 2.033 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_CTRL_0.SEND_LANE_SEQ SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE Q SEQ_EN 0.087 2.176 DATA_GENERATOR_0.waveform_gen_0.DATA_OUT[0] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE Q waveform_gen_0_DATA_OUT[0] 0.108 2.250 DATA_GENERATOR_0.waveform_gen_0.SINE_CNT[5] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE Q SINE_CNT[5] 0.108 2.307 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_CTRL_0.TX_STATE_1[0] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE Q TX_STATE[0] 0.108 2.330 ================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreJESD204BTX_0.LANE_0.genblk6\.mux2_data_out[2] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE D N_449_i 9.745 1.546 CoreJESD204BTX_0.LANE_0.genblk6\.mux2_data_out[3] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE D N_447_i 9.745 1.546 CoreJESD204BTX_0.LANE_0.genblk6\.mux2_data_out[4] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE D N_445_i 9.745 1.603 CoreJESD204BTX_0.LANE_0.genblk6\.mux2_data_out[5] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE D N_443_i 9.745 1.603 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.genblk4\.DATA_ILA[5] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE D DATA_ILA_28[5] 9.745 1.853 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.genblk4\.DATA_ILA[6] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE D DATA_ILA_28[6] 9.745 1.947 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.genblk4\.DATA_ILA[10] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE D DATA_ILA_28[10] 9.745 1.947 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.genblk4\.DATA_ILA[11] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE D DATA_ILA_28[11] 9.745 1.947 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.genblk4\.DATA_ILA[4] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE D DATA_ILA_28[4] 9.745 1.947 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.genblk4\.DATA_ILA[12] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE D DATA_ILA_28[12] 9.745 1.947 ============================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.745 - Propagation time: 8.198 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 1.546 Number of logic level(s): 9 Starting point: DATA_GENERATOR_0.waveform_gen_0.DATA_OUT[3] / Q Ending point: CoreJESD204BTX_0.LANE_0.genblk6\.mux2_data_out[3] / D The start point is clocked by SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock [rising] on pin CLK The end point is clocked by SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------- DATA_GENERATOR_0.waveform_gen_0.DATA_OUT[3] SLE Q Out 0.108 0.108 - waveform_gen_0_DATA_OUT[3] Net - - 0.585 - 1 DATA_GENERATOR_0.PRBS_WAV_SEL_0.m22_1_2 CFG3 A In - 0.693 - DATA_GENERATOR_0.PRBS_WAV_SEL_0.m22_1_2 CFG3 Y Out 0.100 0.793 - m22_1 Net - - 0.556 - 1 DATA_GENERATOR_0.PRBS_WAV_SEL_0.m22 CFG4 B In - 1.349 - DATA_GENERATOR_0.PRBS_WAV_SEL_0.m22 CFG4 Y Out 0.165 1.513 - N_23_0 Net - - 0.678 - 3 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_CTRL_0.genblk1\.un1_DATA_IN_1_NE_5_1 CFG4 D In - 2.192 - CoreJESD204BTX_0.LANE_0.CJESDTX_TX_CTRL_0.genblk1\.un1_DATA_IN_1_NE_5_1 CFG4 Y Out 0.326 2.518 - un1_DATA_IN_1_NE_5_1 Net - - 0.556 - 1 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_CTRL_0.genblk1\.un1_DATA_IN_1_NE_5 CFG4 B In - 3.074 - CoreJESD204BTX_0.LANE_0.CJESDTX_TX_CTRL_0.genblk1\.un1_DATA_IN_1_NE_5 CFG4 Y Out 0.148 3.222 - un1_DATA_IN_1_NE_5 Net - - 0.630 - 2 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_CTRL_0.genblk1\.alignment_sent27 CFG4 D In - 3.852 - CoreJESD204BTX_0.LANE_0.CJESDTX_TX_CTRL_0.genblk1\.alignment_sent27 CFG4 Y Out 0.326 4.179 - alignment_sent27 Net - - 0.792 - 7 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_CTRL_0.SEND_DATA_1_0[0] CFG4 D In - 4.971 - CoreJESD204BTX_0.LANE_0.CJESDTX_TX_CTRL_0.SEND_DATA_1_0[0] CFG4 Y Out 0.317 5.288 - SEND_DATA_1[0] Net - - 0.556 - 1 CoreJESD204BTX_0.LANE_0.CJESDTX_TX_CTRL_0.SEND_DATA[0] CFG4 C In - 5.844 - CoreJESD204BTX_0.LANE_0.CJESDTX_TX_CTRL_0.SEND_DATA[0] CFG4 Y Out 0.203 6.047 - txctrl2txacg_sd[0] Net - - 0.888 - 13 DATA_GENERATOR_0.PRBS_WAV_SEL_0.m57_0 CFG4 D In - 6.935 - DATA_GENERATOR_0.PRBS_WAV_SEL_0.m57_0 CFG4 Y Out 0.326 7.261 - m57 Net - - 0.630 - 2 DATA_GENERATOR_0.PRBS_WAV_SEL_0.N_447_i CFG4 B In - 7.891 - DATA_GENERATOR_0.PRBS_WAV_SEL_0.N_447_i CFG4 Y Out 0.148 8.040 - N_447_i Net - - 0.159 - 1 CoreJESD204BTX_0.LANE_0.genblk6\.mux2_data_out[3] SLE D In - 8.198 - ====================================================================================================================================== Total path delay (propagation time + setup) of 8.454 is 2.424(28.7%) logic and 6.029(71.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.psel SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE Q psel 0.108 14.463 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.state[1] SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE Q state[1] 0.087 17.781 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.SDIF0_PENABLE SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE Q SF2_JESD204B_DEMO_sb_0_SDIF0_INIT_APB_PENABLE 0.108 17.795 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.paddr[15] SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE Q SF2_JESD204B_DEMO_sb_0_SDIF0_INIT_APB_PADDR[15] 0.087 18.520 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.state[0] SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE Q state[0] 0.087 18.601 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SERDESIF_075 APB_PRDATA[0] SF2_JESD204B_DEMO_sb_0_SDIF0_INIT_APB_PRDATA[0] 5.804 31.635 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SERDESIF_075 APB_PRDATA[1] SF2_JESD204B_DEMO_sb_0_SDIF0_INIT_APB_PRDATA[1] 5.759 31.680 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SERDESIF_075 APB_PREADY SF2_JESD204B_DEMO_sb_0_SDIF0_INIT_APB_PREADY 5.566 31.862 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SERDESIF_075 APB_PRDATA[25] SF2_JESD204B_DEMO_sb_0_SDIF0_INIT_APB_PRDATA[25] 6.291 32.014 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SERDESIF_075 APB_PRDATA[8] SF2_JESD204B_DEMO_sb_0_SDIF0_INIT_APB_PRDATA[8] 6.182 32.016 ========================================================================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[0] SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE D prdata[0] 19.745 14.463 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[1] SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE D prdata[1] 19.745 14.463 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[16] SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE D prdata[16] 19.745 14.463 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SERDESIF_075 APB_PSEL SF2_JESD204B_DEMO_sb_0_SDIF0_INIT_APB_PSELx 16.671 14.550 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[2] SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE D prdata[2] 19.745 15.203 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[3] SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE D prdata[3] 19.745 15.203 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[4] SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE D prdata[4] 19.745 15.203 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[5] SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE D prdata[5] 19.745 15.203 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[6] SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE D prdata[6] 19.745 15.203 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[7] SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE D prdata[7] 19.745 15.203 ======================================================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 19.745 - Propagation time: 5.282 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 14.463 Number of logic level(s): 5 Starting point: SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.psel / Q Ending point: SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[0] / D The start point is clocked by SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK [falling] on pin CLK The end point is clocked by SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------- SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.psel SLE Q Out 0.108 0.108 - psel Net - - 0.778 - 4 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.R_SDIF0_PSEL_1 CFG2 A In - 0.886 - SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.R_SDIF0_PSEL_1 CFG2 Y Out 0.087 0.973 - SF2_JESD204B_DEMO_sb_0_SDIF0_INIT_APB_PSELx Net - - 1.148 - 36 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.un1_R_SDIF3_PSEL_1 CFG3 B In - 2.121 - SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.un1_R_SDIF3_PSEL_1 CFG3 Y Out 0.148 2.269 - un1_R_SDIF3_PSEL_1 Net - - 0.745 - 5 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.int_prdata_4_sqmuxa CFG4 D In - 3.014 - SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.int_prdata_4_sqmuxa CFG4 Y Out 0.271 3.286 - int_prdata_4_sqmuxa Net - - 0.933 - 17 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.prdata_0_iv_1[0] CFG3 A In - 4.219 - SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.prdata_0_iv_1[0] CFG3 Y Out 0.077 4.296 - prdata_0_iv_1[0] Net - - 0.556 - 1 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.prdata_0_iv[0] CFG4 D In - 4.852 - SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.prdata_0_iv[0] CFG4 Y Out 0.271 5.123 - prdata[0] Net - - 0.159 - 1 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[0] SLE D In - 5.282 - ========================================================================================================================= Total path delay (propagation time + setup) of 5.537 is 1.219(22.0%) logic and 4.318(78.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_ADDR[14] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PADDR[14] 3.542 0.607 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_ADDR[13] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PADDR[13] 3.548 0.644 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_ADDR[12] DATAHANDLE_FSM_0_DATA_RADDR[10] 3.583 1.087 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_ADDR[15] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PADDR[15] 3.594 1.193 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_SEL SF2_JESD204B_DEMO_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx 3.626 1.299 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 I2C1_SDA_MGPIO0A_H2F_B SF2_JESD204B_DEMO_sb_0_GPIO_0_M2F 3.774 2.328 DATAHANDLE_FSM_0.DATA_WADDR[0] SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q DATAHANDLE_FSM_0_DATA_WADDR[0] 0.108 3.137 DATAHANDLE_FSM_0.DATA_WADDR[1] SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q DATAHANDLE_FSM_0_DATA_WADDR[1] 0.108 3.137 DATAHANDLE_FSM_0.DATA_WADDR[2] SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q DATAHANDLE_FSM_0_DATA_WADDR[2] 0.108 3.137 DATAHANDLE_FSM_0.DATA_WADDR[3] SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q DATAHANDLE_FSM_0_DATA_WADDR[3] 0.108 3.137 ================================================================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[2] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PRDATA_m[2] 8.591 0.607 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[22] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PRDATA_m[22] 8.523 0.617 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[18] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PRDATA_m[18] 8.609 0.743 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[13] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PRDATA_m[13] 8.815 0.831 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[30] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PRDATA_m[30] 8.750 0.844 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[29] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PRDATA_m[29] 8.754 0.848 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[15] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PRDATA_m[15] 8.834 0.850 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[26] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PRDATA_m[26] 8.762 0.856 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[17] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PRDATA_m[17] 8.723 0.857 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[21] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PRDATA_m[21] 8.780 0.874 ======================================================================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 1.409 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.591 - Propagation time: 7.984 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 0.607 Number of logic level(s): 3 Starting point: SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[14] Ending point: SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[2] The start point is clocked by SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE The end point is clocked by SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST MSS_075 F_HM0_ADDR[14] Out 3.542 3.542 - SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PADDR[14] Net - - 1.117 - 1 SF2_JESD204B_DEMO_sb_0.CoreAPB3_0.iPSELS_1_0[0] CFG2 B In - 4.659 - SF2_JESD204B_DEMO_sb_0.CoreAPB3_0.iPSELS_1_0[0] CFG2 Y Out 0.143 4.802 - iPSELS_1[0] Net - - 0.556 - 1 SF2_JESD204B_DEMO_sb_0.CoreAPB3_0.iPSELS[0] CFG4 B In - 5.358 - SF2_JESD204B_DEMO_sb_0.CoreAPB3_0.iPSELS[0] CFG4 Y Out 0.164 5.522 - SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PSELx Net - - 1.057 - 33 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST_RNO_1 CFG4 D In - 6.579 - SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST_RNO_1 CFG4 Y Out 0.288 6.867 - SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PRDATA_m[2] Net - - 1.117 - 1 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST MSS_075 F_HM0_RDATA[2] In - 7.984 - ================================================================================================================================================== Total path delay (propagation time + setup) of 9.393 is 5.546(59.0%) logic and 3.846(41.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[0] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[0] 0.108 7.333 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[1] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[1] 0.108 7.408 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[2] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[2] 0.108 7.425 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[3] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[3] 0.108 7.441 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[4] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[4] 0.108 7.457 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[5] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[5] 0.108 7.473 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[6] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[6] 0.108 7.490 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[7] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[7] 0.108 7.506 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[8] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[8] 0.108 7.522 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[9] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[9] 0.108 7.537 ==================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[12] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[12] 9.745 7.333 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[11] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[11] 9.745 7.350 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[10] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[10] 9.745 7.366 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[9] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[9] 9.745 7.382 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[8] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[8] 9.745 7.399 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[7] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[7] 9.745 7.415 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[6] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[6] 9.745 7.431 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[5] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[5] 9.745 7.447 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[4] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[4] 9.745 7.464 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[3] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[3] 9.745 7.480 ========================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.745 - Propagation time: 2.411 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 7.333 Number of logic level(s): 13 Starting point: SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[0] / Q Ending point: SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[12] / D The start point is clocked by SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock [rising] on pin CLK The end point is clocked by SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------- SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[0] SLE Q Out 0.108 0.108 - count_sdif0[0] Net - - 0.733 - 3 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_s_955 ARI1 B In - 0.841 - SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_s_955 ARI1 FCO Out 0.201 1.042 - count_sdif0_s_955_FCO Net - - 0.000 - 1 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_cry[1] ARI1 FCI In - 1.042 - SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_cry[1] ARI1 FCO Out 0.016 1.058 - count_sdif0_cry[1] Net - - 0.000 - 1 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_cry[2] ARI1 FCI In - 1.058 - SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_cry[2] ARI1 FCO Out 0.016 1.075 - count_sdif0_cry[2] Net - - 0.000 - 1 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_cry[3] ARI1 FCI In - 1.075 - SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_cry[3] ARI1 FCO Out 0.016 1.091 - count_sdif0_cry[3] Net - - 0.000 - 1 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_cry[4] ARI1 FCI In - 1.091 - SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_cry[4] ARI1 FCO Out 0.016 1.107 - count_sdif0_cry[4] Net - - 0.000 - 1 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_cry[5] ARI1 FCI In - 1.107 - SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_cry[5] ARI1 FCO Out 0.016 1.123 - count_sdif0_cry[5] Net - - 0.000 - 1 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_cry[6] ARI1 FCI In - 1.123 - SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_cry[6] ARI1 FCO Out 0.016 1.140 - count_sdif0_cry[6] Net - - 0.000 - 1 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_cry[7] ARI1 FCI In - 1.140 - SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_cry[7] ARI1 FCO Out 0.016 1.156 - count_sdif0_cry[7] Net - - 0.000 - 1 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_cry[8] ARI1 FCI In - 1.156 - SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_cry[8] ARI1 FCO Out 0.016 1.172 - count_sdif0_cry[8] Net - - 0.000 - 1 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_cry[9] ARI1 FCI In - 1.172 - SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_cry[9] ARI1 FCO Out 0.016 1.189 - count_sdif0_cry[9] Net - - 0.000 - 1 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_cry[10] ARI1 FCI In - 1.189 - SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_cry[10] ARI1 FCO Out 0.016 1.205 - count_sdif0_cry[10] Net - - 0.000 - 1 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_cry[11] ARI1 FCI In - 1.205 - SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_cry[11] ARI1 FCO Out 0.016 1.221 - count_sdif0_cry[11] Net - - 0.000 - 1 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_s[12] ARI1 FCI In - 1.221 - SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0_s[12] ARI1 S Out 0.073 1.294 - count_sdif0_s[12] Net - - 1.117 - 1 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[12] SLE D In - 2.411 - ====================================================================================================================== Total path delay (propagation time + setup) of 2.667 is 0.817(30.6%) logic and 1.850(69.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied None Finished final timing analysis (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 202MB peak: 218MB) Finished timing report (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 202MB peak: 218MB) --------------------------------------- Resource Usage Report for SF2_JESD204B_DEMO Mapping to part: m2s090tfbga484std Cell usage: BUFD 80 uses CCC 1 use CLKINT 11 uses MSS_075 1 use RCOSC_25_50MHZ 1 use RCOSC_25_50MHZ_FAB 1 use SERDESIF_075 1 use SYSRESET 1 use CFG1 13 uses CFG2 438 uses CFG3 710 uses CFG4 1132 uses Carry cells: ARI1 144 uses - used for arithmetic functions ARI1 742 uses - used for Wide-Mux implementation Total ARI1 886 uses Sequential Cells: SLE 2733 uses DSP Blocks: 0 of 84 (0%) I/O ports: 33 I/O primitives: 16 INBUF 6 uses OUTBUF 8 uses TRIBUFF 2 uses Global Clock Buffers: 11 of 8 (137%) RAM/ROM usage summary Total Block RAMs (RAM1K18) : 6 of 109 (5%) Total LUTs: 3179 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 216; LUTs = 216; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 2733 + 0 + 216 + 0 = 2949; Total number of LUTs after P&R: 3179 + 0 + 216 + 0 = 3395; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 41MB peak: 218MB) Process took 0h:00m:13s realtime, 0h:00m:12s cputime # Tue Mar 14 16:14:33 2017 ###########################################################]