Synopsys Generic Technology Pre-mapping, Version map201503actrcp1, Build 002R, Built Jul 1 2015 06:58:23 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-3 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) Reading constraint file: E:\Libero_11p6_0_28_capture_test\SF2_JESD204B_DEMO\synthesis\SF2_JESD204B_DEMO_syn.fdc Linked File: SF2_JESD204B_DEMO_scck.rpt Printing clock summary report in "E:\Libero_11p6_0_28_capture_test\SF2_JESD204B_DEMO\synthesis\SF2_JESD204B_DEMO_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 122MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 122MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 122MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 122MB) @W:BN132 : coreresetp.v(1089) | Removing sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int, because it is equivalent to instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int @N:BN362 : rx_ctrl.v(132) | Removing sequential instance MF_PHASE_ST_reg_3 of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s(verilog) because there are no references to its outputs @N:BN362 : rx_ctrl.v(132) | Removing sequential instance F_PHASE_ST_reg_3 of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s(verilog) because there are no references to its outputs @N:BN362 : enc_k.v(171) | Removing sequential instance K_ERR of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_ENC_K_0s_2(verilog) because there are no references to its outputs @N:BN362 : enc_k.v(171) | Removing sequential instance KCODE_6B_1[0] of view:PrimLib.dffs(prim) in hierarchy view:work.CJESDTX_ENC_K_0s_2(verilog) because there are no references to its outputs @N:BN362 : enc_k.v(171) | Removing sequential instance KCODE_6B_1[5:2] of view:PrimLib.dffpatr(prim) in hierarchy view:work.CJESDTX_ENC_K_0s_2(verilog) because there are no references to its outputs @N:BN362 : enc_k.v(171) | Removing sequential instance KCODE_4B[3:0] of view:PrimLib.dffpatr(prim) in hierarchy view:work.CJESDTX_ENC_K_0s_2(verilog) because there are no references to its outputs @N:BN362 : enc_k.v(171) | Removing sequential instance SP_4B_RDP of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_ENC_K_0s_2(verilog) because there are no references to its outputs @N:BN362 : enc_k.v(171) | Removing sequential instance SP_4B_RDN of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_ENC_K_0s_2(verilog) because there are no references to its outputs @N:BN362 : enc_flip.v(99) | Removing sequential instance EN_INV_6B of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_ENC_FLIP_0s_2(verilog) because there are no references to its outputs @N:BN362 : enc_flip.v(99) | Removing sequential instance EN_INV_4B of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_ENC_FLIP_0s_2(verilog) because there are no references to its outputs @N:BN362 : enc_flip.v(99) | Removing sequential instance INV_4B_RD of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_ENC_FLIP_0s_2(verilog) because there are no references to its outputs @N:BN362 : encoder_u.v(83) | Removing sequential instance INVALID_K of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_ENCODER_U_0s(verilog) because there are no references to its outputs @N:BN362 : encoder_l.v(84) | Removing sequential instance INVALID_K of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_ENCODER_L_0s(verilog) because there are no references to its outputs @N:BN362 : epcs_tx_intf.v(41) | Removing sequential instance txvalo of view:PrimLib.dffr(prim) in hierarchy view:work.epcs_tx_intf(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance MDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z13(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z13(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z13(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF3_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z13(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z14(verilog) because there are no references to its outputs @N:BN362 : data_handle_fsm.v(190) | Removing sequential instance WR_ENABLE of view:PrimLib.dffre(prim) in hierarchy view:work.DATAHANDLE_FSM(verilog) because there are no references to its outputs @N:BN362 : rx_ctrl.v(132) | Removing sequential instance MF_PHASE_ST_reg_2 of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s(verilog) because there are no references to its outputs @N:BN362 : rx_ctrl.v(132) | Removing sequential instance F_PHASE_ST_reg_2 of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s(verilog) because there are no references to its outputs @N:BN362 : encoder_u.v(83) | Removing sequential instance BAD_K of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_ENCODER_U_0s(verilog) because there are no references to its outputs @N:BN362 : encoder_l.v(84) | Removing sequential instance BAD_K of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_ENCODER_L_0s(verilog) because there are no references to its outputs @N:BN362 : epcs_tx_intf.v(29) | Removing sequential instance txval_p of view:PrimLib.dffr(prim) in hierarchy view:work.epcs_tx_intf(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z14(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z14(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z14(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z14(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z14(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z14(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z14(verilog) because there are no references to its outputs @N:BN362 : rx_ctrl.v(132) | Removing sequential instance MF_PHASE_ST_reg_1 of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s(verilog) because there are no references to its outputs @N:BN362 : rx_ctrl.v(132) | Removing sequential instance F_PHASE_ST_reg_1 of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s(verilog) because there are no references to its outputs @N:BN362 : enc_flip.v(57) | Removing sequential instance X_7 of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_ENC_FLIP_0s_2(verilog) because there are no references to its outputs @N:BN362 : enc_flip.v(57) | Removing sequential instance Y_3 of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_ENC_FLIP_0s_2(verilog) because there are no references to its outputs @N:BN362 : rx_ctrl.v(132) | Removing sequential instance MF_PHASE_ST_reg_0 of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s(verilog) because there are no references to its outputs @N:BN362 : rx_ctrl.v(132) | Removing sequential instance F_PHASE_ST_reg_0 of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s(verilog) because there are no references to its outputs @N:BN362 : enc_k.v(117) | Removing sequential instance X_DLY[4:0] of view:PrimLib.dffpatr(prim) in hierarchy view:work.CJESDTX_ENC_K_0s_2(verilog) because there are no references to its outputs @N:BN362 : enc_k.v(117) | Removing sequential instance X_EQ_14 of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_ENC_K_0s_2(verilog) because there are no references to its outputs @N:BN362 : enc_k.v(117) | Removing sequential instance X_EQ_13 of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_ENC_K_0s_2(verilog) because there are no references to its outputs @N:BN362 : enc_k.v(117) | Removing sequential instance X_EQ_11 of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_ENC_K_0s_2(verilog) because there are no references to its outputs @N:BN362 : enc_k.v(117) | Removing sequential instance X_EQ_20 of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_ENC_K_0s_2(verilog) because there are no references to its outputs @N:BN362 : enc_k.v(117) | Removing sequential instance X_EQ_18 of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_ENC_K_0s_2(verilog) because there are no references to its outputs @N:BN362 : enc_k.v(117) | Removing sequential instance X_EQ_17 of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_ENC_K_0s_2(verilog) because there are no references to its outputs @N:BN362 : enc_k.v(171) | Removing sequential instance K_ERR of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_ENC_K_0s_0(verilog) because there are no references to its outputs @N:BN362 : enc_k.v(171) | Removing sequential instance K_ERR of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_ENC_K_0s_1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z14(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z14(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z14(verilog) because there are no references to its outputs @N:BN362 : enc_k.v(117) | Removing sequential instance Y_DLY[2:0] of view:PrimLib.dffpatr(prim) in hierarchy view:work.CJESDTX_ENC_K_0s_2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z14(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z14(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z14(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z14(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z14(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z14(verilog) because there are no references to its outputs syn_allowed_resources : blockrams=109 set on top level netlist SF2_JESD204B_DEMO Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 152MB) @S |Clock Summary ***************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ------------------------------------------------------------------------------------------------------------------------------------ SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_3 SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK 25.0 MHz 40.000 declared default_clkgroup SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_1 System 100.0 MHz 10.000 system system_clkgroup ==================================================================================================================================== @W:MT530 : data_handle_fsm.v(131) | Found inferred clock SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock which controls 102 sequential elements including DATAHANDLE_FSM_0.DATA_WADDR1[10:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coreresetp.v(1485) | Found inferred clock SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 30 sequential elements including SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[12:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : sync_dec.v(68) | Found inferred clock SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock which controls 536 sequential elements including CoreJESD204BTX_0.CJESDTX_SYNC_DEC.sync_counter[2:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : sync_enc.v(83) | Found inferred clock SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock which controls 1051 sequential elements including CoreJESD204BRX_0.CJESDRX_SYNC_ENC.SYNC_GEN_ST[2:0]. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file E:\Libero_11p6_0_28_capture_test\SF2_JESD204B_DEMO\synthesis\SF2_JESD204B_DEMO.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 83MB peak: 152MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Jul 21 11:40:17 2015 ###########################################################]