Synopsys Generic Technology Mapper, Version map201503actrcp1, Build 002R, Built Jul 1 2015 06:58:23 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-3 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_1 on net EPCS_3_TX_DATA_1 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_2 on net EPCS_3_TX_DATA_2 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_3 on net EPCS_3_TX_DATA_3 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_4 on net EPCS_3_TX_DATA_4 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_5 on net EPCS_3_TX_DATA_5 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_6 on net EPCS_3_TX_DATA_6 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_7 on net EPCS_3_TX_DATA_7 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_8 on net EPCS_3_TX_DATA_8 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_9 on net EPCS_3_TX_DATA_9 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_10 on net EPCS_3_TX_DATA_10 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_11 on net EPCS_3_TX_DATA_11 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_12 on net EPCS_3_TX_DATA_12 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_13 on net EPCS_3_TX_DATA_13 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_14 on net EPCS_3_TX_DATA_14 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_15 on net EPCS_3_TX_DATA_15 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_16 on net EPCS_3_TX_DATA_16 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_17 on net EPCS_3_TX_DATA_17 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_18 on net EPCS_3_TX_DATA_18 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_19 on net EPCS_3_TX_DATA_19 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_20 on net EPCS_3_TX_DATA_20 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_1 on net EPCS_2_TX_DATA_1 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_2 on net EPCS_2_TX_DATA_2 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_3 on net EPCS_2_TX_DATA_3 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_4 on net EPCS_2_TX_DATA_4 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_5 on net EPCS_2_TX_DATA_5 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_6 on net EPCS_2_TX_DATA_6 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_7 on net EPCS_2_TX_DATA_7 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_8 on net EPCS_2_TX_DATA_8 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_9 on net EPCS_2_TX_DATA_9 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_10 on net EPCS_2_TX_DATA_10 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_11 on net EPCS_2_TX_DATA_11 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_12 on net EPCS_2_TX_DATA_12 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_13 on net EPCS_2_TX_DATA_13 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_14 on net EPCS_2_TX_DATA_14 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_15 on net EPCS_2_TX_DATA_15 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_16 on net EPCS_2_TX_DATA_16 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_17 on net EPCS_2_TX_DATA_17 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_18 on net EPCS_2_TX_DATA_18 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_19 on net EPCS_2_TX_DATA_19 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_20 on net EPCS_2_TX_DATA_20 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_1 on net EPCS_1_TX_DATA_1 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_2 on net EPCS_1_TX_DATA_2 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_3 on net EPCS_1_TX_DATA_3 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_4 on net EPCS_1_TX_DATA_4 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_5 on net EPCS_1_TX_DATA_5 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_6 on net EPCS_1_TX_DATA_6 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_7 on net EPCS_1_TX_DATA_7 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_8 on net EPCS_1_TX_DATA_8 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_9 on net EPCS_1_TX_DATA_9 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_10 on net EPCS_1_TX_DATA_10 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_11 on net EPCS_1_TX_DATA_11 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_12 on net EPCS_1_TX_DATA_12 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_13 on net EPCS_1_TX_DATA_13 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_14 on net EPCS_1_TX_DATA_14 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_15 on net EPCS_1_TX_DATA_15 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_16 on net EPCS_1_TX_DATA_16 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_17 on net EPCS_1_TX_DATA_17 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_18 on net EPCS_1_TX_DATA_18 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_19 on net EPCS_1_TX_DATA_19 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_20 on net EPCS_1_TX_DATA_20 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : sf2_jesd204b_demo_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module SF2_JESD204B_DEMO_sb_FABOSC_0_OSC) @W:MO111 : sf2_jesd204b_demo_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module SF2_JESD204B_DEMO_sb_FABOSC_0_OSC) @W:MO111 : sf2_jesd204b_demo_sb_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module SF2_JESD204B_DEMO_sb_FABOSC_0_OSC) @W:MO111 : sf2_jesd204b_demo_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module SF2_JESD204B_DEMO_sb_FABOSC_0_OSC) @W:MO171 : coreresetp.v(676) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF0_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(695) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF1_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF2_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF3_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(676) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF0_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(695) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF1_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF2_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF3_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(676) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF0_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(695) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF1_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF2_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF3_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(769) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(769) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(1388) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation @W:MO171 : rx_ctrl.v(132) | Sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_RX_CTRL.F_PHASE_reg_0[0] reduced to a combinational gate by constant propagation @W:MO171 : adj_ctrl.v(111) | Sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.F_PHASE_reg_0[0] reduced to a combinational gate by constant propagation @N:BN362 : tx_acg.v(206) | Removing sequential instance CJESDTX_TX_ACG.FCount_U[3:0] of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_JESD204BTX_LANE_Z10(verilog) because there are no references to its outputs @N:BN362 : clock_gen_tx.v(164) | Removing sequential instance CJESDTX_CLOCK_GEN_TX.LMFC_PHASE_1[4:1] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreJESD204BTX_Z11(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(90) | Removing instance UT1B5 of view:work.CJESDTX_MUX4X1_5(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(92) | Removing instance UT1B6 of view:work.CJESDTX_MUX4X1_2_0(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(94) | Removing instance UT1B7 of view:work.CJESDTX_MUX4X1_5(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(86) | Removing instance UT1B3 of view:work.CJESDTX_MUX4X1_1(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(88) | Removing instance UT1B4 of view:work.CJESDTX_MUX4X1_0_0_0(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(90) | Removing instance UT1B5 of view:work.CJESDTX_MUX4X1_0_0_0(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(82) | Removing instance UT1B1 of view:work.CJESDTX_MUX4X1_4_0(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(84) | Removing instance UT1B2 of view:work.CJESDTX_MUX4X1_4_0(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(88) | Removing instance UT1B4 of view:work.CJESDTX_MUX4X1_3(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(90) | Removing instance UT1B5 of view:work.CJESDTX_MUX4X1_3(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(92) | Removing instance UT1B6 of view:work.CJESDTX_MUX4X1_1(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(94) | Removing instance UT1B7 of view:work.CJESDTX_MUX4X1_3(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(101) | Removing instance UT2B1 of view:work.CJESDTX_MUX4X1_6_0(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(80) | Removing instance UT1B0 of view:work.CJESDTX_MUX4X1_1(verilog) because there are no references to its outputs @W:BN132 : mux32x1.v(94) | Removing user instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB5.UT1B7, because it is equivalent to instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB5.UT1B5 @W:BN132 : mux32x1.v(90) | Removing user instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB5.UT1B5, because it is equivalent to instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB5.UT1B4 @W:BN132 : mux32x1.v(84) | Removing user instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB5.UT1B2, because it is equivalent to instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB5.UT1B1 @W:BN132 : mux32x1.v(90) | Removing user instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB4.UT1B5, because it is equivalent to instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB4.UT1B3 @W:BN132 : mux32x1.v(88) | Removing user instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB4.UT1B4, because it is equivalent to instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB4.UT1B2 @W:BN132 : mux32x1.v(88) | Removing user instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB3.UT1B4, because it is equivalent to instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB3.UT1B2 @W:BN132 : mux32x1.v(94) | Removing user instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB2.UT1B7, because it is equivalent to instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB2.UT1B0 @W:BN132 : mux32x1.v(92) | Removing user instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB2.UT1B6, because it is equivalent to instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB2.UT1B2 @W:BN132 : mux32x1.v(92) | Removing user instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB0.UT1B6, because it is equivalent to instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB0.UT1B5 @W:BN132 : mux32x1.v(88) | Removing user instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB0.UT1B4, because it is equivalent to instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB0.UT1B2 Available hyper_sources - for debug and ip models None Found @N:MT480 : sf2_jesd204b_demo_syn.fdc(18) | Assigning clock "SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_TMP_0_FIC_2_APB_M_PCLK" to command: create_clock {n:SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK} -period {40} @N:BN362 : sync_dec.v(107) | Removing sequential instance genblk1\.sync_state of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_SYNC_DEC_2s_0s_0s_6s(verilog) because there are no references to its outputs Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 149MB) @N:MF135 : data_sync_buf.v(87) | Found RAM 'CJESDRX_DATA_SYNC_BUF_0.data_buf[19:0]', 4 words by 20 bits Encoding state machine SYNC_GEN_ST[2:0] (view:work.CJESDRX_SYNC_ENC_0s_0s_2s_10s_0s_0_1_2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @W:MO129 : sync_enc.v(83) | Sequential instance CoreJESD204BRX_0.CJESDRX_SYNC_ENC.SYNC_GEN_ST[0] reduced to a combinational gate by constant propagation @W:MO129 : rx_ctrl.v(132) | Sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_RX_CTRL.MF_PHASE_reg_0[0] reduced to a combinational gate by constant propagation Encoding state machine CG_state[2:0] (view:work.CJESDRX_CGS_0s_0_1_2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine ILA_state[4:0] (view:work.CJESDRX_ILA_FSM_Z2(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 Encoding state machine RIstate[2:0] (view:work.CJESDRX_ILA_FSM_Z2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N: : ila_fsm.v(210) | Found counter in view:work.CJESDRX_ILA_FSM_Z2(verilog) inst R_cnt[6:0] @N:MF135 : eb_ram_rtl.v(65) | Found RAM 'CJESDRX_RAM_EB.EB_RAM[17:0]', 32 words by 18 bits @N: : eb_ctrl.v(149) | Found counter in view:work.CJESDRX_EB_CTRL_0s_2s_9s_18s_18s_0_1(verilog) inst WADDR[4:0] Encoding state machine CD_S_state[2:0] (view:work.CJESDRX_LINK_COMP_Z4(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine CD_M_state[7:0] (view:work.CJESDRX_LINK_COMP_Z4(verilog)) original code -> new code 000 -> 00000001 001 -> 00000010 010 -> 00000100 011 -> 00001000 100 -> 00010000 101 -> 00100000 110 -> 01000000 111 -> 10000000 Encoding state machine FSstate[2:0] (view:work.CJESDRX_IFS_POS_0s_2s_9s_0_1_2_0_1(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine CC_state[1:0] (view:work.CJESDRX_IFS_POS_0s_2s_9s_0_1_2_0_1(verilog)) original code -> new code 00 -> 0 01 -> 1 @N:MO225 : ifs_pos.v(210) | No possible illegal states for state machine CC_state[1:0],safe FSM implementation is disabled Encoding state machine SYNC_STATE[4:0] (view:work.CJESDRX_SYNC_FSM_0s_0_1_2_3_4_4(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 Encoding state machine WA_FSM_STATE[3:0] (view:work.CJESDRX_WORD_ALIGNER_Z5(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : word_aligner.v(734) | No possible illegal states for state machine WA_FSM_STATE[3:0],safe FSM implementation is disabled @N:MF135 : data_sync_buf_tx.v(141) | Found RAM 'DATA_SYNC_BUF_0.data[19:0]', 4 words by 20 bits @N:FX403 : data_sync_buf_tx.v(141) | Property "block_ram" or "no_rw_check" found for RAM DATA_SYNC_BUF_0.data[19:0] with specified coding style. Inferring block RAM. @W:FX107 : data_sync_buf_tx.v(141) | No read/write conflict check. Possible simulation mismatch! @N:MF707 : data_sync_buf_tx.v(141) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for DATA_SYNC_BUF_0.data[19:0] (view:work.CoreJESD204BTX_Z11(verilog)). Encoding state machine TX_STATE_1[2:0] (view:work.CJESDTX_CJESDTX_TX_ACG_0s_0_1_2_0s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:FX404 : wav_gen_16bit.v(171) | Found addmux in view:work.waveform_gen(verilog) inst SAW_DATA16_3[15:0] from un2_SAW_DATA16[15:0] @W:MO160 : wav_gen_16bit.v(135) | Register bit SQR_DATA16[10] is always 0, optimizing ... @W:MO161 : wav_gen_16bit.v(135) | Register bit SQR_DATA16[9] is always 1, optimizing ... @W:MO160 : wav_gen_16bit.v(135) | Register bit SQR_DATA16[4] is always 0, optimizing ... @W:MO160 : wav_gen_16bit.v(135) | Register bit SQR_DATA16[2] is always 0, optimizing ... @W:MO160 : wav_gen_16bit.v(135) | Register bit SQR_DATA16[1] is always 0, optimizing ... @W:MO160 : wav_gen_16bit.v(135) | Register bit SQR_DATA16[0] is always 0, optimizing ... Encoding state machine fsm[3:0] (view:work.DATAHANDLE_FSM(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : data_handle_fsm.v(190) | No possible illegal states for state machine fsm[3:0],safe FSM implementation is disabled @N: : data_handle_fsm.v(131) | Found counter in view:work.DATAHANDLE_FSM(verilog) inst DATA_WADDR1[10:0] Encoding state machine state[2:0] (view:work.CoreConfigP_Z13(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @W:MO160 : coreconfigp.v(255) | Register bit paddr[16] is always 0, optimizing ... Encoding state machine sm0_state[6:0] (view:work.CoreResetP_Z14(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sdif0_state[3:0] (view:work.CoreResetP_Z14(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : coreresetp.v(1170) | No possible illegal states for state machine sdif0_state[3:0],safe FSM implementation is disabled @N: : coreresetp.v(1485) | Found counter in view:work.CoreResetP_Z14(verilog) inst count_sdif0[12:0] @N:BN362 : fadm_or.v(106) | Removing sequential instance CJESDRX_FADM_OR.FPC[0] in hierarchy view:work.CJESDRX_JESD204BRX_LANE_Z6(verilog) because there are no references to its outputs @N:BN362 : fadm_or.v(106) | Removing sequential instance CJESDRX_FADM_OR.FPC[1] in hierarchy view:work.CJESDRX_JESD204BRX_LANE_Z6(verilog) because there are no references to its outputs @N:BN362 : adj_ctrl.v(111) | Removing sequential instance CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.MF_PHASE_reg_0[0] in hierarchy view:work.CJESDRX_JESD204BRX_LANE_Z6(verilog) because there are no references to its outputs @N:BN362 : adj_ctrl.v(111) | Removing sequential instance CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.MF_PHASE_reg_1[0] in hierarchy view:work.CJESDRX_JESD204BRX_LANE_Z6(verilog) because there are no references to its outputs @N:BN362 : adj_ctrl.v(111) | Removing sequential instance CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.MF_PHASE_reg_3[0] in hierarchy view:work.CJESDRX_JESD204BRX_LANE_Z6(verilog) because there are no references to its outputs @N:BN362 : adj_ctrl.v(111) | Removing sequential instance CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.MF_PHASE_reg_2[0] in hierarchy view:work.CJESDRX_JESD204BRX_LANE_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1170) | Removing sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF0_PHY_RESET_N_int in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 180MB peak: 181MB) @N:BN362 : tx_ila.v(473) | Removing sequential instance CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.MFOValue_L[0] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 171MB peak: 181MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 167MB peak: 186MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 169MB peak: 186MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 184MB peak: 186MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 183MB peak: 186MB) @N:MO106 : dec_data.v(78) | Found ROM, 'CoreJESD204BRX_0.LANE_0.CJESDRX_DEC_WA.CJESDRX_DECODER_CI.UB.DATA_5B_0[4:0]', 48 words by 5 bits @N:MO106 : dec_data.v(78) | Found ROM, 'CoreJESD204BRX_0.LANE_0.CJESDRX_DEC_WA.CJESDRX_DECODER_CO.UB.DATA_5B_0[4:0]', 48 words by 5 bits @N:BN362 : wav_gen_16bit.v(163) | Removing sequential instance DATA_GENERATOR_0.waveform_gen_0.SAW_DATA16[0] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs Finished preparing to map (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 183MB peak: 186MB) Finished technology mapping (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 222MB peak: 241MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:09s -4.01ns 3122 / 2012 2 0h:00m:09s -4.01ns 2653 / 2012 3 0h:00m:09s -3.93ns 2652 / 2012 @N:FX271 : eb_ctrl.v(385) | Instance "CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.SC[0]" with 14 loads replicated 1 times to improve timing @N:FX271 : eb_ctrl.v(385) | Instance "CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.SC[1]" with 13 loads replicated 1 times to improve timing @N:FX271 : eb_ctrl.v(183) | Instance "CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[0]" with 100 loads replicated 3 times to improve timing @N:FX271 : ila_fsm.v(318) | Instance "CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ILA_FSM.EB_RE" with 29 loads replicated 2 times to improve timing @N:FX271 : eb_ctrl.v(183) | Instance "CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[1]" with 156 loads replicated 3 times to improve timing @N:FX271 : eb_ctrl.v(385) | Instance "CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.SC[2]" with 15 loads replicated 2 times to improve timing @N:FX271 : eb_ctrl.v(95) | Instance "CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg[2]" with 14 loads replicated 1 times to improve timing @N:FX271 : eb_ctrl.v(95) | Instance "CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg[1]" with 14 loads replicated 2 times to improve timing Timing driven replication report Added 15 Registers via timing driven replication Added 10 LUTs via timing driven replication @N:FX271 : rx_ctrl.v(113) | Instance "CoreJESD204BRX_0.LANE_0.CJESDRX_RX_CTRL.SYNC_REQUEST" with 20 loads replicated 1 times to improve timing @N:FX271 : eb_ctrl.v(183) | Instance "CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.eb_holdcnt[2]" with 4 loads replicated 1 times to improve timing @N:FX271 : eb_ctrl.v(183) | Instance "CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.eb_holdcnt[3]" with 4 loads replicated 1 times to improve timing @N:FX271 : eb_ctrl.v(95) | Instance "CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg[0]" with 14 loads replicated 2 times to improve timing Timing driven replication report Added 5 Registers via timing driven replication Added 3 LUTs via timing driven replication 4 0h:00m:11s -2.68ns 2674 / 2032 5 0h:00m:11s -2.68ns 2684 / 2032 6 0h:00m:11s -2.54ns 2685 / 2032 @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[0] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[1] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[2] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[3] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[4] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[5] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[6] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[7] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[8] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[9] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[10] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[11] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[12] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[13] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[14] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[15] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[16] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[17] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[18] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[19] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[20] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[21] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[22] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[23] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[24] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[25] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[26] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[27] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[28] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[29] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[30] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[31] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[32] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[33] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[34] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDA[35] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[0] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[1] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[2] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[3] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[4] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[5] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[6] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[7] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[8] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[9] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[10] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[11] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[12] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[13] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[14] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[15] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[16] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[17] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[18] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[19] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[20] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[21] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[22] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[23] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[24] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[25] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[26] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[27] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[28] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[29] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[30] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[31] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[32] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[33] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[34] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:BN362 : | Removing sequential instance CoreJESD204BTX_0.DATA_SYNC_BUF_0.data_data_0_0_OLDB[35] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs @N:FP130 : | Promoting Net CoreJESD204BRX_0_CLK_OUT on CLKINT I_488 @N:FP130 : | Promoting Net CoreJESD204BRX_0.syncd_rst_n_0[1] on CLKINT I_489 @N:FP130 : | Promoting Net CoreJESD204BTX_0_CLK_OUT on CLKINT I_490 @N:FP130 : | Promoting Net CoreJESD204BTX_0.syncd_rst_n_0[1] on CLKINT I_491 @N:FP130 : | Promoting Net SF2_JESD204B_DEMO_sb_0_INIT_APB_S_PRESET_N on CLKINT I_492 @N:FP130 : | Promoting Net SF2_JESD204B_DEMO_sb_0_INIT_APB_S_PCLK on CLKINT I_493 @N:FP130 : | Promoting Net SERDES_EPCS_0_EPCS_2_TX_RESET_N on CLKINT I_494 @N:FP130 : | Promoting Net DATAHANDLE_FSM_0_STATUS_OUT[12] on CLKINT I_495 @N:FP130 : | Promoting Net SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT I_496 @N:FP130 : | Promoting Net SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sm0_areset_n_rcosc on CLKINT I_497 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 229MB peak: 241MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 231MB peak: 241MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 5 non-gated/non-generated clock tree(s) driving 2050 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks ==================================================================================== Non-Gated/Non-Generated Clocks ===================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST SERDESIF_075 1371 SERDES_EPCS_0.epcs_rx_intf_0.rxvalo ClockId0002 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST SERDESIF_075 470 SERDES_EPCS_0.epcs_tx_intf_0.txdin_p[3] ClockId0003 SF2_JESD204B_DEMO_sb_0.CCC_0.GL0_INST CLKINT 81 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST ClockId0004 SF2_JESD204B_DEMO_sb_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB_CLKINT CLKINT 19 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[12] ClockId0005 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK_keep clock definition on keepbuf 109 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.SDIF_RELEASED_q2 ========================================================================================================================================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 188MB peak: 241MB) Writing Analyst data base E:\Libero_11p6_0_28_capture_test\SF2_JESD204B_DEMO\synthesis\synwork\SF2_JESD204B_DEMO_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:13s; Memory used current: 223MB peak: 241MB) Writing EDIF Netlist and constraint files @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF J-2015.03M-3 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:14s; Memory used current: 225MB peak: 241MB) Start final timing analysis (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 218MB peak: 241MB) @W:MT246 : sf2_jesd204b_demo_sb_ccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) Found clock SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK with period 40.00ns @W:MT420 : | Found inferred clock SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:SF2_JESD204B_DEMO_sb_0.FABOSC_0.RCOSC_25_50MHZ_CCC" @W:MT420 : | Found inferred clock SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:SF2_JESD204B_DEMO_sb_0.CCC_0.GL0_net" @W:MT420 : | Found inferred clock SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:SERDES_EPCS_0.SERDES_IF2_0.EPCS_2_RX_CLK" @W:MT420 : | Found inferred clock SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:SERDES_EPCS_0.SERDES_IF2_0.EPCS_2_TX_CLK" @S |##### START OF TIMING REPORT #####[ # Timing Report written on Tue Jul 21 11:40:32 2015 # Top view: SF2_JESD204B_DEMO Requested Frequency: 25.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): E:\Libero_11p6_0_28_capture_test\SF2_JESD204B_DEMO\synthesis\SF2_JESD204B_DEMO_syn.fdc @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: -1.728 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock 100.0 MHz 85.3 MHz 10.000 11.727 -1.728 inferred Inferred_clkgroup_3 SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock 100.0 MHz 139.6 MHz 10.000 7.165 2.835 inferred Inferred_clkgroup_2 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK 25.0 MHz 91.1 MHz 40.000 10.973 14.514 declared default_clkgroup SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 110.0 MHz 10.000 9.092 0.908 inferred Inferred_clkgroup_0 SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock 100.0 MHz 362.9 MHz 10.000 2.756 7.244 inferred Inferred_clkgroup_1 =========================================================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK | 40.000 31.562 | No paths - | 20.000 17.776 | 20.000 14.514 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock | Diff grp - | No paths - | No paths - | No paths - SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK | Diff grp - | No paths - | No paths - | No paths - SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock | 10.000 0.908 | No paths - | 5.000 3.801 | 5.000 3.143 SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | Diff grp - | No paths - | No paths - | No paths - SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock | Diff grp - | No paths - | No paths - | No paths - SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | 10.000 7.244 | No paths - | No paths - | No paths - SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock | 10.000 2.835 | No paths - | No paths - | No paths - SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock | Diff grp - | No paths - | No paths - | No paths - SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock | 10.000 -1.728 | No paths - | No paths - | 5.000 3.972 =================================================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR_fast[1] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE Q eb2ram_raddr_fast[1] 0.087 -1.728 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR_fast[0] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE Q eb2ram_raddr_fast[0] 0.108 -1.651 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg[3] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE Q ADJ_NUM_reg[3] 0.108 -1.229 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.SC[3] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE Q SC[3] 0.087 -1.216 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[2] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE Q eb2ram_raddr[2] 0.108 -1.200 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.eb_holdcnt[1] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE Q eb_holdcnt[1] 0.108 -1.079 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[3] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE Q eb2ram_raddr[3] 0.108 -1.047 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_fast[2] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE Q ADJ_NUM_reg_fast[2] 0.108 -1.029 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg_0_rep1 SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE Q CLogB2221_0_rep1 0.108 -0.941 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg[1] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE Q ADJ_NUM_reg[1] 0.087 -0.909 =============================================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[4] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE D SUM[4] 9.745 -1.728 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[3] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE D SUM[3] 9.745 -1.257 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.SC[3] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE D SC_8[3] 9.745 -0.554 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.SC[4] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE D SC_8[4] 9.745 -0.332 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[2] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE D SUM[2] 9.745 -0.265 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.SC[2] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE D SC_8[2] 9.745 0.388 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.SC_2_rep1 SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE D SC_8_rep1[2] 9.745 0.388 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.SC_fast[2] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE D SC_8_fast[2] 9.745 0.388 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[1] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE D SUM[1] 9.745 0.456 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR_1_rep1 SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock SLE D N_236_rep1 9.745 0.456 ================================================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.745 - Propagation time: 11.472 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.728 Number of logic level(s): 11 Starting point: CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR_fast[1] / Q Ending point: CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[4] / D The start point is clocked by SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock [rising] on pin CLK The end point is clocked by SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR_fast[1] SLE Q Out 0.087 0.087 - eb2ram_raddr_fast[1] Net - - 0.976 - 12 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238_1_0 CFG2 A In - 1.063 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238_1_0 CFG2 Y Out 0.100 1.164 - CLogB2238_1 Net - - 0.630 - 2 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238 CFG4 D In - 1.794 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238 CFG4 Y Out 0.470 2.263 - CLogB2238 Net - - 0.715 - 4 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238_RNIMI0E2 CFG4 D In - 2.978 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238_RNIMI0E2 CFG4 Y Out 0.470 3.448 - g0_14_sx_sx Net - - 0.630 - 2 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_0_N_2L1_sx_sx CFG4 D In - 4.078 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_0_N_2L1_sx_sx CFG4 Y Out 0.470 4.548 - CO1_0_0_N_2L1_sx_sx Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_0_N_2L1_sx CFG4 D In - 5.104 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_0_N_2L1_sx CFG4 Y Out 0.470 5.573 - CO1_0_0_N_2L1_sx Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_0_N_2L1 CFG4 D In - 6.129 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_0_N_2L1 CFG4 Y Out 0.442 6.571 - CO1_0_0_1 Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_0 CFG4 C In - 7.126 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_0 CFG4 Y Out 0.209 7.336 - CO1_0_0 Net - - 0.678 - 3 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.g0 CFG4 D In - 8.014 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.g0 CFG4 Y Out 0.428 8.442 - CO2_0_tz Net - - 0.630 - 2 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO2 CFG4 D In - 9.072 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO2 CFG4 Y Out 0.428 9.500 - CO2 Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_5_4_m[4] CFG4 D In - 10.056 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_5_4_m[4] CFG4 Y Out 0.472 10.528 - un1_RADDR_5_4[4] Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_5_1.SUM[4] CFG4 C In - 11.084 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_5_1.SUM[4] CFG4 Y Out 0.230 11.314 - SUM[4] Net - - 0.159 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[4] SLE D In - 11.472 - ==================================================================================================================================================================== Total path delay (propagation time + setup) of 11.728 is 4.532(38.6%) logic and 7.196(61.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.745 - Propagation time: 11.395 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.651 Number of logic level(s): 11 Starting point: CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR_fast[0] / Q Ending point: CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[4] / D The start point is clocked by SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock [rising] on pin CLK The end point is clocked by SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR_fast[0] SLE Q Out 0.108 0.108 - eb2ram_raddr_fast[0] Net - - 0.814 - 5 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238_1_0 CFG2 B In - 0.923 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238_1_0 CFG2 Y Out 0.164 1.087 - CLogB2238_1 Net - - 0.630 - 2 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238 CFG4 D In - 1.717 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238 CFG4 Y Out 0.470 2.187 - CLogB2238 Net - - 0.715 - 4 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238_RNIMI0E2 CFG4 D In - 2.902 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238_RNIMI0E2 CFG4 Y Out 0.470 3.371 - g0_14_sx_sx Net - - 0.630 - 2 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_0_N_2L1_sx_sx CFG4 D In - 4.001 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_0_N_2L1_sx_sx CFG4 Y Out 0.470 4.471 - CO1_0_0_N_2L1_sx_sx Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_0_N_2L1_sx CFG4 D In - 5.027 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_0_N_2L1_sx CFG4 Y Out 0.470 5.496 - CO1_0_0_N_2L1_sx Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_0_N_2L1 CFG4 D In - 6.052 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_0_N_2L1 CFG4 Y Out 0.442 6.494 - CO1_0_0_1 Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_0 CFG4 C In - 7.050 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_0 CFG4 Y Out 0.209 7.259 - CO1_0_0 Net - - 0.678 - 3 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.g0 CFG4 D In - 7.937 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.g0 CFG4 Y Out 0.428 8.365 - CO2_0_tz Net - - 0.630 - 2 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO2 CFG4 D In - 8.995 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO2 CFG4 Y Out 0.428 9.423 - CO2 Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_5_4_m[4] CFG4 D In - 9.979 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_5_4_m[4] CFG4 Y Out 0.472 10.451 - un1_RADDR_5_4[4] Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_5_1.SUM[4] CFG4 C In - 11.007 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_5_1.SUM[4] CFG4 Y Out 0.230 11.237 - SUM[4] Net - - 0.159 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[4] SLE D In - 11.395 - ==================================================================================================================================================================== Total path delay (propagation time + setup) of 11.651 is 4.616(39.6%) logic and 7.035(60.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.745 - Propagation time: 11.244 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.500 Number of logic level(s): 11 Starting point: CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR_fast[1] / Q Ending point: CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[4] / D The start point is clocked by SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock [rising] on pin CLK The end point is clocked by SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR_fast[1] SLE Q Out 0.087 0.087 - eb2ram_raddr_fast[1] Net - - 0.976 - 12 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238_1_0 CFG2 A In - 1.063 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238_1_0 CFG2 Y Out 0.100 1.164 - CLogB2238_1 Net - - 0.630 - 2 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238 CFG4 D In - 1.794 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238 CFG4 Y Out 0.470 2.263 - CLogB2238 Net - - 0.715 - 4 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238_RNIMI0E2_0 CFG4 D In - 2.978 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238_RNIMI0E2_0 CFG4 Y Out 0.470 3.448 - g0_4_1_sx_sx Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_SC_6lto4_RNIBAUP4_0 CFG4 D In - 4.004 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_SC_6lto4_RNIBAUP4_0 CFG4 Y Out 0.470 4.473 - g0_4_1_sx Net - - 0.630 - 2 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2307_2_RNI0I1G5_0[0] CFG4 D In - 5.104 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2307_2_RNI0I1G5_0[0] CFG4 Y Out 0.470 5.573 - g0_4_sx Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_0_0_RNIUTCP9[0] CFG4 B In - 6.129 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_0_0_RNIUTCP9[0] CFG4 Y Out 0.153 6.282 - g0_3_1 Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_1_RNIHC4HC[0] CFG4 D In - 6.838 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_1_RNIHC4HC[0] CFG4 Y Out 0.428 7.265 - ANB0_out Net - - 0.678 - 3 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_sx CFG4 C In - 7.944 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_sx CFG4 Y Out 0.226 8.169 - CO1_0_1 Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0 CFG4 C In - 8.725 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0 CFG4 Y Out 0.230 8.955 - BNC2 Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.SUM[3] CFG4 D In - 9.511 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.SUM[3] CFG4 Y Out 0.472 9.983 - un1_RADDR_5_40[3] Net - - 0.630 - 2 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_5_1.SUM[4] CFG4 D In - 10.613 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_5_1.SUM[4] CFG4 Y Out 0.472 11.086 - SUM[4] Net - - 0.159 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[4] SLE D In - 11.244 - ================================================================================================================================================================ Total path delay (propagation time + setup) of 11.500 is 4.304(37.4%) logic and 7.196(62.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.745 - Propagation time: 11.179 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.434 Number of logic level(s): 11 Starting point: CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR_fast[1] / Q Ending point: CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[4] / D The start point is clocked by SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock [rising] on pin CLK The end point is clocked by SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR_fast[1] SLE Q Out 0.087 0.087 - eb2ram_raddr_fast[1] Net - - 0.976 - 12 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238_1_0 CFG2 A In - 1.063 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238_1_0 CFG2 Y Out 0.100 1.164 - CLogB2238_1 Net - - 0.630 - 2 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238 CFG4 D In - 1.794 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238 CFG4 Y Out 0.470 2.263 - CLogB2238 Net - - 0.715 - 4 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238_RNIMI0E2 CFG4 D In - 2.978 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238_RNIMI0E2 CFG4 Y Out 0.470 3.448 - g0_14_sx_sx Net - - 0.630 - 2 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_0_N_2L1_sx_sx CFG4 D In - 4.078 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_0_N_2L1_sx_sx CFG4 Y Out 0.470 4.548 - CO1_0_0_N_2L1_sx_sx Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_0_N_2L1_sx CFG4 D In - 5.104 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_0_N_2L1_sx CFG4 Y Out 0.470 5.573 - CO1_0_0_N_2L1_sx Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_0_N_2L1 CFG4 D In - 6.129 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_0_N_2L1 CFG4 Y Out 0.442 6.571 - CO1_0_0_1 Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_0 CFG4 C In - 7.126 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_0 CFG4 Y Out 0.209 7.336 - CO1_0_0 Net - - 0.678 - 3 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_x CFG4 D In - 8.014 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_x CFG4 Y Out 0.428 8.442 - CO1_0_x Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO2 CFG4 C In - 8.998 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO2 CFG4 Y Out 0.209 9.207 - CO2 Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_5_4_m[4] CFG4 D In - 9.763 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_5_4_m[4] CFG4 Y Out 0.472 10.235 - un1_RADDR_5_4[4] Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_5_1.SUM[4] CFG4 C In - 10.791 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_5_1.SUM[4] CFG4 Y Out 0.230 11.021 - SUM[4] Net - - 0.159 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[4] SLE D In - 11.179 - ==================================================================================================================================================================== Total path delay (propagation time + setup) of 11.435 is 4.313(37.7%) logic and 7.122(62.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.745 - Propagation time: 11.168 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.423 Number of logic level(s): 11 Starting point: CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR_fast[0] / Q Ending point: CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[4] / D The start point is clocked by SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock [rising] on pin CLK The end point is clocked by SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR_fast[0] SLE Q Out 0.108 0.108 - eb2ram_raddr_fast[0] Net - - 0.814 - 5 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238_1_0 CFG2 B In - 0.923 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238_1_0 CFG2 Y Out 0.164 1.087 - CLogB2238_1 Net - - 0.630 - 2 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238 CFG4 D In - 1.717 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238 CFG4 Y Out 0.470 2.187 - CLogB2238 Net - - 0.715 - 4 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238_RNIMI0E2_0 CFG4 D In - 2.902 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2238_RNIMI0E2_0 CFG4 Y Out 0.470 3.371 - g0_4_1_sx_sx Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_SC_6lto4_RNIBAUP4_0 CFG4 D In - 3.927 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_SC_6lto4_RNIBAUP4_0 CFG4 Y Out 0.470 4.397 - g0_4_1_sx Net - - 0.630 - 2 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2307_2_RNI0I1G5_0[0] CFG4 D In - 5.027 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.CLogB2307_2_RNI0I1G5_0[0] CFG4 Y Out 0.470 5.496 - g0_4_sx Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_0_0_RNIUTCP9[0] CFG4 B In - 6.052 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_0_0_RNIUTCP9[0] CFG4 Y Out 0.153 6.205 - g0_3_1 Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_1_RNIHC4HC[0] CFG4 D In - 6.761 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un13_0_1_iv_1_RNIHC4HC[0] CFG4 Y Out 0.428 7.189 - ANB0_out Net - - 0.678 - 3 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_sx CFG4 C In - 7.867 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0_sx CFG4 Y Out 0.226 8.093 - CO1_0_1 Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0 CFG4 C In - 8.648 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.CO1_0 CFG4 Y Out 0.230 8.878 - BNC2 Net - - 0.556 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.SUM[3] CFG4 D In - 9.434 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_1.SUM[3] CFG4 Y Out 0.472 9.906 - un1_RADDR_5_40[3] Net - - 0.630 - 2 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_5_1.SUM[4] CFG4 D In - 10.536 - CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.un1_RADDR_5_1.SUM[4] CFG4 Y Out 0.472 11.009 - SUM[4] Net - - 0.159 - 1 CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.RADDR[4] SLE D In - 11.168 - ================================================================================================================================================================ Total path delay (propagation time + setup) of 11.423 is 4.388(38.4%) logic and 7.035(61.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- DATA_GENERATOR_0.PRBS_GENERATOR_0.PRBS[2] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE Q PRBS[2] 0.108 2.835 DATA_GENERATOR_0.PRBS_GENERATOR_0.PRBS[3] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE Q PRBS[3] 0.108 3.103 DATA_GENERATOR_0.waveform_gen_0.TRI_DATA16[13] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE Q TRI_DATA16[13] 0.108 3.251 DATA_GENERATOR_0.PRBS_GENERATOR_0.PRBS[4] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE Q PRBS[4] 0.108 3.344 DATA_GENERATOR_0.waveform_gen_0.TRI_DATA16[14] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE Q TRI_DATA16[14] 0.108 3.511 DATA_GENERATOR_0.waveform_gen_0.TRI_DATA16[15] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE Q TRI_DATA16[15] 0.108 3.557 DATA_GENERATOR_0.PRBS_GENERATOR_0.PRBS[0] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE Q PRBS[0] 0.108 3.597 DATA_GENERATOR_0.PRBS_GENERATOR_0.PRBS[1] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE Q PRBS[1] 0.108 3.608 DATA_GENERATOR_0.PRBS_GENERATOR_0.PRBS[7] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE Q PRBS[7] 0.108 3.717 DATA_GENERATOR_0.waveform_gen_0.TRI_ST SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE Q TRI_ST 0.108 3.737 ============================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ CoreJESD204BTX_0.LANE_0.CJESDTX_CJESDTX_TX_ACG.genblk1\.OldOValue[0] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE EN un1_alignment_sent42_0 9.662 2.835 CoreJESD204BTX_0.LANE_0.CJESDTX_CJESDTX_TX_ACG.genblk1\.OldOValue[1] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE EN un1_alignment_sent42_0 9.662 2.835 CoreJESD204BTX_0.LANE_0.CJESDTX_CJESDTX_TX_ACG.genblk1\.OldOValue[2] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE EN un1_alignment_sent42_0 9.662 2.835 CoreJESD204BTX_0.LANE_0.CJESDTX_CJESDTX_TX_ACG.genblk1\.OldOValue[3] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE EN un1_alignment_sent42_0 9.662 2.835 CoreJESD204BTX_0.LANE_0.CJESDTX_CJESDTX_TX_ACG.genblk1\.OldOValue[4] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE EN un1_alignment_sent42_0 9.662 2.835 CoreJESD204BTX_0.LANE_0.CJESDTX_CJESDTX_TX_ACG.genblk1\.OldOValue[5] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE EN un1_alignment_sent42_0 9.662 2.835 CoreJESD204BTX_0.LANE_0.CJESDTX_CJESDTX_TX_ACG.genblk1\.OldOValue[6] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE EN un1_alignment_sent42_0 9.662 2.835 CoreJESD204BTX_0.LANE_0.CJESDTX_CJESDTX_TX_ACG.genblk1\.OldOValue[7] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE EN un1_alignment_sent42_0 9.662 2.835 CoreJESD204BTX_0.LANE_0.mux2_data_out[7] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE D mux2_data_out_4[7] 9.745 2.846 CoreJESD204BTX_0.LANE_0.mux2_data_out[6] SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock SLE D mux2_data_out_4[6] 9.745 2.911 ============================================================================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.338 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.662 - Propagation time: 6.828 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 2.835 Number of logic level(s): 6 Starting point: DATA_GENERATOR_0.PRBS_GENERATOR_0.PRBS[2] / Q Ending point: CoreJESD204BTX_0.LANE_0.CJESDTX_CJESDTX_TX_ACG.genblk1\.OldOValue[0] / EN The start point is clocked by SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock [rising] on pin CLK The end point is clocked by SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------ DATA_GENERATOR_0.PRBS_GENERATOR_0.PRBS[2] SLE Q Out 0.108 0.108 - PRBS[2] Net - - 1.071 - 9 CoreJESD204BTX_0.LANE_0.CJESDTX_CJESDTX_TX_ACG.OCTET_IN_L_m_2_127_i_0_x2 CFG2 A In - 1.180 - CoreJESD204BTX_0.LANE_0.CJESDTX_CJESDTX_TX_ACG.OCTET_IN_L_m_2_127_i_0_x2 CFG2 Y Out 0.103 1.283 - N_99_i Net - - 0.630 - 2 DATA_GENERATOR_0.PRBS_WAV_SEL_0.DATA_OUT_0_o2[2] CFG4 D In - 1.913 - DATA_GENERATOR_0.PRBS_WAV_SEL_0.DATA_OUT_0_o2[2] CFG4 Y Out 0.470 2.382 - DATA_GENERATOR_0_DATA_OUT[2] Net - - 0.630 - 2 CoreJESD204BTX_0.LANE_0.CJESDTX_CJESDTX_TX_ACG.genblk1\.un1_OCTET_IN_L_NE_2 CFG4 D In - 3.012 - CoreJESD204BTX_0.LANE_0.CJESDTX_CJESDTX_TX_ACG.genblk1\.un1_OCTET_IN_L_NE_2 CFG4 Y Out 0.472 3.485 - un1_OCTET_IN_L_NE_2 Net - - 0.678 - 3 CoreJESD204BTX_0.LANE_0.CJESDTX_CJESDTX_TX_ACG.SEND_DATA_0_sqmuxa_1_i_o2_4 CFG4 B In - 4.163 - CoreJESD204BTX_0.LANE_0.CJESDTX_CJESDTX_TX_ACG.SEND_DATA_0_sqmuxa_1_i_o2_4 CFG4 Y Out 0.164 4.327 - SEND_DATA_0_sqmuxa_1_i_o2_4 Net - - 0.556 - 1 CoreJESD204BTX_0.LANE_0.CJESDTX_CJESDTX_TX_ACG.SEND_DATA_0_sqmuxa_1_i_o2 CFG4 C In - 4.883 - CoreJESD204BTX_0.LANE_0.CJESDTX_CJESDTX_TX_ACG.SEND_DATA_0_sqmuxa_1_i_o2 CFG4 Y Out 0.210 5.093 - N_473 Net - - 0.556 - 1 CoreJESD204BTX_0.LANE_0.CJESDTX_CJESDTX_TX_ACG.un1_alignment_sent42_0 CFG4 C In - 5.648 - CoreJESD204BTX_0.LANE_0.CJESDTX_CJESDTX_TX_ACG.un1_alignment_sent42_0 CFG4 Y Out 0.210 5.858 - un1_alignment_sent42_0 Net - - 0.970 - 8 CoreJESD204BTX_0.LANE_0.CJESDTX_CJESDTX_TX_ACG.genblk1\.OldOValue[0] SLE EN In - 6.828 - ========================================================================================================================================== Total path delay (propagation time + setup) of 7.165 is 2.074(29.0%) logic and 5.091(71.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.psel SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE Q psel 0.108 14.514 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.state[1] SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE Q state[1] 0.087 17.776 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.SDIF0_PENABLE SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE Q SF2_JESD204B_DEMO_sb_0_SDIF0_INIT_APB_PENABLE 0.108 17.795 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.state[0] SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE Q state[0] 0.087 18.556 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.paddr[15] SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE Q SF2_JESD204B_DEMO_sb_0_SDIF0_INIT_APB_PADDR[15] 0.087 18.601 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SERDESIF_075 APB_PRDATA[1] SF2_JESD204B_DEMO_sb_0_SDIF0_INIT_APB_PRDATA[1] 5.759 31.562 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SERDESIF_075 APB_PRDATA[0] SF2_JESD204B_DEMO_sb_0_SDIF0_INIT_APB_PRDATA[0] 5.804 31.780 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SERDESIF_075 APB_PRDATA[25] SF2_JESD204B_DEMO_sb_0_SDIF0_INIT_APB_PRDATA[25] 6.291 32.014 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SERDESIF_075 APB_PRDATA[8] SF2_JESD204B_DEMO_sb_0_SDIF0_INIT_APB_PRDATA[8] 6.182 32.123 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SERDESIF_075 APB_PRDATA[29] SF2_JESD204B_DEMO_sb_0_SDIF0_INIT_APB_PRDATA[29] 6.158 32.147 ========================================================================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SERDESIF_075 APB_PSEL N_402_i_0 16.671 14.514 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[1] SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE D prdata[1] 19.825 16.014 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[0] SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE D prdata[0] 19.745 16.311 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.soft_reset_reg[0] SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE EN soft_reset_reg6 19.663 16.341 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.soft_reset_reg[1] SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE EN soft_reset_reg6 19.663 16.341 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.soft_reset_reg[2] SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE EN soft_reset_reg6 19.663 16.341 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.soft_reset_reg[3] SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE EN soft_reset_reg6 19.663 16.341 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.soft_reset_reg[4] SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE EN soft_reset_reg6 19.663 16.341 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.soft_reset_reg[5] SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE EN soft_reset_reg6 19.663 16.341 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.soft_reset_reg[6] SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK SLE EN soft_reset_reg6 19.663 16.341 =========================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 3.329 + Clock delay at ending point: 0.000 (ideal) = Required time: 16.671 - Propagation time: 2.157 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 14.514 Number of logic level(s): 1 Starting point: SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.psel / Q Ending point: SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST / APB_PSEL The start point is clocked by SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK [falling] on pin CLK The end point is clocked by SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK [rising] on pin APB_CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------- SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.psel SLE Q Out 0.108 0.108 - psel Net - - 0.814 - 5 SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.R_SDIF0_PSEL_1_i_o3 CFG2 A In - 0.923 - SF2_JESD204B_DEMO_sb_0.CORECONFIGP_0.R_SDIF0_PSEL_1_i_o3 CFG2 Y Out 0.087 1.010 - N_402_i_0 Net - - 1.148 - 36 SERDES_EPCS_0.SERDES_IF2_0.SERDESIF_INST SERDESIF_075 APB_PSEL In - 2.157 - =================================================================================================================================== Total path delay (propagation time + setup) of 5.486 is 3.524(64.2%) logic and 1.962(35.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_ADDR[15] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PADDR[15] 3.594 0.908 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_ADDR[12] DATAHANDLE_FSM_0_DATA_RADDR[10] 3.583 0.950 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_SEL SF2_JESD204B_DEMO_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx 3.626 1.070 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_ADDR[13] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PADDR[13] 3.548 1.205 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_ADDR[14] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PADDR[14] 3.542 1.261 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 I2C1_SDA_MGPIO0A_H2F_B SF2_JESD204B_DEMO_sb_0_GPIO_0_M2F 3.774 1.486 TPSRAM_1.SF2_JESD204B_DEMO_TPSRAM_1_TPSRAM_R0C2 SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock RAM1K18 A_DOUT[2] TPSRAM_1_RD[18] 2.261 3.067 TPSRAM_0.SF2_JESD204B_DEMO_TPSRAM_0_TPSRAM_R0C0 SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock RAM1K18 A_DOUT[2] TPSRAM_0_RD[2] 2.261 3.094 DATAHANDLE_FSM_0.DATA_WADDR[0] SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q DATAHANDLE_FSM_0_DATA_WADDR[0] 0.108 3.143 DATAHANDLE_FSM_0.DATA_WADDR[1] SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q DATAHANDLE_FSM_0_DATA_WADDR[1] 0.108 3.143 ================================================================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[22] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PRDATA_m[22] 8.406 0.908 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[30] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PRDATA_m[30] 8.633 1.135 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[29] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PRDATA_m[29] 8.637 1.139 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[26] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PRDATA_m[26] 8.645 1.147 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[21] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PRDATA_m[21] 8.663 1.165 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[28] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PRDATA_m[28] 8.688 1.190 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[23] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PRDATA_m[23] 8.701 1.203 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[27] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PRDATA_m[27] 8.705 1.207 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[25] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PRDATA_m[25] 8.709 1.211 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[20] SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PRDATA_m[20] 8.710 1.212 ======================================================================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 1.594 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.406 - Propagation time: 7.498 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 0.908 Number of logic level(s): 2 Starting point: SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[15] Ending point: SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[22] The start point is clocked by SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE The end point is clocked by SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------- SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST MSS_075 F_HM0_ADDR[15] Out 3.594 3.594 - SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PADDR[15] Net - - 1.123 - 2 SF2_JESD204B_DEMO_sb_0.CoreAPB3_0.iPSELS_1[0] CFG2 B In - 4.717 - SF2_JESD204B_DEMO_sb_0.CoreAPB3_0.iPSELS_1[0] CFG2 Y Out 0.143 4.860 - iPSELS_1[0] Net - - 1.051 - 32 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST_RNO_21 CFG4 D In - 5.912 - SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST_RNO_21 CFG4 Y Out 0.470 6.381 - SF2_JESD204B_DEMO_sb_0_AMBA_SLAVE_0_PRDATA_m[22] Net - - 1.117 - 1 SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.MSS_ADLIB_INST MSS_075 F_HM0_RDATA[22] In - 7.498 - ==================================================================================================================================================== Total path delay (propagation time + setup) of 9.092 is 5.801(63.8%) logic and 3.291(36.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[3] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[3] 0.087 7.244 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[0] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[0] 0.108 7.333 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[1] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[1] 0.108 7.408 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[2] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[2] 0.108 7.425 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[4] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[4] 0.108 7.457 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[5] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[5] 0.108 7.473 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[6] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[6] 0.108 7.490 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[7] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[7] 0.108 7.506 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[8] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[8] 0.108 7.522 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[9] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[9] 0.108 7.537 ==================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SF2_JESD204B_DEMO_sb_0.CORERESETP_0.release_sdif0_core SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE EN release_sdif0_core4 9.662 7.244 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[12] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[12] 9.745 7.333 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[11] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[11] 9.745 7.350 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[10] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[10] 9.745 7.366 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[9] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[9] 9.745 7.382 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[8] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[8] 9.745 7.399 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[7] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[7] 9.745 7.415 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[6] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[6] 9.745 7.431 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[5] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[5] 9.745 7.447 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[4] SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[4] 9.745 7.464 ============================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.338 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.662 - Propagation time: 2.418 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 7.244 Number of logic level(s): 2 Starting point: SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[3] / Q Ending point: SF2_JESD204B_DEMO_sb_0.CORERESETP_0.release_sdif0_core / EN The start point is clocked by SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock [rising] on pin CLK The end point is clocked by SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------ SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[3] SLE Q Out 0.087 0.087 - count_sdif0[3] Net - - 0.674 - 2 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.release_sdif0_core4_8 CFG4 D In - 0.762 - SF2_JESD204B_DEMO_sb_0.CORERESETP_0.release_sdif0_core4_8 CFG4 Y Out 0.472 1.234 - release_sdif0_core4_8 Net - - 0.556 - 1 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.release_sdif0_core4 CFG4 D In - 1.790 - SF2_JESD204B_DEMO_sb_0.CORERESETP_0.release_sdif0_core4 CFG4 Y Out 0.470 2.260 - release_sdif0_core4 Net - - 0.159 - 1 SF2_JESD204B_DEMO_sb_0.CORERESETP_0.release_sdif0_core SLE EN In - 2.418 - ======================================================================================================================== Total path delay (propagation time + setup) of 2.756 is 1.367(49.6%) logic and 1.389(50.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Finished final timing analysis (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 218MB peak: 241MB) Finished timing report (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 218MB peak: 241MB) --------------------------------------- Resource Usage Report for SF2_JESD204B_DEMO Mapping to part: m2s090tfbga484std Cell usage: BUFD 80 uses CCC 1 use CLKINT 12 uses MSS_075 1 use RCOSC_25_50MHZ 1 use RCOSC_25_50MHZ_FAB 1 use SERDESIF_075 1 use SYSRESET 1 use CFG1 16 uses CFG2 425 uses CFG3 787 uses CFG4 1393 uses Carry primitives used for arithmetic functions: ARI1 74 uses Sequential Cells: SLE 2033 uses DSP Blocks: 0 I/O ports: 33 I/O primitives: 16 INBUF 6 uses OUTBUF 8 uses TRIBUFF 2 uses Global Clock Buffers: 12 RAM/ROM usage summary Block Rams (RAM1K18) : 7 Total LUTs: 2695 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 252; LUTs = 252; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 2033 + 0 + 252 + 0 = 2285; Total number of LUTs after P&R: 2695 + 0 + 252 + 0 = 2947; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 60MB peak: 241MB) Process took 0h:00m:15s realtime, 0h:00m:15s cputime # Tue Jul 21 11:40:33 2015 ###########################################################]