Synopsys Generic Technology Mapper, Version map201503actrcp1, Build 002R, Built Jul 1 2015 06:58:23 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-3 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 103MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_1 on net EPCS_3_TX_DATA_1 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_2 on net EPCS_3_TX_DATA_2 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_3 on net EPCS_3_TX_DATA_3 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_4 on net EPCS_3_TX_DATA_4 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_5 on net EPCS_3_TX_DATA_5 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_6 on net EPCS_3_TX_DATA_6 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_7 on net EPCS_3_TX_DATA_7 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_8 on net EPCS_3_TX_DATA_8 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_9 on net EPCS_3_TX_DATA_9 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_10 on net EPCS_3_TX_DATA_10 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_11 on net EPCS_3_TX_DATA_11 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_12 on net EPCS_3_TX_DATA_12 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_13 on net EPCS_3_TX_DATA_13 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_14 on net EPCS_3_TX_DATA_14 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_15 on net EPCS_3_TX_DATA_15 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_16 on net EPCS_3_TX_DATA_16 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_17 on net EPCS_3_TX_DATA_17 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_18 on net EPCS_3_TX_DATA_18 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_19 on net EPCS_3_TX_DATA_19 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(107) | Tristate driver EPCS_3_TX_DATA_20 on net EPCS_3_TX_DATA_20 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_1 on net EPCS_2_TX_DATA_1 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_2 on net EPCS_2_TX_DATA_2 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_3 on net EPCS_2_TX_DATA_3 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_4 on net EPCS_2_TX_DATA_4 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_5 on net EPCS_2_TX_DATA_5 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_6 on net EPCS_2_TX_DATA_6 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_7 on net EPCS_2_TX_DATA_7 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_8 on net EPCS_2_TX_DATA_8 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_9 on net EPCS_2_TX_DATA_9 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_10 on net EPCS_2_TX_DATA_10 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_11 on net EPCS_2_TX_DATA_11 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_12 on net EPCS_2_TX_DATA_12 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_13 on net EPCS_2_TX_DATA_13 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_14 on net EPCS_2_TX_DATA_14 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_15 on net EPCS_2_TX_DATA_15 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_16 on net EPCS_2_TX_DATA_16 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_17 on net EPCS_2_TX_DATA_17 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_18 on net EPCS_2_TX_DATA_18 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_19 on net EPCS_2_TX_DATA_19 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(106) | Tristate driver EPCS_2_TX_DATA_20 on net EPCS_2_TX_DATA_20 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_1 on net EPCS_1_TX_DATA_1 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_2 on net EPCS_1_TX_DATA_2 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_3 on net EPCS_1_TX_DATA_3 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_4 on net EPCS_1_TX_DATA_4 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_5 on net EPCS_1_TX_DATA_5 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_6 on net EPCS_1_TX_DATA_6 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_7 on net EPCS_1_TX_DATA_7 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_8 on net EPCS_1_TX_DATA_8 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_9 on net EPCS_1_TX_DATA_9 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_10 on net EPCS_1_TX_DATA_10 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_11 on net EPCS_1_TX_DATA_11 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_12 on net EPCS_1_TX_DATA_12 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_13 on net EPCS_1_TX_DATA_13 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_14 on net EPCS_1_TX_DATA_14 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_15 on net EPCS_1_TX_DATA_15 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_16 on net EPCS_1_TX_DATA_16 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_17 on net EPCS_1_TX_DATA_17 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_18 on net EPCS_1_TX_DATA_18 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_19 on net EPCS_1_TX_DATA_19 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : corejesd204btx.v(105) | Tristate driver EPCS_1_TX_DATA_20 on net EPCS_1_TX_DATA_20 has its enable tied to GND (module CoreJESD204BTX_Z11) @W:MO111 : sf2_jesd204b_demo_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module SF2_JESD204B_DEMO_sb_FABOSC_0_OSC) @W:MO111 : sf2_jesd204b_demo_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module SF2_JESD204B_DEMO_sb_FABOSC_0_OSC) @W:MO111 : sf2_jesd204b_demo_sb_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module SF2_JESD204B_DEMO_sb_FABOSC_0_OSC) @W:MO111 : sf2_jesd204b_demo_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module SF2_JESD204B_DEMO_sb_FABOSC_0_OSC) @W:MO171 : coreresetp.v(676) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF0_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(695) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF1_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF2_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF3_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(676) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF0_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(695) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF1_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF2_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF3_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(676) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF0_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(695) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF1_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF2_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF3_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(769) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(769) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(1388) | Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation @W:MO171 : rx_ctrl.v(132) | Sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_RX_CTRL.F_PHASE_reg_0[0] reduced to a combinational gate by constant propagation @W:MO171 : adj_ctrl.v(111) | Sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.F_PHASE_reg_0[0] reduced to a combinational gate by constant propagation @N:BN362 : tx_acg.v(206) | Removing sequential instance CJESDTX_TX_ACG.FCount_U[3:0] of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_JESD204BTX_LANE_Z10(verilog) because there are no references to its outputs @N:BN362 : clock_gen_tx.v(164) | Removing sequential instance CJESDTX_CLOCK_GEN_TX.LMFC_PHASE_1[4:1] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreJESD204BTX_Z11(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(90) | Removing instance UT1B5 of view:work.CJESDTX_MUX4X1_5(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(92) | Removing instance UT1B6 of view:work.CJESDTX_MUX4X1_2_0(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(94) | Removing instance UT1B7 of view:work.CJESDTX_MUX4X1_5(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(86) | Removing instance UT1B3 of view:work.CJESDTX_MUX4X1_1(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(88) | Removing instance UT1B4 of view:work.CJESDTX_MUX4X1_0_0_0(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(90) | Removing instance UT1B5 of view:work.CJESDTX_MUX4X1_0_0_0(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(82) | Removing instance UT1B1 of view:work.CJESDTX_MUX4X1_4_0(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(84) | Removing instance UT1B2 of view:work.CJESDTX_MUX4X1_4_0(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(88) | Removing instance UT1B4 of view:work.CJESDTX_MUX4X1_3(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(90) | Removing instance UT1B5 of view:work.CJESDTX_MUX4X1_3(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(92) | Removing instance UT1B6 of view:work.CJESDTX_MUX4X1_1(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(94) | Removing instance UT1B7 of view:work.CJESDTX_MUX4X1_3(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(101) | Removing instance UT2B1 of view:work.CJESDTX_MUX4X1_6_0(verilog) because there are no references to its outputs @N:BN115 : mux32x1.v(80) | Removing instance UT1B0 of view:work.CJESDTX_MUX4X1_1(verilog) because there are no references to its outputs @W:BN132 : mux32x1.v(94) | Removing user instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB5.UT1B7, because it is equivalent to instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB5.UT1B5 @W:BN132 : mux32x1.v(90) | Removing user instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB5.UT1B5, because it is equivalent to instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB5.UT1B4 @W:BN132 : mux32x1.v(84) | Removing user instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB5.UT1B2, because it is equivalent to instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB5.UT1B1 @W:BN132 : mux32x1.v(90) | Removing user instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB4.UT1B5, because it is equivalent to instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB4.UT1B3 @W:BN132 : mux32x1.v(88) | Removing user instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB4.UT1B4, because it is equivalent to instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB4.UT1B2 @W:BN132 : mux32x1.v(88) | Removing user instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB3.UT1B4, because it is equivalent to instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB3.UT1B2 @W:BN132 : mux32x1.v(94) | Removing user instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB2.UT1B7, because it is equivalent to instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB2.UT1B0 @W:BN132 : mux32x1.v(92) | Removing user instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB2.UT1B6, because it is equivalent to instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB2.UT1B2 @W:BN132 : mux32x1.v(92) | Removing user instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB0.UT1B6, because it is equivalent to instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB0.UT1B5 @W:BN132 : mux32x1.v(88) | Removing user instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB0.UT1B4, because it is equivalent to instance CoreJESD204BTX_0.LANE_0.ENCODER_16B20B_0.ENCODER_U_0.UD.URN.UB0.UT1B2 Available hyper_sources - for debug and ip models None Found @N:MT480 : sf2_jesd204b_demo_syn.fdc(18) | Assigning clock "SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_TMP_0_FIC_2_APB_M_PCLK" to command: create_clock {n:SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK} -period {40} @N:BN362 : sync_dec.v(107) | Removing sequential instance genblk1\.sync_state of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_SYNC_DEC_2s_0s_0s_6s(verilog) because there are no references to its outputs Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 149MB) @N:MF135 : data_sync_buf.v(87) | Found RAM 'CJESDRX_DATA_SYNC_BUF_0.data_buf[19:0]', 4 words by 20 bits Encoding state machine SYNC_GEN_ST[2:0] (view:work.CJESDRX_SYNC_ENC_0s_0s_2s_10s_0s_0_1_2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @W:MO129 : sync_enc.v(83) | Sequential instance CoreJESD204BRX_0.CJESDRX_SYNC_ENC.SYNC_GEN_ST[0] reduced to a combinational gate by constant propagation @W:MO129 : rx_ctrl.v(132) | Sequential instance CoreJESD204BRX_0.LANE_0.CJESDRX_RX_CTRL.MF_PHASE_reg_0[0] reduced to a combinational gate by constant propagation Encoding state machine CG_state[2:0] (view:work.CJESDRX_CGS_0s_0_1_2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine ILA_state[4:0] (view:work.CJESDRX_ILA_FSM_Z2(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 Encoding state machine RIstate[2:0] (view:work.CJESDRX_ILA_FSM_Z2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N: : ila_fsm.v(210) | Found counter in view:work.CJESDRX_ILA_FSM_Z2(verilog) inst R_cnt[6:0] @N:MF135 : eb_ram_rtl.v(65) | Found RAM 'CJESDRX_RAM_EB.EB_RAM[17:0]', 32 words by 18 bits @N: : eb_ctrl.v(149) | Found counter in view:work.CJESDRX_EB_CTRL_0s_2s_9s_18s_18s_0_1(verilog) inst WADDR[4:0] Encoding state machine CD_S_state[2:0] (view:work.CJESDRX_LINK_COMP_Z4(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine CD_M_state[7:0] (view:work.CJESDRX_LINK_COMP_Z4(verilog)) original code -> new code 000 -> 00000001 001 -> 00000010 010 -> 00000100 011 -> 00001000 100 -> 00010000 101 -> 00100000 110 -> 01000000 111 -> 10000000 Encoding state machine FSstate[2:0] (view:work.CJESDRX_IFS_POS_0s_2s_9s_0_1_2_0_1(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine CC_state[1:0] (view:work.CJESDRX_IFS_POS_0s_2s_9s_0_1_2_0_1(verilog)) original code -> new code 00 -> 0 01 -> 1 @N:MO225 : ifs_pos.v(210) | No possible illegal states for state machine CC_state[1:0],safe FSM implementation is disabled Encoding state machine SYNC_STATE[4:0] (view:work.CJESDRX_SYNC_FSM_0s_0_1_2_3_4_4(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 Encoding state machine WA_FSM_STATE[3:0] (view:work.CJESDRX_WORD_ALIGNER_Z5(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : word_aligner.v(734) | No possible illegal states for state machine WA_FSM_STATE[3:0],safe FSM implementation is disabled @N:MF135 : data_sync_buf_tx.v(141) | Found RAM 'DATA_SYNC_BUF_0.data[19:0]', 4 words by 20 bits @N:FX403 : data_sync_buf_tx.v(141) | Property "block_ram" or "no_rw_check" found for RAM DATA_SYNC_BUF_0.data[19:0] with specified coding style. Inferring block RAM. @W:FX107 : data_sync_buf_tx.v(141) | No read/write conflict check. Possible simulation mismatch! @N:MF707 : data_sync_buf_tx.v(141) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for DATA_SYNC_BUF_0.data[19:0] (view:work.CoreJESD204BTX_Z11(verilog)). Encoding state machine TX_STATE_1[2:0] (view:work.CJESDTX_CJESDTX_TX_ACG_0s_0_1_2_0s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:FX404 : wav_gen_16bit.v(171) | Found addmux in view:work.waveform_gen(verilog) inst SAW_DATA16_3[15:0] from un2_SAW_DATA16[15:0] @W:MO160 : wav_gen_16bit.v(135) | Register bit SQR_DATA16[10] is always 0, optimizing ... @W:MO161 : wav_gen_16bit.v(135) | Register bit SQR_DATA16[9] is always 1, optimizing ... @W:MO160 : wav_gen_16bit.v(135) | Register bit SQR_DATA16[4] is always 0, optimizing ... @W:MO160 : wav_gen_16bit.v(135) | Register bit SQR_DATA16[2] is always 0, optimizing ... @W:MO160 : wav_gen_16bit.v(135) | Register bit SQR_DATA16[1] is always 0, optimizing ... @W:MO160 : wav_gen_16bit.v(135) | Register bit SQR_DATA16[0] is always 0, optimizing ... Encoding state machine fsm[3:0] (view:work.DATAHANDLE_FSM(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : data_handle_fsm.v(190) | No possible illegal states for state machine fsm[3:0],safe FSM implementation is disabled @N: : data_handle_fsm.v(131) | Found counter in view:work.DATAHANDLE_FSM(verilog) inst DATA_WADDR1[10:0] Encoding state machine state[2:0] (view:work.CoreConfigP_Z13(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @W:MO160 : coreconfigp.v(255) | Register bit paddr[16] is always 0, optimizing ... Encoding state machine sm0_state[6:0] (view:work.CoreResetP_Z14(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sdif0_state[3:0] (view:work.CoreResetP_Z14(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : coreresetp.v(1170) | No possible illegal states for state machine sdif0_state[3:0],safe FSM implementation is disabled @N: : coreresetp.v(1485) | Found counter in view:work.CoreResetP_Z14(verilog) inst count_sdif0[12:0] @N:BN362 : fadm_or.v(106) | Removing sequential instance CJESDRX_FADM_OR.FPC[0] in hierarchy view:work.CJESDRX_JESD204BRX_LANE_Z6(verilog) because there are no references to its outputs @N:BN362 : fadm_or.v(106) | Removing sequential instance CJESDRX_FADM_OR.FPC[1] in hierarchy view:work.CJESDRX_JESD204BRX_LANE_Z6(verilog) because there are no references to its outputs @N:BN362 : adj_ctrl.v(111) | Removing sequential instance CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.MF_PHASE_reg_0[0] in hierarchy view:work.CJESDRX_JESD204BRX_LANE_Z6(verilog) because there are no references to its outputs @N:BN362 : adj_ctrl.v(111) | Removing sequential instance CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.MF_PHASE_reg_1[0] in hierarchy view:work.CJESDRX_JESD204BRX_LANE_Z6(verilog) because there are no references to its outputs @N:BN362 : adj_ctrl.v(111) | Removing sequential instance CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.MF_PHASE_reg_3[0] in hierarchy view:work.CJESDRX_JESD204BRX_LANE_Z6(verilog) because there are no references to its outputs @N:BN362 : adj_ctrl.v(111) | Removing sequential instance CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.MF_PHASE_reg_2[0] in hierarchy view:work.CJESDRX_JESD204BRX_LANE_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1170) | Removing sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF0_PHY_RESET_N_int in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 180MB peak: 181MB) @N:BN362 : tx_ila.v(473) | Removing sequential instance CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.MFOValue_L[0] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 170MB peak: 181MB) Constraint Checker successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 97MB peak: 181MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Tue Jul 21 11:40:08 2015 ###########################################################]