@W: CG133 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CLOCK_GEN_RX.v":236:10:236:15|Object sys_st is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CLOCK_GEN_RX.v":237:34:237:40|Object sys_cnt is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CLOCK_GEN_RX.v":238:10:238:29|Object sysref_in_pulse_last is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CLOCK_GEN_RX.v":165:0:165:5|Pruning unused register err_state[1:0]. Make sure that there are no unused intermediate registers.
@W: CL113 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CLOCK_GEN_RX.v":347:4:347:9|Feedback mux created for signal genblk3.F_PHASE_ST. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL113 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CLOCK_GEN_RX.v":347:4:347:9|Feedback mux created for signal genblk3.FC_CNT[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL113 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CLOCK_GEN_RX.v":299:4:299:9|Feedback mux created for signal genblk3.MF_PHASE_ST. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CLOCK_GEN_RX.v":299:4:299:9|Sharing sequential element genblk3.MF_PHASE_ST. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL113 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CLOCK_GEN_RX.v":299:4:299:9|Feedback mux created for signal genblk3.LMFC_CNT[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CLOCK_GEN_RX.v":299:4:299:9|Sharing sequential element genblk3.LMFC_CNT. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL250 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CLOCK_GEN_RX.v":347:4:347:9|All reachable assignments to genblk3.FC_CNT[3:0] assign 0, register removed by optimization
@W: CL250 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CLOCK_GEN_RX.v":347:4:347:9|All reachable assignments to genblk3.F_PHASE_ST assign 0, register removed by optimization
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\ADJ_CTRL.v":112:0:112:5|Pruning unused register f_phase_st_reg[3:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\ADJ_CTRL.v":112:0:112:5|Pruning unused register lmfc_cnt_reg[11:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\ADJ_CTRL.v":112:0:112:5|Pruning unused register fc_cnt_reg[11:0]. Make sure that there are no unused intermediate registers.
@W: CG1283 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\LABDM.v":232:35:232:51|Ignoring localparam RES1 on the instance and using locally defined value
@W: CG1283 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\LABDM.v":232:35:232:51|Ignoring localparam RES2 on the instance and using locally defined value
@W: CG291 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\LINK_COMP.v":400:53:400:60|Ignoring parameter EVEN_ODD in sensitivity list.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\LINK_COMP.v":518:4:518:9|Pruning unused register genblk6.ADJCNT[3:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\LINK_COMP.v":518:4:518:9|Pruning unused register genblk6.ADJDIR. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\LINK_COMP.v":518:4:518:9|Pruning unused register genblk6.PHADJ. Make sure that there are no unused intermediate registers.
@W: CL113 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4333:5:4333:10|Feedback mux created for signal genblk6.FCOUNT_L_6[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL113 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4333:5:4333:10|Feedback mux created for signal genblk6.FCOUNT_L_5[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4333:5:4333:10|Sharing sequential element genblk6.FCOUNT_L_5. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL113 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4333:5:4333:10|Feedback mux created for signal genblk6.FCOUNT_L_4[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4333:5:4333:10|Sharing sequential element genblk6.FCOUNT_L_4. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL113 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4333:5:4333:10|Feedback mux created for signal genblk6.FCOUNT_L_3[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4333:5:4333:10|Sharing sequential element genblk6.FCOUNT_L_3. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL113 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4333:5:4333:10|Feedback mux created for signal genblk6.FCOUNT_L_2[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4333:5:4333:10|Sharing sequential element genblk6.FCOUNT_L_2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL113 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4333:5:4333:10|Feedback mux created for signal genblk6.FCOUNT_L_1[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4333:5:4333:10|Sharing sequential element genblk6.FCOUNT_L_1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL250 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4333:5:4333:10|All reachable assignments to genblk6.FCOUNT_L_6[3:0] assign 0, register removed by optimization
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_L_1[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_L_1[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_L_2[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_L_2[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_L_3[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_L_3[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_L_4[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_L_4[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_L_5[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_L_5[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_L_6[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_L_6[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_U[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Pruning register bit 1 of genblk6.OCOUNT_U[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Pruning unused register genblk6.OCOUNT_L_1[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Pruning unused register genblk6.OCOUNT_L_2[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Pruning unused register genblk6.OCOUNT_L_3[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Pruning unused register genblk6.OCOUNT_L_4[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Pruning unused register genblk6.OCOUNT_L_5[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Pruning unused register genblk6.OCOUNT_L_6[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\FADM_OR.v":179:4:179:9|Pruning unused register genblk2.FS_reg[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\FADM_OR.v":179:4:179:9|Pruning unused register genblk2.MFS_reg[1:0]. Make sure that there are no unused intermediate registers.
@W: CL271 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":177:2:177:7|Pruning unused bits 39 to 30 of buf_data[39:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":379:19:379:24|Optimizing register bit genblk5.wa_sel_d[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":379:19:379:24|Optimizing register bit genblk5.wa_sel_d[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":379:19:379:24|Pruning register bits 2 to 1 of genblk5.wa_sel_d[2:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DEC_RD_L.v":97:3:97:8|Pruning unused register RD. Make sure that there are no unused intermediate registers.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\RESET_SYNC.v":49:16:49:35|Removing wire laneclk_rxvalid_sync, as there is no assignment to it.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\RESET_SYNC.v":223:4:223:9|Sharing sequential element genblk1.lane_active. Add a syn_preserve attribute to the element to prevent sharing.
@W: CG291 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":724:10:724:19|Ignoring parameter DECODER_EN in sensitivity list.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DATA_SYNC_BUF.v":356:6:356:11|Pruning unused register genblk6.dw_cnt[2:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DATA_SYNC_BUF.v":207:1:207:6|Pruning unused register d_cnt[1:0]. Make sure that there are no unused intermediate registers.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":344:20:344:32|Removing wire DATA_OUT_1_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":345:20:345:32|Removing wire DATA_OUT_2_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":346:20:346:32|Removing wire DATA_OUT_3_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":347:20:347:32|Removing wire DATA_OUT_4_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":348:20:348:32|Removing wire DATA_OUT_5_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":349:20:349:32|Removing wire DATA_OUT_6_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":350:20:350:32|Removing wire DATA_OUT_7_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":352:20:352:27|Removing wire SOF_1_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":353:20:353:27|Removing wire SOF_2_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":354:20:354:27|Removing wire SOF_3_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":355:20:355:27|Removing wire SOF_4_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":356:20:356:27|Removing wire SOF_5_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":357:20:357:27|Removing wire SOF_6_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":358:20:358:27|Removing wire SOF_7_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":360:20:360:28|Removing wire SOMF_1_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":361:20:361:28|Removing wire SOMF_2_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":362:20:362:28|Removing wire SOMF_3_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":363:20:363:28|Removing wire SOMF_4_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":364:20:364:28|Removing wire SOMF_5_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":365:20:365:28|Removing wire SOMF_6_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":366:20:366:28|Removing wire SOMF_7_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":368:12:368:24|Removing wire RX_STATE_1_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":369:12:369:24|Removing wire RX_STATE_2_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":370:12:370:24|Removing wire RX_STATE_3_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":371:12:371:24|Removing wire RX_STATE_4_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":372:12:372:24|Removing wire RX_STATE_5_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":373:12:373:24|Removing wire RX_STATE_6_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":374:12:374:24|Removing wire RX_STATE_7_dc, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":380:6:380:23|Removing wire epcs_syncd_rst_n_1, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":381:6:381:23|Removing wire epcs_syncd_rst_n_2, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":382:6:382:23|Removing wire epcs_syncd_rst_n_3, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":383:6:383:23|Removing wire epcs_syncd_rst_n_4, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":384:6:384:23|Removing wire epcs_syncd_rst_n_5, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":385:6:385:23|Removing wire epcs_syncd_rst_n_6, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":386:6:386:23|Removing wire epcs_syncd_rst_n_7, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":433:25:433:33|Removing wire data_in_1, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":434:25:434:33|Removing wire data_in_2, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":435:25:435:33|Removing wire data_in_3, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":436:25:436:33|Removing wire data_in_4, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":437:25:437:33|Removing wire data_in_5, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":438:25:438:33|Removing wire data_in_6, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":439:25:439:33|Removing wire data_in_7, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":440:20:440:29|Removing wire valid_in_0, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":441:20:441:29|Removing wire valid_in_1, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":442:20:442:29|Removing wire valid_in_2, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":443:20:443:29|Removing wire valid_in_3, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":444:20:444:29|Removing wire valid_in_4, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":445:20:445:29|Removing wire valid_in_5, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":446:20:446:29|Removing wire valid_in_6, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":447:20:447:29|Removing wire valid_in_7, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":448:20:448:25|Removing wire k_in_0, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":449:20:449:25|Removing wire k_in_1, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":450:20:450:25|Removing wire k_in_2, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":451:20:451:25|Removing wire k_in_3, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":452:20:452:25|Removing wire k_in_4, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":453:20:453:25|Removing wire k_in_5, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":454:20:454:25|Removing wire k_in_6, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":455:20:455:25|Removing wire k_in_7, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":457:6:457:12|Removing wire aresetn, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":458:6:458:12|Removing wire sresetn, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":464:12:464:19|Removing wire RX_VALID, as there is no assignment to it.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":524:79:524:86|Removing instance DC_RXD_7 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":523:79:523:86|Removing instance DC_RXD_6 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":522:79:522:86|Removing instance DC_RXD_5 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":521:79:521:86|Removing instance DC_RXD_4 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":520:79:520:86|Removing instance DC_RXD_3 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":519:79:519:86|Removing instance DC_RXD_2 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":518:79:518:86|Removing instance DC_RXD_1 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":517:79:517:86|Removing instance DC_RXD_0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":515:77:515:83|Removing instance DC_RK_7 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":514:77:514:83|Removing instance DC_RK_6 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":513:77:513:83|Removing instance DC_RK_5 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":512:77:512:83|Removing instance DC_RK_4 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":511:77:511:83|Removing instance DC_RK_3 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":510:77:510:83|Removing instance DC_RK_2 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":509:77:509:83|Removing instance DC_RK_1 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":508:77:508:83|Removing instance DC_RK_0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":506:77:506:84|Removing instance DC_RCV_7 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":505:77:505:84|Removing instance DC_RCV_6 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":504:77:504:84|Removing instance DC_RCV_5 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":503:77:503:84|Removing instance DC_RCV_4 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":502:77:502:84|Removing instance DC_RCV_3 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":501:77:501:84|Removing instance DC_RCV_2 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":500:77:500:84|Removing instance DC_RCV_1 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":499:77:499:84|Removing instance DC_RCV_0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":497:77:497:84|Removing instance DC_RDE_7 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":496:77:496:84|Removing instance DC_RDE_6 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":495:77:495:84|Removing instance DC_RDE_5 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":494:77:494:84|Removing instance DC_RDE_4 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":493:77:493:84|Removing instance DC_RDE_3 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":492:77:492:84|Removing instance DC_RDE_2 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":491:77:491:84|Removing instance DC_RDE_1 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":490:77:490:84|Removing instance DC_RDE_0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":488:77:488:84|Removing instance DC_ERD_7 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":487:77:487:84|Removing instance DC_ERD_6 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":486:77:486:84|Removing instance DC_ERD_5 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":485:77:485:84|Removing instance DC_ERD_4 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":484:77:484:84|Removing instance DC_ERD_3 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":483:77:483:84|Removing instance DC_ERD_2 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":482:77:482:84|Removing instance DC_ERD_1 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CG133 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\SYNC_DEC.v":61:35:61:46|Object sync_req_cnt is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CLOCK_GEN_TX.v":206:4:206:9|Pruning unused register genblk2.FC_PHASE_ST. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CLOCK_GEN_TX.v":206:4:206:9|Pruning unused register genblk2.fc_cnt[3:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CLOCK_GEN_TX.v":158:4:158:9|Pruning unused register genblk2.lmfc_cnt[3:0]. Make sure that there are no unused intermediate registers.
@W: CL113 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CLOCK_GEN_TX.v":158:4:158:9|Feedback mux created for signal genblk2.LMFC_PHASE_ST. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL250 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CLOCK_GEN_TX.v":158:4:158:9|All reachable assignments to genblk2.LMFC_PHASE_ST assign 0, register removed by optimization
@W: CL207 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\DATA_SYNC_BUF_TX.v":231:4:231:9|All reachable assignments to genblk4.st_fsm[0] assign 1, register removed by optimization.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ACG.v":2173:5:2173:10|Pruning unused register genblk6.FCount_L_6[3:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ACG.v":2173:5:2173:10|Pruning unused register genblk6.FCount_L_5[3:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ACG.v":2173:5:2173:10|Pruning unused register genblk6.FCount_L_4[3:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ACG.v":2173:5:2173:10|Pruning unused register genblk6.FCount_L_3[3:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ACG.v":2173:5:2173:10|Pruning unused register genblk6.FCount_L_2[3:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ACG.v":2173:5:2173:10|Pruning unused register genblk6.FCount_L_1[3:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ACG.v":2137:4:2137:9|Pruning unused register genblk6.OCount_L_1[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ACG.v":2137:4:2137:9|Pruning unused register genblk6.OCount_L_2[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ACG.v":2137:4:2137:9|Pruning unused register genblk6.OCount_L_3[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ACG.v":2137:4:2137:9|Pruning unused register genblk6.OCount_L_4[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ACG.v":2137:4:2137:9|Pruning unused register genblk6.OCount_L_5[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ACG.v":2137:4:2137:9|Pruning unused register genblk6.OCount_L_6[1:0]. Make sure that there are no unused intermediate registers.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ACG.v":2137:4:2137:9|Optimizing register bit genblk6.OCount_U[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ACG.v":2137:4:2137:9|Pruning register bit 1 of genblk6.OCount_U[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CG1283 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\JESD204BTX_LANE.v":500:19:500:32|Ignoring localparam DID on the instance and using locally defined value
@W: CG1283 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\JESD204BTX_LANE.v":500:19:500:32|Ignoring localparam BID on the instance and using locally defined value
@W: CG1283 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\JESD204BTX_LANE.v":500:19:500:32|Ignoring localparam RES1 on the instance and using locally defined value
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ILA.v":368:4:368:9|Pruning unused register genblk4.alignment_sent. Make sure that there are no unused intermediate registers.
@W: CG1283 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\ENCODER_64B80B.v":60:7:60:16|Type of parameter K_WIDTH on the instance BUF_DATA_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\MUX32X6.v":85:3:85:8|Sharing sequential element SEL_R4. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\MUX32X6.v":85:3:85:8|Sharing sequential element SEL_R3. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\MUX32X6.v":85:3:85:8|Sharing sequential element SEL_R2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\MUX32X6.v":85:3:85:8|Sharing sequential element SEL_R0. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\MUX32X6.v":85:3:85:8|Pruning unused register SEL_R5[1:0]. Make sure that there are no unused intermediate registers.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\ENCODER_U.v":58:8:58:13|Removing wire RST_N0, as there is no assignment to it.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\ENCODER_N.v":69:3:69:8|Pruning unused register INV_6B. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\ENCODER_N.v":69:3:69:8|Pruning unused register INV_4B. Make sure that there are no unused intermediate registers.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\RESET_SYNC.v":222:4:222:9|Sharing sequential element genblk1.lane_active. Add a syn_preserve attribute to the element to prevent sharing.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":199:5:199:22|Removing wire epcs_syncd_rst_n_1, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":200:5:200:22|Removing wire epcs_syncd_rst_n_2, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":201:5:201:22|Removing wire epcs_syncd_rst_n_3, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":202:5:202:22|Removing wire epcs_syncd_rst_n_4, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":203:5:203:22|Removing wire epcs_syncd_rst_n_5, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":204:5:204:22|Removing wire epcs_syncd_rst_n_6, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":205:5:205:22|Removing wire epcs_syncd_rst_n_7, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":243:19:243:30|Removing wire LANE_K_OUT_1, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":244:19:244:30|Removing wire LANE_K_OUT_2, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":245:19:245:30|Removing wire LANE_K_OUT_3, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":246:19:246:30|Removing wire LANE_K_OUT_4, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":247:19:247:30|Removing wire LANE_K_OUT_5, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":248:19:248:30|Removing wire LANE_K_OUT_6, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":249:19:249:30|Removing wire LANE_K_OUT_7, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":251:25:251:39|Removing wire LANE_DATA_OUT_1, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":252:25:252:39|Removing wire LANE_DATA_OUT_2, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":253:25:253:39|Removing wire LANE_DATA_OUT_3, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":254:25:254:39|Removing wire LANE_DATA_OUT_4, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":255:25:255:39|Removing wire LANE_DATA_OUT_5, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":256:25:256:39|Removing wire LANE_DATA_OUT_6, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":257:25:257:39|Removing wire LANE_DATA_OUT_7, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":259:21:259:34|Removing wire BUF_DATA_OUT_1, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":260:21:260:34|Removing wire BUF_DATA_OUT_2, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":261:21:261:34|Removing wire BUF_DATA_OUT_3, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":262:21:262:34|Removing wire BUF_DATA_OUT_4, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":263:21:263:34|Removing wire BUF_DATA_OUT_5, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":264:21:264:34|Removing wire BUF_DATA_OUT_6, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":265:21:265:34|Removing wire BUF_DATA_OUT_7, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":281:23:281:32|Removing wire TX_K_1_int, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":282:23:282:32|Removing wire TX_K_2_int, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":283:23:283:32|Removing wire TX_K_3_int, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":284:23:284:32|Removing wire TX_K_4_int, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":285:23:285:32|Removing wire TX_K_5_int, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":286:23:286:32|Removing wire TX_K_6_int, as there is no assignment to it.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":287:23:287:32|Removing wire TX_K_7_int, as there is no assignment to it.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":479:70:479:76|Removing instance DC_DI_7 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":478:70:478:76|Removing instance DC_DI_6 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":477:70:477:76|Removing instance DC_DI_5 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":476:70:476:76|Removing instance DC_DI_4 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":475:70:475:76|Removing instance DC_DI_3 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":474:70:474:76|Removing instance DC_DI_2 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":473:70:473:76|Removing instance DC_DI_1 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\PRBS_GENERATOR.v":56:3:56:8|Pruning unused register data[31:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\PRBS_GENERATOR.v":45:0:45:5|Pruning unused register PRBS_SEL_d[1:0]. Make sure that there are no unused intermediate registers.
@W: CL260 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\PRBS_GENERATOR.v":56:3:56:8|Pruning register bit 31 of PRBS[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CG296 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\DATA_HANDLE_FSM.v":152:9:152:13|Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list.
@W: CG290 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\DATA_HANDLE_FSM.v":154:9:154:16|Referenced variable RDATA_EN is not in sensitivity list.
@W: CG290 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\DATA_HANDLE_FSM.v":155:17:155:24|Referenced variable DATA_OUT is not in sensitivity list.
@W: CG290 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\DATA_HANDLE_FSM.v":157:17:157:25|Referenced variable DATA_OUT1 is not in sensitivity list.
@W: CG133 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\DATA_HANDLE_FSM.v":110:4:110:6|Object SEL is declared but not assigned. Either assign a value or remove the declaration.
@W: CL208 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\DATA_HANDLE_FSM.v":190:0:190:5|All reachable assignments to bit 4 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization.
@W: CL208 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\DATA_HANDLE_FSM.v":190:0:190:5|All reachable assignments to bit 5 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization.
@W: CL208 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\DATA_HANDLE_FSM.v":190:0:190:5|All reachable assignments to bit 6 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization.
@W: CL208 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\DATA_HANDLE_FSM.v":190:0:190:5|All reachable assignments to bit 7 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization.
@W: CL208 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\DATA_HANDLE_FSM.v":190:0:190:5|All reachable assignments to bit 8 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization.
@W: CL208 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\DATA_HANDLE_FSM.v":190:0:190:5|All reachable assignments to bit 9 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization.
@W: CL208 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\DATA_HANDLE_FSM.v":190:0:190:5|All reachable assignments to bit 10 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization.
@W: CL208 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\DATA_HANDLE_FSM.v":190:0:190:5|All reachable assignments to bit 17 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization.
@W: CL208 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\DATA_HANDLE_FSM.v":190:0:190:5|All reachable assignments to bit 18 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization.
@W: CL208 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\DATA_HANDLE_FSM.v":190:0:190:5|All reachable assignments to bit 19 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization.
@W: CL208 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\DATA_HANDLE_FSM.v":190:0:190:5|All reachable assignments to bit 20 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\DATA_HANDLE_FSM.v":199:0:199:5|Optimizing register bit PREADY to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\DATA_HANDLE_FSM.v":199:0:199:5|Pruning unused register PREADY. Make sure that there are no unused intermediate registers.
@W: CG133 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\LED_BLOCK_2.v":76:10:76:19|Object data_0_led is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\PRBS_CHECKER.v":57:3:57:8|Pruning unused register PRBS_DATA_p2[15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\PRBS_CHECKER.v":57:3:57:8|Pruning unused register PRBS_DATA_p3[15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\PRBS_CHECKER.v":57:3:57:8|Pruning unused register d[31:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\PRBS_CHECKER.v":57:3:57:8|Pruning unused register ec[7:0]. Make sure that there are no unused intermediate registers.
@W: CL265 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\PRBS_CHECKER.v":57:3:57:8|Removing unused bit 15 of PRBS_DATA_p1[15:0]. Either assign all bits or reduce the width of the signal.
@W: CL271 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\PRBS_CHECKER.v":57:3:57:8|Pruning unused bits 31 to 16 of prbs_15[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL271 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\PRBS_CHECKER.v":57:3:57:8|Pruning unused bits 31 to 16 of prbs_23[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL271 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\PRBS_CHECKER.v":57:3:57:8|Pruning unused bits 31 to 16 of prbs_31[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL271 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\PRBS_CHECKER.v":57:3:57:8|Pruning unused bits 31 to 16 of prbs_7[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\PRBS_CHECKER.v":57:3:57:8|Pruning register bits 15 to 10 of prbs_7[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CG133 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\delay_line.v":32:10:32:10|Object j is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":244:12:244:20|Removing wire IA_PRDATA, as there is no assignment to it.
@W: CL207 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v":461:4:461:9|All reachable assignments to SDIF1_PENABLE assign 0, register removed by optimization.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1517:4:1517:9|Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers.
@W: CL318 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\SF2_JESD204B_DEMO_sb\FABOSC_0\SF2_JESD204B_DEMO_sb_FABOSC_0_OSC.v":17:7:17:20|*Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\SF2_JESD204B_DEMO_sb\FABOSC_0\SF2_JESD204B_DEMO_sb_FABOSC_0_OSC.v":18:7:18:20|*Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\SF2_JESD204B_DEMO_sb\FABOSC_0\SF2_JESD204B_DEMO_sb_FABOSC_0_OSC.v":19:7:19:16|*Output XTLOSC_CCC has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\SF2_JESD204B_DEMO_sb\FABOSC_0\SF2_JESD204B_DEMO_sb_FABOSC_0_OSC.v":20:7:20:16|*Output XTLOSC_O2F has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL246 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\DATA_HANDLE_FSM.v":69:14:69:18|Input port bits 15 to 13 of PADDR[15:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\DATA_HANDLE_FSM.v":69:14:69:18|Input port bits 1 to 0 of PADDR[15:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":199:5:199:22|*Input epcs_syncd_rst_n_1 to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":259:21:259:34|*Input BUF_DATA_OUT_1[19:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":200:5:200:22|*Input epcs_syncd_rst_n_2 to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":260:21:260:34|*Input BUF_DATA_OUT_2[19:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":201:5:201:22|*Input epcs_syncd_rst_n_3 to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":261:21:261:34|*Input BUF_DATA_OUT_3[19:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":202:5:202:22|*Input epcs_syncd_rst_n_4 to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":262:21:262:34|*Input BUF_DATA_OUT_4[19:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":203:5:203:22|*Input epcs_syncd_rst_n_5 to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":263:21:263:34|*Input BUF_DATA_OUT_5[19:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":204:5:204:22|*Input epcs_syncd_rst_n_6 to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":264:21:264:34|*Input BUF_DATA_OUT_6[19:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":205:5:205:22|*Input epcs_syncd_rst_n_7 to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":265:21:265:34|*Input BUF_DATA_OUT_7[19:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":199:5:199:22|*Input epcs_syncd_rst_n_1 to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":281:23:281:32|*Input TX_K_1_int[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":200:5:200:22|*Input epcs_syncd_rst_n_2 to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":282:23:282:32|*Input TX_K_2_int[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":201:5:201:22|*Input epcs_syncd_rst_n_3 to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":283:23:283:32|*Input TX_K_3_int[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":202:5:202:22|*Input epcs_syncd_rst_n_4 to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":284:23:284:32|*Input TX_K_4_int[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":203:5:203:22|*Input epcs_syncd_rst_n_5 to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":285:23:285:32|*Input TX_K_5_int[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":204:5:204:22|*Input epcs_syncd_rst_n_6 to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":286:23:286:32|*Input TX_K_6_int[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":205:5:205:22|*Input epcs_syncd_rst_n_7 to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":287:23:287:32|*Input TX_K_7_int[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL260 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\ENC_K.v":163:3:163:8|Pruning register bit 1 of K_SEL[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\ENC_K.v":163:3:163:8|Pruning register bit 1 of KCODE_6B[5:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ILA.v":300:0:300:5|Optimizing register bit ILAValue_0[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ILA.v":300:0:300:5|Pruning register bit 0 of ILAValue_0[6:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL247 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ILA.v":100:20:100:36|Input port bit 0 of MULTI_FRAME_START[1:0] is unused
@W: CL247 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ILA.v":101:20:101:34|Input port bit 1 of MULTI_FRAME_END[1:0] is unused
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ACG.v":2137:4:2137:9|Optimizing register bit genblk6.OCount_U[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ACG.v":2137:4:2137:9|Pruning unused register genblk6.OCount_U[0]. Make sure that there are no unused intermediate registers.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CLOCK_GEN_TX.v":206:4:206:9|Optimizing register bit genblk2.FC_PHASE[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CLOCK_GEN_TX.v":158:4:158:9|Optimizing register bit genblk2.LMFC_PHASE[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CLOCK_GEN_TX.v":158:4:158:9|Pruning register bit 0 of genblk2.LMFC_PHASE[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CLOCK_GEN_TX.v":206:4:206:9|Pruning register bit 0 of genblk2.FC_PHASE[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CLOCK_GEN_TX.v":206:4:206:9|Pruning unused register genblk2.FC_PHASE[1]. Make sure that there are no unused intermediate registers.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":344:20:344:32|*Input DATA_OUT_1_dc[15:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":345:20:345:32|*Input DATA_OUT_2_dc[15:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":346:20:346:32|*Input DATA_OUT_3_dc[15:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":347:20:347:32|*Input DATA_OUT_4_dc[15:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":348:20:348:32|*Input DATA_OUT_5_dc[15:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":349:20:349:32|*Input DATA_OUT_6_dc[15:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":350:20:350:32|*Input DATA_OUT_7_dc[15:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":352:20:352:27|*Input SOF_1_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":353:20:353:27|*Input SOF_2_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":354:20:354:27|*Input SOF_3_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":355:20:355:27|*Input SOF_4_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":356:20:356:27|*Input SOF_5_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":357:20:357:27|*Input SOF_6_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":358:20:358:27|*Input SOF_7_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":360:20:360:28|*Input SOMF_1_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":361:20:361:28|*Input SOMF_2_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":362:20:362:28|*Input SOMF_3_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":363:20:363:28|*Input SOMF_4_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":364:20:364:28|*Input SOMF_5_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":365:20:365:28|*Input SOMF_6_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":366:20:366:28|*Input SOMF_7_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":368:12:368:24|*Input RX_STATE_1_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":369:12:369:24|*Input RX_STATE_2_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":370:12:370:24|*Input RX_STATE_3_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":371:12:371:24|*Input RX_STATE_4_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":372:12:372:24|*Input RX_STATE_5_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":373:12:373:24|*Input RX_STATE_6_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":374:12:374:24|*Input RX_STATE_7_dc[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":448:20:448:25|*Input k_in_0[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":440:20:440:29|*Input valid_in_0[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL260 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":188:2:188:7|Pruning register bit 2 of wa_sel_d_mon[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":458:4:458:9|Sharing sequential element D1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":458:4:458:9|Sharing sequential element D2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":458:4:458:9|Sharing sequential element D3. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":458:4:458:9|Sharing sequential element D4. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":458:4:458:9|Sharing sequential element D5. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":458:4:458:9|Sharing sequential element D6. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":458:4:458:9|Sharing sequential element D7. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":458:4:458:9|Sharing sequential element D8. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":458:4:458:9|Sharing sequential element D9. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL260 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":188:2:188:7|Pruning register bit 1 of wa_sel_d_mon[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4385:4:4385:9|Optimizing register bit genblk6.ILAValue[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":198:0:198:5|Optimizing register bit Kcounter[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":198:0:198:5|Optimizing register bit Kcounter[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":198:0:198:5|Optimizing register bit Kcounter[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":198:0:198:5|Pruning register bits 4 to 3 of Kcounter[4:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":198:0:198:5|Pruning register bit 0 of Kcounter[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4385:4:4385:9|Pruning register bit 0 of genblk6.ILAValue[6:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\LINK_COMP.v":370:4:370:9|Optimizing register bit genblk6.map_cnt[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\LINK_COMP.v":370:4:370:9|Pruning register bit 0 of genblk6.map_cnt[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CLOCK_GEN_RX.v":347:4:347:9|Optimizing register bit genblk3.F_PHASE[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CLOCK_GEN_RX.v":299:4:299:9|Optimizing register bit genblk3.MF_PHASE[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CLOCK_GEN_RX.v":299:4:299:9|Pruning register bit 0 of genblk3.MF_PHASE[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CLOCK_GEN_RX.v":347:4:347:9|Pruning register bit 0 of genblk3.F_PHASE[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL169 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CLOCK_GEN_RX.v":347:4:347:9|Pruning unused register genblk3.F_PHASE[1]. Make sure that there are no unused intermediate registers.

