@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\smartfusion2.v":362:7:362:12|Synthesizing module CLKINT in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DATA_CAPTURE.v":19:7:19:26|Synthesizing module CJESDRX_DATA_CAPTURE in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DATA_CAPTURE.v":19:7:19:26|Synthesizing module CJESDRX_DATA_CAPTURE in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DATA_CAPTURE.v":19:7:19:26|Synthesizing module CJESDRX_DATA_CAPTURE in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\SYNC_ENC.v":18:7:18:22|Synthesizing module CJESDRX_SYNC_ENC in library work.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\SYNC_ENC.v":131:46:131:53|Removing redundant assignment.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CLOCK_GEN_RX.v":18:7:18:26|Synthesizing module CJESDRX_CLOCK_GEN_RX in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CGS.v":18:7:18:17|Synthesizing module CJESDRX_CGS in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\ADJ_CTRL.v":19:7:19:22|Synthesizing module CJESDRX_ADJ_CTRL in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\RX_CTRL.v":19:7:19:21|Synthesizing module CJESDRX_RX_CTRL in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\ILA_FSM.v":18:7:18:21|Synthesizing module CJESDRX_ILA_FSM in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\EB_CTRL.v":19:7:19:21|Synthesizing module CJESDRX_EB_CTRL in library work.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\EB_CTRL.v":140:26:140:30|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\EB_CTRL.v":200:38:200:42|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\EB_CTRL.v":214:38:214:42|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\EB_CTRL.v":291:29:291:30|Removing redundant assignment.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\EB_RAM_RTL.v":18:7:18:20|Synthesizing module CJESDRX_RAM_EB in library work.
@N: CL134 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\EB_RAM_RTL.v":69:0:69:5|Found RAM EB_RAM, depth=54, width=18
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\ADJ_BUF.v":18:7:18:21|Synthesizing module CJESDRX_ADJ_BUF in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\LABDM.v":19:7:19:19|Synthesizing module CJESDRX_LABDM in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\LINK_COMP.v":18:7:18:23|Synthesizing module CJESDRX_LINK_COMP in library work.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\LINK_COMP.v":562:45:562:50|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\LINK_COMP.v":563:45:563:50|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\LINK_COMP.v":564:44:564:48|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\LINK_COMP.v":565:42:565:44|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\LINK_COMP.v":566:42:566:44|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\LINK_COMP.v":571:35:571:40|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\LINK_COMP.v":572:35:572:40|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\LINK_COMP.v":573:34:573:38|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\LINK_COMP.v":574:32:574:34|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\LINK_COMP.v":575:32:575:34|Removing redundant assignment.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\FL_AMC.v":18:7:18:20|Synthesizing module CJESDRX_FL_AMC in library work.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\FL_AMC.v":365:29:365:38|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\FL_AMC.v":782:31:782:41|Removing redundant assignment.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":18:7:18:21|Synthesizing module CJESDRX_IFS_POS in library work.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":4394:29:4394:36|Removing redundant assignment.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\FADM_OR.v":18:7:18:21|Synthesizing module CJESDRX_FADM_OR in library work.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\FADM_OR.v":854:29:854:37|Removing redundant assignment.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\JESD204BRX_LANE.v":19:7:19:29|Synthesizing module CJESDRX_JESD204BRX_LANE in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DEC_ERR.v":21:7:21:21|Synthesizing module CJESDRX_DEC_ERR in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DEC_DATA.v":21:7:21:22|Synthesizing module CJESDRX_DEC_DATA in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\SYNC_FSM.v":21:7:21:22|Synthesizing module CJESDRX_SYNC_FSM in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DEC_RD_U.v":22:7:22:22|Synthesizing module CJESDRX_DEC_RD_U in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DECODER_U.v":21:7:21:23|Synthesizing module CJESDRX_DECODER_U in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":18:7:18:26|Synthesizing module CJESDRX_WORD_ALIGNER in library work.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":199:30:199:41|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":527:32:527:37|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":553:32:553:37|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":578:32:578:37|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":603:32:603:37|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":628:32:628:37|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":653:32:653:37|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":678:32:678:37|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":703:32:703:37|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":728:32:728:37|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":753:32:753:37|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":788:48:788:54|Removing redundant assignment.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DEC_WA.v":18:7:18:20|Synthesizing module CJESDRX_DEC_WA in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DEC_RD_L.v":22:7:22:22|Synthesizing module CJESDRX_DEC_RD_L in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DECODER_L.v":21:7:21:23|Synthesizing module CJESDRX_DECODER_L in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\RESET_SYNC.v":24:7:24:24|Synthesizing module CJESDRX_RESET_SYNC in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":19:7:19:20|Synthesizing module CoreJESD204BRX in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DATA_SYNC_BUF.v":19:7:19:27|Synthesizing module CJESDRX_DATA_SYNC_BUF in library work.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DATA_SYNC_BUF.v":213:22:213:26|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DATA_SYNC_BUF.v":235:18:235:24|Removing redundant assignment.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\DATA_CAPTURE.v":19:7:19:26|Synthesizing module CJESDTX_DATA_CAPTURE in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\DATA_CAPTURE.v":19:7:19:26|Synthesizing module CJESDTX_DATA_CAPTURE in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\DATA_CAPTURE.v":19:7:19:26|Synthesizing module CJESDTX_DATA_CAPTURE in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\SYNC_DEC.v":19:7:19:22|Synthesizing module CJESDTX_SYNC_DEC in library work.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\SYNC_DEC.v":86:32:86:43|Removing redundant assignment.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CLOCK_GEN_TX.v":19:7:19:26|Synthesizing module CJESDTX_CLOCK_GEN_TX in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\DATA_SYNC_BUF_TX.v":19:7:19:25|Synthesizing module CJESDTX_SYNC_BUF_TX in library work.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\DATA_SYNC_BUF_TX.v":305:18:305:24|Removing redundant assignment.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ACG.v":19:7:19:20|Synthesizing module CJESDTX_TX_ACG in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ILA.v":19:7:19:20|Synthesizing module CJESDTX_TX_ILA in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_CTRL.v":19:7:19:21|Synthesizing module CJESDTX_TX_CTRL in library work.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_CTRL.v":166:27:166:33|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_CTRL.v":216:50:216:58|Removing redundant assignment.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_CTRL.v":217:55:217:68|Removing redundant assignment.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\JESD204BTX_LANE.v":19:7:19:29|Synthesizing module CJESDTX_JESD204BTX_LANE in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\BUF_DATA.v":1:7:1:22|Synthesizing module CJESDTX_BUF_DATA in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\ENC_FLIP.v":26:7:26:22|Synthesizing module CJESDTX_ENC_FLIP in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\ENC_K.v":53:7:53:19|Synthesizing module CJESDTX_ENC_K in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\MUX4X1.v":22:7:22:20|Synthesizing module CJESDTX_MUX4X1 in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\MUX32X1.v":22:7:22:21|Synthesizing module CJESDTX_MUX32X1 in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\MUX32X6.v":22:7:22:21|Synthesizing module CJESDTX_MUX32X6 in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\ENC_D.v":26:7:26:19|Synthesizing module CJESDTX_ENC_D in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\ENCODER_U.v":22:7:22:23|Synthesizing module CJESDTX_ENCODER_U in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\ENCODER_64B80B.v":19:7:19:28|Synthesizing module CJESDTX_ENCODER_64B80B in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\ENCODER_L.v":22:7:22:23|Synthesizing module CJESDTX_ENCODER_L in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\ENCODER_N.v":22:7:22:23|Synthesizing module CJESDTX_ENCODER_N in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\RESET_SYNC.v":24:7:24:24|Synthesizing module CJESDTX_RESET_SYNC in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":19:7:19:20|Synthesizing module CoreJESD204BTX in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\PRBS_GENERATOR.v":19:7:19:20|Synthesizing module PRBS_GENERATOR in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\PRBS_WAV_SEL.v":20:7:20:18|Synthesizing module PRBS_WAV_SEL in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\wav_gen_16bit.v":4:7:4:18|Synthesizing module waveform_gen in library work.
@N: CG179 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\wav_gen_16bit.v":156:26:156:35|Removing redundant assignment.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\DATA_GENERATOR\DATA_GENERATOR.v":9:7:9:20|Synthesizing module DATA_GENERATOR in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\DATA_HANDLE_FSM.v":22:7:22:20|Synthesizing module DATAHANDLE_FSM in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\ERR_GEN.v":19:7:19:13|Synthesizing module ERR_GEN in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\LED_BLOCK_2.v":19:7:19:19|Synthesizing module LED_DEBUG_BLK in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\PRBS_CHECKER.v":19:9:19:20|Synthesizing module PRBS_CHECKER in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\delay_line.v":19:7:19:16|Synthesizing module delay_line in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\delay_line.v":48:7:48:14|Synthesizing module bufd_bus in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\smartfusion2.v":234:7:234:10|Synthesizing module BUFD in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\epcs_rx_intf.v":18:7:18:18|Synthesizing module epcs_rx_intf in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\epcs_tx_intf.v":19:7:19:18|Synthesizing module epcs_tx_intf in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\smartfusion2.v":376:7:376:9|Synthesizing module VCC in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\smartfusion2.v":372:7:372:9|Synthesizing module GND in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\SERDES_EPCS\SERDES_IF2_0\SERDES_EPCS_SERDES_IF2_0_SERDES_IF2_syn.v":5:7:5:18|Synthesizing module SERDESIF_075 in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\SERDES_EPCS\SERDES_IF2_0\SERDES_EPCS_SERDES_IF2_0_SERDES_IF2.v":5:7:5:41|Synthesizing module SERDES_EPCS_SERDES_IF2_0_SERDES_IF2 in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\SERDES_EPCS\SERDES_EPCS.v":9:7:9:17|Synthesizing module SERDES_EPCS in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\smartfusion2.v":729:7:729:9|Synthesizing module CCC in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\SF2_JESD204B_DEMO_sb\CCC_0\SF2_JESD204B_DEMO_sb_CCC_0_FCCC.v":5:7:5:37|Synthesizing module SF2_JESD204B_DEMO_sb_CCC_0_FCCC in library work.
@N: CG775 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":31:7:31:14|Component CoreAPB3 not found in library "work" or "__hyper__lib__", but found in library COREAPB3_LIB
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_muxptob3.v":30:7:30:23|Synthesizing module COREAPB3_MUXPTOB3 in library COREAPB3_LIB.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":31:7:31:14|Synthesizing module CoreAPB3 in library COREAPB3_LIB.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v":22:7:22:17|Synthesizing module CoreConfigP in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":23:7:23:16|Synthesizing module CoreResetP in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\SgCore\OSC\2.0.101\osc_comps.v":51:7:51:24|Synthesizing module RCOSC_25_50MHZ_FAB in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\SgCore\OSC\2.0.101\osc_comps.v":11:7:11:20|Synthesizing module RCOSC_25_50MHZ in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\SF2_JESD204B_DEMO_sb\FABOSC_0\SF2_JESD204B_DEMO_sb_FABOSC_0_OSC.v":5:7:5:39|Synthesizing module SF2_JESD204B_DEMO_sb_FABOSC_0_OSC in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\smartfusion2.v":268:7:268:11|Synthesizing module INBUF in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\smartfusion2.v":280:7:280:13|Synthesizing module TRIBUFF in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\SF2_JESD204B_DEMO_sb_MSS\SF2_JESD204B_DEMO_sb_MSS_syn.v":5:7:5:13|Synthesizing module MSS_075 in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\SF2_JESD204B_DEMO_sb_MSS\SF2_JESD204B_DEMO_sb_MSS.v":9:7:9:30|Synthesizing module SF2_JESD204B_DEMO_sb_MSS in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\smartfusion2.v":720:7:720:14|Synthesizing module SYSRESET in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\SF2_JESD204B_DEMO_sb\SF2_JESD204B_DEMO_sb.v":9:7:9:26|Synthesizing module SF2_JESD204B_DEMO_sb in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\smartfusion2.v":382:7:382:13|Synthesizing module RAM1K18 in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\top\TPSRAM_0\top_TPSRAM_0_TPSRAM.v":5:7:5:25|Synthesizing module top_TPSRAM_0_TPSRAM in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\top\TPSRAM_1\top_TPSRAM_1_TPSRAM.v":5:7:5:25|Synthesizing module top_TPSRAM_1_TPSRAM in library work.
@N: CG364 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\top\top.v":9:7:9:9|Synthesizing module top in library work.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\work\SF2_JESD204B_DEMO_sb\FABOSC_0\SF2_JESD204B_DEMO_sb_FABOSC_0_OSC.v":14:7:14:9|Input XTL is unused.
@N: CL201 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Trying to extract state machine for register sdif3_state.
@N: CL201 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Trying to extract state machine for register sdif2_state.
@N: CL201 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Trying to extract state machine for register sdif1_state.
@N: CL201 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Trying to extract state machine for register sdif0_state.
@N: CL201 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Trying to extract state machine for register sm0_state.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":29:20:29:28|Input CLK_LTSSM is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":56:20:56:28|Input FPLL_LOCK is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":68:20:68:34|Input SDIF1_SPLL_LOCK is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":72:20:72:34|Input SDIF2_SPLL_LOCK is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":76:20:76:34|Input SDIF3_SPLL_LOCK is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":90:20:90:29|Input SDIF0_PSEL is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":91:20:91:31|Input SDIF0_PWRITE is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":92:20:92:31|Input SDIF0_PRDATA is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":93:20:93:29|Input SDIF1_PSEL is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":94:20:94:31|Input SDIF1_PWRITE is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":95:20:95:31|Input SDIF1_PRDATA is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":96:20:96:29|Input SDIF2_PSEL is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":97:20:97:31|Input SDIF2_PWRITE is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":98:20:98:31|Input SDIF2_PRDATA is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":99:20:99:29|Input SDIF3_PSEL is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":100:20:100:31|Input SDIF3_PWRITE is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":101:20:101:31|Input SDIF3_PRDATA is unused.
@N: CL201 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v":447:4:447:9|Trying to extract state machine for register state.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v":71:24:71:35|Input SDIF1_PREADY is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v":72:24:72:36|Input SDIF1_PSLVERR is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":72:36:72:40|Input IADDR is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":73:13:73:19|Input PRESETN is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":74:13:74:16|Input PCLK is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":105:18:105:25|Input PRDATAS1 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":106:18:106:25|Input PRDATAS2 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":107:18:107:25|Input PRDATAS3 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":108:18:108:25|Input PRDATAS4 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":109:18:109:25|Input PRDATAS5 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":110:18:110:25|Input PRDATAS6 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":111:18:111:25|Input PRDATAS7 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":112:18:112:25|Input PRDATAS8 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":113:18:113:25|Input PRDATAS9 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":114:18:114:26|Input PRDATAS10 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":115:18:115:26|Input PRDATAS11 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":116:18:116:26|Input PRDATAS12 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":117:18:117:26|Input PRDATAS13 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":118:18:118:26|Input PRDATAS14 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":119:18:119:26|Input PRDATAS15 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":122:13:122:20|Input PREADYS1 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":123:13:123:20|Input PREADYS2 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":124:13:124:20|Input PREADYS3 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":125:13:125:20|Input PREADYS4 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":126:13:126:20|Input PREADYS5 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":127:13:127:20|Input PREADYS6 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":128:13:128:20|Input PREADYS7 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":129:13:129:20|Input PREADYS8 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":130:13:130:20|Input PREADYS9 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":131:13:131:21|Input PREADYS10 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":132:13:132:21|Input PREADYS11 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":133:13:133:21|Input PREADYS12 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":134:13:134:21|Input PREADYS13 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":135:13:135:21|Input PREADYS14 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":136:13:136:21|Input PREADYS15 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":139:13:139:21|Input PSLVERRS1 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":140:13:140:21|Input PSLVERRS2 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":141:13:141:21|Input PSLVERRS3 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":142:13:142:21|Input PSLVERRS4 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":143:13:143:21|Input PSLVERRS5 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":144:13:144:21|Input PSLVERRS6 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":145:13:145:21|Input PSLVERRS7 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":146:13:146:21|Input PSLVERRS8 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":147:13:147:21|Input PSLVERRS9 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":148:13:148:22|Input PSLVERRS10 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":149:13:149:22|Input PSLVERRS11 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":150:13:150:22|Input PSLVERRS12 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":151:13:151:22|Input PSLVERRS13 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":152:13:152:22|Input PSLVERRS14 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":153:13:153:22|Input PSLVERRS15 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\LED_BLOCK_2.v":53:7:53:12|Input SOMF_L is unused.
@N: CL201 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\DATA_HANDLE_FSM.v":199:0:199:5|Trying to extract state machine for register fsm.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\DATA_HANDLE_FSM.v":68:12:68:18|Input PENABLE is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\hdl\DATA_HANDLE_FSM.v":70:14:70:19|Input PWDATA is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":129:20:129:28|Input DATA_IN_1 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":130:20:130:28|Input DATA_IN_2 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":131:20:131:28|Input DATA_IN_3 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":132:20:132:28|Input DATA_IN_4 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":133:20:133:28|Input DATA_IN_5 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":134:20:134:28|Input DATA_IN_6 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":135:20:135:28|Input DATA_IN_7 is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":149:6:149:21|Input EPCS_1_TX_STABLE is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":150:6:150:21|Input EPCS_2_TX_STABLE is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":151:6:151:21|Input EPCS_3_TX_STABLE is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":152:6:152:21|Input EPCS_4_TX_STABLE is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":153:6:153:21|Input EPCS_5_TX_STABLE is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":154:6:154:21|Input EPCS_6_TX_STABLE is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CoreJESD204BTX.v":155:6:155:21|Input EPCS_7_TX_STABLE is unused.
@N: CL189 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\ENC_K.v":163:3:163:8|Register bit KCODE_6B[1] is always 1.
@N: CL201 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_CTRL.v":104:0:104:5|Trying to extract state machine for register TX_STATE.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_CTRL.v":54:20:54:27|Input OCTET_FC is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_CTRL.v":55:20:55:27|Input OCTET_7C is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ILA.v":93:6:93:9|Input LMFC is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\TX_ILA.v":99:20:99:28|Input FRAME_END is unused.
@N: CL134 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\DATA_SYNC_BUF_TX.v":371:1:371:6|Found RAM data_buf, depth=4, width=20
@N: CL134 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\DATA_SYNC_BUF_TX.v":371:1:371:6|Found RAM k_buf, depth=4, width=2
@N: CL189 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CLOCK_GEN_TX.v":206:4:206:9|Register bit genblk2.FC_PHASE[1] is always 0.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CLOCK_GEN_TX.v":53:6:53:14|Input SYSREF_IN is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\CLOCK_GEN_TX.v":54:6:54:11|Input SYNC_N is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\SYNC_DEC.v":51:6:51:9|Input LMFC is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BTX\3.1.105\rtl\vlog\core\SYNC_DEC.v":53:6:53:15|Input FORCE_SYNC is unused.
@N: CL134 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DATA_SYNC_BUF.v":220:1:220:6|Found RAM data_buf, depth=4, width=20
@N: CL134 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DATA_SYNC_BUF.v":220:1:220:6|Found RAM k_buf, depth=4, width=2
@N: CL134 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\DATA_SYNC_BUF.v":220:1:220:6|Found RAM valid_buf, depth=4, width=2
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":188:24:188:37|Input EPCS_1_RX_DATA is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":189:24:189:37|Input EPCS_2_RX_DATA is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":190:24:190:37|Input EPCS_3_RX_DATA is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":191:24:191:37|Input EPCS_4_RX_DATA is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":192:24:192:37|Input EPCS_5_RX_DATA is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":193:24:193:37|Input EPCS_6_RX_DATA is unused.
@N: CL159 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CoreJESD204BRX.v":194:24:194:37|Input EPCS_7_RX_DATA is unused.
@N: CL189 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":188:2:188:7|Register bit wa_sel_d_mon[1] is always 0.
@N: CL201 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\WORD_ALIGNER.v":769:2:769:7|Trying to extract state machine for register WA_FSM_STATE.
@N: CL201 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\SYNC_FSM.v":50:3:50:8|Trying to extract state machine for register SYNC_STATE.
@N: CL201 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":295:1:295:6|Trying to extract state machine for register CC_state.
@N: CL201 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\IFS_POS.v":198:0:198:5|Trying to extract state machine for register FS_STATE.
@N: CL201 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\LINK_COMP.v":294:4:294:9|Trying to extract state machine for register CD_M_state.
@N: CL201 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\ILA_FSM.v":505:0:505:5|Trying to extract state machine for register RIstate.
@N: CL201 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\ILA_FSM.v":306:2:306:7|Trying to extract state machine for register ILA_state.
@N: CL135 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\RX_CTRL.v":149:0:149:5|Found sequential shift mf_phase_reg with address depth of 4 words and data bit width of 5.
@N: CL135 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\RX_CTRL.v":149:0:149:5|Found sequential shift f_phase_reg with address depth of 4 words and data bit width of 2.
@N: CL135 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\ADJ_CTRL.v":112:0:112:5|Found sequential shift mf_phase_reg with address depth of 3 words and data bit width of 5.
@N: CL135 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\ADJ_CTRL.v":112:0:112:5|Found sequential shift f_phase_reg with address depth of 3 words and data bit width of 2.
@N: CL201 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CGS.v":370:0:370:5|Trying to extract state machine for register CG_state.
@N: CL189 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\CLOCK_GEN_RX.v":347:4:347:9|Register bit genblk3.F_PHASE[1] is always 0.
@N: CL201 :"C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\component\Actel\DirectCore\CoreJESD204BRX\3.3.104\rtl\vlog\core\SYNC_ENC.v":95:4:95:9|Trying to extract state machine for register SYNC_GEN_ST.
@N|Running in 64-bit mode

