@W: BN132 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MO129 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":676:4:676:9|Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":676:4:676:9|Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":676:4:676:9|Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation.
@W: MT530 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\hdl\data_handle_fsm.v":134:0:134:5|Found inferred clock SF2_JESD204B_DEMO_sb_CCC_0_FCCC|GL0_net_inferred_clock which controls 101 sequential elements including DATAHANDLE_FSM_0.DATA_WADDR1[10:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1485:4:1485:9|Found inferred clock SF2_JESD204B_DEMO_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 30 sequential elements including SF2_JESD204B_DEMO_sb_0.CORERESETP_0.count_sdif0[12:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\3.0.114\rtl\vlog\core\sync_dec.v":73:0:73:5|Found inferred clock SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_TX_CLK_inferred_clock which controls 559 sequential elements including CoreJESD204BTX_0.CJESDTX_SYNC_DEC.sync_counter[2:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\sync_enc.v":81:4:81:9|Found inferred clock SERDES_EPCS_SERDES_IF2_0_SERDES_IF2|EPCS_2_RX_CLK_inferred_clock which controls 1085 sequential elements including CoreJESD204BRX_0.CJESDRX_SYNC_ENC.SYNC_GEN_ST[2:0]. This clock has no specified timing constraint which may adversely impact design performance. 
