@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: MO111 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\corejesd204brx.v":290:14:290:23|Tristate driver RX_STATE_7_1 (in view: work.CoreJESD204BRX_Z9(verilog)) on net RX_STATE_7_1 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND.
@N: MO111 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\corejesd204brx.v":290:14:290:23|Tristate driver RX_STATE_7_2 (in view: work.CoreJESD204BRX_Z9(verilog)) on net RX_STATE_7_2 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND.
@N: MO111 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\corejesd204brx.v":289:14:289:23|Tristate driver RX_STATE_6_1 (in view: work.CoreJESD204BRX_Z9(verilog)) on net RX_STATE_6_1 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND.
@N: MO111 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\corejesd204brx.v":289:14:289:23|Tristate driver RX_STATE_6_2 (in view: work.CoreJESD204BRX_Z9(verilog)) on net RX_STATE_6_2 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND.
@N: MO111 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\corejesd204brx.v":288:14:288:23|Tristate driver RX_STATE_5_1 (in view: work.CoreJESD204BRX_Z9(verilog)) on net RX_STATE_5_1 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND.
@N: MO111 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\corejesd204brx.v":288:14:288:23|Tristate driver RX_STATE_5_2 (in view: work.CoreJESD204BRX_Z9(verilog)) on net RX_STATE_5_2 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND.
@N: MO111 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\corejesd204brx.v":287:14:287:23|Tristate driver RX_STATE_4_1 (in view: work.CoreJESD204BRX_Z9(verilog)) on net RX_STATE_4_1 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND.
@N: MO111 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\corejesd204brx.v":287:14:287:23|Tristate driver RX_STATE_4_2 (in view: work.CoreJESD204BRX_Z9(verilog)) on net RX_STATE_4_2 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND.
@N: MO111 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\corejesd204brx.v":286:14:286:23|Tristate driver RX_STATE_3_1 (in view: work.CoreJESD204BRX_Z9(verilog)) on net RX_STATE_3_1 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND.
@N: MO111 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\corejesd204brx.v":286:14:286:23|Tristate driver RX_STATE_3_2 (in view: work.CoreJESD204BRX_Z9(verilog)) on net RX_STATE_3_2 (in view: work.CoreJESD204BRX_Z9(verilog)) has its enable tied to GND.
@N: BN362 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\rx_ctrl.v":149:0:149:5|Removing sequential instance mf_phase_st_reg[3:0] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\rx_ctrl.v":149:0:149:5|Removing sequential instance lmfc_cnt_reg[15:0] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\rx_ctrl.v":149:0:149:5|Removing sequential instance fc_cnt_reg[15:0] (in view: work.CJESDRX_RX_CTRL_0s_0s_2s_9s_18s_16s_2s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\3.0.114\rtl\vlog\core\sync_dec.v":100:4:100:9|Removing sequential instance genblk1\.sync_state (in view: work.CJESDTX_SYNC_DEC_2s_0s_16s_2s_0s_6s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: MF135 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\data_sync_buf.v":91:1:91:6|RAM genblk6\.CJESDRX_DATA_SYNC_BUF_0.data_buf[19:0] (in view: work.CoreJESD204BRX_Z9(verilog)) is 4 words by 20 bits.
@N: MO231 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\sync_enc.v":81:4:81:9|Found counter in view:work.CJESDRX_SYNC_ENC_2s_0s_0s_2s_9s_54s_0s_0_1_2(verilog) instance sync_cnt[5:0] 
@N: MF135 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\eb_ram_rtl.v":69:0:69:5|RAM CJESDRX_ADJ_BUF.CJESDRX_RAM_EB.EB_RAM[17:0] (in view: work.CJESDRX_LABDM_Z4(verilog)) is 64 words by 18 bits.
@N: MO231 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\ila_fsm.v":304:2:304:7|Found counter in view:work.CJESDRX_ILA_FSM_Z3(verilog) instance R_cnt[6:0] 
@N: MO231 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\eb_ctrl.v":125:1:125:6|Found counter in view:work.CJESDRX_EB_CTRL_0s_2s_9s_18s_54s_0_1_16s_2s(verilog) instance WADDR[5:0] 
@N: MF179 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\link_comp.v":488:26:489:49|Found 16 by 16 bit equality operator ('==') genblk6\.COMP_ERR33 (in view: work.CJESDRX_LINK_COMP_Z5(verilog))
@N: MO225 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\ifs_pos.v":295:1:295:6|There are no possible illegal states for state machine CC_state[1:0] (in view: work.CJESDRX_IFS_POS_Z6(verilog)); safe FSM implementation is not required.
@N: MO225 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\ifs_pos.v":198:0:198:5|There are no possible illegal states for state machine FS_STATE_1[3:0] (in view: work.CJESDRX_IFS_POS_Z6(verilog)); safe FSM implementation is not required.
@N: MO225 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\word_aligner.v":769:2:769:7|There are no possible illegal states for state machine WA_FSM_STATE[3:0] (in view: work.CJESDRX_WORD_ALIGNER_Z8(verilog)); safe FSM implementation is not required.
@N: MF135 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\3.0.114\rtl\vlog\core\data_sync_buf_tx.v":255:1:255:6|RAM DATA_SYNC_BUF_0.data[19:0] (in view: work.CoreJESD204BTX_Z12(verilog)) is 4 words by 20 bits.
@N: MF135 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\3.0.114\rtl\vlog\core\data_sync_buf_tx.v":255:1:255:6|RAM DATA_SYNC_BUF_0.data[19:0] (in view: work.CoreJESD204BTX_Z12(verilog)) is 4 words by 20 bits.
@N: BN362 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\3.0.114\rtl\vlog\core\tx_acg.v":2137:4:2137:9|Removing sequential instance CJESDTX_TX_ACG.genblk6\.OCount_L_0[1] (in view: work.CJESDTX_JESD204BTX_LANE_Z11(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: MO225 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\hdl\data_handle_fsm.v":199:0:199:5|There are no possible illegal states for state machine fsm[3:0] (in view: work.DATAHANDLE_FSM(verilog)); safe FSM implementation is not required.
@N: MO231 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\hdl\data_handle_fsm.v":134:0:134:5|Found counter in view:work.DATAHANDLE_FSM(verilog) instance DATA_WADDR1[10:0] 
@N: MO225 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1170:4:1170:9|There are no possible illegal states for state machine sdif0_state[3:0] (in view: work.CoreResetP_Z15(verilog)); safe FSM implementation is not required.
@N: MO231 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1485:4:1485:9|Found counter in view:work.CoreResetP_Z15(verilog) instance count_sdif0[12:0] 
@N: BN362 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\adj_ctrl.v":112:0:112:5|Removing sequential instance CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.mf_phase_st_reg[0] (in view: work.CJESDRX_JESD204BRX_LANE_Z7(verilog)) because it does not drive other instances.
@N: BN362 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\adj_ctrl.v":112:0:112:5|Removing sequential instance CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.mf_phase_st_reg[1] (in view: work.CJESDRX_JESD204BRX_LANE_Z7(verilog)) because it does not drive other instances.
@N: BN362 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\adj_ctrl.v":112:0:112:5|Removing sequential instance CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.mf_phase_st_reg[2] (in view: work.CJESDRX_JESD204BRX_LANE_Z7(verilog)) because it does not drive other instances.
@N: BN362 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\adj_ctrl.v":112:0:112:5|Removing sequential instance CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.mf_phase_st_reg[3] (in view: work.CJESDRX_JESD204BRX_LANE_Z7(verilog)) because it does not drive other instances.
@N: BN362 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Removing sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF0_PHY_RESET_N_int (in view: work.SF2_JESD204B_DEMO(verilog)) because it does not drive other instances.
@N: MO106 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\dec_data.v":78:6:78:9|Found ROM .delname. (in view: work.SF2_JESD204B_DEMO(verilog)) with 48 words by 5 bits.
@N: MO106 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\dec_data.v":78:6:78:9|Found ROM .delname. (in view: work.SF2_JESD204B_DEMO(verilog)) with 48 words by 5 bits.
@N: BN362 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\hdl\wav_gen_16bit.v":163:0:163:5|Removing sequential instance DATA_GENERATOR_0.waveform_gen_0.SAW_DATA16[0] (in view: work.SF2_JESD204B_DEMO(verilog)) because it does not drive other instances.
@N: BN362 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\hdl\wav_gen_16bit.v":163:0:163:5|Removing sequential instance DATA_GENERATOR_0.waveform_gen_0.SAW_DATA16[1] (in view: work.SF2_JESD204B_DEMO(verilog)) because it does not drive other instances.
@N: FX271 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\eb_ctrl.v":280:0:280:5|Replicating instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.SC[0] (in view: work.SF2_JESD204B_DEMO(verilog)) with 13 loads 1 time to improve timing.
@N: FX271 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\eb_ctrl.v":93:1:93:6|Replicating instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg[0] (in view: work.SF2_JESD204B_DEMO(verilog)) with 14 loads 1 time to improve timing.
@N: FX271 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\eb_ctrl.v":93:1:93:6|Replicating instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg[3] (in view: work.SF2_JESD204B_DEMO(verilog)) with 13 loads 1 time to improve timing.
@N: FX271 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\eb_ctrl.v":93:1:93:6|Replicating instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg[2] (in view: work.SF2_JESD204B_DEMO(verilog)) with 13 loads 2 times to improve timing.
@N: FX271 :"d:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\3.0.125\rtl\vlog\core\eb_ctrl.v":93:1:93:6|Replicating instance CoreJESD204BRX_0.LANE_0.CJESDRX_LABDM.CJESDRX_ADJ_BUF.CJESDRX_EB_CTRL.ADJ_NUM_reg[1] (in view: work.SF2_JESD204B_DEMO(verilog)) with 15 loads 2 times to improve timing.
@N: FP130 |Promoting Net SERDES_EPCS_0_EPCS_2_RX_CLK on CLKINT  I_964 
@N: FP130 |Promoting Net SERDES_EPCS_0_EPCS_2_TX_CLK_0 on CLKINT  I_965 
@N: FP130 |Promoting Net CoreJESD204BTX_0.syncd_rst_n_0[1] on CLKINT  I_966 
@N: FP130 |Promoting Net SERDES_EPCS_0_EPCS_2_RX_RESET_N on CLKINT  I_967 
@N: FP130 |Promoting Net SF2_JESD204B_DEMO_sb_0_INIT_APB_S_PRESET_N on CLKINT  I_968 
@N: FP130 |Promoting Net SF2_JESD204B_DEMO_sb_0_INIT_APB_S_PCLK on CLKINT  I_969 
@N: FP130 |Promoting Net SERDES_EPCS_0_EPCS_2_TX_RESET_N on CLKINT  I_970 
@N: FP130 |Promoting Net SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT  I_971 
@N: FP130 |Promoting Net SF2_JESD204B_DEMO_sb_0.CORERESETP_0.sm0_areset_n_rcosc on CLKINT  I_972 
@N: FX1056 |Writing EDF file: D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\synthesis\SF2_JESD204B_DEMO.edn
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT615 |Found clock SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK with period 40.00ns 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
