@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 
@N: BN362 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\2.3.102\rtl\vlog\core\tx_acg.v":206:1:206:6|Removing sequential instance CJESDTX_TX_ACG.FCount_U[3:0] of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_JESD204BTX_LANE_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\2.3.102\rtl\vlog\core\clock_gen_tx.v":164:4:164:9|Removing sequential instance CJESDTX_CLOCK_GEN_TX.LMFC_PHASE_1[4:1] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreJESD204BTX_Z11(verilog) because there are no references to its outputs 
@N: BN115 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\2.3.102\rtl\vlog\core\mux32x1.v":90:18:90:22|Removing instance UT1B5 of view:work.CJESDTX_MUX4X1_5(verilog) because there are no references to its outputs 
@N: BN115 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\2.3.102\rtl\vlog\core\mux32x1.v":92:18:92:22|Removing instance UT1B6 of view:work.CJESDTX_MUX4X1_2_0(verilog) because there are no references to its outputs 
@N: BN115 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\2.3.102\rtl\vlog\core\mux32x1.v":94:18:94:22|Removing instance UT1B7 of view:work.CJESDTX_MUX4X1_5(verilog) because there are no references to its outputs 
@N: BN115 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\2.3.102\rtl\vlog\core\mux32x1.v":86:18:86:22|Removing instance UT1B3 of view:work.CJESDTX_MUX4X1_1(verilog) because there are no references to its outputs 
@N: BN115 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\2.3.102\rtl\vlog\core\mux32x1.v":88:18:88:22|Removing instance UT1B4 of view:work.CJESDTX_MUX4X1_0_0_0(verilog) because there are no references to its outputs 
@N: BN115 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\2.3.102\rtl\vlog\core\mux32x1.v":90:18:90:22|Removing instance UT1B5 of view:work.CJESDTX_MUX4X1_0_0_0(verilog) because there are no references to its outputs 
@N: BN115 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\2.3.102\rtl\vlog\core\mux32x1.v":82:18:82:22|Removing instance UT1B1 of view:work.CJESDTX_MUX4X1_4_0(verilog) because there are no references to its outputs 
@N: BN115 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\2.3.102\rtl\vlog\core\mux32x1.v":84:18:84:22|Removing instance UT1B2 of view:work.CJESDTX_MUX4X1_4_0(verilog) because there are no references to its outputs 
@N: BN115 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\2.3.102\rtl\vlog\core\mux32x1.v":88:18:88:22|Removing instance UT1B4 of view:work.CJESDTX_MUX4X1_3(verilog) because there are no references to its outputs 
@N: BN115 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\2.3.102\rtl\vlog\core\mux32x1.v":90:18:90:22|Removing instance UT1B5 of view:work.CJESDTX_MUX4X1_3(verilog) because there are no references to its outputs 
@N: BN115 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\2.3.102\rtl\vlog\core\mux32x1.v":92:18:92:22|Removing instance UT1B6 of view:work.CJESDTX_MUX4X1_1(verilog) because there are no references to its outputs 
@N: BN115 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\2.3.102\rtl\vlog\core\mux32x1.v":94:18:94:22|Removing instance UT1B7 of view:work.CJESDTX_MUX4X1_3(verilog) because there are no references to its outputs 
@N: BN115 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\2.3.102\rtl\vlog\core\mux32x1.v":101:18:101:22|Removing instance UT2B1 of view:work.CJESDTX_MUX4X1_6_0(verilog) because there are no references to its outputs 
@N: BN115 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\2.3.102\rtl\vlog\core\mux32x1.v":80:18:80:22|Removing instance UT1B0 of view:work.CJESDTX_MUX4X1_1(verilog) because there are no references to its outputs 
@N: MT480 :"e:/libero_11p6_0_28_capture_test/sf2_jesd204b_demo/synthesis/sf2_jesd204b_demo_syn.fdc":18:0:18:0|Assigning clock "SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_TMP_0_FIC_2_APB_M_PCLK" to command: create_clock {n:SF2_JESD204B_DEMO_sb_0.SF2_JESD204B_DEMO_sb_MSS_0.FIC_2_APB_M_PCLK} -period {40} 
@N: BN362 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\2.3.102\rtl\vlog\core\sync_dec.v":107:4:107:9|Removing sequential instance genblk1\.sync_state of view:PrimLib.dffr(prim) in hierarchy view:work.CJESDTX_SYNC_DEC_2s_0s_0s_6s(verilog) because there are no references to its outputs 
@N: MF135 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\2.5.104\rtl\vlog\core\data_sync_buf.v":87:1:87:6|Found RAM 'CJESDRX_DATA_SYNC_BUF_0.data_buf[19:0]', 4 words by 20 bits 
@N: MF135 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\2.5.104\rtl\vlog\core\eb_ram_rtl.v":65:0:65:5|Found RAM 'CJESDRX_RAM_EB.EB_RAM[17:0]', 32 words by 18 bits 
@N: MO225 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\2.5.104\rtl\vlog\core\ifs_pos.v":210:1:210:6|No possible illegal states for state machine CC_state[1:0],safe FSM implementation is disabled
@N: MO225 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\2.5.104\rtl\vlog\core\word_aligner.v":734:2:734:7|No possible illegal states for state machine WA_FSM_STATE[3:0],safe FSM implementation is disabled
@N: MF135 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\2.3.102\rtl\vlog\core\data_sync_buf_tx.v":141:1:141:6|Found RAM 'DATA_SYNC_BUF_0.data[19:0]', 4 words by 20 bits 
@N: FX403 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\2.3.102\rtl\vlog\core\data_sync_buf_tx.v":141:1:141:6|Property "block_ram" or "no_rw_check" found for RAM DATA_SYNC_BUF_0.data[19:0] with specified coding style. Inferring block RAM.
@N: MF707 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\2.3.102\rtl\vlog\core\data_sync_buf_tx.v":141:1:141:6|Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for DATA_SYNC_BUF_0.data[19:0] (view:work.CoreJESD204BTX_Z11(verilog)).
@N: FX404 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\hdl\wav_gen_16bit.v":171:7:171:8|Found addmux in view:work.waveform_gen(verilog) inst SAW_DATA16_3[15:0] from un2_SAW_DATA16[15:0] 
@N: MO225 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\hdl\data_handle_fsm.v":190:0:190:5|No possible illegal states for state machine fsm[3:0],safe FSM implementation is disabled
@N: MO225 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|No possible illegal states for state machine sdif0_state[3:0],safe FSM implementation is disabled
@N: BN362 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\2.5.104\rtl\vlog\core\fadm_or.v":106:1:106:6|Removing sequential instance CJESDRX_FADM_OR.FPC[0] in hierarchy view:work.CJESDRX_JESD204BRX_LANE_Z6(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\2.5.104\rtl\vlog\core\fadm_or.v":106:1:106:6|Removing sequential instance CJESDRX_FADM_OR.FPC[1] in hierarchy view:work.CJESDRX_JESD204BRX_LANE_Z6(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\2.5.104\rtl\vlog\core\adj_ctrl.v":111:0:111:5|Removing sequential instance CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.MF_PHASE_reg_0[0] in hierarchy view:work.CJESDRX_JESD204BRX_LANE_Z6(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\2.5.104\rtl\vlog\core\adj_ctrl.v":111:0:111:5|Removing sequential instance CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.MF_PHASE_reg_1[0] in hierarchy view:work.CJESDRX_JESD204BRX_LANE_Z6(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\2.5.104\rtl\vlog\core\adj_ctrl.v":111:0:111:5|Removing sequential instance CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.MF_PHASE_reg_3[0] in hierarchy view:work.CJESDRX_JESD204BRX_LANE_Z6(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204brx\2.5.104\rtl\vlog\core\adj_ctrl.v":111:0:111:5|Removing sequential instance CJESDRX_RX_CTRL.CJESDRX_ADJ_CTRL.MF_PHASE_reg_2[0] in hierarchy view:work.CJESDRX_JESD204BRX_LANE_Z6(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Removing sequential instance SF2_JESD204B_DEMO_sb_0.CORERESETP_0.SDIF0_PHY_RESET_N_int in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p6_0_28_capture_test\sf2_jesd204b_demo\component\actel\directcore\corejesd204btx\2.3.102\rtl\vlog\core\tx_ila.v":473:0:473:5|Removing sequential instance CoreJESD204BTX_0.LANE_0.CJESDTX_TX_ILA.MFOValue_L[0] in hierarchy view:work.SF2_JESD204B_DEMO(verilog) because there are no references to its outputs 
