@W: CG133 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CLOCK_GEN_RX.v":240:10:240:15|Object sys_st is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CLOCK_GEN_RX.v":241:34:241:40|Object sys_cnt is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CLOCK_GEN_RX.v":242:10:242:29|Object sysref_in_pulse_last is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CLOCK_GEN_RX.v":169:0:169:5|Pruning unused register err_state[1:0]. Make sure that there are no unused intermediate registers.
@W: CL113 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CLOCK_GEN_RX.v":351:4:351:9|Feedback mux created for signal genblk3.F_PHASE_ST. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL113 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CLOCK_GEN_RX.v":351:4:351:9|Feedback mux created for signal genblk3.FC_CNT[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL113 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CLOCK_GEN_RX.v":303:4:303:9|Feedback mux created for signal genblk3.MF_PHASE_ST. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CLOCK_GEN_RX.v":303:4:303:9|Sharing sequential element genblk3.MF_PHASE_ST. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL113 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CLOCK_GEN_RX.v":303:4:303:9|Feedback mux created for signal genblk3.LMFC_CNT[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CLOCK_GEN_RX.v":303:4:303:9|Sharing sequential element genblk3.LMFC_CNT. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL250 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CLOCK_GEN_RX.v":351:4:351:9|All reachable assignments to genblk3.FC_CNT[3:0] assign 0, register removed by optimization
@W: CL250 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CLOCK_GEN_RX.v":351:4:351:9|All reachable assignments to genblk3.F_PHASE_ST assign 0, register removed by optimization
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\ADJ_CTRL.v":112:0:112:5|Pruning unused register f_phase_st_reg[3:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\ADJ_CTRL.v":112:0:112:5|Pruning unused register lmfc_cnt_reg[11:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\ADJ_CTRL.v":112:0:112:5|Pruning unused register fc_cnt_reg[11:0]. Make sure that there are no unused intermediate registers.
@W: CG1283 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\LABDM.v":229:35:229:51|Ignoring localparam RES1 on the instance and using locally defined value
@W: CG1283 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\LABDM.v":229:35:229:51|Ignoring localparam RES2 on the instance and using locally defined value
@W: CG296 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\LINK_COMP.v":400:13:400:49|Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list.
@W: CG290 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\LINK_COMP.v":424:17:424:27|Referenced variable lcp_octet_4 is not in sensitivity list.
@W: CG290 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\LINK_COMP.v":424:36:424:46|Referenced variable lcp_octet_5 is not in sensitivity list.
@W: CG290 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\LINK_COMP.v":440:17:440:27|Referenced variable lcp_octet_6 is not in sensitivity list.
@W: CG290 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\LINK_COMP.v":440:36:440:46|Referenced variable lcp_octet_7 is not in sensitivity list.
@W: CG290 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\LINK_COMP.v":456:17:456:27|Referenced variable lcp_octet_8 is not in sensitivity list.
@W: CG290 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\LINK_COMP.v":456:36:456:46|Referenced variable lcp_octet_9 is not in sensitivity list.
@W: CG290 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\LINK_COMP.v":472:17:472:28|Referenced variable lcp_octet_10 is not in sensitivity list.
@W: CG290 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\LINK_COMP.v":472:53:472:64|Referenced variable lcp_octet_11 is not in sensitivity list.
@W: CG290 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\LINK_COMP.v":489:17:489:28|Referenced variable lcp_octet_12 is not in sensitivity list.
@W: CG290 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\LINK_COMP.v":489:36:489:47|Referenced variable lcp_octet_13 is not in sensitivity list.
@W: CG290 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\LINK_COMP.v":408:17:408:27|Referenced variable lcp_octet_3 is not in sensitivity list.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\LINK_COMP.v":518:4:518:9|Pruning unused register genblk6.ADJCNT[3:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\LINK_COMP.v":518:4:518:9|Pruning unused register genblk6.ADJDIR. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\LINK_COMP.v":518:4:518:9|Pruning unused register genblk6.PHADJ. Make sure that there are no unused intermediate registers.
@W: CL113 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4333:5:4333:10|Feedback mux created for signal genblk6.FCOUNT_L_6[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL113 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4333:5:4333:10|Feedback mux created for signal genblk6.FCOUNT_L_5[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4333:5:4333:10|Sharing sequential element genblk6.FCOUNT_L_5. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL113 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4333:5:4333:10|Feedback mux created for signal genblk6.FCOUNT_L_4[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4333:5:4333:10|Sharing sequential element genblk6.FCOUNT_L_4. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL113 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4333:5:4333:10|Feedback mux created for signal genblk6.FCOUNT_L_3[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4333:5:4333:10|Sharing sequential element genblk6.FCOUNT_L_3. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL113 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4333:5:4333:10|Feedback mux created for signal genblk6.FCOUNT_L_2[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4333:5:4333:10|Sharing sequential element genblk6.FCOUNT_L_2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL113 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4333:5:4333:10|Feedback mux created for signal genblk6.FCOUNT_L_1[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4333:5:4333:10|Sharing sequential element genblk6.FCOUNT_L_1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL250 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4333:5:4333:10|All reachable assignments to genblk6.FCOUNT_L_6[3:0] assign 0, register removed by optimization
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_L_1[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_L_1[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_L_2[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_L_2[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_L_3[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_L_3[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_L_4[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_L_4[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_L_5[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_L_5[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_L_6[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_L_6[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Optimizing register bit genblk6.OCOUNT_U[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Pruning register bit 1 of genblk6.OCOUNT_U[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Pruning unused register genblk6.OCOUNT_L_1[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Pruning unused register genblk6.OCOUNT_L_2[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Pruning unused register genblk6.OCOUNT_L_3[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Pruning unused register genblk6.OCOUNT_L_4[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Pruning unused register genblk6.OCOUNT_L_5[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4293:4:4293:9|Pruning unused register genblk6.OCOUNT_L_6[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\FADM_OR.v":179:4:179:9|Pruning unused register genblk2.FS_reg[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\FADM_OR.v":179:4:179:9|Pruning unused register genblk2.MFS_reg[1:0]. Make sure that there are no unused intermediate registers.
@W: CL271 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\WORD_ALIGNER.v":177:2:177:7|Pruning unused bits 39 to 30 of buf_data[39:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\WORD_ALIGNER.v":379:19:379:24|Optimizing register bit genblk5.wa_sel_d[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\WORD_ALIGNER.v":379:19:379:24|Optimizing register bit genblk5.wa_sel_d[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\WORD_ALIGNER.v":379:19:379:24|Pruning register bits 2 to 1 of genblk5.wa_sel_d[2:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\DEC_RD_L.v":97:3:97:8|Pruning unused register RD. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\JESD204BRX_LANE.v":261:6:261:11|Pruning unused register genblk4.dw_k[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\JESD204BRX_LANE.v":261:6:261:11|Pruning unused register genblk4.dw_valid[1:0]. Make sure that there are no unused intermediate registers.
@W: CG133 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":301:11:301:23|Object syncd_rst_n_1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":302:11:302:23|Object syncd_rst_n_2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":303:11:303:23|Object syncd_rst_n_3 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":304:11:304:23|Object syncd_rst_n_4 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":305:11:305:23|Object syncd_rst_n_5 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":306:11:306:23|Object syncd_rst_n_6 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":307:11:307:23|Object syncd_rst_n_7 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":353:22:353:30|Removing wire data_in_1, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":354:22:354:30|Removing wire data_in_2, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":355:22:355:30|Removing wire data_in_3, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":356:22:356:30|Removing wire data_in_4, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":357:22:357:30|Removing wire data_in_5, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":358:22:358:30|Removing wire data_in_6, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":359:22:359:30|Removing wire data_in_7, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":360:23:360:32|Removing wire valid_in_0, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":361:23:361:32|Removing wire valid_in_1, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":362:23:362:32|Removing wire valid_in_2, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":363:23:363:32|Removing wire valid_in_3, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":364:23:364:32|Removing wire valid_in_4, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":365:23:365:32|Removing wire valid_in_5, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":366:23:366:32|Removing wire valid_in_6, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":367:23:367:32|Removing wire valid_in_7, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":368:23:368:28|Removing wire k_in_0, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":369:23:369:28|Removing wire k_in_1, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":370:23:370:28|Removing wire k_in_2, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":371:23:371:28|Removing wire k_in_3, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":372:23:372:28|Removing wire k_in_4, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":373:23:373:28|Removing wire k_in_5, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":374:23:374:28|Removing wire k_in_6, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":375:23:375:28|Removing wire k_in_7, as there is no assignment to it.
@W: CG133 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\SYNC_DEC.v":61:35:61:46|Object sync_req_cnt is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CLOCK_GEN_TX.v":206:4:206:9|Pruning unused register genblk2.FC_PHASE_ST. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CLOCK_GEN_TX.v":206:4:206:9|Pruning unused register genblk2.fc_cnt[3:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CLOCK_GEN_TX.v":158:4:158:9|Pruning unused register genblk2.lmfc_cnt[3:0]. Make sure that there are no unused intermediate registers.
@W: CL113 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CLOCK_GEN_TX.v":158:4:158:9|Feedback mux created for signal genblk2.LMFC_PHASE_ST. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL250 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CLOCK_GEN_TX.v":158:4:158:9|All reachable assignments to genblk2.LMFC_PHASE_ST assign 0, register removed by optimization
@W: CL113 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\DATA_SYNC_BUF_TX.v":207:4:207:9|Feedback mux created for signal genblk4.st_fsm[0:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL251 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\DATA_SYNC_BUF_TX.v":207:4:207:9|All reachable assignments to genblk4.st_fsm[0] assign 1, register removed by optimization
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\TX_ACG.v":2173:5:2173:10|Pruning unused register genblk6.FCount_L_6[3:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\TX_ACG.v":2173:5:2173:10|Pruning unused register genblk6.FCount_L_5[3:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\TX_ACG.v":2173:5:2173:10|Pruning unused register genblk6.FCount_L_4[3:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\TX_ACG.v":2173:5:2173:10|Pruning unused register genblk6.FCount_L_3[3:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\TX_ACG.v":2173:5:2173:10|Pruning unused register genblk6.FCount_L_2[3:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\TX_ACG.v":2173:5:2173:10|Pruning unused register genblk6.FCount_L_1[3:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\TX_ACG.v":2137:4:2137:9|Pruning unused register genblk6.OCount_L_1[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\TX_ACG.v":2137:4:2137:9|Pruning unused register genblk6.OCount_L_2[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\TX_ACG.v":2137:4:2137:9|Pruning unused register genblk6.OCount_L_3[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\TX_ACG.v":2137:4:2137:9|Pruning unused register genblk6.OCount_L_4[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\TX_ACG.v":2137:4:2137:9|Pruning unused register genblk6.OCount_L_5[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\TX_ACG.v":2137:4:2137:9|Pruning unused register genblk6.OCount_L_6[1:0]. Make sure that there are no unused intermediate registers.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\TX_ACG.v":2137:4:2137:9|Optimizing register bit genblk6.OCount_U[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\TX_ACG.v":2137:4:2137:9|Pruning register bit 1 of genblk6.OCount_U[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CG1283 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\JESD204BTX_LANE.v":500:19:500:32|Ignoring localparam DID on the instance and using locally defined value
@W: CG1283 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\JESD204BTX_LANE.v":500:19:500:32|Ignoring localparam BID on the instance and using locally defined value
@W: CG1283 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\JESD204BTX_LANE.v":500:19:500:32|Ignoring localparam RES1 on the instance and using locally defined value
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\TX_ILA.v":368:4:368:9|Pruning unused register genblk4.alignment_sent. Make sure that there are no unused intermediate registers.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\MUX32X6.v":85:3:85:8|Sharing sequential element SEL_R4. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\MUX32X6.v":85:3:85:8|Sharing sequential element SEL_R3. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\MUX32X6.v":85:3:85:8|Sharing sequential element SEL_R2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\MUX32X6.v":85:3:85:8|Sharing sequential element SEL_R0. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\MUX32X6.v":85:3:85:8|Pruning unused register SEL_R5[1:0]. Make sure that there are no unused intermediate registers.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\ENCODER_U.v":58:8:58:13|Removing wire RST_N0, as there is no assignment to it.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\ENCODER_N.v":69:3:69:8|Pruning unused register INV_6B. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\ENCODER_N.v":69:3:69:8|Pruning unused register INV_4B. Make sure that there are no unused intermediate registers.
@W: CG133 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":181:10:181:22|Object syncd_rst_n_1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":182:10:182:22|Object syncd_rst_n_2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":183:10:183:22|Object syncd_rst_n_3 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":184:10:184:22|Object syncd_rst_n_4 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":185:10:185:22|Object syncd_rst_n_5 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":186:10:186:22|Object syncd_rst_n_6 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":187:10:187:22|Object syncd_rst_n_7 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":225:19:225:30|Removing wire LANE_K_OUT_1, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":226:19:226:30|Removing wire LANE_K_OUT_2, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":227:19:227:30|Removing wire LANE_K_OUT_3, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":228:19:228:30|Removing wire LANE_K_OUT_4, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":229:19:229:30|Removing wire LANE_K_OUT_5, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":230:19:230:30|Removing wire LANE_K_OUT_6, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":231:19:231:30|Removing wire LANE_K_OUT_7, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":233:25:233:39|Removing wire LANE_DATA_OUT_1, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":234:25:234:39|Removing wire LANE_DATA_OUT_2, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":235:25:235:39|Removing wire LANE_DATA_OUT_3, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":236:25:236:39|Removing wire LANE_DATA_OUT_4, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":237:25:237:39|Removing wire LANE_DATA_OUT_5, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":238:25:238:39|Removing wire LANE_DATA_OUT_6, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":239:25:239:39|Removing wire LANE_DATA_OUT_7, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":241:21:241:34|Removing wire BUF_DATA_OUT_1, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":242:21:242:34|Removing wire BUF_DATA_OUT_2, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":243:21:243:34|Removing wire BUF_DATA_OUT_3, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":244:21:244:34|Removing wire BUF_DATA_OUT_4, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":245:21:245:34|Removing wire BUF_DATA_OUT_5, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":246:21:246:34|Removing wire BUF_DATA_OUT_6, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":247:21:247:34|Removing wire BUF_DATA_OUT_7, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":261:23:261:32|Removing wire TX_K_1_int, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":262:23:262:32|Removing wire TX_K_2_int, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":263:23:263:32|Removing wire TX_K_3_int, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":264:23:264:32|Removing wire TX_K_4_int, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":265:23:265:32|Removing wire TX_K_5_int, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":266:23:266:32|Removing wire TX_K_6_int, as there is no assignment to it.
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":267:23:267:32|Removing wire TX_K_7_int, as there is no assignment to it.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\PRBS_GENERATOR.v":56:3:56:8|Pruning unused register data[31:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\PRBS_GENERATOR.v":45:0:45:5|Pruning unused register PRBS_SEL_d[1:0]. Make sure that there are no unused intermediate registers.
@W: CL260 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\PRBS_GENERATOR.v":56:3:56:8|Pruning register bit 31 of PRBS[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CG296 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\DATA_HANDLE_FSM.v":152:9:152:13|Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list.
@W: CG290 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\DATA_HANDLE_FSM.v":154:9:154:16|Referenced variable RDATA_EN is not in sensitivity list.
@W: CG290 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\DATA_HANDLE_FSM.v":155:17:155:24|Referenced variable DATA_OUT is not in sensitivity list.
@W: CG290 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\DATA_HANDLE_FSM.v":157:17:157:25|Referenced variable DATA_OUT1 is not in sensitivity list.
@W: CG133 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\DATA_HANDLE_FSM.v":110:4:110:6|Object SEL is declared but not assigned. Either assign a value or remove the declaration.
@W: CL208 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\DATA_HANDLE_FSM.v":190:0:190:5|All reachable assignments to bit 4 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization.
@W: CL208 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\DATA_HANDLE_FSM.v":190:0:190:5|All reachable assignments to bit 5 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization.
@W: CL208 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\DATA_HANDLE_FSM.v":190:0:190:5|All reachable assignments to bit 6 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization.
@W: CL208 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\DATA_HANDLE_FSM.v":190:0:190:5|All reachable assignments to bit 7 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization.
@W: CL208 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\DATA_HANDLE_FSM.v":190:0:190:5|All reachable assignments to bit 8 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization.
@W: CL208 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\DATA_HANDLE_FSM.v":190:0:190:5|All reachable assignments to bit 9 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization.
@W: CL208 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\DATA_HANDLE_FSM.v":190:0:190:5|All reachable assignments to bit 10 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization.
@W: CL208 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\DATA_HANDLE_FSM.v":190:0:190:5|All reachable assignments to bit 17 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization.
@W: CL208 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\DATA_HANDLE_FSM.v":190:0:190:5|All reachable assignments to bit 18 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization.
@W: CL208 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\DATA_HANDLE_FSM.v":190:0:190:5|All reachable assignments to bit 19 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization.
@W: CL208 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\DATA_HANDLE_FSM.v":190:0:190:5|All reachable assignments to bit 20 of STATUS_OUT_REG[31:0] assign 0, register removed by optimization.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\DATA_HANDLE_FSM.v":199:0:199:5|Optimizing register bit PREADY to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\DATA_HANDLE_FSM.v":199:0:199:5|Pruning unused register PREADY. Make sure that there are no unused intermediate registers.
@W: CG133 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\LED_BLOCK_2.v":76:10:76:19|Object data_0_led is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\PRBS_CHECKER.v":57:3:57:8|Pruning unused register PRBS_DATA_p2[15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\PRBS_CHECKER.v":57:3:57:8|Pruning unused register PRBS_DATA_p3[15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\PRBS_CHECKER.v":57:3:57:8|Pruning unused register d[31:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\PRBS_CHECKER.v":57:3:57:8|Pruning unused register ec[7:0]. Make sure that there are no unused intermediate registers.
@W: CL265 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\PRBS_CHECKER.v":57:3:57:8|Removing unused bit 15 of PRBS_DATA_p1[15:0]. Either assign all bits or reduce the width of the signal.
@W: CL271 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\PRBS_CHECKER.v":57:3:57:8|Pruning unused bits 31 to 16 of prbs_15[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL271 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\PRBS_CHECKER.v":57:3:57:8|Pruning unused bits 31 to 16 of prbs_23[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL271 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\PRBS_CHECKER.v":57:3:57:8|Pruning unused bits 31 to 16 of prbs_31[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL271 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\PRBS_CHECKER.v":57:3:57:8|Pruning unused bits 31 to 16 of prbs_7[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\PRBS_CHECKER.v":57:3:57:8|Pruning register bits 15 to 10 of prbs_7[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CG133 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\delay_line.v":32:10:32:10|Object j is declared but not assigned. Either assign a value or remove the declaration.
@W: CG775 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":31:7:31:14|Found Component CoreAPB3 in library COREAPB3_LIB
@W: CG360 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":244:12:244:20|Removing wire IA_PRDATA, as there is no assignment to it.
@W: CL207 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v":461:4:461:9|All reachable assignments to SDIF1_PENABLE assign 0, register removed by optimization.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1517:4:1517:9|Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\work\SF2_JESD204B_DEMO_sb\FABOSC_0\SF2_JESD204B_DEMO_sb_FABOSC_0_OSC.v":17:7:17:20|*Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\work\SF2_JESD204B_DEMO_sb\FABOSC_0\SF2_JESD204B_DEMO_sb_FABOSC_0_OSC.v":18:7:18:20|*Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\work\SF2_JESD204B_DEMO_sb\FABOSC_0\SF2_JESD204B_DEMO_sb_FABOSC_0_OSC.v":19:7:19:16|*Output XTLOSC_CCC has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\work\SF2_JESD204B_DEMO_sb\FABOSC_0\SF2_JESD204B_DEMO_sb_FABOSC_0_OSC.v":20:7:20:16|*Output XTLOSC_O2F has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL246 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\DATA_HANDLE_FSM.v":69:14:69:18|Input port bits 15 to 13 of PADDR[15:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\hdl\DATA_HANDLE_FSM.v":69:14:69:18|Input port bits 1 to 0 of PADDR[15:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":147:24:147:37|*Output EPCS_1_TX_DATA has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":148:24:148:37|*Output EPCS_2_TX_DATA has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":149:24:149:37|*Output EPCS_3_TX_DATA has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":150:24:150:37|*Output EPCS_4_TX_DATA has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":151:24:151:37|*Output EPCS_5_TX_DATA has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":152:24:152:37|*Output EPCS_6_TX_DATA has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":153:24:153:37|*Output EPCS_7_TX_DATA has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":189:22:189:27|*Output TX_K_1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":190:22:190:27|*Output TX_K_2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":191:22:191:27|*Output TX_K_3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":192:22:192:27|*Output TX_K_4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":193:22:193:27|*Output TX_K_5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":194:22:194:27|*Output TX_K_6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CoreJESD204BTX.v":195:22:195:27|*Output TX_K_7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL260 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\ENC_K.v":163:3:163:8|Pruning register bit 1 of K_SEL[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\ENC_K.v":163:3:163:8|Pruning register bit 1 of KCODE_6B[5:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\TX_ILA.v":300:0:300:5|Optimizing register bit ILAValue_0[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\TX_ILA.v":300:0:300:5|Pruning register bit 0 of ILAValue_0[6:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL247 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\TX_ILA.v":100:20:100:36|Input port bit 0 of MULTI_FRAME_START[1:0] is unused
@W: CL247 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\TX_ILA.v":101:20:101:34|Input port bit 1 of MULTI_FRAME_END[1:0] is unused
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\TX_ACG.v":2137:4:2137:9|Optimizing register bit genblk6.OCount_U[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\TX_ACG.v":2137:4:2137:9|Pruning unused register genblk6.OCount_U[0]. Make sure that there are no unused intermediate registers.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CLOCK_GEN_TX.v":206:4:206:9|Optimizing register bit genblk2.FC_PHASE[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CLOCK_GEN_TX.v":158:4:158:9|Optimizing register bit genblk2.LMFC_PHASE[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CLOCK_GEN_TX.v":158:4:158:9|Pruning register bit 0 of genblk2.LMFC_PHASE[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CLOCK_GEN_TX.v":206:4:206:9|Pruning register bit 0 of genblk2.FC_PHASE[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BTX\3.0.114\rtl\vlog\core\CLOCK_GEN_TX.v":206:4:206:9|Pruning unused register genblk2.FC_PHASE[1]. Make sure that there are no unused intermediate registers.
@W: CL156 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":368:23:368:28|*Input k_in_0[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":360:23:360:32|*Input valid_in_0[1:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":252:22:252:31|*Output DATA_OUT_1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":253:22:253:31|*Output DATA_OUT_2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":254:22:254:31|*Output DATA_OUT_3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":255:22:255:31|*Output DATA_OUT_4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":256:22:256:31|*Output DATA_OUT_5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":257:22:257:31|*Output DATA_OUT_6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":258:22:258:31|*Output DATA_OUT_7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":260:22:260:26|*Output SOF_1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":261:22:261:26|*Output SOF_2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":262:22:262:26|*Output SOF_3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":263:22:263:26|*Output SOF_4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":264:22:264:26|*Output SOF_5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":265:22:265:26|*Output SOF_6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":266:22:266:26|*Output SOF_7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":268:22:268:27|*Output SOMF_1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":269:22:269:27|*Output SOMF_2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":270:22:270:27|*Output SOMF_3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":271:22:271:27|*Output SOMF_4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":272:22:272:27|*Output SOMF_5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":273:22:273:27|*Output SOMF_6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":274:22:274:27|*Output SOMF_7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":284:14:284:23|*Output RX_STATE_1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":285:14:285:23|*Output RX_STATE_2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":286:14:286:23|*Output RX_STATE_3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":287:14:287:23|*Output RX_STATE_4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":288:14:288:23|*Output RX_STATE_5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":289:14:289:23|*Output RX_STATE_6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CoreJESD204BRX.v":290:14:290:23|*Output RX_STATE_7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL260 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\WORD_ALIGNER.v":188:2:188:7|Pruning register bit 2 of wa_sel_d_mon[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\WORD_ALIGNER.v":458:4:458:9|Sharing sequential element D1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\WORD_ALIGNER.v":458:4:458:9|Sharing sequential element D2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\WORD_ALIGNER.v":458:4:458:9|Sharing sequential element D3. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\WORD_ALIGNER.v":458:4:458:9|Sharing sequential element D4. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\WORD_ALIGNER.v":458:4:458:9|Sharing sequential element D5. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\WORD_ALIGNER.v":458:4:458:9|Sharing sequential element D6. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\WORD_ALIGNER.v":458:4:458:9|Sharing sequential element D7. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\WORD_ALIGNER.v":458:4:458:9|Sharing sequential element D8. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\WORD_ALIGNER.v":458:4:458:9|Sharing sequential element D9. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL260 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\WORD_ALIGNER.v":188:2:188:7|Pruning register bit 1 of wa_sel_d_mon[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4385:4:4385:9|Optimizing register bit genblk6.ILAValue[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":198:0:198:5|Optimizing register bit Kcounter[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":198:0:198:5|Optimizing register bit Kcounter[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":198:0:198:5|Optimizing register bit Kcounter[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":198:0:198:5|Pruning register bits 4 to 3 of Kcounter[4:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":198:0:198:5|Pruning register bit 0 of Kcounter[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\IFS_POS.v":4385:4:4385:9|Pruning register bit 0 of genblk6.ILAValue[6:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\LINK_COMP.v":370:4:370:9|Optimizing register bit genblk6.map_cnt[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\LINK_COMP.v":370:4:370:9|Pruning register bit 0 of genblk6.map_cnt[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CLOCK_GEN_RX.v":351:4:351:9|Optimizing register bit genblk3.F_PHASE[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CLOCK_GEN_RX.v":303:4:303:9|Optimizing register bit genblk3.MF_PHASE[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CLOCK_GEN_RX.v":303:4:303:9|Pruning register bit 0 of genblk3.MF_PHASE[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CLOCK_GEN_RX.v":351:4:351:9|Pruning register bit 0 of genblk3.F_PHASE[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL169 :"D:\11.8\m2s_dg0611_liberov11p7_df\liberodesign\SF2_JESD204B_DEMO\component\Actel\DirectCore\CoreJESD204BRX\3.0.125\rtl\vlog\core\CLOCK_GEN_RX.v":351:4:351:9|Pruning unused register genblk3.F_PHASE[1]. Make sure that there are no unused intermediate registers.

