#--  Synopsys, Inc.
#--  Version Q-2020.03M-SP1
#--  Project file C:\JUNK\m2s_dg0611_liberov11p8_df\liberodesign\Libero_Project\synthesis\run_options.txt
#--  Written on Sun Mar 28 21:10:12 2021


#project files
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/DATA_CAPTURE.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/SYNC_ENC.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/CLOCK_GEN_RX.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/DATA_SYNC_BUF.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/DESCRAMBLER.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/WORD_SHIFT.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/DEC_ERR.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/DEC_DATA.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/DEC_RD_L.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/SYNC_FSM.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/DECODER_L.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/DEC_RD_U.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/DECODER_U.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/WORD_ALIGNER.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/DEC_WA.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/FL_AMC.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/IFS_POS.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/FADM_OR.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/EB_CTRL.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/EB_RAM_RTL.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/ADJ_BUF.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/ILA_FSM.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/LINK_COMP.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/LABDM.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/ADJ_CTRL.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/CGS.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/RX_CTRL.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/JESD204BRX_LANE.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/RESET_SYNC.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BRX/3.3.104/rtl/vlog/core/CoreJESD204BRX.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BTX/3.1.105/rtl/vlog/core/DATA_CAPTURE.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BTX/3.1.105/rtl/vlog/core/PHASE_CHECK.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BTX/3.1.105/rtl/vlog/core/CLOCK_GEN_TX.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BTX/3.1.105/rtl/vlog/core/MUX4X1.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BTX/3.1.105/rtl/vlog/core/MUX32X1.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BTX/3.1.105/rtl/vlog/core/MUX32X6.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BTX/3.1.105/rtl/vlog/core/ENC_D.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BTX/3.1.105/rtl/vlog/core/ENC_FLIP.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BTX/3.1.105/rtl/vlog/core/ENC_K.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BTX/3.1.105/rtl/vlog/core/ENCODER_L.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BTX/3.1.105/rtl/vlog/core/ENCODER_N.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BTX/3.1.105/rtl/vlog/core/ENCODER_U.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BTX/3.1.105/rtl/vlog/core/BUF_DATA.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BTX/3.1.105/rtl/vlog/core/ENCODER_64B80B.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BTX/3.1.105/rtl/vlog/core/SCRAMBLER.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BTX/3.1.105/rtl/vlog/core/TX_ACG.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BTX/3.1.105/rtl/vlog/core/TX_CTRL.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BTX/3.1.105/rtl/vlog/core/TX_ILA.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BTX/3.1.105/rtl/vlog/core/JESD204BTX_LANE.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BTX/3.1.105/rtl/vlog/core/RESET_SYNC.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BTX/3.1.105/rtl/vlog/core/DATA_SYNC_BUF_TX.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BTX/3.1.105/rtl/vlog/core/SYNC_DEC.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreJESD204BTX/3.1.105/rtl/vlog/core/CoreJESD204BTX.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/hdl/DATA_HANDLE_FSM.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/hdl/PRBS_GENERATOR.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/hdl/PRBS_WAV_SEL.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/hdl/wav_gen_16bit.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/work/DATA_GENERATOR/DATA_GENERATOR.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/hdl/ERR_GEN.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/hdl/LED_BLOCK_2.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/hdl/PRBS_CHECKER.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/work/SERDES_EPCS/SERDES_IF2_0/SERDES_EPCS_SERDES_IF2_0_SERDES_IF2_syn.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/work/SERDES_EPCS/SERDES_IF2_0/SERDES_EPCS_SERDES_IF2_0_SERDES_IF2.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/hdl/delay_line.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/hdl/epcs_rx_intf.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/hdl/epcs_tx_intf.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/work/SERDES_EPCS/SERDES_EPCS.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/work/SF2_JESD204B_DEMO_sb/CCC_0/SF2_JESD204B_DEMO_sb_CCC_0_FCCC.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/SgCore/OSC/2.0.101/osc_comps.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/work/SF2_JESD204B_DEMO_sb/FABOSC_0/SF2_JESD204B_DEMO_sb_FABOSC_0_OSC.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/work/SF2_JESD204B_DEMO_sb_MSS/SF2_JESD204B_DEMO_sb_MSS_syn.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/work/SF2_JESD204B_DEMO_sb_MSS/SF2_JESD204B_DEMO_sb_MSS.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreConfigP/7.1.100/rtl/vlog/core/coreconfigp.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreResetP/7.1.100/rtl/vlog/core/coreresetp_pcie_hotreset.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreResetP/7.1.100/rtl/vlog/core/coreresetp.v"
add_file -verilog -lib COREAPB3_LIB "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3_muxptob3.v"
add_file -verilog -lib COREAPB3_LIB "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3_iaddr_reg.v"
add_file -verilog -lib COREAPB3_LIB "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/work/SF2_JESD204B_DEMO_sb/SF2_JESD204B_DEMO_sb.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/work/top/TPSRAM_0/top_TPSRAM_0_TPSRAM.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/work/top/TPSRAM_1/top_TPSRAM_1_TPSRAM.v"
add_file -verilog "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/component/work/top/top.v"
add_file -fpga_constraint "C:/JUNK/m2s_dg0611_liberov11p8_df/liberodesign/Libero_Project/designer/top/synthesis.fdc"


#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#device options
set_option -technology SmartFusion2
set_option -part M2S090T
set_option -package FBGA484
set_option -speed_grade STD
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top"

# hdl_compiler_options
set_option -distributed_compile 0
set_option -hdl_strict_syntax 0

# mapper_without_write_options
set_option -frequency 100.000
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_vhdl 0

# actel_options
set_option -rw_check_on_ram 0

# Microchip G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 12
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -seqshift_to_uram 0
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 0
set_option -report_path 4000
set_option -update_models_cp 0
set_option -preserve_registers 0
set_option -disable_ramindex 0
set_option -rep_clkint_driver 1
set_option -microsemi_enhanced_flow 1
set_option -ternary_adder_decomp 66
set_option -pack_uram_addr_reg 1

# Microchip SmartFusion2
set_option -min_cdc_sync_flops 2
set_option -unsafe_cdc_netlist_property 0

# NFilter
set_option -no_sequential_opt 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./top.edn"
impl -active "synthesis"
