Timing Multi Corner Report Max Delay Analysis

SmartTime Version 12.900.20.24

Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)

Date: Sun Mar 28 21:18:25 2021

Design top
Family SmartFusion2
Die M2S090T
Package 484 FBGA
Temperature Range 0 - 85 C
Voltage Range 1.14 - 1.26 V
Speed Grade STD
Design State Post-Layout
Data source Production
Multi Corner Report Operating Conditions BEST, TYPICAL, WORST
Scenario for Timing Analysis timing_analysis

Summary

Clock Domain Required Period (ns) Required Frequency (MHz) Worst Slack (ns) Operating Conditions
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] 10.000 100.000 1.979 WORST
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] 10.000 100.000 0.765 WORST
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 10.000 100.000 2.693 WORST
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 20.000 50.000 15.574 WORST
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB 40.000 25.000 1.589 BEST

Worst Slack (ns) Operating Conditions
Input to Output

Clock Domain SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0]

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/RADDR[0]:CLK CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/RADDR[4]:D 7.708 1.979 13.384 15.363 0.298 8.021 WORST
Path 2 CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/RADDR[0]:CLK CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/RADDR[5]:D 7.691 1.992 13.367 15.359 0.298 8.008 WORST
Path 3 CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/RADDR[0]:CLK CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/RADDR[3]:D 7.530 2.153 13.206 15.359 0.298 7.847 WORST
Path 4 CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/RADDR[1]:CLK CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/RADDR[4]:D 7.452 2.236 13.127 15.363 0.298 7.764 WORST
Path 5 CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/RADDR[0]:CLK CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/RADDR[2]:D 7.447 2.236 13.123 15.359 0.298 7.764 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/RADDR[0]:CLK
To: CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/RADDR[4]:D
data required time 15.363
data arrival time - 13.384
slack 1.979
Data arrival time calculation
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] 0.000 0.000
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[0] Clock source + 0.000 0.000 r
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB:An net SERDES_EPCS_0/SERDES_IF2_0/EPCS_RXCLK[0] + 3.527 3.527 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB:YEn cell ADLIB:GBM + 0.441 3.968 30 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_RGB1_RGB3:An net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_YWn_GEast + 0.731 4.699 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_RGB1_RGB3:YR cell ADLIB:RGB + 0.372 5.071 142 r
CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/RADDR[0]:CLK net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_RGB1_RGB3_rgbr_net_1 + 0.605 5.676 r
CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/RADDR[0]:Q cell ADLIB:SLE + 0.127 5.803 261 f
CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/un8_RADDR_cry_0:B net CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/N_947_i + 0.951 6.754 f
CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/un8_RADDR_cry_0:UB cell ADLIB:ARI1_CC + 0.272 7.026 1 r
CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/un8_RADDR_cry_0_CC_0:UB[0] net NET_CC_CONFIG1089 + 0.000 7.026 r
CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/un8_RADDR_cry_0_CC_0:CC[6] cell ADLIB:CC_CONFIG + 0.854 7.880 1 f
CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/un8_RADDR_cry_5_FCINST1:CC net NET_CC_CONFIG1108 + 0.000 7.880 f
CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/un8_RADDR_cry_5_FCINST1:CO cell ADLIB:FCEND_BUFF_CC + 0.086 7.966 1 f
CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/RADDR21lto6:C net CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/RADDR21lto6 + 0.587 8.553 f
CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/RADDR21lto6:Y cell ADLIB:CFG4 + 0.427 8.980 2 f
CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/RADDR_0_sqmuxa_13:B net CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/RADDR21 + 0.879 9.859 f
CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/RADDR_0_sqmuxa_13:Y cell ADLIB:CFG2 + 0.193 10.052 11 f
CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/un1_RADDR_3_iv[0]:D net CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/RADDR_0_sqmuxa_13 + 0.792 10.844 f
CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/un1_RADDR_3_iv[0]:Y cell ADLIB:CFG4 + 0.173 11.017 2 r
CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/un1_RADDR_3_iv_RNISQ8C1[0]:B net CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/un1_RADDR_3_iv[0] + 0.905 11.922 r
CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/un1_RADDR_3_iv_RNISQ8C1[0]:UB cell ADLIB:ARI1_CC + 0.276 12.198 1 f
CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/un1_RADDR_3_iv_RNISQ8C1[0]_CC_0:UB[0] net NET_CC_CONFIG899 + 0.000 12.198 f
CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/un1_RADDR_3_iv_RNISQ8C1[0]_CC_0:CC[8] cell ADLIB:CC_CONFIG + 1.016 13.214 1 r
CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/un1_RADDR_3_iv_RNI43VP93[4]:CC net NET_CC_CONFIG924 + 0.000 13.214 r
CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/un1_RADDR_3_iv_RNI43VP93[4]:S cell ADLIB:ARI1_CC + 0.078 13.292 1 r
CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/RADDR[4]:D net CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/un1_RADDR_3_iv_RNI43VP93_S[4] + 0.092 13.384 r
data arrival time 13.384
Data required time calculation
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] Clock Constraint 10.000 10.000
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[0] Clock source + 0.000 10.000 r
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB:An net SERDES_EPCS_0/SERDES_IF2_0/EPCS_RXCLK[0] + 3.527 13.527 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB:YEn cell ADLIB:GBM + 0.441 13.968 30 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_RGB1_RGB3:An net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_YWn_GEast + 0.731 14.699 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_RGB1_RGB3:YR cell ADLIB:RGB + 0.372 15.071 142 r
CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/RADDR[4]:CLK net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_RGB1_RGB3_rgbr_net_1 + 0.590 15.661 r
CoreJESD204BRX_0/LANE_0/CJESDRX_LABDM/CJESDRX_ADJ_BUF/CJESDRX_EB_CTRL/RADDR[4]:D Library setup time ADLIB:SLE - 0.298 15.363
data required time 15.363
Operating Conditions WORST

SET External Setup

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) External Setup (ns) Operating Conditions
Path 1 SEL_IN[0] LED_DEBUG_BLK_0/LED_OUT[4]:D 7.080 7.080 0.204 1.765 WORST
Path 2 SEL_IN[0] LED_DEBUG_BLK_0/LED_OUT[1]:D 6.919 6.919 0.298 1.704 WORST
Path 3 SEL_IN[1] LED_DEBUG_BLK_0/LED_OUT[1]:D 6.677 6.677 0.298 1.462 WORST
Path 4 SEL_IN[2] LED_DEBUG_BLK_0/LED_OUT[4]:D 6.736 6.736 0.204 1.421 WORST
Path 5 SEL_IN[2] LED_DEBUG_BLK_0/LED_OUT[0]:D 6.573 6.573 0.298 1.347 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SEL_IN[0]
To: LED_DEBUG_BLK_0/LED_OUT[4]:D
data required time N/C
data arrival time - 7.080
slack N/C
Data arrival time calculation
SEL_IN[0] 0.000 0.000 f
SEL_IN_ibuf[0]/U0/U_IOPAD:PAD net SEL_IN[0] + 0.000 0.000 f
SEL_IN_ibuf[0]/U0/U_IOPAD:Y cell ADLIB:IOPAD_IN + 1.647 1.647 1 f
SEL_IN_ibuf[0]/U0/U_IOINFF:A net SEL_IN_ibuf[0]/U0/YIN1 + 0.244 1.891 f
SEL_IN_ibuf[0]/U0/U_IOINFF:Y cell ADLIB:IOINFF_BYPASS + 0.169 2.060 3 f
LED_DEBUG_BLK_0/LED_OUT_7_3_1:A net SEL_IN_c[0] + 2.806 4.866 f
LED_DEBUG_BLK_0/LED_OUT_7_3_1:Y cell ADLIB:CFG4 + 0.338 5.204 4 f
LED_DEBUG_BLK_0/LED_OUT_7_3[4]:A net LED_DEBUG_BLK_0/LED_OUT_7_3_1 + 0.587 5.791 f
LED_DEBUG_BLK_0/LED_OUT_7_3[4]:Y cell ADLIB:CFG4 + 0.366 6.157 1 f
LED_DEBUG_BLK_0/LED_OUT_7[4]:C net LED_DEBUG_BLK_0/N_38 + 0.734 6.891 f
LED_DEBUG_BLK_0/LED_OUT_7[4]:Y cell ADLIB:CFG3 + 0.102 6.993 1 f
LED_DEBUG_BLK_0/LED_OUT[4]:D net LED_DEBUG_BLK_0/LED_OUT_7[4] + 0.087 7.080 f
data arrival time 7.080
Data required time calculation
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] N/C N/C
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[0] Clock source + 0.000 N/C r
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB:An net SERDES_EPCS_0/SERDES_IF2_0/EPCS_RXCLK[0] + 3.421 N/C f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB:YEn cell ADLIB:GBM + 0.428 N/C 30 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_RGB1_RGB12:An net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_YWn_GEast + 0.718 N/C f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_RGB1_RGB12:YR cell ADLIB:RGB + 0.361 N/C 45 r
LED_DEBUG_BLK_0/LED_OUT[4]:CLK net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_RGB1_RGB12_rgbr_net_1 + 0.591 N/C r
LED_DEBUG_BLK_0/LED_OUT[4]:D Library setup time ADLIB:SLE - 0.204 N/C
Operating Conditions WORST

SET Clock to Output

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Clock to Out (ns) Operating Conditions
Path 1 LED_DEBUG_BLK_0/LED_OUT[7]:CLK LED_OUT[7] 9.640 15.324 15.324 WORST
Path 2 LED_DEBUG_BLK_0/LED_OUT[6]:CLK LED_OUT[6] 9.068 14.762 14.762 WORST
Path 3 LED_DEBUG_BLK_0/LED_OUT[5]:CLK LED_OUT[5] 9.071 14.749 14.749 WORST
Path 4 LED_DEBUG_BLK_0/LED_OUT[0]:CLK LED_OUT[0] 9.034 14.728 14.728 WORST
Path 5 LED_DEBUG_BLK_0/LED_OUT[3]:CLK LED_OUT[3] 9.010 14.698 14.698 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: LED_DEBUG_BLK_0/LED_OUT[7]:CLK
To: LED_OUT[7]
data required time N/C
data arrival time - 15.324
slack N/C
Data arrival time calculation
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] 0.000 0.000
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[0] Clock source + 0.000 0.000 r
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB:An net SERDES_EPCS_0/SERDES_IF2_0/EPCS_RXCLK[0] + 3.527 3.527 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB:YEn cell ADLIB:GBM + 0.441 3.968 30 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_RGB1_RGB13:An net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_YWn_GEast + 0.743 4.711 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_RGB1_RGB13:YR cell ADLIB:RGB + 0.372 5.083 53 r
LED_DEBUG_BLK_0/LED_OUT[7]:CLK net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_RGB1_RGB13_rgbr_net_1 + 0.601 5.684 r
LED_DEBUG_BLK_0/LED_OUT[7]:Q cell ADLIB:SLE + 0.127 5.811 1 f
LED_OUT_obuf[7]/U0/U_IOOUTFF:A net LED_OUT_c[7] + 5.863 11.674 f
LED_OUT_obuf[7]/U0/U_IOOUTFF:Y cell ADLIB:IOOUTFF_BYPASS + 0.388 12.062 1 f
LED_OUT_obuf[7]/U0/U_IOPAD:D net LED_OUT_obuf[7]/U0/DOUT + 0.084 12.146 f
LED_OUT_obuf[7]/U0/U_IOPAD:PAD cell ADLIB:IOPAD_TRI + 3.178 15.324 0 f
LED_OUT[7] net LED_OUT[7] + 0.000 15.324 f
data arrival time 15.324
Data required time calculation
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] N/C N/C
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[0] Clock source + 0.000 N/C r
LED_OUT[7] N/C f
Operating Conditions WORST

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[0] SERDES_EPCS_0/epcs_rx_intf_0/rxdin_l[4]:ALn 7.692 2.832 7.692 10.524 0.415 4.336 -5.939 WORST
Path 2 SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[0] SERDES_EPCS_0/epcs_rx_intf_0/rxdin_l[6]:ALn 7.692 2.833 7.692 10.525 0.415 4.334 -5.940 WORST
Path 3 SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[0] SERDES_EPCS_0/epcs_rx_intf_0/rxdin_l[17]:ALn 7.695 2.837 7.695 10.532 0.415 4.326 -5.947 WORST
Path 4 SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[0] SERDES_EPCS_0/epcs_rx_intf_0/rxdin_l[15]:ALn 7.679 2.837 7.679 10.516 0.415 4.326 -5.931 WORST
Path 5 SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[0] SERDES_EPCS_0/epcs_rx_intf_0/rxdin_l[14]:ALn 7.695 2.837 7.695 10.532 0.415 4.326 -5.947 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[0]
To: SERDES_EPCS_0/epcs_rx_intf_0/rxdin_l[4]:ALn
data required time 10.524
data arrival time - 7.692
slack 2.832
Data arrival time calculation
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] 0.000 0.000
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[0] Clock source + 0.000 0.000 r
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXRSTN[0] cell ADLIB:SERDESIF_075_IP + 1.748 1.748 187 r
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_2:An net SERDES_EPCS_0.SERDES_IF2_0.EPCS_2_RX_RESET_N + 3.780 5.528 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_2:YWn cell ADLIB:GBM + 0.440 5.968 3 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_2/U0_RGB1_RGB9:An net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_2/U0_YWn + 0.699 6.667 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_2/U0_RGB1_RGB9:YR cell ADLIB:RGB + 0.372 7.039 9 r
SERDES_EPCS_0/epcs_rx_intf_0/rxdin_l[4]:ALn net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_2/U0_RGB1_RGB9_rgbr_net_1 + 0.653 7.692 r
data arrival time 7.692
Data required time calculation
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] Clock Constraint 5.000 5.000
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[0] Clock source + 0.000 5.000 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB:An net SERDES_EPCS_0/SERDES_IF2_0/EPCS_RXCLK[0] + 3.918 8.918 r
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB:YWn cell ADLIB:GBM + 0.452 9.370 3 r
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_RGB1_RGB30:An net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_YWn + 0.649 10.019 r
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_RGB1_RGB30:YR cell ADLIB:RGB + 0.292 10.311 9 f
SERDES_EPCS_0/epcs_rx_intf_0/rxdin_l[4]:CLK net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_RGB1_RGB30_rgbr_net_1 + 0.628 10.939 r
SERDES_EPCS_0/epcs_rx_intf_0/rxdin_l[4]:ALn Library recovery time ADLIB:SLE - 0.415 10.524
data required time 10.524
Operating Conditions WORST

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] to SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0]

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Operating Conditions
Path 1 SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[0] LED_DEBUG_BLK_0/LED_OUT[6]:D 8.647 6.731 8.647 15.378 0.298 WORST
Path 2 SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[0] DATAHANDLE_FSM_0/STATUS_OUT_REG_1[17]:D 7.456 7.902 7.456 15.358 0.298 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[0]
To: LED_DEBUG_BLK_0/LED_OUT[6]:D
data required time 15.378
data arrival time - 8.647
slack 6.731
Data arrival time calculation
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] 0.000 0.000
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[0] Clock source + 0.000 0.000 r
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXIDLE[0] cell ADLIB:SERDESIF_075_IP + 0.733 0.733 2 r
LED_DEBUG_BLK_0/LED_OUT_7_3_1[6]:A net SERDES_EPCS_0_EPCS_2_RX_IDLE + 6.635 7.368 r
LED_DEBUG_BLK_0/LED_OUT_7_3_1[6]:Y cell ADLIB:CFG3 + 0.118 7.486 1 f
LED_DEBUG_BLK_0/LED_OUT_7_3[6]:C net LED_DEBUG_BLK_0/LED_OUT_7_3_1Z[6] + 0.605 8.091 f
LED_DEBUG_BLK_0/LED_OUT_7_3[6]:Y cell ADLIB:CFG4 + 0.117 8.208 1 r
LED_DEBUG_BLK_0/LED_OUT_7[6]:C net LED_DEBUG_BLK_0/N_40 + 0.263 8.471 r
LED_DEBUG_BLK_0/LED_OUT_7[6]:Y cell ADLIB:CFG3 + 0.088 8.559 1 r
LED_DEBUG_BLK_0/LED_OUT[6]:D net LED_DEBUG_BLK_0/LED_OUT_7[6] + 0.088 8.647 r
data arrival time 8.647
Data required time calculation
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] Clock Constraint 10.000 10.000
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[0] Clock source + 0.000 10.000 r
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB:An net SERDES_EPCS_0/SERDES_IF2_0/EPCS_RXCLK[0] + 3.527 13.527 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB:YEn cell ADLIB:GBM + 0.441 13.968 30 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_RGB1_RGB12:An net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_YWn_GEast + 0.740 14.708 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_RGB1_RGB12:YR cell ADLIB:RGB + 0.372 15.080 45 r
LED_DEBUG_BLK_0/LED_OUT[6]:CLK net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_RGB1_RGB12_rgbr_net_1 + 0.596 15.676 r
LED_DEBUG_BLK_0/LED_OUT[6]:D Library setup time ADLIB:SLE - 0.298 15.378
data required time 15.378
Operating Conditions WORST

SET SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 to SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0]

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Operating Conditions
Path 1 SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE PRBS_CHECKER_0/prbs_sel_d_reg[88]:D 3.076 4.920 10.443 15.363 0.298 WORST
Path 2 SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE PRBS_CHECKER_0/prbs_sel_d_reg[89]:D 3.108 4.924 10.475 15.399 0.298 WORST
Path 3 SF2_JESD204B_DEMO_sb_0/CORERESETP_0/INIT_DONE_int:CLK LED_DEBUG_BLK_0/LED_OUT[0]:D 2.258 6.119 9.259 15.378 0.298 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE
To: PRBS_CHECKER_0/prbs_sel_d_reg[88]:D
data required time 15.363
data arrival time - 10.443
slack 4.920
Data arrival time calculation
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 0.000 0.000
SF2_JESD204B_DEMO_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 4.539 4.539
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST:An net SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_net + 0.537 5.076 r
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.209 5.285 9 f
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_RGB1:An net SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.730 6.015 f
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_RGB1:YR cell ADLIB:RGB + 0.372 6.387 1 r
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B net SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_RGB1_YR + 0.479 6.866 r
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB cell ADLIB:IP_INTERFACE + 0.246 7.112 1 r
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE net SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net + 0.255 7.367 r
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CAN_TX_EBL_MGPIO4A_H2F_B cell ADLIB:MSS_075_IP + 1.309 8.676 52 r
PRBS_CHECKER_0/prbs_sel_d_reg[88]:D net SF2_JESD204B_DEMO_sb_0_GPIO_4_M2F + 1.767 10.443 r
data arrival time 10.443
Data required time calculation
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] Clock Constraint 10.000 10.000
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[0] Clock source + 0.000 10.000 r
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB:An net SERDES_EPCS_0/SERDES_IF2_0/EPCS_RXCLK[0] + 3.527 13.527 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB:YEn cell ADLIB:GBM + 0.441 13.968 30 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_RGB1_RGB0:An net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_YWn_GEast + 0.721 14.689 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_RGB1_RGB0:YR cell ADLIB:RGB + 0.372 15.061 32 r
PRBS_CHECKER_0/prbs_sel_d_reg[88]:CLK net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_RGB1_RGB0_rgbr_net_1 + 0.600 15.661 r
PRBS_CHECKER_0/prbs_sel_d_reg[88]:D Library setup time ADLIB:SLE - 0.298 15.363
data required time 15.363
Operating Conditions WORST

Clock Domain SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0]

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 SERDES_EPCS_0/epcs_tx_intf_0/txdout[0]:CLK SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[0] 1.375 0.765 7.248 8.013 1.987 9.235 WORST
Path 2 SERDES_EPCS_0/epcs_tx_intf_0/txdout[12]:CLK SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[12] 1.401 0.782 7.274 8.056 1.944 9.218 WORST
Path 3 SERDES_EPCS_0/epcs_tx_intf_0/txdout[11]:CLK SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[11] 1.332 0.786 7.208 7.994 2.006 9.214 WORST
Path 4 SERDES_EPCS_0/epcs_tx_intf_0/txdout[7]:CLK SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[7] 1.407 0.801 7.254 8.055 1.945 9.199 WORST
Path 5 SERDES_EPCS_0/epcs_tx_intf_0/txdout[10]:CLK SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[10] 1.329 0.812 7.205 8.017 1.983 9.188 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SERDES_EPCS_0/epcs_tx_intf_0/txdout[0]:CLK
To: SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[0]
data required time 8.013
data arrival time - 7.248
slack 0.765
Data arrival time calculation
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] 0.000 0.000
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[0] Clock source + 0.000 0.000 r
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0:An net SERDES_EPCS_0/SERDES_IF2_0/EPCS_TXCLK[0] + 3.745 3.745 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0:YWn cell ADLIB:GBM + 0.440 4.185 4 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0/U0_RGB1_RGB16:An net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0/U0_YWn + 0.689 4.874 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0/U0_RGB1_RGB16:YL cell ADLIB:RGB + 0.372 5.246 17 r
SERDES_EPCS_0/epcs_tx_intf_0/txdout[0]:CLK net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0/U0_RGB1_RGB16_rgbl_net_1 + 0.627 5.873 r
SERDES_EPCS_0/epcs_tx_intf_0/txdout[0]:Q cell ADLIB:SLE + 0.127 6.000 1 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/IP_INTERFACE_185:A net SERDES_EPCS_0/epcs_tx_intf_0_txdout[0] + 0.789 6.789 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/IP_INTERFACE_185:IPA cell ADLIB:IP_INTERFACE + 0.234 7.023 1 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[0] net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXDATA_net[0] + 0.225 7.248 f
data arrival time 7.248
Data required time calculation
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] Clock Constraint 10.000 10.000
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[0] Clock source + 0.000 10.000 r
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[0] Library setup time ADLIB:SERDESIF_075_IP - 1.987 8.013
data required time 8.013
Operating Conditions WORST

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 CoreJESD204BTX_0/RESET_SYNC/genblk1.genblk1[0].epcs_txclk_txstbl_sync_f2[0]:CLK CoreJESD204BTX_0/DC_BDO_0/DATA_OUT[5]:ALn 5.581 4.005 11.439 15.444 0.415 5.995 -0.001 WORST
Path 2 CoreJESD204BTX_0/RESET_SYNC/genblk1.genblk1[0].epcs_txclk_txstbl_sync_f2[0]:CLK CoreJESD204BTX_0/DC_BDO_0/DATA_OUT[18]:ALn 5.581 4.005 11.439 15.444 0.415 5.995 -0.001 WORST
Path 3 CoreJESD204BTX_0/RESET_SYNC/genblk1.genblk1[0].epcs_txclk_txstbl_sync_f2[0]:CLK CoreJESD204BTX_0/DATA_SYNC_BUF_0/genblk4.TX_DATA_OUT[8]:ALn 5.581 4.005 11.439 15.444 0.415 5.995 -0.001 WORST
Path 4 CoreJESD204BTX_0/RESET_SYNC/genblk1.genblk1[0].epcs_txclk_txstbl_sync_f2[0]:CLK CoreJESD204BTX_0/DATA_SYNC_BUF_0/genblk4.TX_DATA_OUT[5]:ALn 5.581 4.005 11.439 15.444 0.415 5.995 -0.001 WORST
Path 5 CoreJESD204BTX_0/RESET_SYNC/genblk1.genblk1[0].epcs_txclk_txstbl_sync_f2[0]:CLK CoreJESD204BTX_0/DATA_SYNC_BUF_0/genblk4.TX_DATA_OUT[18]:ALn 5.581 4.005 11.439 15.444 0.415 5.995 -0.001 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CoreJESD204BTX_0/RESET_SYNC/genblk1.genblk1[0].epcs_txclk_txstbl_sync_f2[0]:CLK
To: CoreJESD204BTX_0/DC_BDO_0/DATA_OUT[5]:ALn
data required time 15.444
data arrival time - 11.439
slack 4.005
Data arrival time calculation
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] 0.000 0.000
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[0] Clock source + 0.000 0.000 r
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0:An net SERDES_EPCS_0/SERDES_IF2_0/EPCS_TXCLK[0] + 3.745 3.745 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0:YWn cell ADLIB:GBM + 0.440 4.185 4 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0/U0_RGB1_RGB16:An net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0/U0_YWn + 0.689 4.874 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0/U0_RGB1_RGB16:YL cell ADLIB:RGB + 0.372 5.246 17 r
CoreJESD204BTX_0/RESET_SYNC/genblk1.genblk1[0].epcs_txclk_txstbl_sync_f2[0]:CLK net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0/U0_RGB1_RGB16_rgbl_net_1 + 0.612 5.858 r
CoreJESD204BTX_0/RESET_SYNC/genblk1.genblk1[0].epcs_txclk_txstbl_sync_f2[0]:Q cell ADLIB:SLE + 0.102 5.960 1 r
CoreJESD204BTX_0/RESET_SYNC/genblk1.genblk1[0].epcs_txclk_txstbl_sync_f2_RNIKKNB[0]:An net CoreJESD204BTX_0/RESET_SYNC/epcs_txclk_txstbl_sync_f2_0Z[0] + 3.308 9.268 f
CoreJESD204BTX_0/RESET_SYNC/genblk1.genblk1[0].epcs_txclk_txstbl_sync_f2_RNIKKNB[0]:YEn cell ADLIB:GBM + 0.441 9.709 4 f
CoreJESD204BTX_0/RESET_SYNC/genblk1.genblk1[0].epcs_txclk_txstbl_sync_f2_RNIKKNB[0]/U0_RGB1_RGB0:An net CoreJESD204BTX_0/RESET_SYNC/genblk1.genblk1[0].epcs_txclk_txstbl_sync_f2_RNIKKNB[0]/U0_YWn_GEast + 0.691 10.400 f
CoreJESD204BTX_0/RESET_SYNC/genblk1.genblk1[0].epcs_txclk_txstbl_sync_f2_RNIKKNB[0]/U0_RGB1_RGB0:YL cell ADLIB:RGB + 0.372 10.772 12 r
CoreJESD204BTX_0/DC_BDO_0/DATA_OUT[5]:ALn net CoreJESD204BTX_0/RESET_SYNC/genblk1.genblk1[0].epcs_txclk_txstbl_sync_f2_RNIKKNB[0]/U0_RGB1_RGB0_rgbl_net_1 + 0.667 11.439 r
data arrival time 11.439
Data required time calculation
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] Clock Constraint 10.000 10.000
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[0] Clock source + 0.000 10.000 r
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0:An net SERDES_EPCS_0/SERDES_IF2_0/EPCS_TXCLK[0] + 3.745 13.745 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0:YEn cell ADLIB:GBM + 0.441 14.186 16 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0/U0_RGB1_RGB13:An net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0/U0_YWn_GEast + 0.695 14.881 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0/U0_RGB1_RGB13:YL cell ADLIB:RGB + 0.372 15.253 12 r
CoreJESD204BTX_0/DC_BDO_0/DATA_OUT[5]:CLK net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0/U0_RGB1_RGB13_rgbl_net_1 + 0.606 15.859 r
CoreJESD204BTX_0/DC_BDO_0/DATA_OUT[5]:ALn Library recovery time ADLIB:SLE - 0.415 15.444
data required time 15.444
Operating Conditions WORST

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] to SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0]

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Operating Conditions
Path 1 CoreJESD204BRX_0/SYNC_ENC_0/SYNC_N:CLK CoreJESD204BTX_0/CJESDTX_SYNC_DEC/sync_counter[2]:D 2.655 7.183 8.356 15.539 0.298 WORST
Path 2 CoreJESD204BRX_0/SYNC_ENC_0/SYNC_N:CLK CoreJESD204BTX_0/CJESDTX_SYNC_DEC/sync_counter[0]:D 2.655 7.183 8.356 15.539 0.298 WORST
Path 3 CoreJESD204BRX_0/SYNC_ENC_0/SYNC_N:CLK CoreJESD204BTX_0/CJESDTX_SYNC_DEC/sync_counter[1]:D 2.654 7.184 8.355 15.539 0.298 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CoreJESD204BRX_0/SYNC_ENC_0/SYNC_N:CLK
To: CoreJESD204BTX_0/CJESDTX_SYNC_DEC/sync_counter[2]:D
data required time 15.539
data arrival time - 8.356
slack 7.183
Data arrival time calculation
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] 0.000 0.000
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[0] Clock source + 0.000 0.000 r
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB:An net SERDES_EPCS_0/SERDES_IF2_0/EPCS_RXCLK[0] + 3.527 3.527 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB:YEn cell ADLIB:GBM + 0.441 3.968 30 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_RGB1_RGB10:An net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_YWn_GEast + 0.747 4.715 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_RGB1_RGB10:YR cell ADLIB:RGB + 0.372 5.087 130 r
CoreJESD204BRX_0/SYNC_ENC_0/SYNC_N:CLK net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB/U0_RGB1_RGB10_rgbr_net_1 + 0.614 5.701 r
CoreJESD204BRX_0/SYNC_ENC_0/SYNC_N:Q cell ADLIB:SLE + 0.127 5.828 8 f
CoreJESD204BTX_0/CJESDTX_SYNC_DEC/sync_counter_5_iv_i[2]:C net CoreJESD204BTX_0.CJESDTX_SYNC_DEC.SYNC_N + 2.324 8.152 f
CoreJESD204BTX_0/CJESDTX_SYNC_DEC/sync_counter_5_iv_i[2]:Y cell ADLIB:CFG4 + 0.117 8.269 1 r
CoreJESD204BTX_0/CJESDTX_SYNC_DEC/sync_counter[2]:D net CoreJESD204BTX_0/CJESDTX_SYNC_DEC/sync_counter_5_iv_i[2] + 0.087 8.356 r
data arrival time 8.356
Data required time calculation
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] Clock Constraint 10.000 10.000
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[0] Clock source + 0.000 10.000 r
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0:An net SERDES_EPCS_0/SERDES_IF2_0/EPCS_TXCLK[0] + 3.745 13.745 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0:YEn cell ADLIB:GBM + 0.441 14.186 16 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0/U0_RGB1_RGB2:An net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0/U0_YWn_GEast + 0.680 14.866 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0/U0_RGB1_RGB2:YR cell ADLIB:RGB + 0.372 15.238 45 r
CoreJESD204BTX_0/CJESDTX_SYNC_DEC/sync_counter[2]:CLK net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0/U0_RGB1_RGB2_rgbr_net_1 + 0.599 15.837 r
CoreJESD204BTX_0/CJESDTX_SYNC_DEC/sync_counter[2]:D Library setup time ADLIB:SLE - 0.298 15.539
data required time 15.539
Operating Conditions WORST

SET SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 to SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0]

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Operating Conditions
Path 1 SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE ERR_GEN_0/TX_DATA_OUT[14]:D 7.258 0.938 14.625 15.563 0.298 WORST
Path 2 SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE ERR_GEN_0/TX_DATA_OUT[10]:D 7.258 0.938 14.625 15.563 0.298 WORST
Path 3 SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE ERR_GEN_0/TX_DATA_OUT[7]:D 7.257 0.954 14.624 15.578 0.298 WORST
Path 4 SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE ERR_GEN_0/TX_DATA_OUT[2]:D 7.256 0.954 14.623 15.577 0.298 WORST
Path 5 SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE ERR_GEN_0/TX_DATA_OUT[0]:D 7.257 0.954 14.624 15.578 0.298 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE
To: ERR_GEN_0/TX_DATA_OUT[14]:D
data required time 15.563
data arrival time - 14.625
slack 0.938
Data arrival time calculation
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 0.000 0.000
SF2_JESD204B_DEMO_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 4.539 4.539
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST:An net SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_net + 0.537 5.076 r
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.209 5.285 9 f
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_RGB1:An net SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.730 6.015 f
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_RGB1:YR cell ADLIB:RGB + 0.372 6.387 1 r
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B net SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_RGB1_YR + 0.479 6.866 r
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB cell ADLIB:IP_INTERFACE + 0.246 7.112 1 r
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE net SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net + 0.255 7.367 r
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_SDO_MGPIO6A_H2F_B cell ADLIB:MSS_075_IP + 1.397 8.764 12 f
ERR_GEN_0/TX_DATA_OUT_4[14]:A net SF2_JESD204B_DEMO_sb_0_GPIO_6_M2F + 5.656 14.420 f
ERR_GEN_0/TX_DATA_OUT_4[14]:Y cell ADLIB:CFG2 + 0.117 14.537 1 r
ERR_GEN_0/TX_DATA_OUT[14]:D net ERR_GEN_0/TX_DATA_OUT_4[14] + 0.088 14.625 r
data arrival time 14.625
Data required time calculation
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[0] Clock Constraint 10.000 10.000
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[0] Clock source + 0.000 10.000 r
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0:An net SERDES_EPCS_0/SERDES_IF2_0/EPCS_TXCLK[0] + 3.745 13.745 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0:YEn cell ADLIB:GBM + 0.441 14.186 16 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0/U0_RGB1_RGB15:An net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0/U0_YWn_GEast + 0.697 14.883 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0/U0_RGB1_RGB15:YL cell ADLIB:RGB + 0.372 15.255 12 r
ERR_GEN_0/TX_DATA_OUT[14]:CLK net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_0/U0_RGB1_RGB15_rgbl_net_1 + 0.606 15.861 r
ERR_GEN_0/TX_DATA_OUT[14]:D Library setup time ADLIB:SLE - 0.298 15.563
data required time 15.563
Operating Conditions WORST

Clock Domain SF2_JESD204B_DEMO_sb_0/CCC_0/GL0

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[21] 6.133 2.693 13.500 16.193 1.174 7.307 WORST
Path 2 SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[15] 6.129 2.739 13.496 16.235 1.132 7.261 WORST
Path 3 DATAHANDLE_FSM_0/DATA_WADDR[1]:CLK TPSRAM_1/top_TPSRAM_1_TPSRAM_R0C3/INST_RAM1K18_IP:B_ADDR[4] 1.763 2.787 8.804 11.591 0.559 4.426 WORST
Path 4 SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[30] 5.989 2.813 13.356 16.169 1.198 7.187 WORST
Path 5 DATAHANDLE_FSM_0/DATA_WADDR[0]:CLK TPSRAM_1/top_TPSRAM_1_TPSRAM_R0C3/INST_RAM1K18_IP:B_ADDR[3] 1.790 2.814 8.817 11.631 0.519 4.372 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE
To: SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[21]
data required time 16.193
data arrival time - 13.500
slack 2.693
Data arrival time calculation
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 0.000 0.000
SF2_JESD204B_DEMO_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 4.539 4.539
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST:An net SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_net + 0.537 5.076 r
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.209 5.285 9 f
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_RGB1:An net SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.730 6.015 f
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_RGB1:YR cell ADLIB:RGB + 0.372 6.387 1 r
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B net SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_RGB1_YR + 0.479 6.866 r
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB cell ADLIB:IP_INTERFACE + 0.246 7.112 1 r
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE net SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net + 0.255 7.367 r
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:I2C1_SDA_MGPIO0A_H2F_B cell ADLIB:MSS_075_IP + 1.710 9.077 32 f
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST_RNO_20:B net SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/SF2_JESD204B_DEMO_sb_0_GPIO_0_M2F + 2.235 11.312 f
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST_RNO_20:Y cell ADLIB:CFG3 + 0.173 11.485 1 r
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_16:A net SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/AMBA_SLAVE_0_PRDATAS0_m[21] + 1.537 13.022 r
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_16:IPA cell ADLIB:IP_INTERFACE + 0.228 13.250 1 r
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[21] net SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/F_HM0_RDATA_net[21] + 0.250 13.500 r
data arrival time 13.500
Data required time calculation
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 Clock Constraint 10.000 10.000
SF2_JESD204B_DEMO_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 10.000 r
Clock generation + 4.539 14.539
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST:An net SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_net + 0.537 15.076 r
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.209 15.285 9 f
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_RGB1:An net SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.730 16.015 f
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_RGB1:YR cell ADLIB:RGB + 0.372 16.387 1 r
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B net SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_RGB1_YR + 0.479 16.866 r
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB cell ADLIB:IP_INTERFACE + 0.246 17.112 1 r
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE net SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net + 0.255 17.367 r
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[21] Library setup time ADLIB:MSS_075_IP - 1.174 16.193
data required time 16.193
Operating Conditions WORST

SET External Setup

No Path

SET Clock to Output

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Clock to Out (ns) Operating Conditions
Path 1 SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE MMUART_1_TXD 7.064 14.431 14.431 WORST
Path 2 SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE MMUART_0_TXD 6.604 13.971 13.971 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE
To: MMUART_1_TXD
data required time N/C
data arrival time - 14.431
slack N/C
Data arrival time calculation
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 0.000 0.000
SF2_JESD204B_DEMO_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 4.539 4.539
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST:An net SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_net + 0.537 5.076 r
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.209 5.285 9 f
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_RGB1:An net SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.730 6.015 f
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_RGB1:YR cell ADLIB:RGB + 0.372 6.387 1 r
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B net SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_RGB1_YR + 0.479 6.866 r
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB cell ADLIB:IP_INTERFACE + 0.246 7.112 1 r
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE net SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net + 0.255 7.367 r
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT cell ADLIB:MSS_075_IP + 2.375 9.742 1 f
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MMUART_1_TXD_PAD/U_IOPAD:D net SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT + 1.552 11.294 f
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MMUART_1_TXD_PAD/U_IOPAD:PAD cell ADLIB:IOPAD_TRI + 3.137 14.431 0 f
MMUART_1_TXD net MMUART_1_TXD + 0.000 14.431 f
data arrival time 14.431
Data required time calculation
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 N/C N/C
SF2_JESD204B_DEMO_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 N/C r
Clock generation + 4.539 N/C
MMUART_1_TXD N/C f
Operating Conditions WORST

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 SF2_JESD204B_DEMO_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sm0_areset_n_clk_base:ALn 4.675 4.905 11.662 16.567 0.415 5.095 0.005 WORST
Path 2 SF2_JESD204B_DEMO_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sdif0_areset_n_clk_base:ALn 4.675 4.905 11.662 16.567 0.415 5.095 0.005 WORST
Path 3 SF2_JESD204B_DEMO_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sm0_areset_n_q1:ALn 4.675 4.917 11.662 16.579 0.415 5.083 -0.007 WORST
Path 4 SF2_JESD204B_DEMO_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sdif0_areset_n_q1:ALn 4.675 4.917 11.662 16.579 0.415 5.083 -0.007 WORST
Path 5 SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sm0_areset_n_clk_base:CLK SF2_JESD204B_DEMO_sb_0/CORERESETP_0/ddr_settled_clk_base:ALn 4.247 5.341 11.247 16.588 0.415 4.659 -0.003 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SF2_JESD204B_DEMO_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK
To: SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sm0_areset_n_clk_base:ALn
data required time 16.567
data arrival time - 11.662
slack 4.905
Data arrival time calculation
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 0.000 0.000
SF2_JESD204B_DEMO_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 4.539 4.539
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST:An net SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_net + 0.537 5.076 r
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.209 5.285 9 f
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB7:An net SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.747 6.032 f
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB7:YR cell ADLIB:RGB + 0.372 6.404 3 r
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK net SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB7_rgbr_net_1 + 0.583 6.987 r
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/MSS_HPMS_READY_int:Q cell ADLIB:SLE + 0.102 7.089 1 r
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sdif0_areset_n:B net SF2_JESD204B_DEMO_sb_0/CORERESETP_0/MSS_HPMS_READY_int + 0.379 7.468 r
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sdif0_areset_n:Y cell ADLIB:CFG2 + 0.088 7.556 1 r
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sdif0_areset_n_RNISB46:An net SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sm0_areset_n + 1.953 9.509 f
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sdif0_areset_n_RNISB46:YEn cell ADLIB:GBM + 0.441 9.950 1 f
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sdif0_areset_n_RNISB46/U0_RGB1:An net SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sdif0_areset_n_RNISB46/U0_YWn_GEast + 0.720 10.670 f
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sdif0_areset_n_RNISB46/U0_RGB1:YL cell ADLIB:RGB + 0.372 11.042 14 r
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sm0_areset_n_clk_base:ALn net SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sm0_areset_n_arst + 0.620 11.662 r
data arrival time 11.662
Data required time calculation
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 Clock Constraint 10.000 10.000
SF2_JESD204B_DEMO_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 10.000 r
Clock generation + 4.539 14.539
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST:An net SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_net + 0.537 15.076 r
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.209 15.285 9 f
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB7:An net SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.747 16.032 f
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB7:YL cell ADLIB:RGB + 0.372 16.404 8 r
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sm0_areset_n_clk_base:CLK net SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB7_rgbl_net_1 + 0.578 16.982 r
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sm0_areset_n_clk_base:ALn Library recovery time ADLIB:SLE - 0.415 16.567
data required time 16.567
Operating Conditions WORST

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] to SF2_JESD204B_DEMO_sb_0/CCC_0/GL0

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Operating Conditions
Path 1 SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[0] DATAHANDLE_FSM_0/DATA_WADDR[7]:ALn 7.710 3.883 7.710 11.593 WORST
Path 2 SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[0] DATAHANDLE_FSM_0/DATA_WADDR[0]:ALn 7.710 3.883 7.710 11.593 WORST
Path 3 SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[0] DATAHANDLE_FSM_0/DATA_WADDR[8]:ALn 7.693 3.887 7.693 11.580 WORST
Path 4 SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[0] DATAHANDLE_FSM_0/DATA_WADDR[6]:ALn 7.693 3.887 7.693 11.580 WORST
Path 5 SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[0] DATAHANDLE_FSM_0/DATA_WADDR[3]:ALn 7.710 3.894 7.710 11.604 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[0]
To: DATAHANDLE_FSM_0/DATA_WADDR[7]:ALn
data required time 11.593
data arrival time - 7.710
slack 3.883
Data arrival time calculation
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[0] 0.000 0.000
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[0] Clock source + 0.000 0.000 r
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXRSTN[0] cell ADLIB:SERDESIF_075_IP + 1.748 1.748 187 r
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_2:An net SERDES_EPCS_0.SERDES_IF2_0.EPCS_2_RX_RESET_N + 3.780 5.528 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_2:YEn cell ADLIB:GBM + 0.441 5.969 9 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_2/U0_RGB1_RGB3:An net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_2/U0_YWn_GEast + 0.728 6.697 f
SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_2/U0_RGB1_RGB3:YR cell ADLIB:RGB + 0.372 7.069 21 r
DATAHANDLE_FSM_0/DATA_WADDR[7]:ALn net SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST_RNI2JRB_2/U0_RGB1_RGB3_rgbr_net_1 + 0.641 7.710 r
data arrival time 7.710
Data required time calculation
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 Clock Constraint 5.000 5.000
SF2_JESD204B_DEMO_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 5.000 f
Clock generation + 4.594 9.594
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST:An net SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_net + 0.546 10.140 f
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.240 10.380 9 r
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB3:An net SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.707 11.087 r
SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB3:YR cell ADLIB:RGB + 0.292 11.379 15 f
DATAHANDLE_FSM_0/DATA_WADDR[7]:CLK net SF2_JESD204B_DEMO_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB3_rgbr_net_1 + 0.629 12.008 r
DATAHANDLE_FSM_0/DATA_WADDR[7]:ALn Library recovery time ADLIB:SLE - 0.415 11.593
data required time 11.593
Operating Conditions WORST

SET SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT to SF2_JESD204B_DEMO_sb_0/CCC_0/GL0

No Path

SET SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB to SF2_JESD204B_DEMO_sb_0/CCC_0/GL0

No Path

Clock Domain SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 SF2_JESD204B_DEMO_sb_0/CORERESETP_0/count_sdif0[11]:CLK SF2_JESD204B_DEMO_sb_0/CORERESETP_0/release_sdif0_core:EN 3.157 16.418 13.420 29.838 0.363 3.582 WORST
Path 2 SF2_JESD204B_DEMO_sb_0/CORERESETP_0/count_sdif0[7]:CLK SF2_JESD204B_DEMO_sb_0/CORERESETP_0/release_sdif0_core:EN 2.797 16.778 13.060 29.838 0.363 3.222 WORST
Path 3 SF2_JESD204B_DEMO_sb_0/CORERESETP_0/count_sdif0[0]:CLK SF2_JESD204B_DEMO_sb_0/CORERESETP_0/release_sdif0_core:EN 2.738 16.882 12.956 29.838 0.363 3.118 WORST
Path 4 SF2_JESD204B_DEMO_sb_0/CORERESETP_0/count_sdif0[3]:CLK SF2_JESD204B_DEMO_sb_0/CORERESETP_0/release_sdif0_core:EN 2.647 16.928 12.910 29.838 0.363 3.072 WORST
Path 5 SF2_JESD204B_DEMO_sb_0/CORERESETP_0/count_sdif0[8]:CLK SF2_JESD204B_DEMO_sb_0/CORERESETP_0/release_sdif0_core:EN 2.587 17.002 12.836 29.838 0.363 2.998 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SF2_JESD204B_DEMO_sb_0/CORERESETP_0/count_sdif0[11]:CLK
To: SF2_JESD204B_DEMO_sb_0/CORERESETP_0/release_sdif0_core:EN
data required time 29.838
data arrival time - 13.420
slack 16.418
Data arrival time calculation
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 0.000 0.000
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net SF2_JESD204B_DEMO_sb_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 3.648 3.648 r
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.179 3.827 1 r
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net SF2_JESD204B_DEMO_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 4.258 8.085 f
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.441 8.526 3 f
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An net SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.733 9.259 f
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YL cell ADLIB:RGB + 0.372 9.631 18 r
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/count_sdif0[11]:CLK net SF2_JESD204B_DEMO_sb_0/FABOSC_0_RCOSC_25_50MHZ_O2F + 0.632 10.263 r
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/count_sdif0[11]:Q cell ADLIB:SLE + 0.127 10.390 2 f
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/release_sdif0_core4_7:B net SF2_JESD204B_DEMO_sb_0/CORERESETP_0/count_sdif0[11] + 1.005 11.395 f
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/release_sdif0_core4_7:Y cell ADLIB:CFG4 + 0.338 11.733 1 f
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/release_sdif0_core4:B net SF2_JESD204B_DEMO_sb_0/CORERESETP_0/release_sdif0_core4_7 + 0.261 11.994 f
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/release_sdif0_core4:Y cell ADLIB:CFG4 + 0.193 12.187 1 f
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/release_sdif0_core:EN net SF2_JESD204B_DEMO_sb_0/CORERESETP_0/release_sdif0_core4 + 1.233 13.420 f
data arrival time 13.420
Data required time calculation
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Clock Constraint 20.000 20.000
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 20.000 r
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net SF2_JESD204B_DEMO_sb_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 3.648 23.648 r
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.179 23.827 1 r
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net SF2_JESD204B_DEMO_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 4.258 28.085 f
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.441 28.526 3 f
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An net SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.733 29.259 f
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YL cell ADLIB:RGB + 0.372 29.631 18 r
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/release_sdif0_core:CLK net SF2_JESD204B_DEMO_sb_0/FABOSC_0_RCOSC_25_50MHZ_O2F + 0.570 30.201 r
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/release_sdif0_core:EN Library setup time ADLIB:SLE - 0.363 29.838
data required time 29.838
Operating Conditions WORST

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK SF2_JESD204B_DEMO_sb_0/CORERESETP_0/count_sdif0[6]:ALn 3.982 15.574 14.240 29.814 0.415 4.426 0.029 WORST
Path 2 SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK SF2_JESD204B_DEMO_sb_0/CORERESETP_0/count_sdif0[4]:ALn 3.982 15.574 14.240 29.814 0.415 4.426 0.029 WORST
Path 3 SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK SF2_JESD204B_DEMO_sb_0/CORERESETP_0/count_sdif0[2]:ALn 3.982 15.574 14.240 29.814 0.415 4.426 0.029 WORST
Path 4 SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK SF2_JESD204B_DEMO_sb_0/CORERESETP_0/count_sdif0[10]:ALn 3.982 15.574 14.240 29.814 0.415 4.426 0.029 WORST
Path 5 SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK SF2_JESD204B_DEMO_sb_0/CORERESETP_0/count_sdif0[8]:ALn 3.982 15.575 14.240 29.815 0.415 4.425 0.028 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK
To: SF2_JESD204B_DEMO_sb_0/CORERESETP_0/count_sdif0[6]:ALn
data required time 29.814
data arrival time - 14.240
slack 15.574
Data arrival time calculation
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 0.000 0.000
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net SF2_JESD204B_DEMO_sb_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 3.648 3.648 r
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.179 3.827 1 r
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net SF2_JESD204B_DEMO_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 4.258 8.085 f
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.441 8.526 3 f
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An net SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.735 9.261 f
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YL cell ADLIB:RGB + 0.372 9.633 11 r
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK net SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbl_net_1 + 0.625 10.258 r
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:Q cell ADLIB:SLE + 0.102 10.360 1 r
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIL4R4:An net SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_0 + 1.671 12.031 f
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIL4R4:YEn cell ADLIB:GBM + 0.441 12.472 1 f
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIL4R4/U0_RGB1:An net SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIL4R4/U0_YWn_GEast + 0.741 13.213 f
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIL4R4/U0_RGB1:YL cell ADLIB:RGB + 0.372 13.585 14 r
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/count_sdif0[6]:ALn net SF2_JESD204B_DEMO_sb_0/CORERESETP_0/sdif0_areset_n_rcosc + 0.655 14.240 r
data arrival time 14.240
Data required time calculation
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Clock Constraint 20.000 20.000
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 20.000 r
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net SF2_JESD204B_DEMO_sb_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 3.648 23.648 r
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.179 23.827 1 r
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net SF2_JESD204B_DEMO_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 4.258 28.085 f
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.441 28.526 3 f
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An net SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.733 29.259 f
SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YL cell ADLIB:RGB + 0.372 29.631 18 r
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/count_sdif0[6]:CLK net SF2_JESD204B_DEMO_sb_0/FABOSC_0_RCOSC_25_50MHZ_O2F + 0.598 30.229 r
SF2_JESD204B_DEMO_sb_0/CORERESETP_0/count_sdif0[6]:ALn Library recovery time ADLIB:SLE - 0.415 29.814
data required time 29.814
Operating Conditions WORST

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 to SF2_JESD204B_DEMO_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

No Path

Clock Domain SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB SF2_JESD204B_DEMO_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN 1.913 1.589 1.913 3.502 0.288 -1.589 BEST
Path 2 SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB SF2_JESD204B_DEMO_sb_0/CORECONFIGP_0/state[0]:D 1.336 2.224 1.336 3.560 0.237 -2.224 BEST
Path 3 SF2_JESD204B_DEMO_sb_0/CORECONFIGP_0/psel:CLK SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:APB_PSEL 8.549 8.439 15.221 23.660 3.133 23.122 WORST
Path 4 SF2_JESD204B_DEMO_sb_0/CORECONFIGP_0/SDIF0_PENABLE:CLK SERDES_EPCS_0/SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:APB_PENABLE 6.255 13.034 12.918 25.952 0.841 13.932 WORST
Path 5 SF2_JESD204B_DEMO_sb_0/CORECONFIGP_0/psel:CLK SF2_JESD204B_DEMO_sb_0/CORECONFIGP_0/soft_reset_reg[13]:EN 4.929 14.516 11.601 26.117 0.363 10.968 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB
To: SF2_JESD204B_DEMO_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN
data required time 3.502
data arrival time - 1.913
slack 1.589
Data arrival time calculation
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB 0.000 0.000
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB Clock source + 0.000 0.000 r
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PENABLE cell ADLIB:MSS_075_IP + 0.587 0.587 3 r
SF2_JESD204B_DEMO_sb_0/CORECONFIGP_0/next_state4:A net SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE + 0.514 1.101 r
SF2_JESD204B_DEMO_sb_0/CORECONFIGP_0/next_state4:Y cell ADLIB:CFG2 + 0.098 1.199 1 f
SF2_JESD204B_DEMO_sb_0/CORECONFIGP_0/state_ns_0_a3[0]:A net SF2_JESD204B_DEMO_sb_0/CORECONFIGP_0/next_state4 + 0.064 1.263 f
SF2_JESD204B_DEMO_sb_0/CORECONFIGP_0/state_ns_0_a3[0]:Y cell ADLIB:CFG3 + 0.060 1.323 2 f
SF2_JESD204B_DEMO_sb_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0:A net SF2_JESD204B_DEMO_sb_0/CORECONFIGP_0/state_ns[0] + 0.157 1.480 f
SF2_JESD204B_DEMO_sb_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0:Y cell ADLIB:CFG3 + 0.060 1.540 1 f
SF2_JESD204B_DEMO_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN net SF2_JESD204B_DEMO_sb_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0 + 0.373 1.913 f
data arrival time 1.913
Data required time calculation
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB Max Delay Constraint 0.000 0.000
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB Clock source + 0.000 0.000 r
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST_RNIN0J7:An net SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB + 2.531 2.531 f
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST_RNIN0J7:YEn cell ADLIB:GBM + 0.257 2.788 4 f
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST_RNIN0J7/U0_RGB1:An net SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST_RNIN0J7/U0_YWn_GEast + 0.426 3.214 f
SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST_RNIN0J7/U0_RGB1:YR cell ADLIB:RGB + 0.218 3.432 11 r
SF2_JESD204B_DEMO_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:CLK net SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/MSS_ADLIB_INST_RNIN0J7/U0_RGB1_YR + 0.358 3.790 r
SF2_JESD204B_DEMO_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN Library setup time ADLIB:SLE - 0.288 3.502
data required time 3.502
Operating Conditions BEST

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET SF2_JESD204B_DEMO_sb_0/CCC_0/GL0 to SF2_JESD204B_DEMO_sb_0/SF2_JESD204B_DEMO_sb_MSS_0/CLK_CONFIG_APB

No Path

Path Set Pin to Pin

SET Input to Output

No Path

Path Set User Sets