| Project Settings |
|---|
| Project Name | SF2_Standby_syn | Implementation Name | synthesis |
| Top Module | [auto] | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 10000 |
| Disable I/O Insertion | 0 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
36 |
5 |
0 |
- |
0m:01s |
- |
2/17/2016
9:53:26 AM |
| (premap) | Complete |
3 |
2 |
0 |
0m:04s |
0m:04s |
335MB |
2/17/2016
9:53:32 AM |
| (fpga_mapper) | Complete |
127 |
126 |
0 |
02m:02s |
02m:03s |
455MB |
2/17/2016
9:55:36 AM |
| Multi-srs Generator |
Complete | | | | 0m:01s | | | 2/17/2016
9:53:28 AM |
| Area Summary |
|---|
| |
| Carry Cells | 37882 |
Sequential Cells | 33683 |
| DSP Blocks (MACC)
(dsp_used) | 42 |
I/O Cells | 39 |
| Global Clock Buffers | 6 |
Block Rams (RAM1K18)
(v_ram) | 55 |
| Block Rams (RAM64x18)
(v_ram) | 56 |
LUTs
(total_luts) | 37911 |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| SF2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | 304.4 MHz | 6.715 |
| System | 100.0 MHz | 149.5 MHz | 3.309 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 1 / 0 |
| |
|